Power supply control method, switching power supply and electronic equipment

Abstract

The embodiment of the invention provides a power supply control method, a switching power supply and electronic equipment, the method is applied to the switching power supply, and the switching power supply is realized based on an LLC topological structure of bootstrap power supply of a floating drive circuit. The power supply control method comprises the following steps: when the switching power supply starts power supply for the first time after being powered on, outputting a first continuous high-frequency narrow pulse signal with a preset first duration to the second driving circuit; after the first continuous high-frequency narrow pulse signal is output, a first driving signal is output to the first driving circuit, a second driving signal is output to the second driving circuit, the first driving signal is used for controlling on-off of the first power tube, and the second driving signal is used for controlling on-off of the second power tube. The embodiment of the invention solves the problem of wave loss of the first driving circuit of the first power tube.

Description

Technical Field

[0001] The present application relates to the technical field of switching power supplies, and in particular to a power supply control method, a switching power supply and an electronic device. Background Art

[0002] Switching power supplies are increasingly widely used, and high power density, high efficiency, high reliability and low cost have become the development trend of switching power supplies. LLC topology has certain advantages in efficiency and cost, and is increasingly used in switching power supplies, among which LLC topology based on floating drive bootstrap power supply is widely used in switching power supplies.

[0003] However, in the LLC topology based on floating drive bootstrap power supply, the bootstrap capacitor needs the lower bridge arm power tube to be turned on to realize bootstrap charging, that is, the lower bridge arm power tube can be turned on to charge the bootstrap capacitor of the floating ground drive circuit of the upper bridge arm power tube, and when the bootstrap capacitor is charged to above the preset voltage, the floating ground drive circuit can work normally and drive the power tube of the upper bridge arm. Therefore, when the processor of the switching power supply starts the LLC topology, after outputting the drive signal to the drive circuit of the upper and lower bridge arm power tubes and before the bootstrap capacitor is charged to the preset voltage, the floating ground drive circuit of the upper bridge arm power tube cannot work normally, and thus cannot output the drive signal to drive the upper power tube, resulting in the problem of asymmetric drive of the upper and lower bridge arms (that is, the drive wave loss of the upper bridge arm power tube). Summary of the invention

[0004] The embodiments of the present application provide a power supply control method, a switching power supply and an electronic device to solve the problem of asymmetric driving of the upper and lower bridge arms (i.e., drive wave loss of the upper bridge arm power tube) in an LLC topology based on floating drive bootstrap power supply.

[0005] In a first aspect, the present application provides a power supply control method, which is applied to a switching power supply, wherein the switching power supply is implemented based on an LLC topology structure of bootstrap power supply of a floating drive circuit, and the switching power supply includes: a first power tube, a second power tube, a first drive circuit, a second drive circuit, and a bootstrap capacitor, wherein the first power tube and the second power tube are connected in series between a first voltage input terminal and a second voltage input terminal of the switching power supply, the first drive circuit connects the two ends of the bootstrap capacitor, and the first drive circuit connects the first end and the control end of the first power tube, and the first end of the first power tube is an end connected to the second power tube; the power supply control method includes: when the switching power supply starts powering for the first time after power is powered on, outputting a first continuous high-frequency narrow pulse signal of a preset first duration to the second drive circuit; after the output of the first continuous high-frequency narrow pulse signal ends, outputting a first drive signal to the first drive circuit, and outputting a second drive signal to the second drive circuit, the first drive signal is used to control the on and off of the first power tube, and the second drive signal is used to control the on and off of the second power tube. When the switching power supply is powered on and the power supply is started for the first time, the method first outputs a first continuous high-frequency narrow pulse signal to the second drive circuit, charges the voltage of the bootstrap capacitor to a value not lower than the undervoltage recovery point of the first drive circuit, ensures that the bootstrap capacitor can supply power to the first drive circuit, and enables the first drive circuit to operate normally, and then outputs a drive signal to the first drive circuit and the second drive circuit, thereby solving the problem of asymmetric driving of the upper and lower bridge arms when the power supply is started for the first time after startup in an LLC topology based on floating drive bootstrap power supply, that is, the problem of wave loss in the first drive circuit.

[0006] Optionally, the preset first time duration is greater than or equal to a second time duration, and the second time duration is the time duration for the voltage of the bootstrap capacitor to increase from 0V to a preset first voltage when a first continuous high-frequency narrow pulse signal is output to the second drive circuit.

[0007] Optionally, the first drive signal and the second drive signal have opposite phases, and a first valid drive signal of the first drive signal is earlier than a first valid drive signal of the second drive signal.

[0008] Optionally, it also includes: when the switching power supply is in intermittent mode, stops outputting the first driving signal to the first driving circuit and stops outputting the second driving signal to the second driving circuit, periodically outputs a second continuous high-frequency narrow pulse signal of a preset third duration to the second driving circuit. When the switching power supply is in intermittent mode and stops driving the first power tube and the second power tube, the method periodically outputs a second continuous high-frequency narrow pulse signal of a preset third duration to the second driving circuit, thereby ensuring that the voltage of the bootstrap capacitor will not drop to the undervoltage recovery point of the first driving circuit, and can supply power to the first driving circuit at any time to ensure the normal operation of the first driving circuit, thereby solving the problem of asymmetric driving of the upper and lower bridge arms that may occur in the intermittent mode, that is, the problem of wave loss of the first driving circuit.

[0009] Optionally, the time interval between the end moment of the second continuous high-frequency narrow pulse signal of the previous third duration and the start moment of the second continuous high-frequency narrow pulse signal of the next third duration is less than or equal to the time it takes for the bootstrap capacitor to drop from the target voltage to a preset first voltage when the second drive circuit is not working, and the first voltage is the minimum supply voltage for the second drive circuit to work normally.

[0010] Optionally, the third time duration is greater than or equal to a fourth time duration, and the fourth time duration is the time duration for the voltage of the bootstrap capacitor to increase from the preset first voltage to the target voltage when a second continuous high-frequency narrow pulse signal is output to the second drive circuit.

[0011] Optionally, it also includes: when it is determined that the output voltage of the switching power supply is lower than a preset third voltage and a second continuous high-frequency narrow pulse signal is being output to the second drive circuit, the second continuous high-frequency narrow pulse signal being output to the second drive circuit is stopped, a first drive signal is output to the first drive circuit, and a second drive signal is output to the second drive circuit.

[0012] Optionally, it also includes: when it is determined that the switching power supply is converted from intermittent mode to continuous mode and is outputting a second continuous high-frequency narrow pulse signal to the second drive circuit, stopping the second continuous high-frequency narrow pulse signal being output to the second drive circuit, outputting a first drive signal to the first drive circuit, and outputting a second drive signal to the second drive circuit.

[0013] Optionally, it also includes: when the switching power supply is in intermittent mode and stops outputting the first drive signal to the first drive circuit and stops outputting the second drive signal to the second drive circuit, obtaining the real-time voltage of the bootstrap capacitor, and when the real-time voltage of the bootstrap capacitor is lower than a preset second voltage, outputting a third continuous high-frequency narrow pulse signal of a preset fifth duration to the second drive circuit.

[0014] Optionally, the fifth time duration is greater than or equal to a sixth time duration, and the sixth time duration is the time duration for the voltage of the bootstrap capacitor to increase from the preset first voltage to the target voltage when a third continuous high-frequency narrow pulse signal is output to the second drive circuit.

[0015] Optionally, it also includes: when it is determined that the output voltage of the switching power supply is lower than a preset third voltage and a third continuous high-frequency narrow pulse signal is being output to the second drive circuit, the third continuous high-frequency narrow pulse signal being output to the second drive circuit is stopped, a first drive signal is output to the first drive circuit, and a second drive signal is output to the second drive circuit.

[0016] Optionally, it also includes: when it is determined that the switching power supply is converted from intermittent mode to continuous mode and is outputting a third continuous high-frequency narrow pulse signal to the second drive circuit, stopping the third continuous high-frequency narrow pulse signal being output to the second drive circuit, outputting a first drive signal to the first drive circuit and outputting a second drive signal to the second drive circuit.

[0017] In a second aspect, an embodiment of the present application provides a switching power supply, which is implemented based on an LLC topology structure with bootstrap power supply of a floating drive circuit. The switching power supply includes: a first power tube, a second power tube, a first drive circuit, a second drive circuit and a bootstrap capacitor, the first power tube and the second power tube are connected in series between a first voltage input terminal and a second voltage input terminal of the switching power supply, the first drive circuit connects the two ends of the bootstrap capacitor, and the first drive circuit connects the first end and the control end of the first power tube, the first end of the first power tube is an end connected to the second power tube; the switching power supply also includes a processor; the processor is used to execute the method described in any one of the first aspects.

[0018] In a third aspect, an embodiment of the present application provides an electronic device, comprising the switching power supply described in the second aspect.

[0019] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, which, when executed on a computer, enables the computer to execute any of the methods described in the first aspect.

[0020] In a fifth aspect, an embodiment of the present application provides a computer program, which, when executed by a computer, is used to execute the method of the first aspect.

[0021] In one possible design, the program in the fifth aspect may be stored in whole or in part on a storage medium packaged together with the processor, or may be stored in whole or in part on a memory not packaged together with the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the structure of an LLC topology provided in an embodiment of the present application;

[0023] Figure 2A A structural schematic diagram of a full-bridge LLC topology provided in an embodiment of the present application;

[0024] Figure 2B A schematic diagram of a structure of a resonant capacitor symmetrical half-bridge LLC topology provided in an embodiment of the present application;

[0025] Figure 2C A schematic diagram of a structure of an asymmetric half-bridge LLC topology provided in an embodiment of the present application;

[0026] Figure 3 A schematic diagram of the structure of a bootstrap power supply circuit of a driving circuit 1 of LLC topology provided in an embodiment of the present application;

[0027] Figure 4 A signal timing diagram of a lost wave of a driving circuit 1 provided in an embodiment of the present application;

[0028] Figure 5 A schematic diagram of the signal timing for precharging the lower tube provided in an embodiment of the present application;

[0029] Figure 6 A schematic diagram showing the principle that the lower tube pre-charging causes the resonant capacitor discharge voltage to deviate from the midpoint provided in an embodiment of the present application;

[0030] Figure 7 A schematic diagram of a structure of a switching power supply based on a resonant capacitor symmetrical half-bridge LLC topology provided in an embodiment of the present application;

[0031] Fig. 8A A signal timing diagram of a power supply control method provided in an embodiment of the present application;

[0032] Figure 8B A schematic diagram illustrating the principle of the power supply control method provided in an embodiment of the present application;

[0033] Fig. 9A A comparison diagram of the time variation curves of the bootstrap capacitor charging voltage and the resonant capacitor discharging voltage provided in the embodiment of the present application;

[0034] Fig. 9B A comparison diagram of time variation curves of the bootstrap capacitor charging current and the resonant capacitor discharging current provided in an embodiment of the present application;

[0035] Fig. 10A A schematic diagram of a flow chart of a power supply control method provided in an embodiment of the present application;

[0036] Fig. 10B A signal timing diagram of a power supply control method provided in an embodiment of the present application;

[0037] Fig.11A Another schematic diagram of a flow chart of a power supply control method provided in an embodiment of the present application;

[0038] Fig. 11B Another signal timing diagram of the power supply control method provided in an embodiment of the present application;

[0039] Fig.12 Another schematic diagram of a flow chart of a power supply control method provided in an embodiment of the present application;

[0040] Fig.13 A schematic diagram of another flow chart of the power supply control method provided in the embodiment of the present application. DETAILED DESCRIPTION

[0041] The terms used in the implementation section of this application are only used to explain the specific embodiments of this application and are not intended to limit this application.

[0042] First, the nouns involved in the embodiments of the present application are exemplified.

[0043] LLC converter: A series resonant converter that achieves output regulation through frequency modulation.

[0044] PSU: Power Supply Unit.

[0045] Bootstrapping: It uses electronic components such as boost diodes and capacitors to superimpose the voltage when the capacitor is discharged and the power supply voltage to increase the voltage to the target value.

[0046] Fault isolation: The faulty part is automatically disconnected from the system to prevent the fault from spreading further.

[0047] Active and standby power supply: In a multi-switch power supply parallel power supply system, one or more switch power supplies serve as the main power supply module, and the other switch power supplies serve as backup.

[0048] Cold backup: that is, offline backup. During normal operation, the backup switching power supply does not participate in load sharing, and the load is borne by the main switching power supply.

[0049] Switching power supplies are increasingly used, and high power density, high efficiency, high reliability and low cost have become the development trend of switching power supplies. LLC topology has certain advantages in efficiency and cost, and is increasingly used in switching power supplies.

[0050] The LLC topology consists of two inductive components and one capacitive component, for example Figure 1In the circuit shown, the inductor L1, the primary inductor of the transformer T and the capacitor C are connected in series to form a resonant cavity, wherein the side formed by the inductor L1, the primary inductor and the capacitor C can be called the primary side, which is used to receive the input voltage, and the secondary inductor side of the transformer T can be called the secondary side, which is used to output the voltage. The primary inductor of the transformer T specifically refers to the inductance of the primary coil of the transformer, and the secondary inductor specifically refers to the inductance of the secondary coil of the transformer T.

[0051] LLC topologies can further include: Figure 2A The full-bridge LLC topology shown, Figure 2B The resonant capacitor symmetrical half-bridge LLC topology shown, and Figure 2C The asymmetric half-bridge LLC topology shown in the figure is shown in the figure.

[0052] Combination Figure 2A to Figure 2C It can be seen that, regardless of whether the LLC topology is a full-bridge structure or a half-bridge structure, the driving circuits of the power tubes of the upper and lower bridge arms do not share a common ground. If the bus ground is used as the reference ground, the driving circuit of the power tube of the lower bridge arm (hereinafter referred to as the lower tube) shares a common ground with the reference ground, and the power supply design of the driving circuit is relatively easy to implement. However, the driving circuit of the power tube of the upper bridge arm (hereinafter referred to as the upper tube) does not share a common ground with the reference ground, and is a floating ground drive. The power supply schemes for the floating ground driving circuit of the upper tube usually include an independent isolated auxiliary source power supply scheme and a bootstrap power supply scheme. Among them, the bootstrap power supply scheme has a simple circuit and flexible wiring layout, and is more commonly used. Therefore, the LLC topology based on the floating ground driving circuit bootstrap power supply has certain advantages and is widely used.

[0053] However, the bootstrap capacitor of the floating driving circuit of the upper tube needs the lower tube to be turned on to realize bootstrap charging, that is, the bootstrap capacitor of the floating driving circuit of the upper tube can be charged only when the lower tube is turned on. Figure 3 As shown, the driving circuit 1 of the upper tube Q1 has a bootstrap capacitor C0. When the voltage of the bootstrap capacitor C0 reaches a preset voltage (the preset voltage can also be called the undervoltage recovery point of the driving circuit 1), the bootstrap capacitor C0 supplies power to the driving circuit 1 of the upper tube Q1, and the driving circuit 1 of the upper tube Q1 works normally, and outputs a driving signal to drive the upper tube Q1 to turn on or off. Figure 3 The diode connected in parallel with the upper tube Q1 is the body diode of the upper tube Q1, the capacitor connected in parallel with the upper tube Q1 is the parasitic capacitance of the upper tube Q1, the diode connected in parallel with the lower tube Q2 is the body diode of the lower tube Q2, and the capacitor connected in parallel with the lower tube Q2 is the parasitic capacitance of the lower tube Q2, which will not be elaborated here.

[0054] However, the bootstrap capacitor C0 can only be charged when the lower tube Q2 is turned on. Figure 4As shown, the driving circuit 2 of the lower tube Q2 starts to output a periodic driving signal normally. After driving the lower tube Q2 to be turned on periodically, the bootstrap capacitor C0 starts to charge when the lower tube Q2 is turned on. Based on different circuit parameters, the driving circuit 2 outputs one or more cycles ( Figure 4 After the bootstrap capacitor C0 receives the drive signal (taking 3 cycles as an example), the bootstrap capacitor C0 can be charged to the undervoltage recovery point of the drive circuit 1. At this time, the drive circuit 1 of the upper tube Q1 starts to work normally and outputs the drive signal to control the upper tube Q1 to turn on or off. Therefore, during the charging of the bootstrap capacitor, the drive circuit 1 of the upper tube Q1 cannot work normally because the voltage of the bootstrap capacitor C0 is continuously lower than the undervoltage recovery point of the drive circuit 1, and thus cannot output the drive signal to drive the upper tube Q1 to turn on, resulting in asymmetric driving of the upper and lower bridge arms and the problem of wave loss in the drive of the upper tube Q1.

[0055] The asymmetry of the upper and lower bridge arms when the drive is just starting (the upper tube drive drops the wave) makes the resonant current of the LLC topology circuit asymmetric, and the power tube cannot achieve zero voltage switching (ZVS), which will cause excessive stress on the hard switch of the power tube and reduce reliability. In addition, when the LLC topology circuit of the light-load or cold backup standby switching power supply works in intermittent mode, the lower tube is not turned on during the intermittent wave, and the upper tube bootstrap power supply voltage slowly decreases, triggering the undervoltage protection of the floating drive circuit. When the wave is generated again, the upper tube drops the wave due to the undervoltage of the bootstrap power supply. This condition will not only cause the above-mentioned hard switching loss and excessive tube stress, but also cause the output drop in the sudden load condition in the intermittent mode to be too large, resulting in reduced system power supply reliability. In addition, when the switching power supply works in the main and standby power supply scenario, when the main switching power supply fails, if the standby switching power supply works in the intermittent mode, at the moment of sudden loading, due to the undervoltage drop of the floating ground driving circuit of the upper tube in the LLC topology circuit, the standby switching power supply will not be connected in time, and the main and standby switching speed will be slow, resulting in system power failure.

[0056] In order to avoid a series of problems caused by the upper tube driver losing the wave in the first few cycles of the wave due to the undervoltage of the bootstrap power supply of the floating drive circuit, a Figure 5 A power supply control method is shown in FIG. Figure 5 As shown in the figure, before starting the LLC topology switching power supply, a driving signal is sent to the lower tube Q2 in advance, so that the lower tube Q2 is turned on for a period of time to pre-charge the bootstrap capacitor. After the voltage of the bootstrap capacitor is normal, the wave is officially started to power the electronic device. This pre-charging solution can solve a series of problems caused by the upper tube Q1 driving wave loss caused by the undervoltage of the bootstrap capacitor power supply.

[0057] However, this pre-charging solution brings new problems. Figure 6 As shown, Figure 2BTaking the resonant capacitor symmetrical half-bridge LLC topology shown in the figure as an example, during the pre-charging period, the lower tube Q2 is turned on and the Figure 6 The resonant capacitor voltage at point A discharges to a lower voltage, causing the switching power supply to start up and officially start oscillating. When drive circuit 1 and drive circuit 2 output drive signals normally, the resonant capacitor voltage discharge deviates from the midpoint voltage Vin / 2 of the input voltage Vin, causing the resonant cavity current in the first few cycles to be asymmetric, which can also cause serious hard switching and excessive power tube stress problems.

[0058] To this end, the embodiments of the present application also provide a power supply control method, a switching power supply and an electronic device to solve the problem of asymmetric driving of the upper and lower bridge arms (i.e., floating drive wave loss of the upper tube) in the LLC topology based on floating drive bootstrap power supply.

[0059] In addition, the power supply control method of the embodiment of the present application can prevent the switching power supply from having a serious problem of excessive stress caused by hard switching.

[0060] The power supply control method provided in the embodiment of the present application can be applied to a switching power supply of LLC topology based on a floating drive circuit bootstrap power supply. Figure 7 The schematic diagram is a structural diagram of a switching power supply based on LLC topology with floating drive and bootstrap power supply. Figure 2B Taking the resonant capacitor symmetrical half-bridge LLC topology as an example, the switching power supply may include:

[0061] Processor, output voltage detection circuit, drive circuit 1, drive circuit 2, bootstrap charging current limiting resistor R (hereinafter referred to as current limiting resistor R), diode D, bootstrap capacitor C0, resonant capacitor symmetrical half-bridge LLC topology circuit.

[0062] It is understood that the resonant capacitor symmetrical half-bridge LLC topology circuit is only an example and can also be replaced by Figure 2A The full-bridge LLC topology shown or Figure 2C The asymmetric LLC topology shown in the figure and other LLC topology circuits.

[0063] The current limiting resistor R, the diode D and the bootstrap capacitor C0 can form a bootstrap charging circuit. The current limiting resistor R plays a role in current limiting, and the diode D plays a role in preventing current backflow.

[0064] like Figure 7 As shown, the resonant capacitor symmetrical half-bridge LLC topology circuit includes: an upper tube Q1, a lower tube Q2, a first capacitor C1, a second capacitor C2, an inductor L1 and a transformer T, wherein:

[0065] The positive input end of the resonant capacitor symmetrical half-bridge LLC topology circuit is connected to the negative input end through the upper tube Q1 and the lower tube Q2 connected in series, and the positive input end is also connected to the negative input end through the first capacitor C1 and the second capacitor C2 connected in series. Assume that the upper tube Q1 and the lower tube Q2 are connected to each other at point B, the first capacitor C1 and the second capacitor C2 are connected to each other at point A, and point B is connected to point A through the series inductor L1 and the primary inductor of the transformer T.

[0066] Figure 7 The figure also shows the body diode and parasitic capacitance of the upper tube Q1, as well as the body diode and parasitic capacitance of the lower tube Q2, which will not be described in detail here.

[0067] Optionally, the negative input terminal of the resonant capacitor symmetrical half-bridge LLC topology circuit can be connected to the analog ground AGND.

[0068] The output voltage detection circuit is connected to the processor, and is used to detect the real-time voltage of the output voltage Vout of the switching power supply, and send the real-time voltage of the output voltage Vout to the processor. The specific circuit structure of the output voltage detection circuit is not limited in the embodiment of the present application, and can be implemented by related technologies, as long as the real-time voltage of the output voltage Vout can be detected.

[0069] The processor is connected to the first end of the driving circuit 1; the second end of the driving circuit 1 is connected to the gate of the upper tube Q1, the third end is connected to the source of the upper tube Q1, the two ends of the bootstrap capacitor C0 are respectively connected to the third end and the fourth end of the driving circuit 1, and one end of the bootstrap capacitor C0 connected to the third end of the driving circuit 1 is also connected to the voltage supply end VCC through a diode D and a current limiting resistor R. The processor can output a driving signal of the upper tube Q1 to the first end of the driving circuit 1, and the driving circuit 1 can amplify the power of the driving signal and output it to the gate of the upper tube Q1 through the third end to control the on and off of the upper tube Q1.

[0070] The processor is also connected to the first end of the driving circuit 2, and the second end of the driving circuit 2 is connected to the gate of the lower tube Q2. The processor can output the driving signal of the lower tube Q2 to the first end of the driving circuit 2, and the driving circuit 2 can amplify the power of the driving signal and output it to the gate of the lower tube Q2 through the second end to control the on and off of the lower tube Q2.

[0071] When the lower tube Q2 is turned on, when the branch formed by the voltage supply terminal VCC, the current limiting resistor R, the diode D, the bootstrap capacitor C0 and the lower tube Q2 is turned on, the voltage supply terminal VCC can charge the bootstrap capacitor C0.

[0072] when Figure 7When the switching power supply shown is set in an electronic device, the processor of the switching power supply can be connected to the processor of the electronic device, the input terminal Vin of the switching power supply can be connected to the power output terminal of the electronic device, such as a plug, and the output terminal Vout of the switching power supply can power the devices in the electronic device. Figure 7 The voltage of 400V received by the input end of the switching power supply is only an example, and the embodiment of the present application does not limit the specific value of the voltage received by the input end of the switching power supply.

[0073] In some embodiments, the power supply control method provided in the embodiments of the present application can be specifically executed by a processor in the switching power supply.

[0074] In a power supply control method provided in the present application, after the switching power supply input is powered on, it is determined when the first wave is transmitted, that is, after the switching power supply input is powered on, when the first external power supply is triggered, in other words, the processor determines to output the driving signal to the driving circuit 1 and the driving circuit 2 respectively for the first time to drive the upper tube Q1 and the lower tube Q2 to work, so that when the output end of the switching power supply supplies power to the outside, the processor first outputs a continuous high-frequency narrow pulse signal with a duration of T1 to the driving circuit 2 of the lower tube Q2, and then outputs the driving signal to the driving circuit 1 and the driving circuit 2 respectively to drive the upper tube Q1 and the lower tube Q2 to work respectively.

[0075] The power supply control method comprises:

[0076] Step S1: When determining to transmit the first wave, output a first continuous high-frequency narrow pulse signal with a duration of T1 to the driving circuit 2.

[0077] The first continuous high-frequency narrow pulse signal with a duration of T1 is output to the driving circuit 2 to make the lower tube Q2 turn on briefly multiple times to charge the bootstrap capacitor C0, so that the voltage of the bootstrap capacitor C0 increases to reach or exceed the undervoltage recovery point of the driving circuit 1. The undervoltage recovery point of the driving circuit 1 refers to the minimum supply voltage at which the driving circuit 1 can work normally.

[0078] The above duration T1 refers to the overall duration of the first continuous high-frequency narrow pulse signal. For the realization of the first continuous high-frequency narrow pulse signal, please refer to Fig. 8A , I won’t go into details here.

[0079] The specific value of the width t1 of each pulse in the above-mentioned first continuous high-frequency narrow pulse signal is related to the switching performance of the lower tube Q2. In some embodiments, the width t1 of each pulse is greater than or equal to the end-to-end maximum hardware delay of the entire drive link (from the processor to the lower tube Q2) of the lower tube Q2, so that each pulse in the first continuous high-frequency narrow pulse signal can normally drive the lower tube Q2 to switch from off to on, and then from on to off, to ensure the normal operation of the lower tube Q2.

[0080] The specific value of the width t1 of each pulse in the above-mentioned first continuous high-frequency narrow pulse signal is also related to the hardware circuit filtering time of the driving circuit. In some embodiments, the width t1 of each pulse is greater than or equal to the hardware circuit filtering time of the driving circuit 2, thereby preventing the first continuous high-frequency narrow pulse signal from being unable to be transmitted to the lower tube Q2 through the driving circuit 2 to drive the lower tube Q2 to work.

[0081] The value of the duration T1 of the first continuous high-frequency narrow pulse signal is related to the capacity of the bootstrap capacitor C0. Under the condition that other parameters of the first continuous high-frequency narrow pulse signal (such as frequency and pulse width) are constant, the larger the capacity of the bootstrap capacitor C0 is, the longer the duration T1 of the first continuous high-frequency narrow pulse signal is, and the smaller the capacity of the bootstrap capacitor C0 is, the shorter the duration T1 of the first continuous high-frequency narrow pulse signal is. In some embodiments, under the condition that other parameters of the first continuous high-frequency narrow pulse signal are constant, the duration T1 of the first continuous high-frequency narrow pulse signal is greater than or equal to the minimum duration for charging the voltage of the bootstrap capacitor C0 from 0V to the undervoltage recovery point of the drive circuit 1.

[0082] It should be noted that the first continuous high-frequency narrow pulse signal and the subsequent second continuous high-frequency narrow pulse signal in the embodiment of the present application are both continuous high-frequency narrow pulse signals, and the first and second are only used to distinguish continuous high-frequency narrow pulse signals.

[0083] Step S2: After the first continuous high-frequency narrow pulse signal ends, drive signal 1 is output to drive circuit 1, and drive signal 2 is output to drive circuit 2.

[0084] The above-mentioned drive signal 1 is used to drive the upper tube Q1 to be turned on and off (switch), and the above-mentioned drive signal 2 is used to drive the lower tube Q2 to be turned on and off. The implementation of the drive signal 1 and the drive signal 2 can refer to the implementation of the drive signal in the related art, which will not be repeated here.

[0085] Optionally, the phases of the driving signal 1 and the driving signal 2 are opposite. It should be noted that the dead time of the driving circuit is not considered here.

[0086] Optionally, the first effective driving signal of the driving signal 1 is earlier than the first effective driving signal of the driving signal 2. The above-mentioned effective driving signal refers to the signal in the driving signal that drives the switch tube to turn on. For example, if the high-level signal in the driving signal can drive the upper tube Q1 and the lower tube Q2 to turn on, the effective driving signal is the high-level signal in the driving signal, and the first high-level signal of the driving signal 1 is earlier than the first high-level signal of the driving signal 2. In other words, the first rising edge of the driving signal 1 is higher than the first rising edge of the driving signal 2. By outputting the driving signal 1 and the driving signal 2 with the above-mentioned characteristics, the upper tube Q1 can be turned on earlier than the lower tube Q2, thereby reducing the discharge of the resonant capacitor voltage caused by the turning on of the lower tube Q2, and further reducing the deviation between the voltage at point A and the midpoint voltage Vin / 2.

[0087] Fig. 8A It is a signal timing diagram provided in an embodiment of the present application, including the signal output by the processor to the drive circuit 1 and the drive circuit 2, the signal output by the drive circuit 1, the signal output by the drive circuit 2, the output voltage Vout of the switching power supply, and the voltage of the bootstrap capacitor C0.

[0088] Combination Figure 7 The switching power supply structure shown in Fig. 8A In the signal timing diagram shown, stage 1 represents the period after the switching power supply input is powered on and before the processor determines to transmit the wave for the first time. In this stage, the switching power supply is in a state of not supplying power to the outside (such as a device in an electronic device), that is, the processor does not output a driving signal to the driving circuit 1 and the driving circuit 2. At this time, it can also be considered that the processor outputs a continuous low-level signal to the driving circuit 1 and the driving circuit 2. In this stage, since the lower tube Q2 is not conducting, the voltage of the bootstrap capacitor C0 is continuously 0. In this stage, the switching power supply does not output a voltage, that is, the output voltage Vout is 0.

[0089] Phase 2 means that after the processor determines to send a wave and before outputting a driving signal to driving circuit 1 and driving circuit 2, Fig. 8A As shown, when the processor determines to send a wave, the processor outputs a first continuous high-frequency narrow pulse signal with a duration of T1 to the drive circuit 2, and the processor keeps not outputting a drive signal to the drive circuit 1. At this time, it can be considered that the processor outputs a low-level signal to the drive signal 2. At this stage, the first continuous high-frequency narrow pulse signal output by the processor to the drive circuit 2 is amplified by the drive circuit 2 and output to the gate of the lower tube Q2, so that the lower tube Q2 can be turned on briefly repeatedly, and the bootstrap capacitor C0 can be charged when the lower tube Q2 is briefly turned on. After a period of time T1, it can be charged to reach or exceed the undervoltage recovery point of the above-mentioned drive circuit 1. At this stage, the switching power supply does not output voltage, and the output voltage Vout is 0.

[0090] In stage 3, after the processor outputs the first continuous high-frequency narrow pulse signal to the driving circuit 2, the processor outputs the driving signal 1 to the driving circuit 1 to drive the upper tube Q1 to work normally after the driving circuit 1 performs power amplification, and the processor outputs the driving signal 2 to the driving circuit 2 to drive the lower tube Q2 to work normally after the driving circuit 2 performs power amplification. In this stage, since the bootstrap capacitor C0 has been pre-charged to a value not less than the undervoltage recovery point of the driving circuit 1, the driving circuit 1 can work normally, so that all the received driving signals 1 can be power-amplified and output to the gate of the upper tube Q1 without wave loss; and since the lower tube Q2 is turned on, the bootstrap capacitor C0 can keep the voltage above the undervoltage recovery point of the driving circuit 1. See Fig. 8A , if the voltage of the bootstrap capacitor C0 does not reach the target voltage V2 in the previous stage 2, the bootstrap capacitor C0 can be charged to the target voltage V1 under the condition of sufficient time in this stage, and the target voltage V2 can be less than the saturation voltage of the bootstrap capacitor C0. In this stage, the output voltage Vout of the switching power supply gradually increases to a preset voltage to supply power to the outside. Optionally, the target voltage V2 of the bootstrap capacitor C0 can be the voltage of the bootstrap capacitor C0 when the switching power supply is in continuous mode.

[0091] It is understandable that the signal timing diagram in the embodiment of the present application is only used for explanation of the principle, and other practical factors such as circuit delay are not considered. Therefore, it is not used to limit the possible signal timing of the circuit in practical applications. For example, in practical applications, when the processor outputs a high-frequency narrow pulse signal to the down tube Q2 through the driving circuit 2, the voltage growth curve of the bootstrap capacitor C0 may not be Fig. 8A The smooth curve shown in Fig. 8A It is only used to illustrate that the voltage variation trend of the bootstrap capacitor C0 in this stage is gradually increasing.

[0092] Based on the above analysis, see Figure 8B As shown, after the processor determines to send a wave and before outputting a driving signal to the driving circuit 1 and the driving circuit 2, a first continuous high-frequency narrow pulse signal with a duration of T1 is first output to the driving circuit 2, and the voltage of the bootstrap capacitor C0 can be charged to a value not less than the undervoltage recovery point of the driving circuit 1, to ensure that the bootstrap capacitor C0 can power the driving circuit 1, so that the driving circuit 1 can work normally, and then when the driving signal is output to the driving circuit 1 and the driving circuit 2, the driving circuit 1 and the driving circuit 2 can work normally, thereby solving the problem of asymmetric driving of the upper and lower bridge arms (that is, upper tube drive wave loss) in the LLC topology based on floating drive bootstrap power supply.

[0093] In addition, see Figure 8B As shown, when the first continuous high-frequency narrow pulse signal briefly turns on the lower tube Q2, there is still a problem of resonant capacitor discharge. Fig. 9AThe charging voltage curve of the bootstrap capacitor C0 and the discharging voltage curve of the resonant capacitor are compared as shown in the figure. Fig. 9B As shown in the comparison diagram of the bootstrap capacitor charging current curve and the resonant capacitor discharging current curve, although the bootstrap capacitor C0 is charged and the resonant capacitor is discharged during the conduction period of the lower tube Q2, the charging voltage of the bootstrap capacitor C0 changes very quickly in the early stage of the conduction of the lower tube Q2, while the resonant capacitor discharge voltage changes slowly in the early stage of the conduction of the lower tube Q2. Therefore, the first continuous high-frequency narrow pulse signal is used to drive the lower tube Q2 to turn on and supply power to the bootstrap capacitor C0. When the frequency is increased, the equivalent inductive reactance of the resonant inductor L1 can be increased, thereby reducing the discharge current of the resonant capacitor, and then reducing the resonant capacitor discharge speed during the charging period of the bootstrap capacitor C0. Therefore, the resonant capacitor voltage at point A will not be discharged to a lower voltage, in other words, it will not deviate too much from the midpoint voltage Vin / 2 of the input voltage Vin, so relative to Figure 5 The bootstrap capacitor pre-charging method shown in the figure continuously outputs a high-level signal to the driving circuit 2. The embodiment of the present application outputs a first continuous high-frequency narrow pulse signal to the driving circuit. While realizing the pre-charging of the bootstrap capacitor C0, the resonant capacitor voltage at point A will not be discharged to a lower voltage. In other words, it will not deviate too much from the midpoint voltage Vin / 2 of the input voltage Vin. Therefore, when the processor normally outputs the driving signal through the driving circuit 1 and the driving circuit 2, there will be no serious asymmetry problem of the resonant cavity current in the first few cycles, and there will be no serious problem of excessive stress and over-specification of the power tube caused by hard switching.

[0094] The embodiment of the present application also provides another power supply control method, which can implement power supply control of the switching power supply when the switching power supply is in a burst mode.

[0095] In one embodiment, in intermittent mode, if the output voltage of the switching power supply drops to a preset first voltage threshold VL, the processor outputs a driving signal to the driving circuit 1 and the driving circuit 2 respectively, driving the upper tube Q1 and the lower tube Q2 to work, so that the output voltage of the switching power supply gradually increases. When it increases to a preset second voltage threshold VH, the processor stops outputting driving signals to the driving circuit 1 and the driving circuit 2 respectively until the output voltage of the switching power supply drops to the preset first voltage threshold VL again. The processor outputs driving signals to the driving circuit 1 and the driving circuit 2 respectively again, and repeats this process so that the output voltage of the switching power supply is always maintained at not less than the preset first voltage threshold VL and not higher than the preset second voltage threshold VH.

[0096] However, when the output voltage of the switching power supply rises to the preset second voltage threshold VH and the processor stops outputting drive signals to the drive circuit 1 and the drive circuit 2 respectively, because the drive circuit 1 has a very small circuit loss, the voltage of the bootstrap capacitor C0 will gradually decrease, and even decrease to below the undervoltage recovery point of the above-mentioned drive circuit 1. Therefore, when the output voltage of the switching power supply decreases to the preset first voltage threshold VL again, the processor again outputs drive signals to the drive circuit 1 and the drive circuit 2 respectively, and the following may occur: Figure 4 The problem of wave loss in the driving circuit 1 of the upper tube Q1 is shown.

[0097] To this end, in the power supply control method provided in the embodiment of the present application, when the switching power supply is in intermittent mode and the processor stops outputting drive signals to the drive circuit 1 and the drive circuit 2, the processor can periodically output a second continuous high-frequency narrow pulse signal with a duration of T2 to the drive circuit 2, so that the voltage of the charging capacitor C0 is always maintained above the undervoltage recovery point of the drive circuit 1, thereby solving the problem of possible wave loss in the drive circuit 1 of the upper tube Q1.

[0098] In one embodiment, the power supply control method is as follows: Fig. 10A As shown, including:

[0099] Step 101: When the switching power supply is in intermittent mode and does not output drive signal 1 to drive circuit 1 and does not output drive signal 2 to drive circuit 2, a second continuous high-frequency narrow pulse signal with a duration of T2 is periodically output to drive circuit 2.

[0100] Optionally, T2 is greater than or equal to the time it takes for the voltage of the bootstrap capacitor to reach the target voltage from the undervoltage recovery point of the drive circuit 1 when the second high-frequency narrow pulse signal is output to the drive circuit 2 .

[0101] Optionally, the specific value of the target voltage of the bootstrap capacitor is not limited in the embodiment of the present application, and the target voltage of the bootstrap capacitor is less than the saturation voltage of the bootstrap capacitor.

[0102] Optionally, the time interval T0 between the end moment of the previous second continuous high-frequency narrow pulse signal with a duration of T2 and the start moment of the next second continuous high-frequency narrow pulse signal with a duration of T2 is less than or equal to the time it takes for the bootstrap capacitor C0 to drop from the target voltage to the undervoltage recovery point of the drive circuit 1 when the drive circuit 2 is not working (the lower tube Q2 is not turned on).

[0103] The specific value of the width t2 of each pulse in the above-mentioned second continuous high-frequency narrow pulse signal is related to the switching performance of the lower tube Q2. In some embodiments, the width t2 of each pulse is greater than or equal to the end-to-end maximum hardware delay of the entire drive link (from the processor to the lower tube Q2) of the lower tube Q2, so that each pulse in the second continuous high-frequency narrow pulse signal can normally drive the lower tube Q2 to switch from off to on, and then from on to off, to ensure the normal operation of the lower tube Q2.

[0104] The specific value of the width t2 of each pulse in the above-mentioned second continuous high-frequency narrow pulse signal is also related to the hardware circuit filtering time of the driving circuit. In some embodiments, the width t2 of each pulse is greater than or equal to the hardware circuit filtering time of the driving circuit 2, thereby preventing the second continuous high-frequency narrow pulse signal from being unable to be transmitted to the lower tube Q2 through the driving circuit 2 to drive the lower tube Q2 to work.

[0105] Step 102 : Determine that the output voltage is lower than the first voltage threshold and that the second continuous high-frequency narrow pulse signal is not being output to the drive circuit 2 , output the drive signal 1 to the drive circuit 1 , and output the drive signal 2 to the drive circuit 2 .

[0106] It can be understood that after the processor stops outputting drive signal 1 to drive circuit 1 and stops outputting drive signal 2 to drive circuit 2, the real-time output voltage of the switching power supply can be obtained periodically or continuously from the output voltage detection circuit to determine whether the real-time output voltage is lower than the preset first voltage threshold VL, until it is determined that the real-time output voltage address is the preset first voltage threshold VL, triggering the execution of step 103.

[0107] Optionally, the reasons causing the output voltage to drop to the first voltage threshold may include but are not limited to: the load at the output end of the switching power supply consumes electrical energy, causing the output voltage of the switching power supply to gradually decrease until it reaches the first voltage threshold; or, the load at the output end of the switching power supply increases, but the overload condition is not reached, at which time the switching power supply is still in intermittent mode.

[0108] The implementation of the driving signal 1 and the driving signal 2 in this step can refer to the relevant description of step S2, which will not be repeated here.

[0109] Step 103 : Determine that the output voltage reaches the second voltage threshold, stop outputting drive signal 1 to drive circuit 1 , and stop outputting drive signal 2 to drive circuit 2 .

[0110] After step 103 , the processor may return to step 101 and restart the step of periodically outputting a second continuous high-frequency narrow pulse signal having a duration of T2 to the driving circuit 2 .

[0111] Combination Fig. 10BThe signal timing diagram shown takes the switching power supply entering the intermittent mode as an example, assuming that the output voltage of the switching power supply is the second voltage threshold VH, and the voltage of the bootstrap capacitor C0 is the target voltage Vds;

[0112] In stage 1, after the switching power supply enters the intermittent mode for a period of time T0, the output voltage of the switching power supply gradually decreases, and the voltage of the bootstrap capacitor C0 also gradually decreases to a point close to the undervoltage recovery point Vbo of the drive circuit 1, and the processor does not output a drive signal to the drive circuit 1 and the drive circuit 2;

[0113] In stage 2, the processor outputs a second continuous high-frequency narrow pulse signal with a duration of T2 to the drive circuit 2, and keeps not outputting a drive signal to the drive circuit 1. The voltage of the bootstrap capacitor C0 is pulled up to the target voltage Vds. In this stage, the output voltage of the switching power supply is still gradually decreasing, but has not dropped to the first voltage threshold VL.

[0114] In stage 3, the duration of this stage is T0. During this stage, the processor stops outputting the second continuous high-frequency narrow pulse signal to the driving circuit 2, and does not output a driving signal to the driving circuit 1 and the driving circuit 2; the output voltage of the switching power supply gradually decreases, but does not fall to the first voltage threshold VL; the voltage of the bootstrap capacitor C0 gradually decreases again to a point close to the undervoltage recovery point Vbo of the driving circuit 1.

[0115] In stage 4, the processor outputs a second continuous high-frequency narrow pulse signal with a duration of T2 to the drive circuit 2, and keeps not outputting a drive signal to the drive circuit 1. The voltage of the bootstrap capacitor C0 is pulled up to the target voltage Vds. In this stage, the output voltage of the switching power supply is still gradually decreasing, but has not dropped to the first voltage threshold VL.

[0116] In stage 5, the duration of this stage is less than T0. During this stage, the processor stops outputting the second continuous high-frequency narrow pulse signal to the driving circuit 2, and does not output the driving signal to the driving circuit 1 and the driving circuit 2; the output voltage of the switching power supply gradually decreases, and finally drops to the first voltage threshold VL; the voltage of the bootstrap capacitor C0 gradually decreases, but is still higher than the undervoltage recovery point Vbo of the driving circuit 1.

[0117] In stage 6, since the output voltage of the switching power supply is as low as the first voltage threshold VL, the processor continues to output drive signal 1 to drive circuit 1 and continues to output drive signal 2 to drive circuit 2 until the output voltage of the switching power supply reaches the second voltage threshold VH.

[0118] Taking the high level signal as an effective driving signal as an example, the first effective driving signal of the driving signal 1 is earlier than the first effective driving signal of the driving signal 2 .

[0119] It is understood that if the switching power supply is still in intermittent mode at the end of stage 6, a similar operation can be repeated. Fig. 10B or Fig. 11B The signal timing shown is that when the processor does not output drive signal 1 to drive circuit 1 and does not output drive signal 2 to drive circuit 2, a second continuous high-frequency narrow pulse signal with a duration of T2 is periodically output to drive circuit 2 so that the voltage of bootstrap capacitor C0 is not lower than the undervoltage recovery point of drive circuit 1.

[0120] Understandable, Fig. 10B In the signal timing diagram shown, when the switching power supply is in intermittent mode and the processor stops outputting drive signals to drive circuit 1 and drive circuit 2, the processor outputs the second continuous high-frequency narrow pulse signal with a duration of T2 to drive circuit 2 twice, which is only an example. The above number of times can be reduced to 1 time, 0 times, or increased to 3 times or more. The specific number of times depends on the specific time from the time the processor stops outputting drive signals to drive circuit 1 and drive circuit 2 until the output voltage drops to the first voltage threshold.

[0121] Fig. 10B Taking the example that when the processor detects that the output voltage is lower than the first voltage threshold, the processor does not output the second continuous high-frequency narrow pulse signal to the driving circuit 2, in another embodiment provided in the present application, taking the example that when the processor detects that the output voltage is lower than the first voltage threshold, the processor is outputting the second continuous high-frequency narrow pulse signal to the driving circuit 2. Fig.11A As shown, the power supply control method is Fig. 10A The main difference of the control method shown is that step 102 is replaced by step S111.

[0122] Step 111: Determine that the output voltage is lower than the first voltage threshold and that a second continuous high-frequency narrow pulse signal is being output to drive circuit 2, stop outputting the second continuous high-frequency narrow pulse signal to drive circuit 2, output drive signal 1 to drive circuit 1, and output drive signal 2 to drive circuit 2.

[0123] The implementation of the driving signal 1 and the driving signal 2 in this step can refer to the relevant description of step S2, which will not be repeated here.

[0124] Combination Fig. 11B The signal timing diagram shown takes the switching power supply entering the intermittent mode as an example, assuming that the output voltage of the switching power supply is the second voltage threshold VH, and the voltage of the bootstrap capacitor C0 is the target voltage Vds;

[0125] In stage 1, after the switching power supply enters the intermittent mode for a period of time T0, the output voltage of the switching power supply gradually decreases, and the voltage of the bootstrap capacitor C0 also gradually decreases to a point close to the undervoltage recovery point Vbo of the drive circuit 1, and the processor does not output a drive signal to the drive circuit 1 and the drive circuit 2;

[0126] In stage 2, the processor outputs a second continuous high-frequency narrow pulse signal with a duration of T2 to the drive circuit 2, and keeps not outputting a drive signal to the drive circuit 1. The voltage of the bootstrap capacitor C0 is pulled up to the target voltage Vds. In this stage, the output voltage of the switching power supply is still gradually decreasing, but has not dropped to the first voltage threshold VL.

[0127] In stage 3, the duration of this stage is T0. During this stage, the processor stops outputting the second continuous high-frequency narrow pulse signal to the driving circuit 2, and does not output a driving signal to the driving circuit 1 and the driving circuit 2; the output voltage of the switching power supply gradually decreases, but does not fall to the first voltage threshold VL; the voltage of the bootstrap capacitor C0 gradually decreases again to a point close to the undervoltage recovery point Vbo of the driving circuit 1.

[0128] In stage 4, the processor outputs a second continuous high-frequency narrow pulse signal to the drive circuit 2, and keeps not outputting a drive signal to the drive circuit 1. During the T3 duration when the processor outputs the second continuous high-frequency narrow pulse signal to the drive circuit 2, the voltage of the bootstrap capacitor C0 is pulled up but does not reach the target voltage Vds. In this stage, the output voltage of the switching power supply is still gradually decreasing and eventually drops to the first voltage threshold VL.

[0129] In stage 5, since the output voltage is as low as the first voltage threshold VL, the processor stops outputting the second continuous high-frequency narrow pulse signal to the drive circuit 2, outputs the drive signal 1 to the drive circuit 1, and outputs the drive signal 2 to the drive circuit 2, until the output voltage of the switching power supply reaches the second voltage threshold VH. In this stage, the voltage of the bootstrap capacitor C0 is pulled up to the target voltage Vds.

[0130] Taking the high level signal as an effective driving signal as an example, the first effective driving signal of the driving signal 1 is earlier than the first effective driving signal of the driving signal 2 .

[0131] It is understood that if the switching power supply is still in intermittent mode at the end of stage 5, a similar operation can be repeated. Fig. 10B or Fig. 11B The signal timing shown is that when the processor does not output drive signal 1 to drive circuit 1 and does not output drive signal 2 to drive circuit 2, a second continuous high-frequency narrow pulse signal with a duration of T2 is periodically output to drive circuit 2 so that the voltage of bootstrap capacitor C0 is not lower than the undervoltage recovery point of drive circuit 1.

[0132] Fig. 10A and Fig.11A In the example, the switching power supply is in intermittent mode. In other embodiments provided in the present application, Fig. 10A Step 1032, Fig.11AThe trigger condition in step 111 in can be replaced by determining that the output voltage is lower than the first voltage threshold value to: the switching power supply switches from intermittent mode to continuous mode. When the load at the output end of the switching power supply changes from a light load to a heavy load, the switching power supply can switch from intermittent mode to continuous mode. The embodiment of the present application does not limit how the processor specifically determines that the load changes from a light load to a heavy load. For example, in one example, an output voltage feedback signal can be provided in the switching power supply, and the switching frequency of the LLC is automatically closed-loop adjusted according to the output voltage feedback signal. When the load is reduced, the switching frequency is increased accordingly. When the LLC switching frequency reaches a preset maximum switching frequency, if the load continues to be reduced, the intermittent mode is entered. In the intermittent mode, if the load increases, the LLC switching frequency determined according to the output voltage feedback signal is not higher than the preset switching frequency maximum threshold, then the intermittent mode can be switched to the continuous mode.

[0133] The power supply control method of the embodiment of the present application is described below through specific examples.

[0134] Example 1

[0135] A certain telecommunication equipment adopts a non-redundant power supply design, with a single switching power supply or multiple switching power supplies in parallel. Each switching power supply can be implemented based on the LLC topology, for example Figure 7 As shown in the figure, the load at the power supply output changes with the system task of the telecommunication equipment. In order to improve the light load efficiency of the switching power supply, the switching power supply works in intermittent mode when the load is light and in continuous mode when the load is heavy.

[0136] When or after the telecommunication equipment is started, the switch power supply is triggered to start and power the components of the telecommunication equipment. At this time, the Fig. 8A In the method shown, before the processor of the switching power supply transmits the driving signals to the driving circuit 1 and the driving circuit 2 respectively, the first continuous high-frequency narrow pulse signal with a duration of T1 is first transmitted to the driving circuit 2 of the lower tube Q2, thereby avoiding the problem of wave loss of the driving circuit 1 of the upper tube Q1, and preventing the problem of excessive hard switching stress of the power tube caused by the asymmetry of the resonant cavity current when the discharge of the resonant capacitor seriously deviates from the midpoint.

[0137] When the switching power supply works in intermittent mode, it can perform Fig. 10A and / or Fig.11AIn the power supply control method shown, during the period when the processor stops outputting drive signals to the drive circuit 1 and the drive circuit 2, the processor can periodically output a second continuous high-frequency narrow pulse signal with a duration of T2 to the drive circuit 2, so that the voltage of the bootstrap capacitor of the switching power supply is always maintained above the undervoltage recovery point of the drive circuit 1, so that when the output voltage of the switching power supply is lowered to the first voltage threshold VL due to the energy consumption of the load or the sudden increase of the load, the processor transmits drive signals to the drive circuit 1 and the drive circuit 2 respectively, and the drive circuit 1 of the upper tube Q1 does not have the problem of wave loss, thereby solving the problem of untimely output response caused by wave loss of the drive circuit 1 of the upper tube Q1; and preventing the problem of excessive hard switch stress of the power tube caused by the asymmetry of the resonant cavity current when the discharge of the resonant capacitor seriously deviates from the midpoint.

[0138] In addition, when the switching power supply operates in intermittent mode, it can perform Fig. 10A and / or Fig.11A In the power supply control method shown, during the period when the processor stops outputting drive signals to the drive circuit 1 and the drive circuit 2, the processor can periodically output a second continuous high-frequency narrow pulse signal with a duration of T2 to the drive circuit 2, so that the voltage of the charging capacitor of the switching power supply is always maintained above the undervoltage recovery point of the drive circuit 1, so that when the load at the output end of the switching power supply suddenly changes from a light load to a heavy load, and the working mode of the switching power supply changes from an intermittent mode to a continuous mode, when the processor transmits drive signals to the drive circuit 1 and the drive circuit 2 respectively, the drive circuit 1 of the upper tube Q1 will not have a wave loss problem; and, the problem of excessive hard switch stress of the power tube caused by the asymmetry of the resonant cavity current when the discharge of the resonant capacitor seriously deviates from the midpoint is prevented.

[0139] Optionally, when the processor outputs driving signals to driving circuit 1 and driving circuit 2, the first valid driving signal output to driving circuit 1 is earlier than the first valid driving signal output to driving circuit 2, thereby better preventing the problem of excessive hard switching stress of the power tube caused by the asymmetry of the resonant cavity current when the discharge of the resonant capacitor deviates seriously from the midpoint.

[0140] Moreover, during the period when the processor stops outputting driving signals to driving circuit 1 and driving circuit 2, the driving circuit 2 of the lower tube Q2 periodically outputs a second continuous high-frequency narrow pulse signal with a duration of T2, which can improve the stress (including thermal stress and voltage stress) of the power tube, avoid the problem of excessive stress on the power tube caused by hard switching, and improve the power supply efficiency and reliability of the switching power supply.

[0141] Optionally, when the processor changes from intermittent mode to continuous mode because the output voltage is lower than the first voltage threshold VL in intermittent mode or because the load becomes heavy load, the priority of the processor outputting the drive signal to drive circuit 1 and drive circuit 2 is higher than the priority of outputting the second continuous high-frequency narrow pulse signal. In other words, the processor outputting the second continuous high-frequency narrow pulse signal to drive circuit 2 can be interrupted at any time. That is, when the processor outputs the second continuous high-frequency narrow pulse signal to drive circuit 2, if the processor determines to output the drive signal to drive circuit 1 and drive circuit 2, the processor can stop outputting the second continuous high-frequency narrow pulse signal to drive circuit 2, and then output the drive signal to drive circuit 1 and drive circuit 2 to improve the response speed of the switching power supply.

[0142] Example 2:

[0143] A certain telecommunication equipment adopts a redundant power supply design scheme, which is equipped with at least two parallel switching power supplies. The switching power supplies can be implemented based on LLC topology, for example Figure 7 As shown. The load at the power supply output changes with the system task of the telecommunication equipment. To improve the light-load efficiency of the switching power supply, the switching power supply operates in intermittent mode when light-loaded and in continuous mode when heavy-loaded. At least two parallel switching power supplies operate in hot backup mode, which is also load-sharing mode.

[0144] In this example, when or after the telecommunication equipment is started, the switching power supply is triggered to start and power is supplied to the devices of the telecommunication equipment. The power supply control method when the switching power supply is operating in intermittent mode and the power supply control method when the switching power supply changes from intermittent mode to continuous mode because the load changes from light load to heavy load can be realized by referring to Example 1 and will not be described in detail here.

[0145] When the switching power supply works in intermittent mode, it can perform Fig. 10A and / or Fig.11AIn the power supply control method shown, during the period when the processor stops outputting drive signals to the drive circuit 1 and the drive circuit 2, the processor can periodically output a second continuous high-frequency narrow pulse signal with a duration of T2 to the drive circuit 2, so that the voltage of the charging capacitor of the switching power supply is always maintained above the undervoltage recovery point of the drive circuit 1, so that when some power supplies of multiple switching power supplies of the telecommunication equipment are suddenly isolated (the failed switching power supply automatically disconnects from the power supply system without affecting the operation of other switching power supplies), and the number of failed switch units is not greater than the number of redundant switching power supplies, when the output voltage of the switching power supply that has not failed drops to the first voltage threshold VL due to a sudden increase in load, or when the input is in continuous mode due to an increase in load to a heavy load, when the processor transmits drive signals to the drive circuit 1 and the drive circuit 2 respectively, the drive circuit 1 of the upper tube Q1 will not have a problem of untimely output response due to wave loss; and the problem of excessive hard switch stress of the power tube caused by asymmetric current in the resonant cavity when the discharge of the resonant capacitor seriously deviates from the midpoint is prevented.

[0146] Example 3

[0147] A certain telecommunication equipment adopts a redundant power supply design solution and is equipped with at least two switching power supplies. The switching power supplies can be implemented based on LLC topology, for example Figure 7 As shown. The load at the power output changes with the system tasks of the telecommunication equipment. To improve the light-load efficiency of the switching power supply, the switching power supply operates in intermittent mode when light-loaded and in continuous mode when heavy-loaded. At least two switching power supplies operate in cold backup mode, that is, offline backup, the main switching power supply supplies power to the load, and the backup switching power supply does not supply power to the load.

[0148] In this example, when or after the telecommunication equipment is started, the main switch power supply is triggered to start and power is supplied to the devices of the telecommunication equipment. The power supply control method when the main switch power supply operates in intermittent mode is implemented. The power supply control method when the main switch power supply switches from intermittent mode to continuous mode because the load changes from light load to heavy load can be referred to in Example 1 and will not be described in detail here.

[0149] After the telecommunication equipment is started, the standby switching power supply can work in the intermittent mode. During the period when the processor of the standby switching power supply stops outputting driving signals to its own driving circuit 1 and driving circuit 2, the processor of the standby switching power supply can periodically output a second continuous high-frequency narrow pulse signal with a duration of T2 to the driving circuit 2 of the standby switching power supply, so that the voltage of the charging capacitor of the standby switching power supply is always maintained above the undervoltage recovery point of the driving circuit 1. Therefore, if the main switching power supply fails and stops supplying power to the load (the device of the telecommunication equipment), the standby switching power supply takes over. For the standby switching power supply, it is equivalent to a sudden load in the no-load state. When the output voltage of the processor of the standby switching power supply drops to the first voltage threshold VL due to a sudden increase in load, or the input continuous mode is caused by an increase in load to a heavy load, the processor can immediately transmit driving signals to the driving circuit 1 and the driving circuit 2 respectively, and the driving circuit 1 of the upper tube Q1 will not have the problem of untimely output response due to wave loss; and the problem of excessive hard switching stress of the power tube caused by asymmetric current in the resonant cavity when the discharge of the resonant capacitor seriously deviates from the midpoint is prevented.

[0150] The power supply control method of the embodiment of the present application can be applied to various scenarios such as powering on and starting the switching power supply, remote power on and off, sleep restart, cold backup to hot backup, intermittent mode, etc. It can also be applied to light load, low voltage output, standby, standby and other states in the intermittent mode. By outputting a continuous high-frequency narrow pulse signal before the first wave transmission, or periodically outputting a continuous high-frequency narrow pulse signal during the drive interruption, the voltage of the bootstrap capacitor of the switching power supply is not lower than the undervoltage recovery point of the drive circuit 1, so as to solve the problem of wave loss that may occur in the drive circuit 1 of the upper tube Q1, and further solve the problem of untimely output response caused by wave loss of the drive circuit 1 of the upper tube Q1, and prevent the problem of excessive hard switch stress of the power tube caused by the asymmetry of the resonant cavity current when the discharge of the resonant capacitor deviates seriously from the midpoint.

[0151] In another power supply control method provided in an embodiment of the present application, Fig.12 As shown, it may include:

[0152] Step 121: When the switching power supply is in intermittent mode and does not output drive signal 1 to drive circuit 1 and does not output drive signal 2 to drive circuit 2, the real-time voltage of the bootstrap capacitor C0 is obtained, and when the real-time voltage of the bootstrap capacitor is lower than the undervoltage recovery point of the drive circuit 1, a third continuous high-frequency narrow pulse signal with a duration of T3 is output to the drive circuit 2.

[0153] Optionally, T3 is greater than or equal to the time taken for the voltage of the bootstrap capacitor to reach the target voltage from the undervoltage recovery point of the drive circuit 1 when the third continuous high-frequency narrow pulse signal is output to the drive circuit 2 .

[0154] The specific value of the width t3 of each pulse in the third continuous high-frequency narrow pulse signal is related to the switching performance of the lower tube Q2. In some embodiments, the width t3 of each pulse is greater than or equal to the end-to-end maximum hardware delay of the entire drive link (from the processor to the lower tube Q2) of the lower tube Q2, so that each pulse in the third continuous high-frequency narrow pulse signal can normally drive the lower tube Q2 to switch from off to on, and then from on to off, to ensure the normal operation of the lower tube Q2.

[0155] The specific value of the width t3 of each pulse in the third continuous high-frequency narrow pulse signal is also related to the hardware circuit filtering time of the driving circuit. In some embodiments, the width t3 of each pulse is greater than or equal to the hardware circuit filtering time of the driving circuit 2, thereby preventing the third continuous high-frequency narrow pulse signal from being unable to be transmitted to the lower tube Q2 through the driving circuit 2 to drive the lower tube Q2 to work.

[0156] Optionally, a voltage detection circuit of the bootstrap capacitor C0 may be provided in the switching power supply to detect the real-time voltage of the bootstrap capacitor C0, so that the processor can obtain the real-time voltage of the bootstrap capacitor C0 from the voltage detection circuit of the bootstrap capacitor C0.

[0157] Step 122 : When it is determined that the output voltage is lower than the first voltage threshold and the third continuous high-frequency narrow pulse signal is not being output to the driving circuit 2 , the driving signal 1 is output to the driving circuit 1 , and the driving signal 2 is output to the driving circuit 2 .

[0158] Step 123 : Determine that the output voltage reaches the second voltage threshold, stop outputting drive signal 1 to drive circuit 1 , and stop outputting drive signal 2 to drive circuit 2 .

[0159] At this time, the processor can re-execute step 121, thereby ensuring that the voltage of the bootstrap capacitor C0 is not lower than the undervoltage recovery point of the drive circuit 1 when the switching power supply is in intermittent mode and does not output the drive signal 1 to the drive circuit 1 and does not output the drive signal 2 to the drive circuit 2.

[0160] In another power supply control method provided in an embodiment of the present application, Fig.13 As shown, it may include:

[0161] Step 131: When the switching power supply is in intermittent mode and does not output drive signal 1 to drive circuit 1 and does not output drive signal 2 to drive circuit 2, the real-time voltage of the bootstrap capacitor C0 is obtained, and when the voltage of the bootstrap capacitor is lower than the undervoltage recovery point of the drive circuit 1, a third continuous high-frequency narrow pulse signal with a duration of T3 is output to the drive circuit 2.

[0162] Step 132: When it is determined that the output voltage is lower than the first voltage threshold and the third continuous high-frequency narrow pulse signal is being output to the driving circuit 2, stop outputting the third continuous high-frequency narrow pulse signal to the driving circuit 2, output the driving signal 1 to the driving circuit 1, and output the driving signal 2 to the driving circuit 2.

[0163] Step 133 : Determine that the output voltage reaches the second voltage threshold, stop outputting drive signal 1 to drive circuit 1 , and stop outputting drive signal 2 to drive circuit 2 .

[0164] At this time, the processor can re-execute step 131, thereby ensuring that the voltage of the bootstrap capacitor C0 is not lower than the undervoltage recovery point of the drive circuit 1 when the switching power supply is in intermittent mode and does not output the drive signal 1 to the drive circuit 1 and does not output the drive signal 2 to the drive circuit 2.

[0165] Fig.12 and Fig.13 The specific application scenarios of the power supply control method of the embodiment of the present application can refer to the above-mentioned examples 1 to 3, which will not be repeated here.

[0166] Optionally, Fig.12 The step 122 and the step 132 of determining that the output voltage is lower than the first voltage threshold may be replaced by: the switching power supply is switched from the intermittent mode to the continuous mode. Specific descriptions and examples may refer to the above embodiments, which will not be repeated here.

[0167] An embodiment of the present application provides a switching power supply, including: a processor, used to execute the method provided by the embodiment of the present application.

[0168] An embodiment of the present application also provides an electronic device, including the switching power supply shown in the above embodiment.

[0169] The embodiment of the present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer-readable storage medium is run on a computer, the computer executes the method provided by the embodiment of the present application.

[0170] The embodiment of the present application also provides a computer program product, which includes a computer program. When the computer program is run on a computer, it enables the computer to execute the method provided by the embodiment of the present application.

[0171] In the embodiments of the present application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. Among them, A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can be represented by: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, c can be single or multiple.

[0172] Those of ordinary skill in the art will appreciate that the various units and algorithm steps described in the embodiments disclosed herein can be implemented in a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0173] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0174] In several embodiments provided in the present application, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory; hereinafter referred to as: ROM), random access memory (Random Access Memory; hereinafter referred to as: RAM), disk or optical disk, and other media that can store program codes.

[0175] The above is only a specific implementation of the present application. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. The protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A power supply control method, characterized in that: The method is applied to a switching power supply, which is implemented based on an LLC topology structure of a floating drive circuit bootstrap power supply. The switching power supply includes: a first power tube, a second power tube, a first drive circuit, a second drive circuit, and a bootstrap capacitor. The first power tube and the second power tube are connected in series between a first voltage input terminal and a second voltage input terminal of the switching power supply. The first drive circuit connects the two ends of the bootstrap capacitor, and the first drive circuit connects the first end and the control end of the first power tube. The first end of the first power tube is an end connected to the second power tube. The power supply control method includes: When the switching power supply starts supplying power for the first time after being powered on, a first continuous high-frequency narrow pulse signal with a preset first duration is output to the second driving circuit; After the output of the first continuous high-frequency narrow pulse signal is completed, a first drive signal is output to the first drive circuit, and a second drive signal is output to the second drive circuit. The first drive signal is used to control the on and off of the first power tube, and the second drive signal is used to control the on and off of the second power tube.

2. The method according to claim 1, characterized in that The preset first time duration is greater than or equal to a second time duration, and the second time duration is the time duration for the voltage of the bootstrap capacitor to increase from 0V to a preset first voltage when a first continuous high-frequency narrow pulse signal is output to the second drive circuit.

3. The method according to claim 1, characterized in that The first driving signal and the second driving signal are in opposite phases, and a first valid driving signal of the first driving signal is earlier than a first valid driving signal of the second driving signal.

4. The method according to any one of claims 1 to 3, characterized in that: Also includes: When the switching power supply is in intermittent mode and stops outputting the first drive signal to the first drive circuit and stops outputting the second drive signal to the second drive circuit, a second continuous high-frequency narrow pulse signal of a preset third duration is periodically output to the second drive circuit.

5. The method according to claim 4, characterized in that The time interval between the end moment of the second continuous high-frequency narrow pulse signal of the previous third time period and the start moment of the second continuous high-frequency narrow pulse signal of the next third time period is less than or equal to the time it takes for the bootstrap capacitor to drop from the target voltage to the preset first voltage when the second drive circuit is not working, and the first voltage is the minimum supply voltage for the first drive circuit to work normally.

6. The method according to claim 4, characterized in that The third time duration is greater than or equal to a fourth time duration, and the fourth time duration is the time duration for the voltage of the bootstrap capacitor to increase from the preset first voltage to the target voltage when a second continuous high-frequency narrow pulse signal is output to the second drive circuit.

7. The method according to claim 4, characterized in that Also includes: When it is determined that the output voltage of the switching power supply is lower than a preset third voltage and a second continuous high-frequency narrow pulse signal is being output to the second drive circuit, the second continuous high-frequency narrow pulse signal being output to the second drive circuit is stopped, and a first drive signal is output to the first drive circuit and a second drive signal is output to the second drive circuit.

8. The method according to claim 4, characterized in that Also includes: When it is determined that the switching power supply is converted from intermittent mode to continuous mode and is outputting a second continuous high-frequency narrow pulse signal to the second drive circuit, the second continuous high-frequency narrow pulse signal being output to the second drive circuit is stopped, and the first drive signal is output to the first drive circuit and the second drive signal is output to the second drive circuit.

9. The method according to any one of claims 1 to 3, characterized in that: Also includes: When the switching power supply is in intermittent mode and stops outputting the first drive signal to the first drive circuit and stops outputting the second drive signal to the second drive circuit, the real-time voltage of the bootstrap capacitor is obtained. When the real-time voltage of the bootstrap capacitor is lower than a preset second voltage, a third continuous high-frequency narrow pulse signal with a preset fifth duration is output to the second drive circuit.

10. A switching power supply, characterized in that: The switching power supply is implemented based on an LLC topology structure with bootstrap power supply based on a floating drive circuit. The switching power supply includes: a first power tube, a second power tube, a first drive circuit, a second drive circuit and a bootstrap capacitor. The first power tube and the second power tube are connected in series between a first voltage input terminal and a second voltage input terminal of the switching power supply. The first drive circuit connects the two ends of the bootstrap capacitor. In addition, the first drive circuit connects the first end and the control end of the first power tube. The first end of the first power tube is an end connected to the second power tube. The switching power supply also includes a processor. The processor is used to execute the method described in any one of claims 1 to 9.

11. An electronic device, characterized in that: A switching power supply comprising the switching power supply as claimed in claim 10.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which, when executed on a computer, enables the computer to execute the method according to any one of claims 1 to 9.

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