Transfer printing for radio frequency applications

Abstract

The invention relates to transfer printing for radio frequency applications. A semiconductor structure for amplifying an RF signal includes a cascode structure including a [mu] TP GaN transistor on an SOI wafer or die.

Description

Description of the case

[0001] This application is a divisional application of the invention patent application with application date of May 12, 2020, application number 202010400269.4, and invention name “Transfer printing for radio frequency applications”. Technical Field

[0002] The present invention relates to transfer printing for RF applications, and more particularly to micro transfer printing of GaN components onto SOI wafers. Background Art

[0003] GaN is a relatively new technology compared to other semiconductors such as Si and GaAs, but GaN has become the technology of choice for high RF, high power applications such as those required to send signals over long distances or at high-end power levels. GaN transistors offer high power density, high operating temperature, improved efficiency, low on-resistance, and can operate in different frequency bands from 1 GHz to 110 GHz. Figure 1 A schematic diagram of a cross section of a GaN transistor 2 is shown. A GaN layer 4 is formed on a high resistivity (HR) silicon substrate 6 and an AlGaN buffer layer 8. A heavily doped n++ region 10 of GaN is connected to metal contacts 12 (drain and source). A gate 14 is isolated from the GaN layer 4 by a thin AlN layer 16.

[0004] GaN on SiC combines the high power density capabilities of GaN with the excellent thermal conductivity and low RF losses of SiC (Silicon Carbide). GaN on SiC is the combination of choice for high power density RF performance.

[0005] GaN-on-Si has much worse thermal performance and higher RF losses, but is cheaper. GaN-on-Si is a combination of choice for price-sensitive power electronics applications.

[0006] Silicon-on-insulator (SOI) technology is used in semiconductor manufacturing, especially microelectronics, to reduce parasitic capacitance by having a layered silicon-insulator-silicon substrate structure instead of bulk Si. SOI CMOS offers lower power consumption for analog and digital RF hybrid circuits in the design of low-power RF transceivers due to its low leakage capability.

[0007] To achieve some of the advantages of both GaN and SOI in high-power applications, attempts have been made to grow GaN on SOI by isolating GaN transistors using trench etching. Careful strain engineering techniques are required to control the stress accumulated in the wafer during growth.

[0008] Alternatively, GaN devices can be transferred from an original / source wafer to a target SOI wafer using micro-transfer printing [1]. In this process, the GaN device is separated / lifted from the native wafer on which the GaN device was grown and then reattached to the SOI wafer.

[0009] [1] R. Lener, and others "Heterogeneous Integration of Microscale GalliumNitride Transistors by Micro-Transfer-Printing". 2016 IEEE 66th Electronic Components and Technology Conference, pp. 1186-1189. Summary of the invention

[0010] Aspects of the invention provide a semiconductor structure and a method of manufacturing for RF applications as set out in the accompanying claims.

[0011] Preferred embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic cross section of a GaN transistor on a silicon substrate;

[0013] Figure 2a is a schematic diagram of a monolithic hybrid switch branch according to an embodiment;

[0014] Figure 2b is a schematic cross-sectional view of a semiconductor structure having a GaN transistor micro-transfer printed onto an SOI wafer according to an embodiment;

[0015] Figure 3a shows a layout of a SPDT (single pole double throw) switch using a hybrid branch according to an embodiment;

[0016] Figure 3b shows a layout of a SPDT using pure GaN branches according to an embodiment;

[0017] Figure 4 is a circuit diagram of a semiconductor structure according to an embodiment;

[0018] Figure 5 is a circuit diagram of a semiconductor structure according to another embodiment;

[0019] Figure 6 is a circuit diagram of a semiconductor structure according to another embodiment;

[0020] Figure 7is a circuit diagram of a SPDT switch according to an embodiment;

[0021] Figure 8 is a circuit diagram of a SPDT switch according to another embodiment;

[0022] Fig. 9 is a circuit diagram of a SPDT switch with hybrid switch branches according to an embodiment;

[0023] Fig.10 is a circuit diagram of a SPDT switch with hybrid switch branches according to another embodiment;

[0024] Fig.11 shows a schematic diagram of an amplification unit according to an embodiment;

[0025] Fig.12 is a circuit diagram including a low noise amplifier (LNA) according to an embodiment;

[0026] Fig.13 shows a graph of 2-port S-parameters of a simulated LNA plotted against frequency according to an embodiment;

[0027] Fig.14 shows a simulated noise figure (NF) on the left and a K factor on the right of an LNA plotted against frequency according to an embodiment;

[0028] Fig.15 shows upper and lower OIP3 as a function of the center frequency of the LNA according to an embodiment;

[0029] Fig.16 is a circuit diagram of a semiconductor structure according to an embodiment;

[0030] Fig.17 is a circuit diagram of a semiconductor structure according to another embodiment;

[0031] Fig.18 is a circuit diagram of an LNA having a common source and common gate structure according to an embodiment;

[0032] Fig.19 is a schematic diagram of a two-stage amplifier according to an embodiment;

[0033] Fig.20a is the electrical schematic diagram of a two-stage amplifier;

[0034] Fig.20b is an electrical schematic diagram of a two-stage amplifier using a micro-transfer printed GaN transistor for the second stage according to an embodiment;

[0035] Fig.21 is a circuit diagram of an LNA using micro-transfer printed GaN transistors according to an embodiment;

[0036] Fig. 22 is a circuit diagram of a two-stage LNA using micro-transfer printed GaN transistors for the second stage according to an embodiment;

[0037] Fig.23 is a circuit diagram of a two-stage LNA using micro-transfer printed GaN transistors for the first and second stages according to another embodiment;

[0038] Fig.24 is a circuit diagram of an N-stage LNA using micro-transfer printed GaN transistors according to an embodiment; and

[0039] Fig.25 is a circuit diagram of an N-stage LNA using an SOI cascode structure and micro-transfer printed GaN transistors according to another embodiment. DETAILED DESCRIPTION

[0040] Nowadays, more and more applications require high linearity, high power handling, low noise figure and low power consumption. Since these requirements are in most cases contradictory, they are difficult to achieve in MMIC (monolithic microwave integrated circuit) circuits. Therefore, system-in-package (SiP) technology is usually used to encapsulate several integrated circuits from several technologies into a single module in order to benefit from the best of each of them. The dies are then connected together using bonding wires or bumps. This SiP technology allows system-level integration of several dies / technologies.

[0041] The embodiments described herein allow monolithic integration of GaN and SOI technologies via micro-transfer printing. CMOS devices as well as high electron mobility transistors (HEMTs) are fabricated separately in their process environments and can have different wafer diameters. The idea would be to design most of the circuit on SOI technology and print only some HEMTs on top of the SOI wafer to enhance the overall RF circuit performance.

[0042] The technology has the advantage of having monolithic circuits, which results in smaller, cheaper, and less complex circuits than packaged systems. In addition to reducing complexity and cost, this heterogeneous design approach allows for better control of parasitic elements and performance. Another advantage is related to the performance of GaN transistors. Existing GaN-on-silicon technology has poor vertical isolation. Micro-transfer printing can significantly reduce this vertical leakage, thereby increasing the breakdown voltage of the HEMT.

[0043] This heterogeneous design approach can combine the best of GaN and SOI. Therefore, it is possible to achieve good noise figure (NF), good isolation and very high power handling capability with high integration in a single chip.

[0044] Base station applications require switches to handle high powers ranging from a few watts (W) to over 100W. A practical switch solution is obtained using PIN diodes that can handle high powers. The main disadvantage is that their static power consumption reduces the overall energy efficiency of the system. Compared with MOS transistors, GaN transistors show high power handling, low static power consumption (mainly due to gate leakage) and good linearity, so GaN transistors can be a serious competitor.

[0045] On the other hand, SOI is the leading technology for switching applications. SOI MOS transistors are characterized by low RonxCoff (R on xC off , the switch's key figure of merit (FOM)) provides very good low-power performance. SOI is a cost-effective technology for RF systems-on-chip (SOC) for applications up to 10 GHz, without significant performance loss, and also reduces crosstalk. To achieve such performance, it is necessary to use advanced SOI technology with low voltage maintenance, which is the only disadvantage of this technology. The power handling capability can be enhanced by stacking multiple transistors, but is limited by the saturation effect of the stacked transistors: Zhu, Y., Klimashov, O., and Bartle, D. (November 2014). “Analytical model of voltagedivision inside stacked-FET switch”. In 2014 Asia-Pacific Microwave Conference (pp. 750-752). IEEE.

[0046] According to an embodiment, GaN micro transfer printing (μTP) on SOI wafer enables a monolithic design with shorter interconnects, which prevents losses and transitions between the chip and the substrate. Interconnects are provided directly between two stacked chips using metal (e.g., thick copper), also known as a redistribution layer (RDL). When micro transfer printing is performed, one or more small chips, each containing one or more GaN devices, are lifted from the native silicon substrate and placed on the SOI wafer.

[0047] The embodiments described herein can overcome the bottlenecks of SOI and GaN technologies by combining SOI and GaN technologies using micro-printing technology. In one embodiment, at least some of the existing problems are solved by hybrid branches. The hybrid branches consist of one or several stacked GaN p-Hemt (high electron mobility transistor) and stacked SOI MOS devices.

[0048] Figure 2aA schematic diagram of a monolithic hybrid switch branch 18 is shown. The branch 18 has two or more stacked SOI MOS transistors 20 connected in series with two or more stacked GaN p-Hemts 22. The stacked SOI transistors 20 are controlled by an SOI gate control network 24, while the stacked GaN transistors are controlled by a GaN gate control network 26. In this configuration, Coff is driven by the minimum value (SOI transistor) and Ron is determined by the maximum value (GaN transistor). A compromise can be selected when sizing the two transistors to achieve the specified isolation, return loss, and insertion loss. The second parameter to consider is the voltage distribution across the transistors. In the off state, the GaN impedance is much lower than the impedance of the MOS transistor. In the off state, a large MOS transistor must be used to match the GaN impedance. This combination of GaN and SOI technology can provide enhanced low-power performance compared to GaN alone, and can provide improved high-power handling compared to SOI alone.

[0049] Figure 2b 2 is a schematic cross-sectional view of a semiconductor structure with a GaN transistor 22 micro-transfer printed onto an SOI wafer 23. The GaN transistor 22 is connected to the top metal 25 of the SOI 23 through a thick copper RDL 27.

[0050] Figure 3a shows a top view of the layout of a GaN and SOI hybrid design 30, and Figure 3b A similar top view of a design 32 using only a GaN p-Hemt (still micro-printed on the SOI wafer) is shown for comparison. Both layouts represent single-pole double-throw (SPDT) switches. The design operates over a frequency band from DC to 6GHz. The required power handling is 47dBm and the size is optimized for lowest insertion loss at 6GHz. A thick copper layer 34 on top connects the GaN transistor to the SOI component.

[0051] The simulated performance of the two SPDT designs is shown in Table 1. These performances were achieved at the chip level, without de-embedding applied. The interconnects were simulated using Keysight’s Momentum EM simulator, while the transistors were considered either as an electrical model of a GaN transistor or as an extracted view of a SOI transistor. The hybrid combination showed better performance over all considered operating bandwidths, except for return loss. Isolation was enhanced by 5 dB on average.

[0052] Table 1 – Simulated Performance of SPDT Design

[0053]

[0054] Figures 4 to 9A circuit diagram of an embodiment described herein is shown. Similar or corresponding features of the embodiments in different drawings have been given the same reference numerals to aid understanding. Figure 4 A μTP (i.e., micro-transfer printed) GaN transistor 40 (i.e., a GaN transistor micro-printed on an SOI wafer) is shown, wherein a resistor 42 is connected to the gate of the transistor 40. The resistor 42 is formed on the SOI and / or μTP GaN chiplet. After micro-printing, the resistor formed on the SOI wafer can be connected to the GaN transistor 40 through a thick copper redistribution layer (RDL).

[0055] Figure 5 Two μTP GaN transistors 40 are shown connected in series. Both transistors 40 are connected to their corresponding resistors 42 on the SOI wafer / die (“die” refers to the diced chip after dicing the wafer). Each resistor 42 can have the same or different resistance. The two transistors 40 are preferably transferred to the SOI wafer in the same process step. Connecting two or more GaN transistors in series in a switch branch on the SOI wafer / die can improve the switching performance by increasing the maximum voltage that can be handled. Each μTP GaN transistor 40 should be able to handle a peak voltage of about 50V. Ideally, the two transistors in series will support an RF voltage of 100V, which corresponds to 50dBm / 100W (with a 50Ω load). It can be beneficial to have some margin in power handling, so one or several other transistors can be added in series to reduce the drain-to-source voltage on the first two transistors. The power handling can be increased by stacking more GaN transistors.

[0056] Figure 6 A μTP GaN transistor 40 is shown in series with one or more SOI transistors 44. The gate of the GaN transistor 40 is connected to a resistor 42, and the gate and body of the SOI transistor are connected to its respective resistor 42. The resistor 42 connected to the SOI transistor 44 is made on SOI. The resistor 42 connected to the GaN transistor 40 can be made in GaN or SOI. The GaN transistor 40 can be connected to the SOI resistor 42 and the SOI transistor 44 through thick copper RDL.

[0057] Figure 7 A circuit diagram of a SPDT switch 46 according to an embodiment is shown. Two switch branches 48 and 50 are connected to RF port 1 52 and RF port 2 54 respectively and an antenna 56. Each branch comprises three μTP GaN transistors 40 connected in series.

[0058] All gates are connected to a resistor 42 in parallel with a diode 58. The purpose of the resistor 42 is to avoid any RF leakage from the drain or source to the gate and to have a floating RF node at the gate so that the gate power level moves in sync with the drain or source. The purpose of the diode 58 is to provide a path for the μTP GaN gate DC current. Without this diode 58, the DC gate current will produce a voltage drop across the gate resistor Rg, and the voltage actually applied to the gate will be a DC bias modified by this voltage drop. This can be a problem in the off state where the DC gate current is not negligible. The gate voltage can be significantly modified by this voltage drop, so the transistor 40 will be less open than expected.

[0059] All gates are biased using bias block 60 which provides a negative voltage to turn off the switch. The μTP GaN switch is normally ON, so applying ground on the gate is sufficient to turn on the μTP GaN switch. A switch driver 62 is used to pass the right DC voltage on the right gate. Other architectures may have 1, 3 or 4 arms / branches etc. connected to the corresponding RF ports.

[0060] Figure 8 Shows something like Figure 7 , but with only two μTP GaN transistors 40 in each switch branch 48 and 50. Each gate of the transistors 40 is connected to a resistor 42 in parallel with a diode 58.

[0061] Fig. 9 A circuit diagram of a SPDT switch 46 is shown with hybrid branches 64 and 66. Each branch includes a μTPGaN transistor 40 and a stacked SOI transistor 44. A second bias block 68 and switch driver 70 are used to control the SOI transistor 44, although in other embodiments a single bias block and switch driver may be used to control all GaN transistors 40 and SOI transistors 44. Fig.10 A similar circuit diagram of a SPDT switch 46 is shown, but in which two μTP GaN transistors 40 are connected in series in each branch 64 and 66 .

[0062] although Figures 7 to 10 Each of the 10 ...

[0063] One embodiment includes a low noise amplifier (LNA) using heterogeneous integration of GaN technology and SOI technology to enhance the linearity of the circuit.

[0064] Fig.11 A cell 74 for amplifying RF signals that may be used in an LNA according to an embodiment is shown. The cell 74 comprises a common source SOI nMOS transistor 76 in series with a common gate micro-printed GaN HEMT 78 forming a cascode structure (having a common source transistor directly in series with a common gate transistor).

[0065] The advantage of this topology is that the use of discrete GaN HEMTs improves the overall linearity of SOI technology. These μTP GaN transistors are able to handle large supply voltages, which is the main disadvantage of silicon-based transistors. This enables the structure to produce greater output power, resulting in greater IP3 (FOM used to characterize the linearity of the LNA). In addition, the GaN HEMTs are used as cascodes because the IP3 of a system consisting of n cascaded stages is imposed by the last stage, as shown in Equation 1.

[0066] #timg# （1）

[0067] For these reasons, using GaN as the cascode transistors will improve LNA linearity performance (OIP3, output third-order intercept point) compared to using an all-SOI LNA.

[0068] Another reason for using such a heterogeneous cell 74 is to provide low continuous power consumption compared to pure GaN designs. SOI technology provides low leakage and low current MOS transistors, which are particularly advantageous for this application.

[0069] Fig.12 An LNA design 80 is shown. The LNA design 80 uses a degenerate LNA architecture including unit 74, wherein Fig.11 The cell 74 of the SOI transistor 76 and μTP GaN transistor 78 shown is used as an amplifier cell. The different passive and active parts are implemented on a PCB 84, either formed on SOI 82 (i.e., native SOI component) or micro-printed (i.e., μTP GaN transistor 78). The SOI chip can be flip-chipped on the PCB for characterization.

[0070] The LNA can meet the 5G NR (sub-6GHz) standard. The operating frequency band is 5.9GHz to 7.1GHz and corresponds to the US unlicensed band. The supply voltage is set to 5.5V and corresponds to the typical base station voltage. The common source transistor gate voltage is set to achieve an IP3 specification of 28dBm across the entire band. The common gate bias voltage is then adjusted so that the nMOS drain voltage is set to 1.2V, which is its typical value.

[0071] The circuit was simulated, and the S parameter simulation results are as follows Fig.13 As shown, NF 86 and K factor 88 are Fig.14 The continuous power consumption is 165mW. The input and output are well matched to 50Ω in the band. The amplifier exhibits a maximum gain of 16.6dB in the band and a minimum isolation of -26dB. The amplifier is unconditionally stable up to 10GHz. The NF is below 1.7dB in the band with a minimum value of 1.24dB at 6.8GHz.

[0072] OIP3 simulation results are as follows Fig.15 The power of the two input fundamental tones was set to -30dBm with a 1MHz tone separation. From 6.35GHz all the way to 7.1GHz, both the upper OIP3 90 and lower OIP3 92 were above 28dBm. At 6.8GHz, the maximum OIP3 was 30.6dBm.

[0073] All performance and specifications are summarized in Table 2 and are given at 6.5 GHz (located in the middle of the band).

[0074] Table 2 – Summary of DC, Small Signal (SP), and Noise (NF) Performance

[0075]

[0076] Table 3 compares the LNA design to existing products. The performance is comparable, except that the power consumption is reduced by 1 / 3 compared to Analog and 1 / 5 compared to Qorvo[3]. The size of the chip is not representative as this chip is a demonstrator.

[0077] Table 3 – Comparison with existing devices

[0078]

[0079] Table 3 continued

[0080]

[0081] [2] HMC982A-Die: GaAs MMIC Low Noise Amplifier, 3.5-7.0GHz Datasheet, https: / / www.analog.com / en / products / hmc392a-die.html#product-documentation

[0082] [3] Preliminary product data sheet TGA2611 2-6GHz GaN LNA, https: / / www.qorvo.com / products / p / TGA2611

[0083] Micro-printing technology enables different technologies to be integrated together at the die level, which can improve circuit performance while keeping the circuit area small.

[0084] Fig.16 A cell 94 for an LNA or PA is shown with two μTP GaN p-Hemts 96 connected in series on a SOI wafer / die. The μTP GaN transistors can be on the same chiplet or on separate chiplets. Fig.17 A cell 94 with a μTP GaN p-Hemt 96 for an LNA is shown with an inductor 98 connected to the source of the μTP GaN p-Hemt 96. The inductor 98 is formed on a SOI wafer and connected to the GaN HEMT using RDL.

[0085] Fig.18 A circuit diagram of an LNA design 80 is shown including a cascode cell 74 comprising an SOI transistor 76 in series with a μTP GaN p-Hemt 78 and a linearizer 100 between the two transistors to improve linearity. A diode in series with a capacitor and in parallel with a resistor allows a nonlinear current to be generated at the third order intermodulation frequency to cancel the MOS drain component at the same frequency. The linearizer 100 is formed on an SOI wafer.

[0086] Another LNA design for meeting the 5G mmWave standard is described. Fig.19 As shown, two stages 102 and 104 are designed using cascade. When n stages are cascaded, the IP3 of the entire system is imposed by the last stage, as shown in Equation 1.

[0087] Therefore, using GaN for the second stage LNA 104 will improve the LNA linearity performance (IIP3 and CP1) compared to using an all SOI LNA.For the first stage 102, SOI transistors may be used to benefit from their good noise performance.

[0088] To evaluate the advantages of using GaN in the second stage, two circuits at 28 GHz were designed:

[0089] •The first to use SOI architecture throughout the first and second levels.

[0090] •For the second design, GaN transistors were used in the second stage.

[0091] The schematic diagrams of the two LNAs are shown in Fig.20a and 20b In Fig.20a In FIG. 1 , two stages 106 and 108 mounted in a common source and common gate configuration are cascaded for use in the entire SOI circuit. Fig.20bIn the heterogeneous LNA in FIG. 1 , the first stage 110 is in a cascode configuration. Since the nominal drain-source voltage for the GaN transistor 112 should be higher than that for the SOI transistor, the second stage 114 is designed using a common source architecture. The purpose is to use the same power supply as the first stage 110.

[0092] The simulated DC, small signal (SP), and noise (NF) performance of the two LNA versions are summarized in Table 4. The performance between the two versions is similar, and both meet the specifications (i.e., 5G standard requirements).

[0093] Table 4 – DC, small signal (SP) and noise (NF) performance of the two LNA versions

[0094]

[0095] Two figures of merit are used to quantify the linearity of a circuit:

[0096] • Input compression point CP1.

[0097] • Enter the third intercept point IP3.

[0098] Using GaN transistors 112 in the second stage 114 improves these parameters by almost 10 dB. The simulated CP1 for the heterogeneous solution is about -13 dBm, while the full SOI LNA is -21 dBm. Regarding IP3, simulations show 6 dBm for the heterogeneous LNA and -10 dBm for the full SOI version.

[0099] The LNA designed using micro-printed GaN transistors has been benchmarked against other LNAs designed using different technologies (CMOS and SiGe) that exhibit high integration capabilities. As shown in Table 5, the LNA described in this article exhibits higher linearity due to the use of GaN on SOI transistors with comparable performance in other parameters.

[0100] Table 5 – LNA reference

[0101]

[0102] [4] J.Luo, and others "A 28 GHz LNA using defected ground structure for 5Gapplication". Microw Opt Technol Lett. 2018:60:1067-1318.

[0103] [5] M. Elkholy, and others "A Wideband Variable Gain LNA With High OIP3 for5G Using 40-nm Bulk CMOS". 2017 IEEE MICROWAVE AND WIRELESS COMPONENTSLETTERS.

[0104] [6] E. Adabi, B. Heydari, M. Bohsali, and A. M. Niknejad, “30 GHz CMOS lownoise amplifier”, in Proc. IEEE Radio Freq. Integr. Circuits (RFIC) Symp., June 2007, pp. 625–628.

[0105] [7] Q. Ma, DMW Leenaerts, and PGM Baltus, “Silicon-basedtruetime-delay phased-array front-ends at Ka-band,” IEEE Trans. Microw., Volume 63, No. 9, Pages 2942–2952, September 2015.

[0106] Fig.21 A circuit diagram of an LNA 116 according to an embodiment is shown. The LNA 116 includes a μTP GaN transistor 112 on SOI connected to other SOI components. The source of the GaN transistor is connected to an inductor 118 formed on the SOI wafer.

[0107] Fig. 22 A circuit diagram of a two-stage amplifier 120 is shown, including two connected LNAs 116 and 122. The first LNA 122 (first stage) includes two SOI transistors 124 in a common source and common gate structure, and the second LNA 116 (second stage) includes a μTP GaN transistor 112 with a common source. The second LNA 116 is equivalent to Fig.21 A single bias block 126 formed on the SOI wafer is used to power both stages 116 and 122. Both stages 116 and 122 preferably use the same power supply.

[0108] Fig.23 A circuit diagram of another two-stage amplifier 120 comprising two connected LNAs 116 on a SOI wafer / die is shown. The two LNAs comprise respective common-source μTP GaN transistors 112.

[0109] Fig.24 A circuit diagram of an N-stage amplifier 124 (having N>2 amplifier stages) according to an embodiment is shown. Three LNAs 116a, 116b, 116c are shown, and the dashed lines between the output of the second LNA 116b and the input of the third LNA 116c indicate any number of further LNAs connected therebetween. Each amplifier stage may be formed by one LNA, e.g. Fig.21 Each LNA includes a μTP GaN transistor 112. Each LNA 116a, b, c can be powered by the same power supply or a different power supply. The bias block 126 and other components of the circuit are formed directly on the SOI wafer.

[0110] Fig.25 Shows something like Fig.24 1 is a circuit diagram of an N-stage amplifier, but the first stage includes an SOI cascode structure 122 having an SOI transistor 124.

[0111] Although specific embodiments of the present invention have been described above, it should be understood that the present invention may be practiced in a manner other than that described. The above description is intended to be illustrative rather than limiting. It will be apparent to those skilled in the art that the invention may be modified without departing from the scope of the above claims.

[0112] Each and every feature disclosed or shown in this specification may be included in the present invention either alone or in any suitable combination with any other features disclosed or shown herein.

[0113] The invention may be defined by any of the following numbered clauses, which correspond to the claims of the parent application as filed:

[0114] 1. A semiconductor structure for radio frequency applications, comprising:

[0115] a first μTP GaN transistor on a SOI wafer or die; and

[0116] A first resistor is connected to the gate of the first transistor.

[0117] 2. The semiconductor structure according to clause 1, further comprising:

[0118] a second μTP GaN transistor on the SOI wafer or die; and

[0119] A second resistor is connected to the gate of the second transistor.

[0120] 3. The semiconductor structure according to clause 1, further comprising:

[0121] an SOI transistor formed on the SOI wafer in series with the first μTP GaN transistor;

[0122] a second resistor connected to the gate of the SOI transistor; and

[0123] A third resistor is connected to the body of the SOI transistor.

[0124] 4. The semiconductor structure of clause 1, 2 or 3, further comprising: two or more stacked SOI transistors formed on the SOI wafer in series with the first μTP GaN transistor.

[0125] 5. The semiconductor structure according to clause 1, further comprising:

[0126] a first switch branch comprising one or more μTP GaN transistors on the SOI wafer, and the first switch branch is connected to a first RF port;

[0127] A second switch branch includes one or more μTP GaN transistors on the SOI wafer or die and the second switch branch is connected to a second RF port, wherein each μTP GaN transistor in the first switch branch and the second switch branch has a gate connected to a corresponding resistor.

[0128] 6. The semiconductor structure of clause 5, wherein the first switch branch and the second switch branch each comprise three μTP GaN transistors.

[0129] 7. The semiconductor structure of clause 5, wherein each respective resistor is connected in parallel with a diode.

[0130] 8. The semiconductor structure of clause 5, wherein the μTP GaN transistor in the first switch branch and / or the μTP GaN transistor in the second switch branch are on the same chiplet.

[0131] 9. The semiconductor structure of clause 5, further comprising:

[0132] a switch driver formed on the SOI wafer and connected to the first switch branch and the second switch branch;

[0133] Bias block, connected to the switch driver.

[0134] 10. The semiconductor structure of clause 5, wherein the first switch branch and the second switch branch each comprise a stacked SOI transistor connected in series with the one or more μTP GaN transistors.

[0135] 11. The semiconductor structure of clause 10, further comprising a second switch driver and a second bias block formed on the SOI wafer for controlling the stacked SOI transistors.

[0136] 12. The semiconductor structure of clause 1, wherein the structure is a SPDT switch.

[0137] 13. A semiconductor structure according to any of clauses 5 to 11, further comprising one or more further switch branches, wherein the or each further switch branch comprises one or more μTP GaN transistors on the SOI wafer or die.

[0138] 14. The semiconductor structure of clause 13, wherein the structure is an N-pole, M-throw, NPMT switch.

[0139] 15. A semiconductor structure for amplifying an RF signal, comprising:

[0140] Cascode structures, including μTP GaN transistors on a SOI wafer or die.

[0141] 16. The semiconductor structure of clause 15, wherein the cascode structure further comprises a SOI transistor formed on the SOI wafer and connected to the μTP GaN transistor.

[0142] 17. The semiconductor structure of clause 15, wherein the cascode structure further comprises a second μTP GaN transistor on the SOI wafer or die and connected to the μTP GaN transistor.

[0143] 18. The semiconductor structure of clause 15, further comprising an inductor connected to a source of the μTP GaN transistor.

[0144] 19. The semiconductor structure of any of clauses 15 to 18, further comprising a linearizer formed on the SOI wafer.

[0145] 20. A semiconductor structure for amplifying an RF signal, comprising:

[0146] A first LNA on the SOI wafer; and

[0147] A second LNA is on the SOI wafer and connected to the first LNA, wherein the second LNA includes μTP GaN transistors.

[0148] 21. The semiconductor structure of clause 20, wherein the first LNA comprises a cascode structure including a first transistor and a second transistor connected in series.

[0149] 22. The semiconductor structure of clause 21, wherein the first transistor and / or the second transistor is a SOI transistor formed on the SOI wafer.

[0150] 23. The semiconductor structure of clause 22, wherein the first LNA comprises a μTP GaN transistor.

[0151] 24. A semiconductor structure according to clause 20, further comprising one or more further LNAs connected together on the SOI wafer to, in use, amplify an RF signal applied to the first LNA.

[0152] 25. A semiconductor structure according to any of clauses 20 to 24, wherein the first LNA and the second LNA are powered by the same power supply.

[0153] 26. A method of manufacturing a structure according to clause 1, 15 or 20 using a micro transfer printing process.

Claims

1. A semiconductor structure for amplifying an RF signal, comprising: Cascode structures, including μTP GaN transistors on a SOI wafer or die.

2. The semiconductor structure according to claim 1, wherein: The cascode structure also includes an SOI transistor formed on the SOI wafer and connected to the μTP GaN transistor.

3. The semiconductor structure according to claim 1, wherein: The cascode structure also includes a second μTP GaN transistor on the SOI wafer or die and connected to the μTP GaN transistor. 4 . The semiconductor structure of claim 1 , further comprising an inductor connected to a source of the μTP GaN transistor. 5 . The semiconductor structure according to claim 1 , further comprising a linearizer formed on the SOI wafer.

6. A method of manufacturing the structure according to claim 1 using a micro transfer printing process.

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