An insulated gate bipolar transistor with trench gate structure and a method of manufacturing the same

Abstract

This invention relates to an insulated gate bipolar transistor (IGBT) with a trench gate structure and its fabrication method. The transistor includes: a substrate, a nucleation layer, a stress-regulating layer, a collector region, an N-type buffer layer, an N-type drift layer, a P-type emitter region, a channel layer, and a barrier layer, stacked sequentially. At least a portion of the collector region is a P-type collector region. A two-dimensional electron gas is formed between the channel layer and the barrier layer. A first emitter metal is in contact with the P-type emitter region, and a dielectric layer is disposed between the first emitter metal and the barrier layer and the channel layer. A second emitter metal covers the first emitter metal and is in contact with the upper surface of the channel layer. A gate metal extends into the N-type drift layer, and a dielectric layer is disposed between the gate metal and the barrier layer, the channel layer, the P-type emitter region, and the N-type drift layer. A collector metal penetrates the substrate, the nucleation layer, and the stress-regulating layer and extends to the lower surface of the collector region. This transistor reduces scattering effects and improves the electron mobility of the device.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor devices, and particularly relates to an insulated gate bipolar transistor with a trench gate structure and a preparation method thereof. BACKGROUND

[0002] Gallium nitride (GaN) material has excellent physical and electrical properties, such as high temperature resistance, radiation resistance, wide band gap, high breakdown field strength, and high electron mobility. GaN trench gate insulated gate bipolar transistors (IGBTs) are widely used in the fields of power semiconductor devices, microwave radio frequency devices, power electronic devices, and optoelectronic devices.

[0003] In the field of power semiconductor devices, metal oxide field effect transistors (MOSFETs) have high switching speed, high input impedance, and low on-state voltage drop, and are often used in low-voltage, high-frequency application scenarios, but their current carrying capacity is poor, and their performance is poor under high voltage and large current conditions. In addition to metal oxide field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs) are also one of the commonly used electronic components. IGBT combines the high current density characteristics of bipolar transistors (BJT) and the voltage control characteristics of MOSFET, and is a transistor with high input impedance, high switching speed, and low on-state resistance under high voltage conditions.

[0004] However, in the traditional IGBT emitter, electrons and ionized donors are located in the same layer, which greatly increases the influence of scattering effect. SUMMARY

[0005] In order to solve the above problems existing in the prior art, the application provides an insulated gate bipolar transistor with a trench gate structure and a preparation method thereof. The technical problem to be solved by the application is solved by the following technical scheme:

[0006] The application provides an insulated gate bipolar transistor with a trench gate structure, comprising:

[0007] A substrate, a nucleation layer, a stress adjustment layer, a collector region, an N-type buffer layer, an N-type drift layer, a P-type emitter region, a channel layer and a barrier layer are sequentially stacked from bottom to top, and a two-dimensional electron gas is formed between the channel layer and the barrier layer;

[0008] A first emitter metal penetrating through the barrier layer, the channel layer and contacting the P-type emitter region, and a dielectric layer is arranged between the first emitter metal and the barrier layer and the channel layer; a second emitter metal covering the first emitter metal and contacting the upper surface of the channel layer;

[0009] A gate metal penetrating through the barrier layer, the channel layer, the P-type emitter region and extending to the inside of the N-type drift layer, and a dielectric layer is arranged between the gate metal and the barrier layer, the channel layer, the P-type emitter region, the N-type drift layer; the gate metal is located between adjacent second emitter metals;

[0010] A collector metal penetrating through the substrate, the nucleation layer, the stress adjustment layer and extending to the lower surface of the collector region.

[0011] In an embodiment of the present application, the first emitter metal is arranged in a first emitter groove and contacts the P-type emitter region, the first emitter groove extending from the upper surface of the barrier layer to the P-type emitter region.

[0012] The second emitter metal covers the first emitter metal and extends into a second emitter groove, the second emitter groove extending from the upper surface of the barrier layer to the upper surface of the channel layer.

[0013] The gate metal is arranged in a gate groove, the gate groove extending from the upper surface of the barrier layer to the inside of the N-type drift layer; the second emitter groove is located between the first emitter groove and the gate groove.

[0014] The collector metal is arranged in a collector groove and extends to the lower surface of the collector region; the collector groove extends from the lower surface of the substrate to the lower surface of the collector region.

[0015] In an embodiment of the present application, further comprising an isolation mesa and an isolation region,

[0016] The isolation mesa is formed by etching the end of the channel layer and the barrier layer until the surface of the P-type emitter region.

[0017] The isolation region is located at both ends of the P-type emitter region and on the surface of the N-type drift layer.

[0018] In an embodiment of the present application, further comprising an interconnection metal and a passivation layer, wherein,

[0019] The interconnection metal contacts the second emitter metal, and a dielectric layer is arranged between the interconnection metal and the isolation region and the gate metal; the passivation layer covers the interconnection metal.

[0020] In an embodiment of the present application, the collector region is a P-type collector region.

[0021] In an embodiment of the present application, part of the collector region is a P-type collector region and part of the collector region is an N-type collector region, the P-type collector region and the N-type collector region contacting each other.

[0022] In one embodiment of the present invention, the materials of the nucleation layer, stress conditioning layer, collector region, N-type buffer layer, N-type drift layer, P-type emitter region, and channel layer all include GaN; the material of the barrier layer includes AlGaN.

[0023] The doping concentration of both the collector region and the P-type emitter region is 1e16-1e21 cm⁻¹. -3 Furthermore, the doping concentration of the collector region is less than that of the second doped layer. The collector region is a P-type emitter region; the doping concentration of the N-type buffer layer is 1e16-1e21cm. -3 The doping concentration of the N-type drift layer is 1e15-1e18 cm⁻¹ -3 Furthermore, the doping concentration of the N-type buffer layer is greater than the doping concentration of the N-type drift layer;

[0024] The nucleation layer has a thickness of 50-500 nm, the stress adjustment layer has a thickness of 100-5000 nm, the collector region has a thickness of 50-1000 nm, the N-type buffer layer has a thickness of 50-1000 nm, the N-type drift layer has a thickness of 500-20000 nm, the P-type emitter region has a thickness of 50-1000 nm, the channel layer has a thickness of 10-500 nm, and the barrier layer has a thickness of 10-50 nm.

[0025] Another embodiment of the present invention provides a method for fabricating an insulated gate bipolar transistor with a trench gate structure, comprising the steps of:

[0026] The following layers are sequentially fabricated on the substrate from bottom to top: a nucleation layer, a stress conditioning layer, a current collector region, an N-type buffer layer, an N-type drift layer, a P-type emitter region, a channel layer, and a barrier layer.

[0027] The barrier layer and channel layer of the emitter region are etched until the P-type emitter region is formed to create the first emitter groove;

[0028] The barrier layer, channel layer, and P-type emitter region of the gate region are etched, and the gate groove is formed by over-etching into the interior of the drift layer;

[0029] The barrier layer, channel layer and P-type emitter region are etched to form a mesa isolation layer;

[0030] The substrate, nucleation layer, stress conditioning layer and collector region are etched down to the collector region to form a collector groove;

[0031] Annealing the sample activates the doped ions in the current collector region and the P-type emitter region;

[0032] A first dielectric layer is grown on the upper surface of the barrier layer, in the first emitter recess, and in the gate recess;

[0033] Ion implantation is performed in the P-type emission region of the isolation region to form the isolation region;

[0034] A gate metal is deposited on the upper surface of the first dielectric layer within the gate recess;

[0035] A second dielectric layer is grown on the upper surface of the first dielectric layer and the upper surface of the gate metal;

[0036] Etch the first dielectric layer and the second dielectric layer in the first emitter groove until the P-type emitter region is reached;

[0037] A first emitter metal is deposited on the surface of the second dielectric layer within the first emitter groove, such that the bottom of the first emitter metal contacts the P-type emitter region;

[0038] Between the first emitter recess and the gate recess, the second dielectric layer, the first dielectric layer, the barrier layer and the surface of the channel layer in the emitter region are etched to form the second emitter recess;

[0039] A second emitter metal is deposited on the surface of the first emitter metal and within the second emitter groove;

[0040] Collector metal is deposited in the collector groove and on the lower surface of the substrate.

[0041] In one embodiment of the present invention,

[0042] The substrate is sequentially fabricated from bottom to top with the following layers: a core layer, a stress-modulating layer, a current collector region, an N-type buffer layer, an N-type drift layer, a P-type emitter region, a channel layer, and a barrier layer, including:

[0043] Using MOCVD technology, a nucleation layer, a stress conditioning layer, a collector region, an N-type buffer layer, an N-type drift layer, a P-type emitter region, a channel layer, and a barrier layer are grown sequentially from bottom to top on the substrate, wherein the collector region is a P-type collector region;

[0044] Alternatively, using MOCVD, a nucleation layer, a stress-modulating layer, and an undoped GaN layer are grown sequentially from bottom to top on the substrate; a portion of the undoped GaN layer is ion-implanted to form a P-type collector region, and another portion is ion-implanted to form an N-type collector region, wherein the P-type collector region and the N-type collector region are in contact; using MOCVD, an N-type buffer layer, an N-type drift layer, a P-type emitter region, a channel layer, and a barrier layer are grown sequentially from bottom to top on the P-type collector region and the N-type collector region.

[0045] In one embodiment of the present invention, the step further includes:

[0046] A third dielectric layer is grown on the surface of the second emitter metal and the surface of the second dielectric layer;

[0047] The third and second dielectric layers of the emitter region are etched down to the surface of the second emitter metal.

[0048] Interconnect metal is deposited on the surface of the second emitter metal and on the surface of the third dielectric layer of the gate region;

[0049] A passivation layer is deposited on the surface of the interconnect metal.

[0050] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0051] 1. The insulated gate bipolar transistor of the present invention forms a barrier layer and a channel layer, and a two-dimensional electron gas is formed between the barrier layer and the channel layer. The two-dimensional electron gas is separated from the ionized donors in the barrier layer, thus greatly reducing the scattering effect and improving the electron mobility of the device.

[0052] 2. The insulated gate bipolar transistor of the present invention introduces a P-type collector region and an N-type buffer layer, and a PN junction is formed between the P-type collector region and the N-type buffer layer. It combines the advantages of BJT structure on the basis of MOSFET and improves the current conduction capability of the device.

[0053] 3. In this invention, the insulated gate bipolar transistor shorts the N-type collector region in the P-type collector region to form a reverse-conducting IGBT. This allows the PiN diode formed by the N-type collector region, the N-type drift layer, and the P-type emitter region to conduct when the IGBT is reverse biased, providing a channel for excess carriers in the drift layer and shortening the IGBT's turn-off time. Attached Figure Description

[0054] Figure 1 A schematic diagram of an insulated gate bipolar transistor with a trench gate structure is provided in an embodiment of the present invention;

[0055] Figure 2 A schematic diagram of another insulated gate bipolar transistor with a trench gate structure provided in an embodiment of the present invention;

[0056] Figures 3a-3r A schematic diagram illustrating the fabrication process of an insulated gate bipolar transistor with a trench gate structure, provided in an embodiment of the present invention;

[0057] Figures 4a-4c This is a schematic diagram illustrating part of the fabrication process of an insulated gate bipolar transistor with a trench gate structure, provided as an embodiment of the present invention. Detailed Implementation

[0058] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0059] Example 1

[0060] Please see Figure 1 , Figure 1 This is a schematic diagram of an insulated gate bipolar transistor with a trench gate structure provided in an embodiment of the present invention.

[0061] The insulated gate bipolar transistor with a trench gate structure includes: a substrate 1, a nucleation layer 2, a stress conditioning layer 3, a collector region 4, an N-type buffer layer 5, an N-type drift layer 6, a P-type emitter region 7, a channel layer 8, a barrier layer 9, a gate metal 12, a first emitter metal 14, a second emitter metal 15, and a collector metal 19.

[0062] The substrate 1, nucleation layer 2, stress adjustment layer 3, collector region 4, N-type buffer layer 5, N-type drift layer 6, P-type emitter region 7, channel layer 8 and barrier layer 9 are stacked sequentially from bottom to top. At least a portion of the collector region 4 is a P-type collector region, and a two-dimensional electron gas is formed between the channel layer 8 and the barrier layer 9. The first emitter metal 14 penetrates the barrier layer 9 and the channel layer 8 and contacts the P-type emitter region 7. A dielectric layer is disposed between the first emitter metal 14 and the barrier layer 9 and the channel layer 8. The second emitter metal 15 covers the first emitter metal 14 and contacts the upper surface of the channel layer 8. The gate metal 12 penetrates the barrier layer 9, the channel layer 8, and the P-type emitter region 7 and extends into the interior of the N-type drift layer 6. A dielectric layer is disposed between the gate metal 12 and the barrier layer 9, the channel layer 8, the P-type emitter region 7, and the N-type drift layer 6. The gate metal 12 is located between adjacent second emitter metals 15. The collector metal 19 penetrates the substrate 1, the nucleation layer 2, and the stress adjustment layer 3 and extends to the lower surface of the collector region 4.

[0063] In one specific embodiment, a first emitter metal 14 is disposed within a first emitter recess and contacts a P-type emitter region 7, the first emitter recess extending from the upper surface of the barrier layer 9 to the P-type emitter region 7; a second emitter metal 15 covers the first emitter metal 14 and extends into a second emitter recess, the second emitter recess extending from the upper surface of the barrier layer 9 to the upper surface of the channel layer 8; a gate metal 12 is disposed within a gate recess, the gate recess extending from the upper surface of the barrier layer 9 to the interior of the N-type drift layer 6; a second emitter recess is located between the first emitter recess and the gate recess; a collector metal 19 is disposed within a collector recess and extends to the lower surface of the collector region 4; the collector recess extends from the lower surface of the substrate 1 to the lower surface of the collector region 4.

[0064] Specifically, the first emitter groove penetrates the barrier layer 9 and the channel layer 8, extending to either the surface of the P-type emitter region 7 or its interior. A dielectric layer is disposed on the side of the first emitter groove, extending to the surface of the barrier layer 9. The first emitter metal 14 is disposed within the first emitter groove, with its bottom contacting the P-type emitter region 7 and its side contacting the dielectric layer, forming a groove structure. Simultaneously, the first emitter metal 14 extends onto the dielectric layer on the surface of the barrier layer 9.

[0065] The gate trench extends through the barrier layer 9, the channel layer 8, and the P-type emitter region 7, with its bottom located inside the N-type drift layer 6. The inner surface of the gate trench is covered by a dielectric layer that extends onto the barrier layer 9 surrounding the gate trench. The gate metal 12 covers the dielectric layer inside the gate trench and extends to overlap the surface of the dielectric layer surrounding the gate trench.

[0066] The second emitter recess is located in the emitter region between the first emitter recess and the gate recess, with its bottom located on the upper surface of the channel layer 8. The second emitter metal 15 fills the recess structure formed by the first emitter metal 14 and extends from the upper surface of the first emitter metal 14 into the interior of the second emitter recess to contact the channel layer 8.

[0067] It should be noted that there are n gates, where n is a positive integer greater than or equal to 1. Correspondingly, there are n+1 emitters, and the gates are placed between adjacent emitters. That is, the number of gates can be one or more, depending on the required current.

[0068] A collector groove is formed at the bottom of the transistor, extending through the substrate 1, nucleation layer 2, stress-adjusting layer 3, and down to the lower surface of the collector region 4. Collector metal 19 covers the surface of the collector groove and extends to the lower surface of the substrate 1.

[0069] Specifically, collector region 4 serves as the collector of the BJT device, and first emitter metal 14 serves as the emitter ohmic metal of the BJT device; N-type buffer layer 5 serves as the drain of the MOSFET device, and second emitter metal 15 serves as the source ohmic contact metal of the MOSFET device; first emitter metal 14 and second emitter metal 15 together form the emitter of the insulated gate bipolar transistor IGBT.

[0070] In this embodiment, an insulated gate bipolar transistor is formed by etching a gate groove to serve as the gate region of the IGBT, etching a first emitter groove that contacts the P-type emitter region 7, etching a second emitter groove that contacts the two-dimensional electron gas to serve as the emitter region of the IGBT, and etching a collector groove at the bottom of the substrate to serve as the collector region of the IGBT.

[0071] In one specific embodiment, the insulated gate bipolar transistor further includes an isolation mesa and an isolation region 11, wherein the isolation mesa is formed by etching the ends of the channel layer 8 and the barrier layer 9 up to the surface of the P-type emitter region 7; the isolation region 11 is located at both ends of the P-type emitter region 7 and on the surface of the N-type drift layer 6.

[0072] Specifically, the ends of the channel layer 8 and the barrier layer 9 are etched away to form isolation mesas. The isolation region 11 is formed by ion implantation at the end of the P-type emitter region 7.

[0073] Furthermore, the dielectric layer between the first emitter metal 14 and the first emitter groove extends to the side of the isolation platform and the upper surface of the isolation region 11, and the first emitter metal 14 located at the end extends to the isolation region 11 and partially covers the dielectric layer.

[0074] In one specific embodiment, the insulated gate bipolar transistor further includes an interconnect metal 17 and a passivation layer 18. The interconnect metal 17 is in contact with the second emitter metal 15 and a dielectric layer is disposed between it and the isolation region 11 and the gate metal 12. The passivation layer 18 covers the interconnect metal 17.

[0075] Specifically, the upper surface of isolation region 11, the upper surface of the first emitter metal 14 on the surface of isolation region 11, and the surface of gate metal 12 are all covered with a dielectric layer. Interconnect metal 17 is covered with a dielectric layer and is in direct contact with the second emitter metal 15. Passivation layer 18 is located on the upper surface of interconnect metal 17.

[0076] In one specific embodiment, collector region 4 is a P-type collector region, meaning that the entire area of ​​collector region 4 is a P-type collector region, such as... Figure 1 As shown.

[0077] In one specific embodiment, a portion of the collector region 4 is a P-type collector region 41, and the other portion is an N-type collector region 42, with the P-type collector region 41 and the N-type collector region 42 in contact with each other.

[0078] Specifically, P-type ion implantation is performed at one end of collector region 4 to form P-type collector region 41, and N-type ion implantation is performed at the other end to form N-type collector region 42. The P-type collector region 41 and the N-type collector region 42 are short-circuited, thereby forming a reverse-conducting IGBT, such as... Figure 2 As shown, Figure 2 This is a schematic diagram of another insulated gate bipolar transistor with a trench gate structure provided in an embodiment of the present invention.

[0079] In this embodiment, the insulated gate bipolar transistor shorts the N-type collector region in the P-type collector region to form a reverse-conducting IGBT. This allows the PiN diode formed by the N-type collector region, the N-type drift layer, and the P-type emitter region to conduct when the IGBT is reverse biased, providing a channel for excess carriers in the drift layer and shortening the IGBT's turn-off time.

[0080] In one specific embodiment, substrate 1 is sapphire, SOI, Si, GaN, AlN, diamond, or other composite substrates. The nucleation layer 2, stress-adjusting layer 3, current collector region 4, N-type buffer layer 5, N-type drift layer 6, P-type emitter region 7, and channel layer 8 are all made of GaN. The barrier layer 9 is made of AlGaN. It should be noted that the channel layer 8 and barrier layer 9 in this embodiment can also be made of other materials capable of forming a two-dimensional electron gas.

[0081] The doping concentrations of collector region 4 and P-type emitter region 7 are both 1e16-1e21cm. -3 Furthermore, the doping concentration of collector region 4 is lower than that of P-type emitter region 7. The doping concentration of N-type buffer layer 5 is 1e16-1e21cm. -3 The doping concentration of the N-type drift layer 6 is 1e15-1e18 cm⁻¹. -3 Furthermore, the doping concentration of the N-type buffer layer 5 is greater than that of the N-type drift layer 6, meaning that the material of the N-type buffer layer 5 is N+GaN, and the material of the N-type drift layer 6 is N-GaN.

[0082] The nucleation layer 2 has a thickness of 50-500 nm, the stress conditioning layer 3 has a thickness of 100-5000 nm, the collector region 4 has a thickness of 50-1000 nm, the N-type buffer layer 5 has a thickness of 50-1000 nm, the N-type drift layer 6 has a thickness of 500-20000 nm, the P-type emitter region 7 has a thickness of 50-1000 nm, the channel layer 8 has a thickness of 10-500 nm, and the barrier layer 9 has a thickness of 10-50 nm.

[0083] Specifically, when collector region 4 is a P-type collector region, the doping concentration of the P-type collector region is 1e16-1e21cm. -3 The thickness is 50-1000 nm. When part of the collector region 4 is a P-type collector region 41 and the other part is an N-type collector region 42, the doping concentration of the P-type collector region 41 is 1e16-1e21 cm⁻¹. -3 The thickness is 50-1000 nm, and the doping concentration of the N-type collector region 42 is 1e16-1e21 cm⁻¹. -3 The thickness is 50-1000nm.

[0084] The gate metal 12 is made of TiN / Ti / Al / Ti multilayer metal or Ni / Au multilayer metal. The first emitter metal 14, the second emitter metal 15, and the collector metal 19 are all made of Ti / Al / TiN or other Ti / Al-based metal combinations.

[0085] It needs to be explained that, Figure 1 and Figure 2The insulated gate bipolar transistor shown is a cellular structure, and the actual device is formed by a periodic arrangement of several cellular structures.

[0086] The insulated gate bipolar transistor of this embodiment forms a barrier layer and a channel layer, and a two-dimensional electron gas is formed between the barrier layer and the channel layer. The two-dimensional electron gas is separated from the ionized donors in the barrier layer, thus greatly reducing the scattering effect and improving the electron mobility of the device.

[0087] The insulated gate bipolar transistor of this embodiment introduces a P-type collector region and an N-type buffer layer, and a PN junction is formed between the P-type collector region and the N-type buffer layer. It combines the advantages of the BJT structure with the MOSFET, thereby improving the current conduction capability of the device.

[0088] Example 2

[0089] Based on Example 1, this example illustrates a method for fabricating an insulated gate bipolar transistor with a trench gate structure, using collector region 4 as an example of a P-type collector region.

[0090] Please see Figures 3a-3r , Figures 3a-3r This is a schematic diagram illustrating the fabrication process of an insulated gate bipolar transistor with a trench gate structure, provided as an embodiment of the present invention. The fabrication method includes the following steps:

[0091] S1. On substrate 1, from bottom to top, the following layers are sequentially fabricated: nucleation layer 2, stress adjustment layer 3, current collector region 4, N-type buffer layer 5, N-type drift layer 6, P-type emitter region 7, channel layer 8, and barrier layer 9.

[0092] Specifically, using MOCVD technology, a nucleation layer 2, a stress-regulating layer 3, a P-type collector region 4, an N-type buffer layer 5, an N-type drift layer 6, a P-type emitter region 7, a channel layer 8, and a barrier layer 9 are sequentially grown on substrate 1, as follows: Figure 3a As shown.

[0093] S2, the barrier layer 9 and channel layer 8 of the etched emitter region are used to form the first emitter groove up to the P-type emitter region 7, such as Figure 3b As shown.

[0094] Specifically, dry etching is used, with BCl3 / Cl2 as the reaction gas, to etch the barrier layer 9, the channel layer 8, and up to the P-type emitter region 7 in the emitter region. The etching can be done to the interior of the P-type emitter region 7 or to the surface of the P-type emitter region 7 to form the first emitter groove.

[0095] S3, etch the barrier layer 9, channel layer 8, and P-type emitter region 7 into the gate region, and etch over to the interior of the drift layer 6 to form a gate recess, such as Figure 3c As shown.

[0096] Specifically, dry etching is used, with BCl3 / Cl2 as the reaction gas, to etch the barrier layer 9, channel layer 8, and P-type emitter region 7 in the gate region, and to over-etch a portion of the N-type drift layer 6 to form a gate groove.

[0097] S4, the barrier layer 9, the channel layer 8, and the P-type emitter region 7, etched together, form the isolation mesa, as shown. Figure 3d As shown.

[0098] Specifically, dry etching is used, with BCl3 / Cl2 as the reaction gas, to etch the channel layer 8 and barrier layer 9 outside the active region up to the P-type emitter region 7, forming an isolation mesa.

[0099] S5. Etch the substrate 1, nucleation layer 2, stress adjustment layer 3, and finally the collector region 4 to form a collector groove, such as... Figure 3e As shown.

[0100] Specifically, dry etching is used, with BCl3 / Cl2 as the reaction gas, to etch the substrate 1, nucleation layer 2 and stress conditioning layer 3 in the collector region from the substrate 1.

[0101] S6. Anneal the sample to activate the doped ions in collector region 4 and P-type emitter region 7.

[0102] Specifically, the sample is annealed at high temperature (800-850℃) to activate the doped ions in collector region 4 and P-type emitter region 7. For example, annealing at 825℃ in a nitrogen atmosphere for 20 minutes activates the H-passivated Mg doped ions in collector region 4 and P-type emitter region 7.

[0103] S7. A first dielectric layer 10 is grown on the upper surface of the barrier layer 9, within the first emitter recess and the gate recess, as follows: Figure 3f As shown.

[0104] Specifically, a first dielectric layer 10 is grown on the upper surface of the barrier layer 9, the first emitter recess, the gate recess, and the surface of the isolation mesa using ALD or PECVD processes, and serves as the gate dielectric layer. The material of the first dielectric layer 10 includes one or more of Al2O3, HfO2, SiO2, TiO2, AlON, and AlTiO; the first dielectric layer 10 can also be a multilayer gate dielectric.

[0105] S8. Ion implantation is performed in the P-type emission region 7 of the isolation region to form the isolation region 11, such as... Figure 3g As shown.

[0106] Specifically, ion implantation isolation is performed in the P-type emission region 7 outside the active region through the first dielectric layer 10. The implanted ions can be N or Ar, forming an isolation region 11.

[0107] S9. Deposit gate metal 12 on the upper surface of the first dielectric layer 10 within the gate trench, such as... Figure 3h As shown.

[0108] Specifically, gate metal 12 is deposited on the first dielectric layer 10 within the gate recess using an electron beam evaporation process.

[0109] S10. A second dielectric layer 13 is grown on the upper surface of the first dielectric layer 10 and the upper surface of the gate metal 12, such as... Figure 3i As shown.

[0110] Specifically, a second dielectric layer 13 is grown on the upper surface of the first dielectric layer 10 and the upper surface of the gate metal 12 using a PECVD process. The material of the second dielectric layer 13 includes one or more of Al2O3, SiO2, and Si3N4.

[0111] S11, Etch the first dielectric layer 10 and the second dielectric layer 13 in the first emitter groove until the P-type emitter region 7 is reached, such as Figure 3j As shown.

[0112] Specifically, dry etching is used, employing BCl3 / Cl2 as the reaction gas, to etch the first dielectric layer 10 and the second dielectric layer 13 in the first emitter groove until the P-type emission region 7 at the bottom of the first emitter groove is exposed.

[0113] S12. A first emitter metal 14 is deposited on the surface of the second dielectric layer 13 within the first emitter groove, such that the bottom of the first emitter metal 14 contacts the P-type emitter region 7, as shown. Figure 3k As shown.

[0114] Specifically, using electron beam evaporation, a first emitter metal 14 is deposited on the surface of the second dielectric layer 13 within the first emitter groove, with the bottom of the first emitter metal 14 in contact with the P-type emitter region 7.

[0115] S13. Between the first emitter recess and the gate recess, the second dielectric layer 13, the first dielectric layer 10, and the barrier layer 9 in the emitter region are etched down to the surface of the channel layer 8 to form the second emitter recess. Figure 3l As shown.

[0116] Specifically, dry etching is used, employing BCl3 / Cl2 as the reaction gas, to etch the surface of the second dielectric layer 13, the first dielectric layer 10, the barrier layer 9, and up to the channel layer 8 between the first emitter recess and the gate recess, forming the second emitter recess.

[0117] S14. A second emitter metal 15 is deposited on the surface of the first emitter metal 14 and in the second emitter groove, such as... Figure 3m As shown.

[0118] Specifically, using electron beam evaporation, a second emitter metal 15 is deposited on the surface of the first emitter metal 14, inside the second emitter groove, and on the device surface between the first emitter metal 14 and the second emitter groove.

[0119] Furthermore, after obtaining the second emitter metal 15, as... Figure 3o As shown, the following steps can also be performed:

[0120] S15, a third dielectric layer 16 is grown on the surface of the second emitter metal 15 and the surface of the second dielectric layer 13, such as Figure 3n As shown.

[0121] Specifically, a third dielectric layer 16 is grown on the surface of the second emitter metal 15 and the second dielectric layer 13 using a PECVD process.

[0122] S16, etch the third dielectric layer 16 and the second dielectric layer 13 of the emitter region until the surface of the second emitter metal 15 is reached, such as Figure 3o As shown.

[0123] Specifically, dry etching is used, employing BCl3 / Cl2 as the reaction gas, to etch the third dielectric layer 16 and the second dielectric layer 13 in the emitter region until reaching the surface of the second emitter metal 15.

[0124] S17, Interconnect metal 17 is deposited on the surface of the second emitter metal 15 and the surface of the third dielectric layer 16 in the gate region, such as Figure 3p As shown.

[0125] Specifically, using an electron beam evaporation process, interconnect metal 17 is deposited on the surface of the second emitter metal 15 and the surface of the third dielectric layer 16 in the gate region.

[0126] S18. A passivation layer 18 is deposited on the surface of the interconnect metal 17, such as... Figure 3q As shown.

[0127] Specifically, a passivation layer 18 is deposited on the surface of the interconnect metal 17 using a PECVD process.

[0128] S19. Deposit collector metal 19 in the collector groove and on the lower surface of substrate 1, such as... Figure 3r As shown.

[0129] Specifically, electron beam evaporation is used to deposit collector metal 19 in the collector groove and on the lower surface of substrate 1.

[0130] The insulated gate bipolar transistor of this embodiment forms a barrier layer and a channel layer, and a two-dimensional electron gas is formed between the barrier layer and the channel layer. The two-dimensional electron gas is separated from the ionized donors in the barrier layer, thus greatly reducing the scattering effect and improving the electron mobility of the device.

[0131] The insulated gate bipolar transistor of this embodiment introduces a P-type collector region and an N-type buffer layer, and a PN junction is formed between the P-type collector region and the N-type buffer layer. It combines the advantages of the BJT structure with the MOSFET, thereby improving the current conduction capability of the device.

[0132] Example 3

[0133] Based on Example 1, this example illustrates a method for fabricating an insulated gate bipolar transistor with a trench gate structure, using a portion of the P-type collector region 4 as collector region 41 and another portion as N-type collector region 42.

[0134] Please see Figures 4a-4c , Figures 4a-4c This is a schematic diagram illustrating a partial fabrication process of an insulated gate bipolar transistor with a trench gate structure, provided as an embodiment of the present invention. The fabrication method includes the following steps:

[0135] S1. On substrate 1, from bottom to top, the following layers are sequentially fabricated: nucleation layer 2, stress adjustment layer 3, current collector region 4, N-type buffer layer 5, N-type drift layer 6, P-type emitter region 7, channel layer 8, and barrier layer 9.

[0136] Specifically, firstly, using MOCVD technology, a core layer 2, a stress-modulating layer 3, and an undoped GaN layer are sequentially grown on substrate 1 from bottom to top, such as... Figure 4a As shown. Then, a portion of the undoped GaN layer is implanted with P-type ions (e.g., Mg ions) to form a P-type current collector region 41, and another portion is implanted with N-type ions (e.g., Si ions) to form an N-type current collector region 42. The P-type current collector region 41 and the N-type current collector region 42 are in contact, as shown. Figure 4b As shown. Next, using MOCVD technology, an N-type buffer layer 5, an N-type drift layer 6, a P-type emitter region 7, a channel layer 8, and a barrier layer 9 are sequentially grown from bottom to top on the P-type collector region 41 and the N-type collector region 42, as shown. Figure 4c As shown.

[0137] S2, the barrier layer 9 and the channel layer 8 of the etched emitter region are used to form the first emitter groove up to the P-type emitter region 7.

[0138] S3, etch the barrier layer 9, channel layer 8, and P-type emitter region 7 of the gate region, and etch over to the interior of the drift layer 6 to form a gate groove.

[0139] S4, the barrier layer 9, the channel layer 8, and the P-type emission region 7 are etched to form the isolation mesa.

[0140] S5. Etch the substrate 1, nucleation layer 2, stress adjustment layer 3, and finally the collector region 4 to form the collector groove.

[0141] S6. Anneal the sample to activate the doped ions in collector region 4 and P-type emitter region 7.

[0142] S7. A first dielectric layer 10 is grown on the upper surface of the barrier layer 9, in the first emitter groove and the gate groove.

[0143] S8. Ion implantation is performed in the P-type emission region 7 of the isolation region to form the isolation region 11.

[0144] S9. Deposit gate metal 12 on the upper surface of the first dielectric layer 10 within the gate recess.

[0145] S10. A second dielectric layer 13 is grown on the upper surface of the first dielectric layer 10 and the upper surface of the gate metal 12.

[0146] S11, Etch the first dielectric layer 10 and the second dielectric layer 13 in the first emitter groove until the P-type emitter region 7.

[0147] S12. A first emitter metal 14 is deposited on the surface of the second dielectric layer 13 in the first emitter groove, such that the bottom of the first emitter metal 14 contacts the P-type emitter region 7.

[0148] S13. Between the first emitter recess and the gate recess, the second dielectric layer 13, the first dielectric layer 10, the barrier layer 9 and the surface of the channel layer 8 in the emitter region are etched to form the second emitter recess.

[0149] S14. Deposit the second emitter metal 15 on the surface of the first emitter metal 14 and in the second emitter groove.

[0150] S15. A third dielectric layer 16 is grown on the surface of the second emitter metal 15 and the surface of the second dielectric layer 13.

[0151] S16, etch the third dielectric layer 16 and the second dielectric layer 13 of the emitter region until the surface of the second emitter metal 15.

[0152] S17. Interconnect metal 17 is deposited on the surface of the second emitter metal 15 and the surface of the third dielectric layer 16 in the gate region.

[0153] S18, A passivation layer 18 is deposited on the surface of the interconnect metal 17.

[0154] S19. Deposit collector metal 19 in the collector groove and on the lower surface of substrate 1.

[0155] For details on the implementation of steps S2-S9, please refer to Example 2. This example will not repeat them here.

[0156] In this embodiment, the insulated gate bipolar transistor shorts the N-type collector region in the P-type collector region to form a reverse-conducting IGBT. This allows the PiN diode formed by the N-type collector region, the N-type drift layer, and the P-type emitter region to conduct when the IGBT is reverse biased, providing a channel for excess carriers in the drift layer and shortening the IGBT's turn-off time.

[0157] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. An insulated gate bipolar transistor with a trench gate structure, characterized in that, include: The substrate (1), nucleation layer (2), stress adjustment layer (3), collector region (4), N-type buffer layer (5), N-type drift layer (6), P-type emitter region (7), channel layer (8) and barrier layer (9) are stacked sequentially from bottom to top, wherein at least a portion of the collector region (4) is a P-type collector region, and a two-dimensional electron gas is formed between the channel layer (8) and the barrier layer (9); A first emitter metal (14) penetrates the barrier layer (9) and the channel layer (8) and contacts the P-type emitter region (7), and a dielectric layer is disposed between the first emitter metal (14) and the barrier layer (9) and the channel layer (8); a second emitter metal (15) covers the first emitter metal (14) and contacts the upper surface of the channel layer (8); A gate metal (12) extends through the barrier layer (9), the channel layer (8), the P-type emitter region (7) and into the interior of the N-type drift layer (6), and a dielectric layer is disposed between the gate metal (12) and the barrier layer (9), the channel layer (8), the P-type emitter region (7), and the N-type drift layer (6); the gate metal (12) is located between adjacent second emitter metals (15); Collector metal (19) that penetrates the substrate (1), the nucleation layer (2), the stress conditioning layer (3) and extends to the lower surface of the collector region (4).

2. The insulated gate bipolar transistor with a trench gate structure according to claim 1, characterized in that, The first emitter metal (14) is disposed in the first emitter groove and in contact with the P-type emitter region (7), and the first emitter groove extends from the upper surface of the barrier layer (9) to the P-type emitter region (7); The second emitter metal (15) covers the first emitter metal (14) and extends into the second emitter groove, which extends from the upper surface of the barrier layer (9) to the upper surface of the channel layer (8); The gate metal (12) is disposed in the gate groove, which extends from the upper surface of the barrier layer (9) to the interior of the N-type drift layer (6); the second emitter groove is located between the first emitter groove and the gate groove; The collector metal (19) is disposed in the collector groove and extends to the lower surface of the collector region (4); the collector groove extends from the lower surface of the substrate (1) to the lower surface of the collector region (4).

3. The insulated gate bipolar transistor with a trench gate structure according to claim 1, characterized in that, It also includes isolation countertops and isolation areas (11), The isolation platform is formed by etching the ends of the channel layer (8) and the barrier layer (9) down to the surface of the P-type emission region (7); The isolation zone (11) is located at both ends of the P-type emission zone (7) and on the surface of the N-type drift layer (6).

4. The insulated gate bipolar transistor with a trench gate structure according to claim 3, characterized in that, It also includes interconnect metal (17) and passivation layer (18), wherein, The interconnect metal (17) is in contact with the second emitter metal (15), and a dielectric layer is provided between the interconnect metal (17) and the isolation region (11) and the gate metal (12); The passivation layer (18) covers the interconnect metal (17).

5. The insulated gate bipolar transistor with a trench gate structure according to claim 1, characterized in that, The collector area (4) is a P-type collector area.

6. The insulated gate bipolar transistor with a trench gate structure according to claim 1, characterized in that, A portion of the collector region (4) is a P-type collector region (41), and the other portion is an N-type collector region (42), and the P-type collector region (41) and the N-type collector region (42) are in contact with each other.

7. The insulated gate bipolar transistor with a trench gate structure according to claim 1, characterized in that, The materials of the nucleation layer (2), stress adjustment layer (3), collector region (4), N-type buffer layer (5), N-type drift layer (6), P-type emitter region (7), and channel layer (8) all include GaN; the material of the barrier layer (9) includes AlGaN. The doping concentration of both the collector region (4) and the P-type emitter region (7) is 1e16-1e21cm. -3 Furthermore, the doping concentration of the collector region (4) is less than that of the P-type emitter region (7); the doping concentration of the N-type buffer layer (5) is 1e16-1e21cm. -3 The doping concentration of the N-type drift layer (6) is 1e15-1e18 cm⁻¹. -3 Furthermore, the doping concentration of the N-type buffer layer (5) is greater than the doping concentration of the N-type drift layer (6); The nucleation layer (2) has a thickness of 50-500 nm, the stress adjustment layer (3) has a thickness of 100-5000 nm, the collector region (4) has a thickness of 50-1000 nm, the N-type buffer layer (5) has a thickness of 50-1000 nm, the N-type drift layer (6) has a thickness of 500-20000 nm, the P-type emitter region (7) has a thickness of 50-1000 nm, the channel layer (8) has a thickness of 10-500 nm, and the barrier layer (9) has a thickness of 10-50 nm.

8. A method for fabricating an insulated gate bipolar transistor with a trench gate structure, characterized in that, Including the following steps: The following layers are sequentially fabricated on the substrate (1) from bottom to top: nucleation layer (2), stress adjustment layer (3), current collector region (4), N-type buffer layer (5), N-type drift layer (6), P-type emitter region (7), channel layer (8) and barrier layer (9); The barrier layer (9) and channel layer (8) of the emitter region are etched up to the P-type emitter region (7) to form the first emitter groove; The barrier layer (9), channel layer (8), and P-type emitter region (7) of the gate region are etched, and a gate groove is formed by etching into the interior of the drift layer (6); The barrier layer (9), channel layer (8) of the etched isolation mesa region are formed up to the P-type emitter region (7); The substrate (1), nucleation layer (2), and stress adjustment layer (3) of the collector region are etched down to the collector region (4) to form a collector groove; Anneal the sample to activate the doped ions in the current collector region (4) and the P-type emitter region (7); A first dielectric layer (10) is grown on the upper surface of the barrier layer (9), in the first emitter groove and in the gate groove; Ion implantation is performed in the P-type emission region (7) of the isolation region to form the isolation region (11); Gate metal (12) is deposited on the upper surface of the first dielectric layer (10) within the gate recess; A second dielectric layer (13) is grown on the upper surface of the first dielectric layer (10) and the upper surface of the gate metal (12); The first dielectric layer (10) and the second dielectric layer (13) in the first emitter groove are etched down to the P-type emitter region (7); A first emitter metal (14) is deposited on the surface of the second dielectric layer (13) in the first emitter groove, such that the bottom of the first emitter metal (14) is in contact with the P-type emitter region (7); Between the first emitter recess and the gate recess, the second dielectric layer (13), the first dielectric layer (10), the barrier layer (9) of the emitter region are etched down to the surface of the channel layer (8) to form the second emitter recess; A second emitter metal (15) is deposited on the surface of the first emitter metal (14) and in the second emitter groove; Collector metal (19) is deposited in the collector groove and on the lower surface of the substrate (1).

9. The method for fabricating an insulated gate bipolar transistor with a trench gate structure according to claim 8, characterized in that, A core layer (2), a stress-adjusting layer (3), a current collector region (4), an N-type buffer layer (5), an N-type drift layer (6), a P-type emitter region (7), a channel layer (8), and a barrier layer (9) are sequentially fabricated on a substrate (1) from bottom to top, including: Using MOCVD process, a nucleation layer (2), a stress adjustment layer (3), a collector region (4), an N-type buffer layer (5), an N-type drift layer (6), a P-type emitter region (7), a channel layer (8), and a barrier layer (9) are grown sequentially from bottom to top on the substrate (1), wherein the collector region (4) is a P-type collector region. Alternatively, an MOCVD process can be used to grow a nucleation layer (2), a stress-adjusting layer (3), and an undoped GaN layer sequentially from bottom to top on the substrate (1); A portion of the undoped GaN layer is implanted with P-type ions to form a P-type collector region (41), and another portion is implanted with N-type ions to form an N-type collector region (42), wherein the P-type collector region (41) and the N-type collector region (42) are in contact; Using MOCVD technology, an N-type buffer layer (5), an N-type drift layer (6), a P-type emitter region (7), a channel layer (8), and a barrier layer (9) are grown sequentially from bottom to top on the P-type collector region (41) and the N-type collector region (42).

10. The method for fabricating an insulated gate bipolar transistor with a trench gate structure according to claim 8, characterized in that, It also includes the following steps: A third dielectric layer (16) is grown on the surface of the second emitter metal (15) and the surface of the second dielectric layer (13); The third dielectric layer (16) and the second dielectric layer (13) of the emitter region are etched down to the surface of the second emitter metal (15); Interconnect metal (17) is deposited on the surface of the second emitter metal (15) and the surface of the third dielectric layer (16) of the gate region; A passivation layer (18) is deposited on the surface of the interconnect metal (17).

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