SiC MOSFET cellular structure and preparation method, device and equipment thereof

Abstract

The invention relates to a SiC MOSFET cellular structure and a preparation method, device and equipment thereof. The method comprises the following steps: providing a substrate; forming a first epitaxial layer covering the substrate; forming P-type columns in the first epitaxial layer, wherein the P-type columns extend to a preset depth from the top surface of the first epitaxial layer to the inside of the first epitaxial layer and are distributed at intervals along a first direction parallel to the top surface; forming a second epitaxial layer covering the top surface of the first epitaxial layer; performing an ion implantation process on the second epitaxial layer to form P-type contact regions which pass through the top surface of the second epitaxial layer, penetrate through the second epitaxial layer along the direction towards the substrate, are arranged one to one with the P-type columns and are in contact with each other; the P-type column and the P-type contact region respectively comprise a cambered-surface-shaped side surface. The transverse electric field changes a triangular electric field in the epitaxial layer into a trapezoidal or rectangular electric field, thereby improving the withstand voltage of the device. Therefore, the same withstand voltage can reduce the thickness of the epitaxial layer of the device and reduce the on-resistance. When reverse bias is formed, a depletion layer is generated, a vertical electric field is formed, and the withstand voltage of the device is further improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a SiC MOSFET cell structure and its fabrication method, device, and equipment. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used and high-performance power devices with advantages such as fast switching speed, low loss, and simple drive circuits.

[0003] Existing trench-gate silicon carbide (SiC) MOSFET device structures require the introduction of a trench gate structure within a low-concentration N-type doped epitaxial layer to form a vertical channel. To prevent breakdown due to electric field concentration at the bottom of the trench gate, a sufficiently thick epitaxial layer is needed to mitigate the electric field intensity. However, the on-resistance increases rapidly with increasing breakdown voltage. To reduce on-resistance, the chip area must be increased, which limits further reduction in cell size and hinders improvements in conductive channel density. A larger wafer area necessitates a larger package size, thus increasing cost. Summary of the Invention

[0004] Therefore, it is necessary to provide a SiC MOSFET cell structure and its fabrication method, device, and equipment to address the technical problems in the existing technology, which can at least improve the voltage withstand capability of the device while ensuring the cell size.

[0005] In a first aspect, this application provides a method for fabricating a SiC MOSFET cell structure, comprising: providing a substrate;

[0006] Forming a first epitaxial layer covering the substrate;

[0007] P-shaped pillars are formed within the first epitaxial layer, extending from the top surface of the first epitaxial layer into the first epitaxial layer to a predetermined depth, and spaced apart along a first direction parallel to the top surface.

[0008] A second epitaxial layer is formed, covering the top surface of the first epitaxial layer;

[0009] An ion implantation process is performed on the second epitaxial layer to form a P-type contact region that extends through the top surface of the second epitaxial layer and penetrates the second epitaxial layer in the direction toward the substrate, and is one-to-one with the P-type pillars and in contact with each other; wherein, both the P-type pillars and the P-type contact regions include arc-shaped side surfaces.

[0010] In the SiC MOSFET cell structure fabrication method described in the above embodiments, epitaxial growth is performed twice using different epitaxial layer thicknesses based on the voltage withstand capability of the SiC MOSFET device. In the first epitaxial layer of the SiC MOSFET cell structure, trench etching and epitaxial backfilling are used to form P-type pillars. Adjacent P-type pillars contact the N-type first epitaxial layer to form a PN junction, thereby forming a superjunction structure. The electric field in the drift region changes from a traditional triangular distribution to a rectangular distribution, significantly improving the device's breakdown voltage. Compared to a flat superjunction structure, the P-pillars with curved side surfaces have a higher doping concentration, requiring a shallower depth to maintain charge balance, thus reducing the difficulty of filling the first trench.

[0011] A P-type contact region is formed in the second epitaxial layer, which is one-to-one with the P-pillar. In addition to forming an ohmic contact with the metal, the P-type contact region can prevent free electrons from diffusing into the neighboring cells.

[0012] In some embodiments, forming a P-shaped pillar includes: forming a first trench in a first epitaxial layer that extends into the first epitaxial layer to a predetermined depth and is spaced apart along a first direction;

[0013] The first P-type material layer is formed by filling the first trench;

[0014] A portion of the first P-type material layer is removed to form a P-type pillar; wherein the top surface of the P-type pillar is flush with the top surface of the first epitaxial layer.

[0015] In some embodiments, before forming the P-type contact region, the method further includes: performing an ion implantation process on the second epitaxial layer to form a second P-type material layer that completely overlaps with the second epitaxial layer;

[0016] An N-type material layer is formed on the second P-type material layer, extending through the top surface of the second P-type material layer and into the second P-type material layer; and after forming the P-type contact region, the remaining second P-type material layer is used to form the P-type body region; the remaining N-type material layer is used to form the N-type source region.

[0017] In some embodiments, the first dimension of the P-type contact area along the first direction within the P-type body region first increases and then decreases in the direction toward the substrate; the second dimension of the P-type pillar along the first direction first increases and then decreases in the direction toward the substrate; the maximum value of the first dimension is greater than the maximum value of the second dimension.

[0018] In some embodiments, forming a trench structure in a second epitaxial layer between adjacent P-type contact areas includes: forming a second trench extending inwardly through the top surface of the second epitaxial layer between adjacent P-type contact areas;

[0019] A gate oxide layer is formed covering the inner surface of the second trench;

[0020] The second trench is filled to form a gate conductive layer whose top surface is flush with the top surface of the gate oxide layer.

[0021] In some embodiments, the conductivity type of both the first epitaxial layer and the second epitaxial layer is N-type.

[0022] In some embodiments, the ion implantation dose in the P-type contact region is greater than that in the P-type column and P-type body regions.

[0023] Secondly, this application also provides a SiC MOSFET cell structure, including a substrate, and a first epitaxial layer and a second epitaxial layer stacked sequentially on the top surface of the substrate in a direction away from the substrate;

[0024] The first epitaxial layer includes P-shaped pillars extending from the top surface of the first epitaxial layer into the first epitaxial layer to a predetermined depth and spaced apart along a first direction parallel to the top surface.

[0025] The second epitaxial layer includes a top surface extending through the second epitaxial layer and a P-type contact region extending through the second epitaxial layer in the direction toward the substrate, and being disposed one-to-one with and in contact with the P-type pillars; wherein the P-type pillars and the P-type contact regions both include arc-shaped side surfaces.

[0026] In the aforementioned SiC MOSFET cell structure, the first epitaxial layer forms N-pillars. By alternating N / P pillars, the breakdown voltage can be increased while maintaining a low on-resistance, thereby significantly reducing the device's conduction loss and improving the constraint relationship between breakdown voltage and on-resistance in traditional power SiC MOSFETs. The P-type contact region can prevent free electrons from diffusing into adjacent cells.

[0027] In some embodiments, the preset depth is associated with the vertical distance between the P-shaped pillar and the substrate, and the vertical distance is not less than 0.5 micrometers.

[0028] Thirdly, this application also provides a SiC MOSFET power device, comprising a cell structure prepared by the preparation method described in any of the above embodiments; or comprising a cell structure described in any of the above embodiments.

[0029] The SiC MOSFET power device provided in this application can withstand higher voltages with the same cell size and even with a thinner epitaxial layer. Compared with traditional superjunction trench gate SiC MOSFET power devices, it has the advantages of low on-resistance, high voltage withstand capability, and low process difficulty.

[0030] Fourthly, this application also provides an electronic device comprising a cell structure prepared by the preparation method described in any of the above embodiments; or comprising a SiC MOSFET power device as described in the above embodiments; or a SiC MOSFET power device as described in the above embodiments. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 A cross-sectional schematic diagram of a SiC MOSFET cell structure provided in the prior art;

[0033] Figure 2 A schematic cross-sectional view of a conventional superjunction SiC MOSFET cell structure provided in the prior art;

[0034] Figure 3 This is a flowchart of a method for fabricating a SiC MOSFET cell structure provided in one embodiment;

[0035] Figure 4 This is a cross-sectional schematic diagram of the structure obtained after forming the first epitaxial layer in step S104 of the SiC MOSFET cell structure fabrication method provided in one embodiment.

[0036] Figure 5 This is a cross-sectional schematic diagram of the structure obtained after forming the first trench in step S1062 of the SiC MOSFET cell structure fabrication method provided in one embodiment;

[0037] Figure 6 This is a schematic cross-sectional view of the structure obtained after forming the first P-type material layer in step S1064 of the SiC MOSFET cell structure fabrication method provided in one embodiment.

[0038] Figure 7 This is a schematic cross-sectional view of the structure obtained after forming a P-type pillar in step S1066 of the SiC MOSFET cell structure fabrication method provided in one embodiment.

[0039] Figure 8 This is a schematic cross-sectional view of the structure obtained after forming the second epitaxial layer in step S108 of the SiC MOSFET cell structure fabrication method provided in one embodiment.

[0040] Figure 9 This is a schematic cross-sectional view of the structure obtained after forming an N-type material layer in step S1104 of the SiC MOSFET cell structure fabrication method provided in one embodiment.

[0041] Figure 10aThis is a cross-sectional schematic diagram of the structure obtained after forming a P-type contact region in step S1106 of the SiC MOSFET cell structure fabrication method provided in one embodiment.

[0042] Figure 10b This is a schematic cross-sectional view of a half-cell structure of a SiC MOSFET cell structure provided in one embodiment;

[0043] Figure 11 for Figure 10a A schematic cross-sectional view of the semiconductor structure obtained after the second trench is formed in the SiC MOSFET cell structure shown.

[0044] Figure 12 for Figure 11 The diagram shows a cross-sectional view of the semiconductor structure obtained after the gate oxide layer is formed on the SiC MOSFET cell structure shown.

[0045] Figure 13 for Figure 12 The diagram shows a cross-sectional view of the semiconductor structure obtained after the gate conductive layer is formed in the SiC MOSFET cell structure shown.

[0046] Figure 14 for Figure 13 The diagram shows a cross-sectional view of the semiconductor structure obtained after the source / drain metal layers are formed in the SiC MOSFET cell structure shown.

[0047] Explanation of reference numerals in the attached figures:

[0048] 10. Substrate; 20. First epitaxial layer; 201. First trench; 202. First P-type material layer; 21. P-type pillar; 30. Second epitaxial layer; 301. Second P-type material layer; 302. N-type material layer; 31. P-type contact region; 32. P-type body region; 33. N-type source region; 401. Second trench; 40. Trench gate structure; 41. Gate oxide layer; 42. Gate conductive layer; 43. Gate dielectric layer; 50. Source metal layer; 60. Drain metal layer. Detailed Implementation

[0049] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0051] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0052] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0053] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0054] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of this application, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of this application.

[0055] Existing trench-gate SiC MOSFET device structures, such as Figure 1 As shown above, the trench gate structure of the trench gate SiC MOSFET device is embedded in the epitaxial layer to form a vertical channel. Figure 2 This diagram shows a cross-sectional schematic of a conventional superjunction SiC MOSFET cell structure in the prior art. As one of the important and mature technologies in this field, the superjunction is based on charge balance. Its core principle is to achieve higher breakdown voltage and lower on-resistance without affecting switching speed by introducing alternating, highly doped P-type and N-type semiconductor pillars in the drift region. Compared to traditional SiC MOSFET power devices, it achieves a better trade-off between on-resistance and breakdown voltage, thus gaining widespread use.

[0056] Due to the unique properties of SiC materials, the fabrication of SiC superjunctions presents certain challenges. The main methods include multiple epitaxial-ion implantation processes and trench etching-epitaxy backfilling processes. The former can form high-quality superjunctions with relatively low interface state density and lattice defects, but the lateral width of the P pillars cannot be controlled. Furthermore, since the epitaxial cost of SiC is much higher than that of Si, the process cost increases rapidly with the increase of epitaxial thickness. The latter can effectively reduce impurity compensation between N / P pillars, but as the cell size shrinks, the aspect ratio of the P pillars further increases, and the device yield decreases due to limitations in the backfilling process.

[0057] In this embodiment, the substrate may include a first surface located on the front side and a back surface, i.e., a second surface, opposite to the front side. Ignoring the flatness of the first and second surfaces, a first direction parallel to the first surface is defined, and the direction toward the substrate includes a second direction perpendicular to the first surface of the substrate. Intersecting (e.g., perpendicular) first and third directions are defined on the top and bottom surfaces of the substrate (i.e., the plane in which the substrate lies). For example, the arrangement direction of the P-shaped pillars is the first direction, and the first and second directions are perpendicular to each other. In this embodiment, the first direction is defined as the Y-axis direction, and the second direction is defined as the X-axis direction.

[0058] Based on this, please refer to Figure 3 This application provides a method for fabricating a SiC MOSFET cell structure, comprising: steps S102-S110.

[0059] The semiconductor structure obtained after steps S102-S110 can be found in [reference]. Figure 14 For ease of understanding this application, Figure 14 This application provides an example of a SiC MOSFET cell structure prepared using the method described herein. Other suitable examples of SiC MOSFET cell structures prepared using this application are also possible, and no limitations are imposed herein.

[0060] Step S102: Provide substrate 10.

[0061] For example, substrate 10 can be a single-layer structure or a multi-layer structure. For instance, substrate 10 can include a SiC substrate or any combination of other semiconductor materials, insulating materials, and conductive materials. SiC is mainly classified into 3C-SiC, 4C-SiC, and 6C-SiC according to different crystal forms. These three crystal forms have different material properties, and a specific substrate 10 can be selected according to the type, function, and other characteristics of the power device. Therefore, the type of substrate should not limit the scope of protection of this disclosure. Substrate 10 may include word line structures and capacitor contact structures, etc., which are not closely related to the inventive point of this solution and are therefore omitted.

[0062] Step S104: Form a first epitaxial layer 20 covering the substrate 10.

[0063] For example, the first epitaxial layer 20 has the same conductivity type and material as the substrate 10, but the doping concentration in the substrate 10 is greater than the doping concentration in the first epitaxial layer 20. In the embodiments mentioned in this application, the substrate 10 and the first epitaxial layer 20 include N-type ionic impurities, such as pentavalent elements, nitrogen (N), phosphorus (P), arsenic (As), etc., to provide additional free electrons, enabling the substrate 10 and the first epitaxial layer 20 to exhibit N-type conductivity characteristics. It should be understood that specific numerical parameters such as doping concentration can be set in other ways, and are not strictly limited in this embodiment.

[0064] Specifically, please refer to Figure 4 The structure described above can be formed using one or more deposition processes, including but not limited to chemical vapor deposition (CVD), atomic layer deposition (ALD), and high-density plasma (HDP). The thickness (dimension along the OX direction) of the first epitaxial layer 20 is greater than the thickness of the substrate 10, and the specific thickness can be determined according to the voltage that the SiC MOSFET power device needs to withstand.

[0065] Step S106: Form P-shaped pillars 21 in the first epitaxial layer 20, extending from the top surface of the first epitaxial layer 20 to a predetermined depth D, and spaced apart in the OY direction parallel to the top surface.

[0066] For example, D represents a preset depth. The material of the P-type pillar 21 can be the same as or different from that of the first epitaxial layer 20. In this embodiment, the material of the P-type pillar 21 includes SiC. It can be a trivalent impurity doped with P-type ions, such as boron (B) or aluminum (Al), to provide a small number of free holes and form a P-type conductive type.

[0067] Specifically, please refer to Figures 5-7 In some embodiments, step S106 further includes:

[0068] Please see Figure 5 Step S1062: Form a first trench 201 in the first epitaxial layer 20 that extends into the first epitaxial layer 20 to a preset depth D and is spaced apart along the OY direction.

[0069] For example, dry etching and / or wet etching can be used. Dry etching includes at least one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high-density plasma etching (HDP). The etching solution used in the wet etching process can be hydrofluoric acid (HF), nitric acid (HNO3), or potassium hydroxide (KOH). Both processes have their advantages and disadvantages, and the specific choice should be made according to different processing objects, requirements, and actual conditions. Of course, those skilled in the art will understand that this step usually requires a photolithography process using a mask to define the position and shape of the first trench 201 before etching is performed to form the first trench 201.

[0070] The depth D (dimension along the OX direction) of the first trench 201 must be less than the thickness of the first epitaxial layer 20.

[0071] Please see Figure 6 Step S1064: Form a first P-type material layer 202 by filling the first trench 201.

[0072] Specifically, the first P-type material layer 202 filling the first trench 201 can be obtained by any of the following growth processes, but not limited to vapor phase epitaxy (VPE), liquid phase epitaxy (LVPE), and molecular beam epitaxy (MBE).

[0073] It should be noted that the doping concentration of the first P-type material layer 202 is comparable to that of the first epitaxial layer 20.

[0074] Please see Figure 7 Step S1066: Remove part of the first P-type material layer 202 to form a P-type pillar 21; wherein the top surface of the P-type pillar 21 is flush with the top surface of the first epitaxial layer 20.

[0075] Specifically, planarization processes such as chemical mechanical polishing (CMP) or etch-back can be used to remove the first P-type material layer whose top surface is higher than the top surface of the first epitaxial layer 20. The remaining first P-type material layer is used to form P-type pillars. The N-type first epitaxial layer 20 located adjacent to the P-type pillars forms N-type pillars, which are alternately arranged with the P-type pillars along the OY direction.

[0076] Since the doping concentrations of P-type and N-type pillars are similar and they have built-in lateral electric fields, when the device is reverse blocked, the electric field lines of the N-type pillars all point to the adjacent P-type pillars. The charge field and the potential field are perpendicular to each other, which effectively reduces the intensity of the peak electric field in the device and prevents the device from being broken down prematurely.

[0077] Please see Figure 8 Step S108: Form a second epitaxial layer 30 covering the top surface of the first epitaxial layer 20.

[0078] For example, the second epitaxial layer 30 has the same conductivity type and material as the first epitaxial layer 20, and can be formed by any of the following processes: CVD, ALD, or HDP. In the embodiments provided in this application, the first epitaxial layer 20 is used to form a superjunction structure, and the second epitaxial layer 30 is used to form the overall SiC MOSFET cell structure. Compared with the prior art method of directly generating the overall MOSFET cell structure in one step and forming the superjunction structure within the overall structure, the trench depth required for separately preparing the superjunction structure is shallower, thereby reducing the filling difficulty.

[0079] Step S110: Perform an ion implantation process on the second epitaxial layer 30 to form a P-type contact area 31 that passes through the top surface of the second epitaxial layer 30 and penetrates the second epitaxial layer 30 along the OX direction, and is one-to-one with the P-type pillar 21 and in contact with each other; wherein, both the P-type pillar 21 and the P-type contact area 31 include arc-shaped side surfaces.

[0080] In some embodiments, the first dimension of the P-type contact area 31 along the OY direction within the P-type body area 32 first increases and then decreases in the OX direction; the second dimension of the P-type post 21 along the OY direction first increases and then decreases in the OX direction; the maximum value of the first dimension is greater than the maximum value of the second dimension.

[0081] Specifically, the curved side surface can avoid leakage caused by charge accumulation at right angles. P-type pillars with curved side surfaces have a higher doping concentration than P-type pillars with flat side surfaces. If the width remains constant, the depth of the P-type pillar required to achieve charge balance is shallower, making filling easier; if the depth remains constant, the width of the P-type pillar required to achieve charge balance is smaller, and the cell size can be further reduced.

[0082] Specifically, please refer to Figures 9-10b In some embodiments, step S110 further includes:

[0083] Step S1102: The second epitaxial layer 30 is subjected to an ion implantation process to form a second P-type material layer 301 that completely overlaps with the second epitaxial layer 30;

[0084] Step S1104: An N-type material layer 302 is formed on the second P-type material layer 301, extending through the top surface of the second P-type material layer 301 and into the second P-type material layer 301.

[0085] Please see Figure 9 Specifically, without the need for a mask, a blanket-type ion implantation process is performed on the second epitaxial layer 30 and the second P-type material layer. The N-type material layer 302 is heavily doped, and the doping concentration is greater than that of the first epitaxial layer 20.

[0086] Please see Figure 10a Step S1106: An ion implantation process is performed on the second P-type material layer 301 and the N-type material layer 302 to form a heavily doped P-type contact region 31. The remaining second P-type material layer 301 is used to form the P-type body region 32; the remaining N-type material layer is used to form the N-type source region 33. The ion implantation dose of the P-type contact region 31 is greater than that of the P-type pillar 21 and the P-type body region 32, and it is used to form an ohmic contact with the source metal, and as... Figure 10b As shown, the P-type body region 32 and N-type source region 33 within the adjacent SiC MOSFET cell structure A and cell structure B are isolated.

[0087] Step S1108: Perform a rapid thermal annealing process on the structure obtained in step S1106.

[0088] Specifically, the rapid thermal annealing process can activate internal doped ions and repair lattice damage caused by ultra-high energy ion implantation. During this process, doped ions in the P-type pillar 21 will diffuse laterally to a certain extent. Therefore, it is necessary to appropriately reduce the width of the first trench 201 obtained by etching (the dimension along the OY direction) so that it is smaller than the lateral diffusion distance of the P-pillar, thereby ensuring the accuracy of the superjunction structure after ion diffusion.

[0089] Please see Figures 11-14 In some embodiments, after step S110, a trench gate structure 40 is formed in the second epitaxial layer 30 between adjacent P-type contact areas 31.

[0090] Please see Figure 11 A second trench 401 is formed between adjacent P-type contact areas 31, extending inward from the top surface of the second epitaxial layer 30.

[0091] For example, selective masking and etching are used to create a second trench 401 between adjacent P-pillars 21. The second trench 401 penetrates the second epitaxial layer 30 and extends into the first epitaxial layer 20, with a width (dimension along the OY direction) smaller than the spacing between adjacent P-pillars 21. The corners of the second trench 401 are rounded to reduce the electric field strength at the bottom corners.

[0092] Please see Figure 12A gate oxide layer 41 is formed covering the inner surface of the second trench 401.

[0093] For example, the material of the gate oxide layer includes, but is not limited to, silicon dioxide (SiO2), aluminum oxide (Al2O3), titanium oxide (TiO2), strontium titanate (SrTiO3), or a combination of the above materials.

[0094] Please see Figure 13 The second trench 401 is filled to form a gate conductive layer 42 whose top surface is flush with the top surface of the gate oxide layer 41.

[0095] For example, the above structure is formed by combining CMP process and deposition process, and the material of gate conductive layer 42 may include, but is not limited to, doped polysilicon or metal material.

[0096] In the SiC MOSFET cell structure fabrication method provided in this application, by changing the fabrication order of the trench gate structure 40 with the P-type contact region 31, the P-type body region 32 and the N-type source region, the influence of high-energy ion implantation on the trench gate structure 40 is avoided, thus ensuring the quality of the trench gate structure 40.

[0097] Please see Figure 14 This application also includes forming a gate dielectric layer 43 on the top surface of the trench gate structure 40; a drain metal layer 60 on the back side of the substrate 10; and a source metal layer 50 on the second epitaxial layer 30 and the front side of the trench gate structure 40, which will not be described in detail here. The source metal layer 50 and the drain metal layer 60 may be made of one or more of the following metals, but not limited to tungsten (W), silver (Ag), gold (Au), aluminum (Al), chromium (Cr), titanium (Ti), nickel (Ni), and copper (Cu).

[0098] It should be understood that, although Figure 3 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 3 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0099] Please see Figure 14In some embodiments, this application provides a SiC MOSFET cell structure, including a substrate 10 and a first epitaxial layer 20 and a second epitaxial layer 30 stacked sequentially on the top surface of the substrate 10 along the XO direction (opposite to OX). The first epitaxial layer 20 includes P-type pillars 21 extending from the top surface of the first epitaxial layer 20 into the first epitaxial layer 20 to a predetermined depth D and spaced apart in the OY direction. The second epitaxial layer 30 includes P-type contact regions 31 extending from the top surface of the second epitaxial layer 30 and penetrating the second epitaxial layer 30 along the OX direction, and being disposed one-to-one with and in contact with the P-type pillars 21. The P-type pillars 21 and the P-type contact regions 31 both include arc-shaped side surfaces.

[0100] Specifically, the vertically conductive N-type first epitaxial layer 20 is sandwiched between the P-type body region 32 and the P-type pillar 21. In the OY direction, the P-type pillar 21 forms a PN junction with both sides of the N-region; in the OX direction, the P-type pillar 21 forms a PN junction with the N-region surrounding the bottom. When reverse biased, a depletion layer is generated, forming a vertical electric field, which further improves the device's breakdown voltage. Therefore, the same breakdown voltage can be achieved by reducing the thickness of the first epitaxial layer and lowering the on-resistance.

[0101] Please continue reading. Figure 14 In some embodiments, the preset depth D is associated with the vertical distance between the P-shaped pillar 21 and the substrate 10; the vertical distance is not less than 0.5 micrometers.

[0102] Specifically, in the above-mentioned SiC MOSFET cell structure, a semi-superjunction structure is used to replace the traditional full superjunction structure. In practical applications, due to the shallower trenches, the semi-superjunction structure has lower manufacturing costs and higher conversion value.

[0103] In some embodiments, this application also provides a SiC MOSFET power device.

[0104] When the SiC MOSFET power device is turned on, an inversion layer is formed in the P-type body region 32 to create a conductive channel. Electrons in the N-type source region 33 flow to the drain under the drive of the source-drain voltage. When the SiC MOSFET is turned off, the P-type pillar 21 and the N-type first epitaxial layer 20 form a PN junction. Depletion layers are formed on both sides of the PN junction, establishing a horizontal rectangular lateral electric field, thereby optimizing the internal electric field distribution of the device and improving the device's withstand voltage. In addition, the device requires a thinner epitaxial layer to withstand the same voltage, thus reducing the device's on-resistance.

[0105] In some embodiments, this application also provides an electronic device. Obviously, according to the principles of the present invention, the N-type and P-type in the embodiments can be interchanged without affecting the content of the present invention.

[0106] This application provides a SiC MOSFET cell structure, its fabrication method, device, and equipment, which have the following unexpected technical effects:

[0107] In the SiC MOSFET cell structure provided in this application, P-type pillars are introduced into the N-type first epitaxial layer of the conventional SiC MOSFET cell structure, forming alternating P-type and N-type pillars along a first direction. This improves the electric field distribution within the SiC MOSFET cell structure and enhances the device's breakdown voltage. As the cell size continues to shrink, the SiC MOSFET cell structure fabrication method ensures that the aspect ratio of the deep trench is not too large, thereby reducing the fabrication difficulty of the superjunction structure and improving the overall cost-effectiveness of the electronic device. This allows SiC MOSFET power devices based on this cell structure to reduce power loss, improve energy utilization efficiency, and exhibit better breakdown voltage and lower on-resistance compared to SiC MOSFET power devices with the same cell size or epitaxial layer thickness.

[0108] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0109] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for preparing a SiC MOSFET cell, characterized in that: include: providing a substrate; forming a first epitaxial layer covering the substrate; Forming in the first epitaxial layer P-type columns extending through the top surface of the first epitaxial layer into the first epitaxial layer to a preset depth and spaced apart along a first direction parallel to the top surface; forming a second epitaxial layer covering a top surface of the first epitaxial layer; An ion implantation process is performed on the second epitaxial layer to form a P-type contact region which passes through the top surface of the second epitaxial layer and penetrates the second epitaxial layer in a direction toward the substrate and is arranged one-to-one with the P-type column and contacts with each other; wherein the P-type column and the P-type contact region both include a side surface with an arc shape.

2. The preparation method according to claim 1, characterized in that: Forming the P-type column includes: forming first trenches in the first epitaxial layer, the first trenches extending into the first epitaxial layer to a preset depth and spaced apart along the first direction; Forming a first P-type material layer filling the first trench; A portion of the first P-type material layer is removed to form the P-type column; wherein the top surface of the P-type column is flush with the top surface of the first epitaxial layer.

3. The preparation method according to claim 1, characterized in that: Before forming the P-type contact region, it also includes: Performing an ion implantation process on the second epitaxial layer to form a second P-type material layer completely overlapping the second epitaxial layer; forming an N-type material layer on the second P-type material layer, passing through a top surface of the second P-type material layer and extending into the second P-type material layer; and After forming the P-type contact region, the remaining second P-type material layer is used to form a P-type body region; and the remaining N-type material layer is used to form an N-type source region.

4. The preparation method according to claim 3, characterized in that: A first dimension of the P-type contact region along the first direction in the P-type body region first increases and then decreases in a direction toward the substrate; The second dimension of the P-type column along the first direction first increases and then decreases in the direction toward the substrate; The maximum value of the first dimension is greater than the maximum value of the second dimension.

5. The preparation method according to any one of claims 1 to 4, characterized in that: A trench gate structure is formed in the second epitaxial layer between adjacent P-type contact regions, comprising: forming a second trench extending inwardly through the top surface of the second epitaxial layer between adjacent P-type contact regions; forming a gate oxide layer covering the inner surface of the second trench; The second trench is filled to form a gate conductive layer whose top surface is flush with the top surface of the gate oxide layer.

6. The preparation method according to any one of claims 1 to 4, characterized in that: Include at least one of the following characteristics: The conductivity types of the first epitaxial layer and the second epitaxial layer are both N-type; The ion implantation dosage of the P-type contact region is greater than that of the P-type column and the P-type body region.

7. A SiC MOSFET cell structure, characterized in that: It comprises a substrate, and a first epitaxial layer and a second epitaxial layer which are located on the top surface of the substrate and are sequentially stacked in a direction away from the substrate; The first epitaxial layer includes P-type columns extending into the first epitaxial layer to a preset depth through the top surface of the first epitaxial layer and spaced apart along a first direction parallel to the top surface; The second epitaxial layer includes a P-type contact region which passes through the top surface of the second epitaxial layer and penetrates the second epitaxial layer in a direction toward the substrate and is arranged one-to-one with the P-type column and contacts each other; wherein the P-type column and the P-type contact region both include arc-shaped side surfaces.

8. The SiC MOSFET cell structure according to claim 7, characterized in that: The preset depth is associated with a vertical distance between the P-type pillar and the substrate; The vertical spacing is not less than 0.5 microns.

9. A SiC MOSFET power device, characterized in that: It includes a cellular structure prepared by the preparation method described in any one of claims 1 to 6; or it includes the cellular structure described in any one of claims 7 to 8.

10. An electronic device, characterized in that: A cellular structure comprising a cellular structure prepared by the preparation method according to any one of claims 1 to 6; A cellular structure comprising any one of claims 7 to 8; or A SiC MOSFET power device comprising the SiC MOSFET power device as claimed in claim 9.

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