Metal-oxide-semiconductor field effect transistor (MOSFET) device of gallium oxide heterojunction and manufacturing method

Abstract

The invention discloses a gallium oxide heterojunction MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a manufacturing method thereof, and mainly solves the problem of high on-resistance of the existing similar devices. The invention discloses a Ga2O3 heterojunction field effect transistor which comprises a drain electrode (1), a Ga2O3 substrate (2), a Ga2O3 epitaxial layer (3), a Ga2O3 layer (4) injected with acceptor ions, a grid electrode (8) and a source electrode (9), and an unintentionally doped Ga2O3 layer (5) and an AlGaO layer (6) are sequentially arranged on the Ga2O3 layer (4) injected with the acceptor ions to form a heterojunction; a groove is formed in the middle of the AlGaO layer (6), and an insulated gate dielectric layer (7) is arranged on the inner wall of the groove; a grid electrode (8) is positioned at the upper part of the insulated gate dielectric layer; and the source electrodes (9) are positioned at the two ends of the AlGaO layer (6). According to the invention, two-dimensional electron gas 2DEG is generated through the introduced heterojunction, the mobility of carriers is improved, the on-resistance is reduced, the on-current is improved, and the device can be used as a power and high-voltage switching device.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a gallium oxide heterojunction metal oxide semiconductor field effect transistor, which can be used for power devices and switch devices. Background Art

[0002] Compared with SiC and GaN semiconductor materials, β-Ga2O3 has many unique advantages. The band gap of β-Ga2O3 is 4.8-4.9eV, and the theoretical breakdown field strength can be as high as 8MV / cm, which is more than twice the theoretical limit of SiC and GaN. The Baliga figure of merit is much higher than other semiconductor materials. In addition, high-quality single crystal β-Ga2O3 can be mass-produced by melting methods, including optical floating zone method, guided mode method, Czochralski method and vertical Bridgman method, which will greatly reduce the cost of future materials. And β-Ga2O3 can be produced in 1×10 15 -1×10 20 cm -3 Precise electron concentration control can be achieved within an ultra-wide range. In order to fully utilize β-Ga2O3 materials, vertical devices have become mainstream because they can achieve higher power density chips. In addition, improving the breakdown voltage of vertical MOSFETs does not require sacrificing chip area because the breakdown voltage is proportional to the thickness of the drift layer. However, the lack of p-type doping technology has limited the development of bipolar power devices, resulting in little research on β-Ga2O3 vertical transistors, and more efforts are needed to achieve high-performance enhancement mode transistors.

[0003] Early vertical β-Ga2O3 field effect transistors can be divided into fin transistors FinFET and current aperture vertical pad transistors CAVET. Recently, u-type gate trench MOSFET based on N ion implantation has been prepared. In this structure, the trench is etched from the source to the drift layer, and the gate oxide is grown on the sidewalls and then filled with appropriate conductive materials. After the gate voltage is applied, the current flows along the channel on the sidewalls of the trench.

[0004] Yongjian Ma et al. published an article titled "702.3 A·cm -2 / 10.4mΩ·cm 2 β-Ga2O3U-Shape Trench Gate MOSFETWith N-Ion Implantation," gives a U-shaped gate trench MOSFET device structure, such as Figure 1As shown, it includes a drain, a Ga2O3 substrate, a Ga2O3 epitaxial layer, a Ga2O3 layer injected with main ions, a highly doped n-type Ga2O3 layer, and a source from bottom to top; a groove is provided on the surface of the highly doped n-type Ga2O3 layer, which is sunken toward the Ga2O3 substrate, and the bottom of the groove reaches the Ga2O3 epitaxial layer; the groove includes an insulating gate dielectric layer and a gate. This device will introduce a large number of etching defects when etching the groove, resulting in poor channel surface quality, reduced channel carrier mobility, and a large on-resistance. Reverse breakdown characteristics Summary of the invention

[0005] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and to provide a gallium oxide heterojunction MOSFET device and a method for manufacturing the same, so as to increase the channel carrier mobility and improve the conduction performance of the device.

[0006] The key technology for achieving the purpose of the present invention is to increase the carrier concentration and mobility in the device channel by changing the structure of the device to compensate for the low conduction performance caused by etching damage.

[0007] To achieve the above object, the technical solution of the present invention is as follows:

[0008] 1. A gallium oxide heterojunction MOSFET device, comprising: a drain, a Ga2O3 substrate, a Ga2O3 epitaxial layer, a Ga2O3 layer implanted with acceptor ions, a gate and a source, characterized in that: an unintentionally doped Ga2O3 layer and an AlGaO layer are sequentially arranged on the Ga2O3 layer implanted with acceptor ions to improve carrier concentration and carrier mobility; a groove is arranged in the middle of the AlGaO layer, and an insulating gate dielectric layer is arranged on the inner wall of the groove; the gate is located on the upper part of the insulating gate dielectric layer; and the source is located at both ends of the AlGaO layer.

[0009] Furthermore, the direction of the groove is from the surface of the AlGaO layer downward, and the bottom thereof reaches the Ga2O3 epitaxial layer, with a depth of 4um-6um.

[0010] Furthermore, the Ga2O3 substrate is doped with Sn or Si with high n-doping + β-Ga2O3 material, doping concentration is 1×10 18 -5×10 19 cm -3 , with a thickness of 300-600nm; the Ga2O3 epitaxial layer is doped with Sn or Si low n - β-Ga2O3 material, doping concentration is 5×10 15 -1×10 17 cm -3 , thickness is 6-10um.

[0011] Furthermore, the Ga2O3 layer injected with acceptor ions is made of high-resistance layer β-Ga2O3 material doped with N or Mg, and its doping concentration is 1×10 18 -5×10 18 Pieces / cm 3 , with a thickness of 400-800nm; the highly doped n-type Ga2O3 layer is doped with Sn or Si + β-Ga2O3 material, doping concentration is 1×10 19 -5×10 19 cm -3 , with a thickness of 100-200nm; the AlGaO layer is made of highly doped AlGaO material doped with Si, with a doping concentration of 1×10 18 -5×10 18 cm -3 , with a thickness of 20-30nm; the insulating gate dielectric layer is made of Al2O3 material, with a thickness of 20-60nm.

[0012] 2. A method for manufacturing a gallium oxide heterojunction MOSFET device, characterized in that it comprises the following steps:

[0013] S1) using an MBE process, depositing a β-Ga2O3 material with a thickness of 4-10 um on the Ga2O3 substrate layer to form a Ga2O3 epitaxial layer;

[0014] S2) depositing a β-Ga2O3 material with a thickness of 400-800 nm on the Ga2O3 epitaxial layer by using MOCVD and ion implantation process to form a Ga2O3 layer implanted with acceptor ions;

[0015] S3) using a MOCVD process, depositing a β-Ga2O3 material with a thickness of 100-200 nm on the Ga2O3 layer implanted with acceptor ions to form an unintentionally doped n-type Ga2O3 layer;

[0016] S4) using a MOCVD process, depositing an AlGaO material with a thickness of 20-30 nm on the unintentionally doped n-type Ga2O3 layer to form a highly doped AlGaO layer;

[0017] S5) using RIE process to etch a groove on the surface of the highly doped n-type Ga2O3 layer, wherein the bottom of the groove reaches the Ga2O3 epitaxial layer and has a depth of 4um-6um;

[0018] S6) using an ALD process, depositing Al2O3 with a thickness of 20-60 nm on the inner wall of the trench and the AlGaO layer to form an insulating gate dielectric layer;

[0019] S7) using E-Beam and stripping process, depositing 20-60nm / 120-250nm Ni / Au on the insulating gate dielectric layer, and then placing it in acetone solution for stripping to form a gate;

[0020] S8) using an E-Beam process, depositing 20-60nm / 120-250nm of Ti / Au on both ends of the AlGaO layer, and then annealing for 1-3min in a N2 atmosphere at 300-550°C to form a source electrode;

[0021] S9) Using the E-Beam process, after depositing 20-60nm / 120-250nm of Ti / Au on the back side of the Ga2O3 substrate, annealing is performed for 1-3min in a N2 atmosphere at 300-550°C to form a drain, thereby completing the device manufacturing.

[0022] The present invention sequentially arranges an unintentionally doped Ga2O3 layer and an AlGaO layer on a Ga2O3 layer injected with acceptor ions, which can form a heterojunction to generate a two-dimensional electron gas. Since the two-dimensional electron gas moves only in a thin layer with a thickness of 4nm, it has a high carrier concentration and a high carrier mobility, which can effectively reduce the lattice scattering between impurities, so that the electrons in the two-dimensional electron gas have an extremely high maximum saturation velocity, effectively reduce the on-resistance, and improve the on-capability of the device. At the same time, since the present invention arranges a groove in the middle of the AlGaO layer and arranges a high-k insulating gate dielectric layer on the inner wall of the groove, it can not only significantly reduce the electron tunneling effect, reduce the gate leakage current and the device power consumption, but also has a lower gate-source capacitance, significantly improving the switching speed of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the structure of an existing gallium oxide MOSFET device;

[0024] Figure 2 A schematic diagram of the structure of a gallium oxide heterojunction MOSFET according to the present invention;

[0025] Figure 3 The figure is a schematic diagram of the preparation process of the gallium oxide heterojunction MOSFET device of the present invention. DETAILED DESCRIPTION

[0026] The following results and drawings describe the embodiments of the present invention in detail, but are not limited to the embodiments described herein.

[0027] refer to Figure 2 The gallium oxide heterojunction MOSFET device of this example includes: a drain 1, a Ga2O3 substrate 2, a Ga2O3 epitaxial layer 3, a Ga2O3 layer 4 injected with acceptor ions, an unintentionally doped Ga2O3 layer 5, an AlGaO layer 6, an insulating gate dielectric layer 7, a gate 8 and a source 9. Among them:

[0028] The Ga2O3 substrate 2 is a highly n-doped Ga2O3 substrate doped with Sn or Si. + β-Ga2O3 material, doping concentration is 1×10 18 -5×10 19 cm -3 , thickness is 300-600nm;

[0029] The drain electrode 1 is located on the back of the Ga2O3 substrate 2 and is made of a metal material of Ti / Au with a thickness of 20-60nm / 120-250nm;

[0030] The Ga2O3 epitaxial layer 3 is located on the upper part of the Ga2O3 substrate 2 and is made of low-doped Sn or Si. - β-Ga2O3 material, doping concentration is 5×10 15 -1×10 17 cm -3 , thickness is 4-10um;

[0031] The Ga2O3 layer 4 injected with acceptor ions is located on the upper part of the Ga2O3 epitaxial layer 3, and is made of a high-resistance layer β-Ga2O3 material doped with N or Mg, with a doping concentration of 1×10 18 -5×10 18 Pieces / cm 3 , thickness is 400-800nm;

[0032] The unintentionally doped n-type Ga2O3 layer 5 is located on the upper part of the Ga2O3 layer 4 injected with acceptor ions, and is made of β-Ga2O3 material with a carrier concentration of 1×10 15 -1×10 16 cm -3 , thickness is 100-200nm;

[0033] The AlGaO layer 6 is located on the upper part of the unintentionally doped n-type Ga2O3 layer 5, and is made of AlGaO material doped with Si, with a doping concentration of 1×10 18 -5×10 18 cm -3 , with a thickness of 20-30nm; a groove is opened in the middle of the AlGaO layer for making an insulating gate dielectric layer;

[0034] The insulating gate dielectric layer 7 is located at the bottom and sidewall of the groove of the AlGaO layer 6, and is made of Al2O3 material with a thickness of 20-60nm;

[0035] The gate 8 is located on the upper part of the insulating gate dielectric layer 7 and is made of 20-60nm / 120-250nm Ni / Au metal material;

[0036] The source electrode 9 is located at both ends of the AlGaO layer 6 and is made of a metal material of 20-60nm / 120-250nm Ti / Au.

[0037] Reference Figure 3 The present invention provides the following three embodiments of the method for manufacturing a gallium oxide heterojunction MOSFET device:

[0038] Example 1: Doping n in Sn + On the β-Ga2O3 material substrate, a 100nm thick and 1×10 15 cm -3 The unintentionally doped Ga2O3 layer has a thickness of 20nm and a Si doping concentration of 1×10 18 cm -3 Gallium oxide heterojunction MOSFET device with AlGaO layer.

[0039] Step 1: Using MBE process, a Ga2O3 epitaxial layer is grown on the Ga2O3 substrate layer, such as Figure 3 (a).

[0040] 1.1) The Sn doping concentration is 1×10 18 cm -3 , thickness of 300nm + β-Ga2O3 substrate 2, sequentially cleaned with organic matter and deionized water, and dried with high-purity N2;

[0041] 1.2) After cleaning, the highly doped n + The β-Ga2O3 substrate is placed in a molecular beam epitaxy MBE growth chamber, high-purity 6N Ga and high-purity 4N SnO2 powders are heated in a K chamber to provide Ga and Sn elements, and a mixed gas of 5% O3 and 95% O2 is used to provide oxygen elements;

[0042] 1.3) Set 2×10 for Ga element -4 Pa pressure to make it enter the reaction chamber, and introduce a mixed gas with a flow rate of 5 sccm into the reaction chamber, and heat the substrate to 560 ° C to obtain a doping concentration of 5×10 15 cm -3 , Sn-doped n- - β-Ga2O3 epitaxial layer 3.

[0043] Step 2, using MOCVD and ion implantation process, grow a Ga2O3 layer implanted with acceptor ions on the Ga2O3 epitaxial layer, such as Figure 3 (b).

[0044] 2.1) Using TEGa and O2 as gallium source and oxygen source, and N2 as carrier gas, a thin film is grown on the β-Ga2O3 epitaxial layer by chemical vapor deposition (MOCVD);

[0045] 2.2) Place the film in an ion implanter and inject at a dose of 1×10 14 cm -3 , under the process condition of an implantation energy of 380 KeV, ion implantation is performed on the film to form a β-Ga2O3 layer implanted with N ions;

[0046] 2.3) The sample after N ion implantation was placed in a tubular annealing furnace at 1100°C for 25 min to activate the N ions and obtain an implantation concentration of 1×10 18 Pieces / cm 3 , a Ga2O3 layer 4 with acceptor ions having a thickness of 400nm.

[0047] Step 3: Using MOCVD process, an unintentionally doped Ga2O3 layer is grown on the Ga2O3 layer implanted with acceptor ions, such as Figure 3 (c).

[0048] Using chemical vapor deposition (MOCVD) method, TEGa and O2 were used as gallium source and oxygen source, N2 was used as carrier gas, TEGa and O2 flow rates were 50sccm and 2000sccm respectively, the reaction chamber temperature was 600℃, and the growth pressure was 20Torr. Under the process conditions, the epitaxial carrier concentration on the Ga2O3 layer with acceptor ions was 1×10 15 cm -3 , an unintentionally doped Ga2O3 layer 5 with a thickness of 100 nm.

[0049] Step 4: Using MOCVD process, grow AlGaO layer on the unintentionally doped Ga2O3 layer. Figure 3 (d).

[0050] Using MOCVD, TEGa, TMAl and O2 were used as gallium source, aluminum source and oxygen source, N2 was used as carrier gas, the flow rates of TEGa, TMAl and O2 were 50sccm, 20sccm and 2000sccm respectively, the reaction chamber temperature was 600℃, and the growth pressure was 20Torr. Under the process conditions, the epitaxial doping concentration of 1×10 18 cm -3 , an AlGaO layer 6 with a thickness of 20 nm.

[0051] Step 5: Use RIE process to etch grooves on the surface of the AlGaO layer, such as Figure 3 (e).

[0052] Reactive ion etching (RIE) was used to etch the AlGaO layer surface under the process conditions of a chamber pressure of 5.0 Pa, a plasma power of 150 W, and a BCl3 and Ar flow rate of 20 sccm and 10 sccm, respectively, to form a groove with a depth of 4 μm, and the etching damage was repaired with hot phosphoric acid.

[0053] Step 6: Using ALD process, an insulating gate dielectric layer is formed. Figure 3 (f).

[0054] By using the atomic layer deposition ALD process, under the process conditions of trimethylaluminum TMA and H2O as aluminum source and oxygen source, a reaction chamber temperature of 200°C and a growth rate of 0.07nm / cycle, Al2O3 with a thickness of 20nm is deposited on the inner wall of the trench to form an insulating gate dielectric layer 7.

[0055] Step 7, making a gate electrode, such as Figure 3 (g).

[0056] 7.1) Ni with a thickness of 20 nm and Au with a thickness of 120 nm are sequentially deposited on the insulating gate dielectric layer by an electron beam evaporation E-Beam process. After the metal deposition is completed, it is placed in an acetone solution for stripping to form a gate electrode 8;

[0057] 7.2) The peeled samples were placed in acetone solution, anhydrous ethanol solution, and deionized water for ultrasonic cleaning for 5 minutes each, and then blown dry with pure N2.

[0058] Step 8, make the source electrode, such as Figure 3 (h).

[0059] 8.1) Ti with a thickness of 20 nm and Au with a thickness of 120 nm are sequentially deposited in the source region by electron beam evaporation (E-Beam) process;

[0060] 8.2) The deposited metal is ultrasonically cleaned in acetone and anhydrous ethanol solutions for 5 minutes, and then cleaned with plasma water for 5 minutes, and then blown dry with high-purity N2 to form a source electrode 9;

[0061] 8.3) Thermal annealing was performed at a temperature of 470°C and a nitrogen flow rate of 3 L / min for 1 minute to form a good ohmic resistor.

[0062] Step 9, make a drain electrode, such as Figure 3 (i).

[0063] 9.1) Ti with a thickness of 20 nm and Au with a thickness of 120 nm are sequentially deposited in the drain region by electron beam evaporation (E-Beam) process;

[0064] 9.2) The deposited metal is ultrasonically cleaned in acetone and anhydrous ethanol solutions for 5 minutes, and then cleaned with plasma water for 5 minutes. After being blown dry with high-purity N2, a drain electrode 1 is formed. Then, thermal annealing is performed for 1 minute at a temperature of 470°C and a nitrogen flow rate of 3L / min to form a good ohmic resistance, thereby completing the device manufacturing.

[0065] Example 2, in Sn doped n + On the β-Ga2O3 material substrate, a 150nm thick and 5×10 15 cm -3 The unintentionally doped Ga2O3 layer has a thickness of 25nm and a Si doping concentration of 3×10 18 cm -3 Gallium oxide heterojunction MOSFET device with AlGaO layer.

[0066] Step 1: Using MBE process, a Ga2O3 epitaxial layer is grown on the Ga2O3 substrate layer. Figure 3 (a).

[0067] The Sn doping concentration is 5×10 19 cm -3 , thickness of 600nm + β-Ga2O3 substrate 2, organic cleaning and deionized water cleaning in turn, and blow-dried with high-purity N2; + The β-Ga2O3 substrate is placed in a molecular beam epitaxy MBE growth chamber, high-purity 6N Ga and high-purity 4N SnO2 powders are heated in a K chamber to provide Ga and Sn elements, and a mixed gas of 5% O3 and 95% O2 is used to provide oxygen elements;

[0068] For Ga element, set 2×10 -4 Pa pressure to make it enter the reaction chamber, and introduce a mixed gas with a flow rate of 5 sccm into the reaction chamber, and heat the substrate to 700 ° C to obtain a doping concentration of 1×10 17 cm -3 , Sn-doped n- - β-Ga2O3 epitaxial layer 3.

[0069] Step 2: Using MOCVD and ion implantation process, a Ga2O3 layer implanted with acceptor ions is grown on the Ga2O3 epitaxial layer, such as Figure 3 (b).

[0070] Setting process conditions with TEGa and O2 as gallium source and oxygen source and N2 as carrier gas, epitaxial thin film is grown on β-Ga2O3 epitaxial layer by chemical vapor deposition MOCVD method;

[0071] The film was placed in an ion implanter and the implantation dose was set to 5×10 14 cm -3 , the process condition of implantation energy of 380Kev, ion implantation of the film to form a β-Ga2O3 layer with N ion implantation;

[0072] The sample after N ion implantation was placed in a tubular annealing furnace at 1100°C for 25 min to activate the N ions and obtain an implantation concentration of 5×10 18 Pieces / cm 3 , a Ga2O3 layer 4 with acceptor ions having a thickness of 800nm.

[0073] Step 3: Using MOCVD process, an unintentionally doped Ga2O3 layer is grown on the Ga2O3 layer injected with acceptor ions, such as Figure 3 (c).

[0074] TEGa and O2 were used as gallium source and oxygen source, N2 was used as carrier gas, the flow rates of TEGa and O2 were 50 sccm and 2000 sccm respectively, the reaction chamber temperature was 600℃, and the growth pressure was 20 Torr. Using chemical vapor deposition MOCVD method, the epitaxial carrier concentration of 5×10 15 cm -3 , an unintentionally doped Ga2O3 layer 5 with a thickness of 150nm.

[0075] Step 4: Using MOCVD process, grow AlGaO layer on the unintentionally doped Ga2O3 layer, such as Figure 3 (d).

[0076] The gallium source is TEGa, the aluminum source is TMAl, the oxygen source is O2, the carrier gas is N2, the flow rates of TEGa, TMAl and O2 are 50sccm, 20sccm and 2000sccm respectively, the reaction chamber temperature is 600℃, and the growth pressure is 20Torr. The MOCVD method is used to epitaxially grow the unintentionally doped Ga2O3 layer with a doping concentration of 3×10 18 cm -3 , an AlGaO layer 6 with a thickness of 25 nm.

[0077] Step 5: Use RIE process to etch grooves on the surface of the AlGaO layer, such as Figure 3 (e).

[0078] The chamber pressure was set to 5.0 Pa, the plasma power was set to 150 W, the flow rates of BCl3 and Ar were set to 20 sccm and 10 sccm respectively, and reactive ion etching (RIE) was used to etch a groove of about 6 um on the surface of the AlGaO layer, and hot phosphoric acid was used to repair the etching damage.

[0079] Step 6: Using ALD process, an insulating gate dielectric layer is formed. Figure 3 (f).

[0080] The aluminum source is trimethylaluminum TMA, the oxygen source is H2O, the reaction chamber temperature is 400°C, and the growth rate is 0.1nm / cycle. Atomic layer deposition ALD process is used to deposit Al2O3 with a thickness of 60nm on the inner wall of the groove to form an insulating gate dielectric layer 7.

[0081] Step 7: Make a gate electrode, such as Figure 3 (g).

[0082] Ni with a thickness of 60 nm and Au with a thickness of 250 nm are sequentially deposited on the insulating gate dielectric layer through the E-Beam process. After the metal deposition is completed, it is placed in an acetone solution for stripping to form a gate electrode 8. The stripped sample is then placed in an acetone solution, an anhydrous ethanol solution, and deionized water for ultrasonic cleaning for 5 minutes each, and then blown dry with pure N2.

[0083] Step 8: Make the source electrode, such as Figure 3 (h).

[0084] Through the E-Beam process, Ti with a thickness of 60nm and Au with a thickness of 250nm are first deposited in the source region in sequence; then the deposited metals are ultrasonically cleaned in acetone and anhydrous ethanol solutions for 5 minutes, and cleaned with plasma water for 5 minutes, and blown dry with high-purity N2 to form a source electrode 9; thereafter, thermal annealing is performed for 1 minute at a temperature of 470°C and a nitrogen flow rate of 3L / min to form a good ohmic resistor.

[0085] Step nine, make a drain electrode, such as Figure 3 (i).

[0086] Through the E-Beam process, Ti with a thickness of 60nm and Au with a thickness of 250nm are first deposited in the drain area; then the deposited metals are ultrasonically cleaned in acetone and anhydrous ethanol solutions for 5 minutes, and cleaned with plasma water for 5 minutes, and blown dry with high-purity N2 to form a drain electrode 1; finally, thermal annealing is performed for 1 minute at a temperature of 470°C and a nitrogen flow rate of 3L / min to form a good ohmic resistance and complete the device manufacturing.

[0087] Example 3, in Sn doped n +On the β-Ga2O3 material substrate, a 200nm thick and 1×10 16 cm -3 The unintentionally doped Ga2O3 layer has a thickness of 30nm and a Si doping concentration of 5×10 18 cm -3 Gallium oxide heterojunction MOSFET device with AlGaO layer.

[0088] Step A, using MBE process, growing Ga2O3 epitaxial layer on Ga2O3 substrate layer, such as Figure 3 (a).

[0089] A1) The Sn doping concentration is 1×10 19 cm -3 , with a thickness of 400nm + β-Ga2O3 substrate 2, sequentially cleaned with organic matter and deionized water, and dried with high-purity N2;

[0090] A2) After cleaning, the highly doped n + The β-Ga2O3 substrate is placed in a molecular beam epitaxy MBE growth chamber, high-purity 6N Ga and high-purity 4N SnO2 powders are heated in a K chamber to provide Ga and Sn elements, and a mixed gas of 5% O3 and 95% O2 is used to provide oxygen elements;

[0091] A3) Set 2×10 for Ga element -4 Pa pressure to make it enter the reaction chamber, and introduce a mixed gas with a flow rate of 5 sccm into the reaction chamber, and heat the substrate to 660 ° C to obtain a doping concentration of 5×10 16 cm -3 , Sn-doped n- - β-Ga2O3 epitaxial layer 3.

[0092] Step B, using MOCVD and ion implantation process, growing a Ga2O3 layer implanted with acceptor ions on the Ga2O3 epitaxial layer, such as Figure 3 (b).

[0093] B1) using TEGa and O2 as gallium source and oxygen source, and N2 as carrier gas, using chemical vapor deposition MOCVD method to grow an epitaxial film on the β-Ga2O3 epitaxial layer;

[0094] B2) Place the film in an ion implanter and inject at a dose of 5×10 14 cm -3 , under the process condition of an implantation energy of 380 KeV, ion implantation is performed on the film to form a β-Ga2O3 layer implanted with N ions;

[0095] B3) The sample after N ion implantation was placed in a tubular annealing furnace at 1100°C for 25 min to activate the N ions and obtain an implantation concentration of 3×10 18 Pieces / cm 3 , a Ga2O3 layer 4 with acceptor ions having a thickness of 600nm.

[0096] Step C, using MOCVD process, growing an unintentionally doped Ga2O3 layer on the Ga2O3 layer implanted with acceptor ions, such as Figure 3 (c).

[0097] Using chemical vapor deposition (MOCVD) method, the epitaxial carrier concentration on the Ga2O3 layer with acceptor ions is 1×10 16 cm -3 , an unintentionally doped Ga2O3 layer 5 with a thickness of 200nm, wherein the deposition process conditions are as follows:

[0098] Using TEGa as gallium source, O2 as oxygen source, and N2 as carrier gas, the flow rates of TEGa and O2 are 50 sccm and 2000 sccm respectively, the reaction chamber temperature is 600°C, and the growth pressure is 20 Torr.

[0099] Step D, using MOCVD process, growing AlGaO layer on the unintentionally doped Ga2O3 layer, such as Figure 3 (d).

[0100] Using chemical vapor deposition (MOCVD), the epitaxial doping concentration of the unintentionally doped Ga2O3 layer was 5×10 18 cm -3 , an AlGaO layer 6 with a thickness of 30 nm, wherein the deposition process conditions are as follows:

[0101] Use TEGa as gallium source, TMAl as aluminum source, O2 as oxygen source, N2 as carrier gas, and set the flow rates of TEGa, TMAl and O2 to be 50sccm, 20sccm and 2000sccm respectively, the reaction chamber temperature to be 600℃, and the growth pressure to be 20Torr.

[0102] Step E: using RIE process to etch grooves on the surface of the AlGaO layer. Figure 3 (e).

[0103] Reactive ion etching (RIE) was used to etch the AlGaO layer surface to form a groove of about 4 μm, and hot phosphoric acid was used to repair the etching damage. The etching process conditions were as follows:

[0104] The chamber pressure was 5.0 Pa, the plasma power was 150 W, and the flow rates of BCl 3 and Ar were 20 sccm and 10 sccm, respectively.

[0105] Step F, using ALD process to form an insulating gate dielectric layer, such as Figure 3 (f).

[0106] By using the atomic layer deposition ALD process, Al2O3 with a thickness of 40 nm is deposited on the inner wall of the trench to form an insulating gate dielectric layer 7, wherein the deposition process conditions are as follows:

[0107] Using trimethylaluminum (TMA) as the aluminum source and H2O as the oxygen source, the reaction chamber temperature was set to 300°C and the growth rate was set to 0.08 nm / cycle.

[0108] Step G, making a gate electrode, such as Figure 3 (g).

[0109] G1) depositing Ni with a thickness of 50 nm and Au with a thickness of 150 nm on the insulating gate dielectric layer in sequence by an E-Beam process. After the metal deposition is completed, the layer is placed in an acetone solution for stripping to form a gate electrode 8;

[0110] G2) The peeled samples were placed in acetone solution, anhydrous ethanol solution, and deionized water for ultrasonic cleaning for 5 minutes each, and then blown dry with pure N2.

[0111] Step H, making a source electrode, such as Figure 3 (h).

[0112] H1) Ti with a thickness of 50 nm and Au with a thickness of 150 nm are sequentially deposited in the source region by an E-Beam process;

[0113] H2) The deposited metal is ultrasonically cleaned in acetone and anhydrous ethanol solutions for 5 minutes, and then cleaned with plasma water for 5 minutes, and blown dry with high-purity N2 to form a source electrode 9; then, thermally annealed for 1 minute at a temperature of 470°C and a nitrogen flow rate of 3L / min to form a good ohmic resistor.

[0114] Step I, making a drain electrode, such as Figure 3 (i).

[0115] I1) Ti with a thickness of 50 nm and Au with a thickness of 150 nm are sequentially deposited in the drain region by an E-Beam process;

[0116] I2) The deposited metal is ultrasonically cleaned in acetone and anhydrous ethanol solutions for 5 minutes, and then cleaned with plasma water for 5 minutes, and blown dry with high-purity N2 to form a drain electrode 1; then, thermal annealing is performed for 1 minute at a temperature of 470°C and a nitrogen flow rate of 3L / min to form a good ohmic resistance, thereby completing the device manufacturing.

[0117] The above descriptions are only three specific examples of the present invention and do not constitute any limitation to the present invention. Obviously, for professionals in this field, after understanding the content and principles of the present invention, it is possible to make various parameter corrections and changes in form and details without departing from the principles and structures of the present invention. However, these corrections and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A gallium oxide heterojunction MOSFET device, comprising: A drain electrode (1), a Ga2O3 substrate (2), a Ga2O3 epitaxial layer (3), a Ga2O3 layer (4) implanted with acceptor ions, a gate electrode (8) and a source electrode (9), characterized in that: An unintentionally doped Ga2O3 layer (5) and an AlGaO layer (6) are sequentially provided on the Ga2O3 layer (4) injected with acceptor ions to increase carrier concentration and carrier mobility; a groove is provided in the middle of the AlGaO layer (6), and an insulating gate dielectric layer (7) is provided on the inner wall of the groove; The gate (8) is located on the upper part of the insulating gate dielectric layer (7); The source electrode (9) is located at two ends of the AlGaO layer (6).

2. The device according to claim 1, characterized in that: The unintentionally doped n-type Ga2O3 layer (5) is made of β-Ga2O3 material with a doping concentration of 1×10 15 -1×10 16 cm -3 , thickness is 100-200nm; The AlGaO layer (6) is made of highly doped AlGaO material doped with Si, with a doping concentration of 1×10 18 -5×10 18 cm -3 , thickness is 20-30nm.

3. The device according to claim 1, characterized in that: The direction of the groove is from the surface of the AlGaO layer (6) downwards, and its bottom reaches the Ga2O3 epitaxial layer (3), with a depth of 4um-6um.

4. The device according to claim 1, characterized in that: The Ga2O3 substrate (2) is a highly n-doped Ga2O3 substrate doped with Sn or Si. + β-Ga2O3 material, doping concentration is 1×10 18 -5×10 19 cm -3 , thickness is 300-600nm; The Ga2O3 epitaxial layer (3) is made of low-n-doped Sn or Si. - β-Ga2O3 material, doping concentration is 5×10 15 -1×10 17 cm -3 , thickness is 4-10um.

5. The device according to claim 1, characterized in that: The Ga2O3 layer (4) injected with acceptor ions is made of high-resistance layer β-Ga2O3 material doped with N or Mg, and its doping concentration is 1×10 18 -5×10 18 Pieces / cm 3 , thickness is 400-800nm; The insulating gate dielectric layer (7) is made of Al2O3 material and has a thickness of 20-60 nm.

6. A method for manufacturing a gallium oxide heterojunction MOSFET device, characterized in that: The steps include: S1) using an MBE process to deposit a β-Ga2O3 material with a thickness of 4-10 um on the Ga2O3 substrate layer (2) to form a Ga2O3 epitaxial layer (3); S2) using an MOCVD process to deposit a β-Ga2O3 material with a thickness of 400-800 nm on the Ga2O3 epitaxial layer (3) to form a Ga2O3 layer (4) implanted with acceptor ions; S3) using a MOCVD process, depositing a β-Ga2O3 material with a thickness of 100-200 nm on the Ga2O3 layer (4) implanted with acceptor ions, to form an unintentionally doped n-type Ga2O3 layer (5); S4) using a MOCVD process, depositing an AlGaO material with a thickness of 20-30 nm on the unintentionally doped n-type Ga2O3 layer (5) to form a highly doped AlGaO layer (6); S5) using RIE process, etching a groove on the surface of the AlGaO layer (6), the bottom of which reaches the Ga2O3 epitaxial layer (3) and has a depth of 4um-6um; S6) using an ALD process to deposit Al2O3 with a thickness of 20-60 nm on the inner wall of the trench and the AlGaO layer (6) to form an insulating gate dielectric layer (7); S7) using an E-Beam process, depositing 20-60nm / 120-250nm Ni / Au on the insulating gate dielectric layer (7), and then placing it in an acetone solution for stripping to form a gate (8); S8) using an E-Beam process, depositing 20-60nm / 120-250nm of Ti / Au on both ends of the AlGaO layer (6), and then annealing for 1-3min in a N2 atmosphere at 300-550°C to form a source electrode (9); S9) Using the E-Beam process, 20-60nm / 120-250nm Ti / Au is deposited on the back side of the Ga2O3 substrate (2), and then annealed for 1-3min in a N2 atmosphere at 300-550°C to form a drain (1), thereby completing device manufacturing.

7. The method according to claim 6, characterized in that The MBE process in step S1) has the following conditions: 6N Ga and high-purity 4N SnO2 powder are used to provide Ga and Sn elements; The corresponding pressure of Ga source is 2×10 -4 Pa; The substrate temperature is 560-700°C; The gas used is a mixture of ozone and oxygen, in which ozone accounts for 5%, oxygen accounts for 95%, and the flow rate is 5sccm.

8. The method according to claim 6, characterized in that The MOCVD process in step S2), step S3) and step S4) has the following condition parameters: TEGa and O2 are used to provide Ga and O elements; The flow rates of TEGa, TMAl, and O2 are 50 sccm, 20 sccm, and 2000 sccm, respectively; The reaction chamber temperature is 600-700°C and the growth pressure is 20 Torr.

9. The method according to claim 6, characterized in that The parameters of the RIE process in step S5) are set as follows: The RIE chamber pressure is 5.0 Pa; The power of plasma is 100W-150W; The flow rates of BCl3 and Ar are 20 sccm and 10 sccm, respectively.

10. The method according to claim 6, characterized in that The ALD process in step S6) has the following conditions: Trimethylaluminum TMA and H2O are used to provide Al and O elements; The reaction chamber temperature is 200-400°C; The growth rate is 0.07~0.1nm / cycle.

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