Display panel mother board and display panel
By setting an outer pulling wiring structure with at least a double-layer conductive layer in the display panel motherboard, the problem of heating in the concentrated area of the outer pulling wiring of the OLED display panel is solved, and the reliability of the product is improved.
Patent Information
- Application Number
- CN202411833330.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-11
- Publication Date
- 2025-03-21
AI Technical Summary
The outer pull-out wire of the OLED display panel is prone to heat up in concentrated areas, resulting in a reduced product reliability.
Set the outer pulling wire in the display panel motherboard to a structure of at least a double-layer conductive layer to reduce the impedance of the outer pulling wire and avoid regional heating.
By reducing the impedance of the outer pull-out trace, the heating risk is reduced and the product reliability is improved.
Smart Images
Figure CN119677322A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of display technology, and in particular, to a display panel motherboard and a display panel. Background Art
[0002] OLED (Organic Light-Emitting Diode) display panels generally use the FOP (FPC on Panel) bonding method to bond the gold fingers on the flexible circuit board FPC to the bonding pads on the display panel. As consumers' requirements for the screen-to-body ratio of OLED displays increase, the border area of the display panel is required to be narrower and narrower. In order to narrow the border area of the display panel, one possible implementation method is to design an external pull pad corresponding to the bonding pad in the non-display panel area of the display panel motherboard, and the bonding pad and the external pull pad are connected through an external pull wiring. However, due to the gap and size between the bonding pads, the external pull wiring becomes thinner, which easily leads to heat in the concentrated area of the external pull wiring, causing burns and other problems that affect product reliability. Summary of the invention
[0003] The present disclosure provides a display panel motherboard and a display panel, which improve the problem of reduced product reliability due to heat generation in concentrated areas on the external pull-out wiring by arranging the external pull-out wiring in the display panel motherboard into a structure with at least a double conductive layer.
[0004] The first aspect of the present disclosure provides a display panel motherboard. The display panel motherboard includes a display panel area and a non-display panel area surrounding the display panel area, and the display panel area includes a bonding area. The display panel motherboard includes a plurality of bonding pads, a plurality of detection pads, and a plurality of external pull-out wirings, the bonding pads are located in the bonding area, the detection pads correspond to the bonding pads one by one, and are located in the non-display panel area, the external pull-out wirings are arranged in the non-display panel area, and are used to connect the bonding pads and the detection pads, and the external pull-out wirings include at least two conductive layers.
[0005] In the above scheme, the impedance of the external pull-out wiring in the display panel motherboard is reduced by setting it to at least a double-layer structure, thereby reducing the risk of regional concentrated overheating on the external pull-out wiring, thereby improving product reliability.
[0006] In a specific embodiment of the first aspect of the present disclosure, the display panel motherboard also includes a plurality of leads located in the display panel area, one end of the lead is connected to at least one circuit to be tested in the bonding pad, the other end of the lead is connected to the external pull-out wiring, the other end of the external pull-out wiring is connected to the detection pad, and the number of conductive layers of the external pull-out wiring is greater than the number of conductive layers of the lead.
[0007] In the above scheme, the number of conductive layers of the external pull-out wiring is not less than the number of conductive layers of the lead wire connected to it, which is conducive to reducing the heat generated on the external pull-out wiring during signal transmission, thereby reducing the probability of problems such as burns in the product.
[0008] In a specific embodiment of the first aspect of the present disclosure, the circuit to be tested includes a first circuit to be tested and a second circuit to be tested, and a plurality of leads are classified into at least a first lead and a second lead, the first lead is connected to the first circuit to be tested, and the second lead is connected to the second circuit to be tested. The display panel motherboard includes a first conductive layer and a second conductive layer stacked together, a portion of the first conductive layer forms the first circuit to be tested and the first lead, and a portion of the second conductive layer forms the second circuit to be tested and the second lead. For example, further, the first circuit to be tested is a gate drive signal line of the display panel motherboard, the first lead and the gate metal pattern of the display panel motherboard are in the same layer structure, and / or the second circuit to be tested is a data signal line of the display panel motherboard, and the second lead and the source-drain metal pattern of the display panel motherboard are in the same layer structure.
[0009] In the above solution, the external wiring can be used to test whether the circuits with different functions in the display panel motherboard are working normally, thereby improving the applicability of the external wiring solution.
[0010] In a specific embodiment of the first aspect of the present disclosure, a partial overlapping area of the first conductive layer and the second conductive layer forms an external pull-out trace.
[0011] In the above scheme, the design scheme of forming the external pull-out wiring by utilizing the first conductive layer and the second conductive layer already in the display panel motherboard does not need to add a new conductive layer to prepare the external pull-out wiring, thereby reducing the processing cost of the external pull-out wiring and also facilitating the thinning of the display panel motherboard.
[0012] In a specific embodiment of the first aspect of the present disclosure, the display panel motherboard further includes a third conductive layer located between the first conductive layer and the second conductive layer, a portion of the first conductive layer forms a first electrode of the capacitor, and a portion of the third conductive layer forms a second electrode of the capacitor. The partially overlapping area of at least two of the first conductive layer, the second conductive layer and the third conductive layer forms an external pull-out wiring.
[0013] In the above solution, the external wiring is prepared by using multiple conductive layers in the display panel motherboard, which can increase the diversity of the external wiring scheme to meet different requirements of the display panel motherboard.
[0014] In a specific embodiment of the first aspect of the present disclosure, the display panel motherboard further includes a third conductive layer located between the first conductive layer and the second conductive layer, and a fourth conductive layer located on a side of the second conductive layer facing away from the third conductive layer. The partially overlapping area of at least two of the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer forms an external pull-out wiring.
[0015] In the above scheme, the four conductive layers included in the display panel motherboard can all form external pull-out routing, without the need to add a new MASK process, and the more conductive layers there are that form the external pull-out routing, the smaller the impedance on the external pull-out routing. At the same time, the selection of more conductive layers reduces the difficulty of wiring of the display panel motherboard (including external pull-out routing and leads).
[0016] In a specific embodiment of the first aspect of the present disclosure, an insulating layer is provided between at least two conductive layers forming the external pull-out wiring, and a film through hole is provided in the insulating layer to achieve electrical connection between the at least two conductive layers.
[0017] In the above scheme, the insulating layer between the conductive layers that form the external pull-out wiring is the corresponding insulating layer formed during the preparation process of the display panel motherboard. In this way, in the process of forming the external pull-out wiring, there is no need to add additional processes to process the above insulating layer, thereby reducing the processing cost of the display panel motherboard.
[0018] In a specific implementation of the first aspect of the present disclosure, each external pull-out wiring is arranged on the same layer.
[0019] In a specific embodiment of the first aspect of the present disclosure, the external pull-out wiring connected to the first lead and the external pull-out wiring connected to the second lead are arranged in different layers.
[0020] In the above solution, the design scheme of arranging the external pull-out wiring connected to different leads in different layers reduces the risk of mutual interference between different detection signals, thereby improving the detection accuracy of the display panel motherboard.
[0021] A second aspect of the present disclosure provides a display panel, which is obtained by cutting off a non-display panel area in the display panel motherboard in the above embodiment. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 A schematic diagram of a planar structure of a display panel motherboard provided in one embodiment of the present disclosure.
[0023] Figure 2 A partial planar structural schematic diagram of a display panel motherboard provided in one embodiment of the present disclosure.
[0024] Figure 3 A cross-sectional schematic diagram of a display panel motherboard provided in one embodiment of the present disclosure.
[0025] Figure 4 A cross-sectional schematic diagram of a display panel motherboard provided in another embodiment of the present disclosure.
[0026] Figure 5 A cross-sectional schematic diagram of a display panel motherboard provided in another embodiment of the present disclosure.
[0027] Figure 6 A cross-sectional schematic diagram of a display panel motherboard provided in another embodiment of the present disclosure.
[0028] Figure 7 A cross-sectional schematic diagram of a display panel motherboard provided in another embodiment of the present disclosure.
[0029] Figure 8 A cross-sectional schematic diagram of a display panel motherboard provided in another embodiment of the present disclosure.
[0030] Fig. 9 A cross-sectional schematic diagram of a display panel motherboard provided in one embodiment of the present disclosure.
[0031] Fig.10 A cross-sectional schematic diagram of a display panel motherboard provided in another embodiment of the present disclosure.
[0032] Fig.11 A cross-sectional schematic diagram of a display panel motherboard provided in another embodiment of the present disclosure.
[0033] Fig.12 A cross-sectional schematic diagram of a display panel motherboard provided in another embodiment of the present disclosure.
[0034] Fig.13 A cross-sectional schematic diagram of a display panel motherboard provided in another embodiment of the present disclosure.
[0035] Fig.14 A cross-sectional schematic diagram of a display panel motherboard provided in another embodiment of the present disclosure.
[0036] Fig.15 A cross-sectional schematic diagram of a display panel motherboard provided in another embodiment of the present disclosure.
[0037] Fig.16 A cross-sectional schematic diagram of a display panel motherboard provided in another embodiment of the present disclosure.
[0038] Fig.17 A cross-sectional schematic diagram of a display panel motherboard provided in another embodiment of the present disclosure.
[0039] Fig.18 A cross-sectional schematic diagram of a display panel motherboard provided in another embodiment of the present disclosure.
[0040] Fig.19 A cross-sectional schematic diagram of a display panel motherboard provided in another embodiment of the present disclosure.
[0041] Fig. 20 A cross-sectional schematic diagram of a display panel motherboard provided in one embodiment of the present disclosure.
[0042] Fig.21 A cross-sectional schematic diagram of a display panel motherboard provided in one embodiment of the present disclosure. DETAILED DESCRIPTION
[0043] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.
[0044] In the preparation process of the display panel, an independent display panel is obtained by cutting the display panel motherboard, and an external pull-out pad is set on the outside of the display panel for CT detection of various circuits inside the display panel, namely Panel TEST. Specifically, after all the film layers of the display panel motherboard are completed, a detection signal can be given through the external pull-out pad. The detection signal can realize a simple screen display for screening defective products.
[0045] Then, in some display panels, such as large / medium-sized flexible screens, the size and spacing of the bonding pads become smaller, which will cause the external pull-out wiring connected to the detection pad to become thinner. Conventional external pull-out wiring is wired with a metal wiring. Therefore, the impedance on the thinned external pull-out wiring becomes larger, and the external pull-out wiring on the large / medium-sized flexible screen will also become longer. In this way, the load of the external pull-out wiring becomes larger, which can easily lead to heat generation in the concentrated area of the external pull-out wiring, causing aging of the external pull-out wiring and causing circuit burns, thereby reducing the reliability of the product.
[0046] In view of this, the embodiments of the present disclosure provide a display panel motherboard and a display panel. By setting the external pull-out wiring in the non-display area of the display panel motherboard to a structure including at least two conductive layers, the impedance of the external pull-out wiring of large / medium-sized flexible screens can be reduced, concentrated regional heating of the external pull-out wiring can be avoided, and reliability problems such as burns during aging can be avoided.
[0047] The disclosed embodiment provides a display panel motherboard. The display panel motherboard includes a display panel area and a non-display panel area surrounding the display panel area, and the display panel area includes a bonding area. The display panel motherboard includes a plurality of bonding pads, a plurality of detection pads, and a plurality of external pull-out wirings. The bonding pads are located in the bonding area, the detection pads correspond to the bonding pads one by one, and are located in the non-display panel area, the external pull-out wirings are arranged in the non-display panel area, and are used to connect the bonding pads and the detection pads, and the external pull-out wirings include at least two conductive layers. In this way, the external pull-out wirings with at least a double-layer structure can reduce the impedance of the external pull-out wirings of large / medium-sized flexible screens, avoid concentrated regional heating of the wirings, and avoid the occurrence of reliability problems such as burns during aging.
[0048] In the following, the display panel motherboard and the display panel according to at least one embodiment of the present disclosure are described in conjunction with the accompanying drawings. In addition, as shown in the accompanying drawings, in at least one embodiment of the present disclosure, a spatial rectangular coordinate system is established with the surface where the display panel motherboard is located as a reference to define the positions of various film layers in the display panel motherboard. In the spatial rectangular coordinate system, the X-axis and the Y-axis are parallel to the surface where the display panel motherboard is located, and the Z-axis is perpendicular to the surface where the display panel motherboard is located.
[0049] In the display panel motherboard 10 provided in at least one embodiment of the present disclosure, as Figure 1 , Figure 2 and Figure 3 As shown, the display panel motherboard 10 includes a display panel area 11 and a non-display panel area 13 surrounding the display panel area 11, and multiple display panel areas 11 can be made on the display panel motherboard 10 at the same time, and each display panel area 11 is correspondingly provided with a non-display panel area 13. The display panel area 11 may include an effective display area 11a (Active Area, AA) and a frame area 12 located around the effective display area 11a, and a bonding area 12a may be provided in the frame area 12, and the bonding pad is located in the bonding area 12a. A plurality of detection pads 14 and a plurality of external pull-out wirings 15 are also provided in the non-display panel area 13, and the detection pads 14 are respectively connected to the bonding pads one by one through the external pull-out wirings 15. The external pull-out wirings 15 include at least two metal layers.
[0050] It should be noted that the structure of the display panel motherboard 10 is not limited to the above embodiments, and it may also include other solutions. For example, the shape of the display panel area 11 of the display panel motherboard 10 is not limited to the rectangle in the above example, and it may also be a circle or other structures. The disclosed embodiment does not specifically limit the conductive layer that forms the external pull-out wiring 15 in the display panel motherboard 10. It may be formed by a separate conductive layer in the display panel motherboard 10, or it may be formed by a conductive layer that forms part of the functional structure in the display panel motherboard 10. The following embodiments will limit the metal layer that forms the external pull-out wiring 15, which will not be repeated here.
[0051] In the disclosed embodiment, in addition to defining the external pull-out wiring 15 located in the non-display panel area 13 for connecting the bonding pad and the detection pad 14, a design scheme for setting wiring in the display area to achieve electrical connection between the bonding pad and the detection pad 14 is introduced next.
[0052] In the display panel motherboard 10 provided in at least one embodiment of the present disclosure, the display panel motherboard 10 further includes a plurality of leads 16 located in the display panel area 11. One end of the lead 16 is connected to at least one circuit to be tested 17 in the bonding pad, the other end of the lead 16 is connected to the external pull-out trace 15, and the other end of the external pull-out trace 15 is connected to the detection pad 14. The number of conductive layers of the external pull-out trace 15 is greater than the number of conductive layers of the lead 16.
[0053] For example, Figure 2 and Figure 3 As shown, in the display panel motherboard 10, the display panel area 11 is provided with a plurality of leads 16, one end of each lead 16 is connected to at least one circuit to be tested 17 in the bonding pad, the other end of the lead 16 is connected to one end of the external pull-out wiring 15 in the non-display panel area 13, and the other end of the external pull-out wiring 15 is connected to the detection pad 14 located in the non-display panel area 13, thus achieving electrical connection between the bonding pad in the bonding area 12a located in the display panel area 11 and the detection pad 14 located in the non-display panel area 13. Generally speaking, the lead 16 is made of the conductive layer of the circuit to be tested 17 connected thereto, and the number of layers of the conductive layer of the external pull-out wiring 15 is greater than the number of layers of the conductive layer of the lead 16, that is, the external pull-out wiring 15 is made of the conductive layer corresponding to the lead 16 and at least one other conductive layer, thus, while reducing the processing cost, improving the problem of reducing the reliability of the display panel motherboard 10 due to the thinning of the external pull-out wiring 15.
[0054] Based on the above embodiments, the present disclosure will next introduce the design of the circuit to be tested 17 connected to the detection pad 14 and the corresponding lead 16 .
[0055] For example, in a display panel motherboard 10 provided in an embodiment of the present disclosure, the circuit to be tested 17 includes a first circuit to be tested 17a and a second circuit to be tested 17b, and the plurality of leads 16 are classified into at least a first lead 16a and a second lead 16b, the first lead 16a is connected to the first circuit to be tested 17a, and the second lead 16b is connected to the second circuit to be tested 17b. The display panel motherboard 10 includes a first conductive layer and a second conductive layer stacked, a portion of the first conductive layer forms the first circuit to be tested 17a and the first lead 16a, and a portion of the second conductive layer forms the second circuit to be tested 17b and the second lead 16b.
[0056] For example, Figure 3 As shown, in the display panel motherboard 10 provided in at least one embodiment of the present disclosure, the first circuit to be tested 17a is a gate drive signal line of the display panel motherboard 10, the first lead 16a and the gate metal pattern 121a are in the same layer structure, and / or the second circuit to be tested 17b is a data signal line of the display panel motherboard 10, the second lead 16b and the source / drain metal pattern 122a of the display panel motherboard 10 are in the same layer structure.
[0057] For example, Figure 3 As shown, the display panel motherboard 10 includes a stacked substrate 110, a driving circuit layer 120 and a light emitting device layer 130, and the light emitting device layer 130 includes a plurality of light emitting devices ( Figure 3 A light emitting device is shown).
[0058] The substrate 110 may be a glass substrate 110 or a flexible substrate 110 .
[0059] The light emitting device layer 130 is located in the effective display area 11a of the display panel area 11 and on the side of the driving circuit layer 120 away from the substrate 110 . Each light emitting device of the light emitting device layer 130 includes a stacked anode 131 , a light emitting functional layer 132 and a cathode 133 .
[0060] The driving circuit layer 120 is located between the substrate 110 and the light-emitting device layer 130, and includes a pixel driving circuit electrically connected to the anode 131 in the light-emitting device. The pixel driving circuit includes a thin film transistor, and also includes a first circuit to be tested 17a (e.g., a gate driving signal line) and a second circuit to be tested 17b (e.g., a data signal line) to drive the light-emitting device layer 130 to emit light for display. The gate driving signal line can be electrically connected to the gate of the transistor in the pixel circuit, and the signal on the gate driving signal line can control the conduction or disconnection of the thin film transistor connected thereto. The data signal line can transmit the data signal provided by the driving chip to the pixel driving circuit, so that the pixel driving circuit generates a driving current, thereby driving the light-emitting device to emit light. At least two conductive layers are required to set these signal lines.
[0061] Specifically, the display panel motherboard 10 includes at least two conductive layers, for example, two conductive layers, specifically, a first metal layer 121 and a second metal layer 122 that are sequentially away from the substrate 110. The first metal layer 121 is used as a first conductive layer, and a portion of it forms a gate electrode and a gate drive signal line of a thin film transistor in a pixel driving circuit. The first metal layer 121 can also be referred to as a gate metal layer. The gate metal layer, i.e., the first metal layer 121, forms a gate electrode of a corresponding thin film transistor by forming a gate metal pattern 121a, and while forming the gate electrode, a first lead 16a is formed for electrically connecting the gate driving circuit to a detection pad 14 located in a non-display panel area 13. The second metal layer 122 is used as a second conductive layer, and a portion of it forms a source and drain electrode of a thin film transistor in a pixel driving circuit by forming a source and drain metal pattern 122a. The data signal line and a second lead 16b are formed in the same layer as the source and drain metal pattern 122a. The second lead 16b is used to realize an electrical connection between the data signal line and the detection pad 14 located in the non-display panel area 13.
[0062] It should be noted that the embodiment of the present disclosure does not limit the structure of the light-emitting device in the display panel motherboard 10. For example, the light-emitting functional layer 132 in the light-emitting device may include a light-emitting layer (Emitting Layer, EML) and any one or more of the following layers: a hole injection layer (Hole Inject Layer, HIL), a hole transport layer (Hole Transport Layer, HTL), an electron blocking layer (Electron Blocking Layer, EBL), an electron injection layer (Electron Inject Layer, EIL), an electron transport layer (Electron Transport Layer, ETL), and a hole blocking layer (Hole Blocking Layer, HBL). For example, the anode 131 and the cathode 133 in the light-emitting device can also be designed according to actual needs. In addition, the circuit to be tested 17 in the embodiment of the present disclosure is not limited to the gate drive signal line and the data signal line in the example, and it can also include other functional signal lines such as touch control to perform crack detection on other functions of the display panel motherboard 10. The above can be designed according to actual needs and will not be repeated here.
[0063] In the display panel motherboard 10 provided in at least one embodiment of the present disclosure, the partially overlapping area of the first conductive layer and the second conductive layer forms an external pull-out trace 15 .
[0064] For example, Figure 4As shown, the first metal layer 121 as the first conductive layer and the second metal layer 122 as the second conductive layer form an external pull-out wiring 15 in the non-display panel area 13 and in the partially overlapping area in the direction perpendicular to the substrate 110. The external pull-out wiring 15 is connected to the corresponding first lead 16a and second lead 16b, thereby realizing the electrical connection between the first circuit to be tested, i.e., the gate drive signal line and the second circuit to be tested, i.e., the data signal line, and the detection pad 14. In this way, there is no need to add a new metal layer and a MASK process, and the thickness of the display panel motherboard 10 in the direction perpendicular to the substrate 110 is not affected, and the production cost is also reduced. More importantly, the external pull-out wiring 15 includes a double-layer structure of the first metal layer 121 and the second metal layer 122, which can improve the reliability of the product by reducing the impedance on the external pull-out wiring 15.
[0065] In addition to thin film transistors, the pixel driving circuit also includes other structures, such as capacitor 125. Taking the pixel driving circuit as a 7T1C circuit as an example, the pixel driving circuit includes a capacitor 125 and seven thin film transistors. Thus, the display panel motherboard 10 includes at least three conductive layers to form the capacitor 125 while forming the thin film transistor. The specific structure is as follows.
[0066] In the display panel motherboard 10 provided in at least one embodiment of the present disclosure, the display panel motherboard 10 further includes a third conductive layer located between the first conductive layer and the second conductive layer, a portion of the first conductive layer forms a first electrode 125a of the capacitor 125, and a portion of the third conductive layer forms a second electrode 125b of the capacitor 125. The partially overlapping area of at least two of the first conductive layer, the second conductive layer, and the third conductive layer forms an external pull-out trace 15.
[0067] For example, Figure 5 As shown, the display panel motherboard 10 includes a stacked substrate 110, a driving circuit layer 120 and a light-emitting device layer 130. The introduction of the substrate 110, the light-emitting device layer 130 and the driving circuit layer 120 can refer to the above examples and will not be repeated here.
[0068] In the case where the display panel motherboard 10 includes three conductive layers, in addition to the capacitor 125 in the pixel driving circuit, the gate metal pattern 121a can also be arranged in multiple layers, for example, two layers.
[0069] Specifically, taking the pixel driving circuit in the display panel motherboard 10 including a P-type transistor and an N-type transistor as an example, the P-type transistor may be a low-temperature polysilicon transistor, which includes P-Si, and the N-type transistor may be an oxide transistor, which includes one or more of IGZO, IGTO, IGO, IZO, AIZO and ATZO. The display panel motherboard 10 includes three conductive layers, specifically, a first metal layer 121, a third metal layer 123 and a second metal layer 122 that are sequentially away from the substrate 110. The first metal layer 121 is used as a first conductive layer to form the gate of the P-type transistor, the first electrode 125a of the capacitor 125, the gate drive signal line and the first lead 16a. The third metal layer 123 located on the side of the first metal layer 121 away from the substrate 110 is used as a third conductive layer to form the gate of the N-type transistor and the second electrode 125b of the capacitor 125. The second metal layer 122 located on the side of the third metal layer 123 away from the first metal layer 121 is used as a second conductive layer to form the source and drain of the P-type transistor, the source and drain of the N-type transistor, the data signal line and the second lead 16b.
[0070] Based on the structure of the display panel motherboard 10, there are many design schemes for the external wiring 15. Figure 6 As shown, the first metal layer 121, the second metal layer 122 and the third metal layer 123 partially overlap in the non-display panel area 13, that is, in the partially overlapping area of the three metal layers in the direction perpendicular to the substrate 110, to form an external pull-out line 15. Figure 5 As shown, the first metal layer 121 and the second metal layer 122 partially overlap in the direction perpendicular to the substrate 110 to form an external pull-out line 15. Figure 7 As shown, the first metal layer 121 and the third metal layer 123 partially overlap in the direction perpendicular to the substrate 110 to form an external pull-out trace 15. Figure 8 As shown, the second metal layer 122 and the third metal layer 123 partially overlap in a direction perpendicular to the substrate 110 to form an external pull-out trace 15 .
[0071] In the display panel motherboard 10, the conductive layer between the light emitting device layer 130 and the substrate 110 is not limited to the above first metal layer 121, the second metal layer 122 and the third metal layer 123, and a fourth metal layer 124 can also be provided, and the fourth metal layer 124 is used to form the wiring of the driving circuit layer 120 in the display panel motherboard 10, so that two wirings that need to be relatively close in the plane space can be provided in different metal layers, thereby reducing the probability of short circuits between wirings of different signals and reducing the difficulty of wiring. The following embodiment specifically introduces the structure of the display panel motherboard 10 including four metal layers.
[0072] In the display panel motherboard 10 provided in at least one embodiment of the present disclosure, the display panel motherboard 10 further includes a third conductive layer located between the first conductive layer and the second conductive layer, and a fourth conductive layer located on a side of the second conductive layer away from the third conductive layer. The partially overlapping area of at least two of the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer forms an external pull-out trace 15.
[0073] For example, Fig. 9 As shown, the display panel motherboard 10 includes a stacked substrate 110, a driving circuit layer 120 and a light-emitting device layer 130. The introduction of the substrate 110, the light-emitting device layer 130 and the driving circuit layer 120 can refer to the above examples and will not be repeated here.
[0074] The driving circuit layer 120 includes a first metal layer 121, a third metal layer 123, a second metal layer 122 and a fourth metal layer 124 which are sequentially stacked on the substrate 110, and a light-emitting device layer 130 is arranged on the side of the fourth metal layer 124 facing away from the substrate 110. The components of the driving circuit formed by the first metal layer 121 as the first conductive layer, the second metal layer 122 as the second conductive layer and the third metal layer 123 as the third conductive layer can refer to the above embodiments, and are not described in detail here. The fourth metal layer 124 as the fourth conductive layer can form part of the wiring of the driving circuit, such as the initialization signal line. Based on the structure of the display panel motherboard 10 including four metal layers, the design schemes of the external pull wiring 15 can include the following.
[0075] For example, the external pull-out wiring 15 includes four metal layers, specifically, Fig. 9 As shown, the external pull-out trace 15 is formed by the partially overlapping area of the first metal layer 121 , the second metal layer 122 , the third metal layer 123 and the fourth metal layer 124 .
[0076] For example, the external pull-out wiring 15 includes three metal layers, specifically, Fig.10 As shown, the external pull-out trace 15 is formed by the partially overlapping area of the first metal layer 121, the second metal layer 122 and the third metal layer 123. Fig.11 As shown, the external pull-out trace 15 is formed by the partially overlapping area of the first metal layer 121, the second metal layer 122 and the fourth metal layer 124. Fig.12 As shown, the external pull-out trace 15 is formed by the partially overlapping area of the first metal layer 121, the third metal layer 123 and the fourth metal layer 124. Fig.13 As shown, the external pull-out trace 15 is formed by the partially overlapping area of the second metal layer 122 , the third metal layer 123 and the fourth metal layer 124 .
[0077] For example, the external pull-out wiring 15 includes two metal layers, specifically, Fig.14As shown, the outer pull-out trace 15 is formed by the partially overlapping area of the first metal layer 121 and the second metal layer 122. Fig.15 As shown, the outer pull-out trace 15 is formed by the partially overlapping area of the first metal layer 121 and the third metal layer 123. Fig.16 As shown, the outer pull-out trace 15 is formed by the partially overlapping area of the first metal layer 121 and the fourth metal layer 124. Fig.17 As shown, the outer pull-out trace 15 is formed by the partially overlapping area of the second metal layer 122 and the third metal layer 123. Fig.18 As shown, the outer pull-out trace 15 is formed by the partially overlapping area of the second metal layer 122 and the fourth metal layer 124. Fig.19 As shown, the external pull-out trace 15 is formed by the partially overlapping area of the third metal layer 123 and the fourth metal layer 124 .
[0078] It should be noted that the structure of the display panel motherboard 10 is not limited to the structures of the above embodiments and examples, and can also be set to other schemes. For example, in the display panel motherboard 10, a fifth metal layer is set between the fourth metal layer 124 and the light-emitting device layer 130, and the external pull-out wiring 15 can be set to a structure including part of the fifth metal layer. For example, in the display panel motherboard 10, an auxiliary metal layer can also be set between the first metal layer 121 and the substrate 110 to achieve preset functions such as shading, electrostatic shielding, etc., and the external pull-out wiring 15 can be set to a structure including part of the auxiliary metal layer. For example, the lead 16, that is, the first lead 16a and the second lead 16b, is not limited to being set in the first metal layer 121 and the second metal layer 122, and is not limited to a single-layer structure. For example, the edge of the lead 16, that is, the connection with the external pull-out wiring 15, after the display panel motherboard 10 is cut to form a display panel, the edge of the lead 16 may be exposed, so the edge of the lead 16 can be set to have an anti-corrosion function. For example, a light emitting device layer 130 may be provided in the frame area 12 of the display panel motherboard 10. In addition, the embodiments of the present disclosure are not limited to the above metal layer materials, which may be one or more of Al, Mo, Cu, Ti or other metal materials with low resistivity. All of the above can be designed according to actual needs and will not be described in detail here.
[0079] It should be noted that a buffer layer may be provided between the substrate 110 and the driving circuit layer 120 of the display panel motherboard 10 of the present disclosure. The buffer layer may be prepared and formed by inorganic materials, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and the buffer layer may be a single layer or a multilayer structure. In addition, in the display panel area 11 of the display panel motherboard 10, adjacent metal layers are insulated in the multilayer metal layers. For example, a gate insulating layer is provided between the first metal layer 121 and the third metal layer 123, a first insulating layer is provided between the third metal layer 123 and the second metal layer 122, and a second insulating layer is provided between the second metal layer 122 and the fourth metal layer 124. The gate insulating layer, the first insulating layer and the second insulating layer may be provided in a single layer or a multilayer structure, and may be made of at least one material selected from silicon oxide and silicon nitride, but is not limited thereto.
[0080] In the display panel motherboard 10 provided in at least one embodiment of the present disclosure, an insulating layer is provided between at least two conductive layers forming the external pull-out wiring 15, and a film through hole is provided in the insulating layer to achieve electrical connection between the at least two conductive layers.
[0081] For example, Fig. 20 As shown, in the non-display panel area 13 of the display panel motherboard 10, the partially overlapping area of the first metal layer 121, the second metal layer 122, the third metal layer 123 and the fourth metal layer 124 forms an external pull-out wiring 15, and the four metal layers of the formed external pull-out wiring 15 are respectively insulated. Specifically, it can be realized by using the corresponding insulating layer in the display panel area 11, and the insulating layers between adjacent metal layers are respectively provided with film layer through holes, so as to realize the electrical connection of the first metal layer 121, the second metal layer 122, the third metal layer 123 and the fourth metal layer 124 forming the external pull-out wiring 15. In this way, there is no need to deal with the insulating layer located in the non-display surface area, which reduces the processing cost of the display panel motherboard 10.
[0082] It should be noted that the design of the external pull-out wiring 15 in the display panel motherboard 10 is not limited to the above embodiments. For example, the at least two metal layers forming the external pull-out wiring 15 can be defined according to the description of the above embodiments, rather than the four metal layers in the example. For example, an insulating layer may not be provided between the multiple layers located in the non-display panel area 13 that form the external pull-out wiring 15, and electrical connection can be achieved through direct contact of multiple metal layers. For example, the shape and position of the film layer through hole in the external pull-out wiring 15 are not limited to those shown in the figure. All of the above can be designed according to actual needs and will not be elaborated here.
[0083] In the display panel motherboard 10 provided in at least one embodiment of the present disclosure, each external pull-out wiring 15 is arranged in the same layer.
[0084] For example, Fig. 20As shown, each external pull-out wiring 15 is formed by the partially overlapping area of the first metal layer 121, the third metal layer 123, the second metal layer 122 and the fourth metal layer 124 located in the non-display panel area 13, that is, each external pull-out wiring 15 is arranged in the same layer.
[0085] In the display panel motherboard 10 provided in at least one embodiment of the present disclosure, the external pull-out wiring 15 connected to the first lead 16 a and the external pull-out wiring 15 connected to the second lead 16 b are arranged in different layers.
[0086] For example, Fig.21 As shown, the external pull-out wiring 15 connected to the first lead 16a, i.e., the first external pull-out wiring 15a, is formed by a partially overlapping area of the first metal layer 121 and the third metal layer 123 located in the non-display panel area 13; the external pull-out wiring 15 connected to the second lead 16b, i.e., the second external pull-out wiring 15b, is formed by a partially overlapping area of the second metal layer 122 and the fourth metal layer 124 located in the non-display panel area 13. The two are arranged in different layers, thus reducing the difficulty of wiring and facilitating processing.
[0087] The disclosed embodiment also provides a display panel. The display panel is obtained by cutting off the non-display panel area in the display panel motherboard in the above embodiment. In the process of preparing the display panel motherboard, a signal can be input to the detection pad to avoid the problem of misalignment during the alignment bonding. After the display panel motherboard is completed, it can be cut along the preset cutting line to obtain a semi-finished display panel with a display panel area and a detection pad, and then the semi-finished display panel is tested using the detection pad to detect whether cracks are generated during the cutting process or whether the crack expansion affects the quality of the product. After crack detection, the non-display panel area containing the detection pad is cut off, and the remaining display panel area is the display panel.
[0088] In the embodiments of the present disclosure, the display panel may be an organic light emitting diode display panel, a liquid crystal display panel, an electronic paper display panel, etc.
[0089] For example, the display panel in the embodiments of the present disclosure may be any product or component with a display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, a navigator, or the like.
[0090] It should be noted that the embodiments of the present disclosure do not describe all structures of the above-mentioned display panel. To realize the necessary functions of the display panel, those skilled in the art may set other structures according to specific application scenarios.
[0091] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.
Claims
1. A display panel motherboard, characterized in that: The display panel motherboard includes a display panel area and a non-display panel area surrounding the display panel area, wherein the display panel area includes a bonding area, wherein the display panel motherboard includes: A plurality of bonding pads located in the bonding area; A plurality of detection pads, corresponding to the bonding pads one by one, and located in the non-display panel area; A plurality of external pull-out wirings are arranged in the non-display panel area and are used to connect the bonding pad and the detection pad. The external pull-out wirings include at least two conductive layers.
2. The display panel motherboard according to claim 1, characterized in that: The display panel motherboard also includes: A plurality of leads are located in the display panel area, one end of each lead is connected to at least one circuit to be tested in the bonding pad, the other end of each lead is connected to the external pull-out wiring, and the other end of each external pull-out wiring is connected to the detection pad; The number of conductive layers of the outer pull-out wiring is greater than the number of conductive layers of the lead wire.
3. The display panel motherboard according to claim 2, characterized in that: The circuit to be tested includes a first circuit to be tested and a second circuit to be tested, the plurality of leads are classified into at least a first lead and a second lead, the first lead is connected to the first circuit to be tested, and the second lead is connected to the second circuit to be tested; and The display panel motherboard comprises a first conductive layer and a second conductive layer stacked together, a portion of the first conductive layer forms the first circuit to be tested and the first lead, and a portion of the second conductive layer forms the second circuit to be tested and the second lead; Preferably, the first circuit to be tested is a gate drive signal line of the display panel motherboard, the first lead and the gate metal pattern of the display panel motherboard are in the same layer structure, and / or The second circuit to be tested is a data signal line of the display panel motherboard, and the second lead line and the source-drain metal pattern of the display panel motherboard are in the same layer structure.
4. The display panel motherboard according to claim 3, characterized in that: The partially overlapping area of the first conductive layer and the second conductive layer forms the outer pull-out trace.
5. The display panel motherboard according to claim 3, characterized in that: The display panel motherboard further includes a third conductive layer located between the first conductive layer and the second conductive layer, a portion of the first conductive layer forms a first electrode of a capacitor, and a portion of the third conductive layer forms a second electrode of the capacitor; wherein, The outer pull-out trace is formed in a partially overlapping area of at least two of the first conductive layer, the second conductive layer and the third conductive layer.
6. The display panel motherboard according to claim 3, characterized in that: The display panel motherboard further includes a third conductive layer located between the first conductive layer and the second conductive layer, and a fourth conductive layer located on a side of the second conductive layer away from the third conductive layer; The outer pull-out wiring is formed by a partial overlapping area of at least two of the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer.
7. The display panel motherboard according to claim 1, characterized in that: An insulating layer is provided between at least two conductive layers forming the outer pull-out wiring, and a film through hole is provided in the insulating layer to achieve electrical connection between the at least two conductive layers.
8. The display panel motherboard according to claim 1, characterized in that: Each of the external pull-out wirings is arranged on the same layer.
9. The display panel motherboard according to claim 3, characterized in that: The external pull-out wiring connected to the first lead and the external pull-out wiring connected to the second lead are arranged in different layers.
10. A display panel, characterized in that: The display panel motherboard is obtained by cutting off the non-display panel area in the display panel motherboard as claimed in any one of claims 1 to 9.