MIM capacitor device and preparation method thereof

Abstract

The embodiment of the invention provides an MIM capacitor device and a preparation method thereof, and the method comprises the steps: forming an interconnection layer on a substrate on which a front-section semiconductor device is formed, the interconnection layer comprises a metal interconnection layer which is located in a device region and is connected with the front-section semiconductor device through a contact hole of the substrate, comprising a plurality of interconnection metal layers and interconnection through holes for connecting the adjacent interconnection metal layers; the first MIM capacitor lower polar plate comprises a plurality of lower polar plate metal layers and lower polar plate through holes connected with the adjacent lower polar plate metal layers; a waterproof layer groove with a preset depth is formed in the edge area of the interconnection layer, and the first MIM capacitor lower pole plate is located on the outer side of at least one side wall of the waterproof layer groove; depositing a waterproof layer on the surface of the interconnection layer; and forming a first MIM upper pole plate metal layer on the surface of the waterproof layer groove. According to the invention, the waterproof layer is used as a capacitor dielectric layer, and an extra MIM capacitor is prepared at the groove of the waterproof layer under the condition that a photomask is not added.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a MIM capacitor device and a preparation method thereof. Background Art

[0002] With the development of integrated circuits, the requirements for the capacity of capacitors are getting higher and higher, especially for MIM capacitors used in circuits of RF front-end modules. They not only need to have a large capacitance, but also require MIM capacitors to have a high Q value under high-frequency application conditions.

[0003] Currently, the industry usually increases the capacitance of MIM capacitors by increasing the capacitance density, increasing the area of ​​MIM capacitors, and designing a composite structure of double-layer or multi-layer MIM capacitors in parallel.

[0004] However, the above method has the problems of serious waste of wafer area and increased cost due to the increase of masks. How to achieve high capacitance density MIM capacitor devices without increasing the number of masks and wasting wafer area has become a technical problem that the industry urgently needs to solve. Summary of the invention

[0005] The present invention provides a MIM capacitor device and a preparation method thereof, which solves the technical problem of how to realize the MIM capacitor device without increasing the number of masks and wasting the wafer area.

[0006] According to a first aspect of the present invention, an embodiment of the present invention provides a method for preparing a MIM capacitor device, comprising:

[0007] A substrate is provided, on which a front-end semiconductor device and a first interlayer dielectric layer are formed, and a contact hole is formed in the first interlayer dielectric layer; wherein the substrate comprises a device region and an edge region, and the front-end semiconductor device is formed in the device region;

[0008] An interconnection layer is formed on the first interlayer dielectric layer; the interconnection layer includes a metal interconnection layer located in the device area and a first MIM capacitor lower plate located in the edge area; the metal interconnection layer is electrically connected to the contact hole, the metal interconnection layer includes a multi-layer interconnection metal layer and an interconnection through hole electrically connected to adjacent interconnection metal layers; the first MIM capacitor lower plate includes a multi-layer lower plate metal layer and a lower plate through hole electrically connected to adjacent lower plate metal layers;

[0009] A waterproof layer groove of a preset depth is formed in the edge area of ​​the interconnection layer; the lower electrode plate of the first MIM capacitor is located outside at least one side wall of the waterproof layer groove;

[0010] Depositing a waterproof layer on the surface of the interconnection layer, wherein the waterproof layer covers the surface of the interconnection layer and the bottom and sidewalls of the trench of the waterproof layer;

[0011] A first MIM upper plate metal layer is formed at the bottom and sidewall of the waterproof layer groove, and the first MIM capacitor lower plate, the waterproof layer, and the first MIM upper plate metal layer constitute a first MIM capacitor.

[0012] Optionally, forming an interconnection layer on the first interlayer dielectric layer includes:

[0013] forming a first interconnect dielectric layer on the first interlayer dielectric layer, wherein a first interconnect metal layer and a first bottom plate metal layer are formed in the first interconnect dielectric layer;

[0014] At least one barrier layer and at least one second interconnect dielectric layer are sequentially formed on the first interconnect dielectric layer, and a first interconnect through hole, a second interconnect metal layer, a first lower electrode plate through hole and a second lower electrode plate metal layer are formed in the second interconnect dielectric layer; the first interconnect through hole penetrates the barrier layer, the first interconnect through hole electrically connects the second interconnect metal layer with the first interconnect metal layer, and the first lower electrode plate through hole penetrates the barrier layer and electrically connects the second lower electrode plate metal layer with the first lower electrode plate metal layer.

[0015] Optionally, the barrier layer and the second interconnect dielectric layer are multiple layers, the multiple barrier layers and the multiple second interconnect dielectric layers are arranged at intervals, and each of the second interconnect dielectric layers is formed with a first interconnect through hole, a second interconnect metal layer, a first lower electrode plate through hole and a second lower electrode plate metal layer;

[0016] The first interconnection through hole is also electrically connected to a second interconnection metal layer of an adjacent second interconnection dielectric layer;

[0017] The first lower plate through hole is also electrically connected to the second lower plate metal layer of the adjacent second interconnect dielectric layer.

[0018] Optionally, the material of the interconnection through hole, the material of the interconnection metal layer, the material of the lower plate through hole and the material of the lower plate metal layer are the same.

[0019] Optionally, forming a waterproof layer groove of a preset depth in the edge area of ​​the interconnection layer includes:

[0020] forming a mask layer on the interconnection layer, wherein the mask layer comprises a waterproof layer pattern, and the waterproof layer pattern is located in the edge area;

[0021] The interconnection layer is etched using the mask layer as a mask to form a waterproof layer groove with a preset depth.

[0022] Optionally, the bottom of the waterproof layer groove is lower than the bottom of the interconnection metal layer in the first interconnection dielectric layer.

[0023] Optionally, the method further includes:

[0024] When forming the top interconnect metal layer in the multi-layer interconnect metal layer, forming a second MIM capacitor bottom plate metal layer;

[0025] When the first MIM upper plate metal layer is formed on the bottom and sidewall of the waterproof layer groove, a second MIM upper plate metal layer is formed on the second MIM capacitor lower plate metal layer;

[0026] The second MIM capacitor lower plate, the waterproof layer, and the second MIM upper plate metal layer constitute a second MIM capacitor.

[0027] Optionally, forming a first MIM upper plate metal layer and a second MIM upper plate metal layer includes:

[0028] Depositing an upper plate metal layer on the waterproof layer;

[0029] Forming a mask layer on the upper plate metal layer, the mask layer comprising a pattern opening of the first MIM capacitor upper plate metal layer and a pattern opening of the second MIM upper plate metal layer;

[0030] The upper electrode plate metal layer is etched using the mask layer as a mask to form a first MIM upper electrode plate metal layer and a second MIM upper electrode plate metal layer.

[0031] According to a second aspect of the present invention, an embodiment of the present invention provides a MIM capacitor device, including:

[0032] A substrate, on which a front-end semiconductor device and a first interlayer dielectric layer have been formed, and a contact hole is formed in the first interlayer dielectric layer; wherein the substrate comprises a device region and an edge region, and the front-end semiconductor device is formed in the device region;

[0033] An interconnection layer, located on the first interlayer dielectric layer, wherein the interconnection layer includes a metal interconnection layer located in the device area, a first MIM capacitor lower plate located in the edge area, and a waterproof layer groove located in the edge area of ​​the interconnection layer; the metal interconnection layer is electrically connected to the contact hole, and the metal interconnection layer includes a multi-layer interconnection metal layer and an interconnection through hole electrically connected to adjacent interconnection metal layers; the first MIM capacitor lower plate is located on the outer side of at least one side wall of the waterproof layer groove, including a multi-layer lower plate metal layer and a lower plate through hole electrically connected to adjacent lower plate metal layers;

[0034] A waterproof layer, located on the surface of the interconnection layer, the waterproof layer covers the surface of the interconnection layer, and the bottom and sidewalls of the trench of the waterproof layer;

[0035] The first MIM upper plate metal layer is formed at the bottom and sidewall of the waterproof layer groove; wherein the first MIM capacitor lower plate, the waterproof layer, and the first MIM upper plate metal layer constitute the first MIM capacitor.

[0036] Optionally, the MIM capacitor device further includes a second MIM capacitor, and the second MIM capacitor includes:

[0037] A second MIM capacitor bottom plate metal layer is formed simultaneously with a top interconnect metal layer in the multi-layer interconnect metal layer;

[0038] A second MIM upper plate metal layer is formed on the waterproof layer and covers a first portion of the second MIM capacitor lower plate metal layer, and the second MIM upper plate metal layer is formed simultaneously with the first MIM capacitor upper plate metal layer;

[0039] The second MIM capacitor lower plate, the waterproof layer, and the second MIM upper plate metal layer constitute the second MIM capacitor.

[0040] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0041] In the MIM capacitor device and its preparation method provided by the technical solution of the present invention, the method forms a first MIM capacitor lower plate outside at least one side wall of the waterproof layer groove, uses the waterproof layer as a capacitor dielectric layer, forms a first MIM upper plate metal layer at the bottom and side wall of the waterproof layer groove, and the first MIM capacitor lower plate, the waterproof layer, and the first MIM upper plate metal layer constitute a first MIM capacitor. Since the waterproof layer is an inherent structure in existing semiconductor devices, the preparation method of the waterproof layer is also an inherent procedure of existing semiconductor devices. This method cleverly realizes the formation of the first MIM capacitor in the process of forming the waterproof layer, and realizes the preparation of an additional MIM capacitor at the waterproof layer groove without adding a photomask, which efficiently utilizes the wafer area; and since the waterproof layer groove is a deep groove, the area of ​​the first MIM capacitor is greatly increased compared to conventional MIM capacitors, thereby greatly improving the capacitance of the MIM capacitor.

[0042] Furthermore, the material of the interconnection through hole, the material of the interconnection metal layer, the material of the lower plate through hole and the material of the lower plate metal layer are the same, so that the lower plate of the first MIM capacitor can be prepared while forming the interconnection layer, without the need for additional processes, saving the number of masks and further saving costs. Furthermore, since the material of the interconnection through hole and the material of the interconnection metal layer are metallic copper, the resistance value of the lower plate of the first MIM capacitor is greatly reduced, and the Q value of the capacitor is improved.

[0043] Furthermore, when forming the top interconnect metal layer in the multi-layer interconnect metal layer, a second MIM capacitor lower plate metal layer is also formed at the same time, and when forming the first MIM upper plate metal layer, a second MIM upper plate metal layer is formed on the second MIM capacitor lower plate metal layer, thereby forming a second MIM capacitor using the second MIM capacitor lower plate metal layer, the waterproof layer, and the second MIM upper plate metal layer. The second MIM capacitor can be connected in parallel with the first MIM capacitor, thereby further increasing the capacitance of the MIM capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0045] Figure 1 A flow chart of a method for preparing a MIM capacitor device provided in one embodiment of the present invention;

[0046] Figure 2 to Figure 20 A schematic diagram of the device structure corresponding to each step of the method for preparing a MIM capacitor device provided in one embodiment of the present invention.

[0047] Description of reference numerals:

[0048] 10-substrate;

[0049] 101 - top silicon layer;

[0050] 102-insulating layer;

[0051] 103 - bottom substrate;

[0052] 104-a first interlayer dielectric layer;

[0053] 105-front-end semiconductor device;

[0054] 106-contact hole blocking layer;

[0055] 107- contact hole;

[0056] 108- a first barrier layer;

[0057] 109-device area;

[0058] 110 - marginal zone;

[0059] 20-interconnection layer;

[0060] 201-first interconnect dielectric layer;

[0061] 202- first oxide layer;

[0062] 203-a first hard mask layer;

[0063] 204- second barrier layer;

[0064] 205-metal material layer;

[0065] 206-second interconnect dielectric layer;

[0066] 207- a second hard mask layer;

[0067] 208- waterproof layer;

[0068] 210 - metal interconnection layer;

[0069] 211 - first interconnect metal layer;

[0070] 212-first interconnection through hole;

[0071] 213 - second interconnect metal layer;

[0072] 220-first MIM capacitor lower plate;

[0073] 221 - first lower plate metal layer;

[0074] 222-first lower plate through hole;

[0075] 223 - second lower plate metal layer;

[0076] 230 - second MIM lower plate metal layer;

[0077] 240-first MIM upper plate metal layer;

[0078] 241 - a third barrier material layer;

[0079] 242-second MIM upper plate metal layer;

[0080] 243- third barrier layer;

[0081] 301- photoresist layer;

[0082] 401-third interconnect dielectric layer;

[0083] 402-through hole;

[0084] 403- fourth interconnect dielectric layer;

[0085] 404 - second metal interconnection layer;

[0086] 405- fourth barrier layer;

[0087] 406-fifth interconnect dielectric layer;

[0088] 407-contact metal layer;

[0089] 408-buffer layer;

[0090] 409 - passivation layer. DETAILED DESCRIPTION

[0091] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0092] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0093] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0094] Before filing this application, the applicant has conducted sufficient research on MIM capacitors. MIM capacitors are widely used in the electronic field as charge storage, coupling, and filtering devices. The preparation of MIM capacitors is an important link in the process flow of semiconductor integrated circuits. With the increasing requirements for semiconductor chip integration and chip performance, there is an urgent need to improve the overall performance of semiconductor devices to achieve faster computing speeds, larger data storage capacity, and more functions, and the requirements for the capacity of capacitors are getting higher and higher. In particular, MIM capacitors are used in the circuits of RF front-end modules, which not only require MIM capacitors to have large capacitance, but also require MIM capacitors to have high Q values ​​under high-frequency application conditions to meet the needs of 5G, Sub-6G, and millimeter waves.

[0095] The quality factor Q can reflect the loss of the capacitor. The higher the quality factor, the smaller the distortion and the better the capacitor performance. The calculation formula of the quality factor Q can be expressed as:

[0096] Q=2πfL / R

[0097] Among them, f is the resonant frequency of the capacitor, L is the inductance value, and R is the resistance value of the resonant circuit. Among them, the resistance value of the upper plate and the lower plate of the MIM capacitor will also affect its Q value. The lower resistance of the upper plate and the lower plate of the MIM capacitor will help reduce the loss of the capacitor, thereby improving the Q value of the capacitor and making it perform better in high-frequency applications.

[0098] The ratio of the charge carried by a capacitor to the voltage U between the two electrodes of the capacitor is called the capacitance of the capacitor. The capacitance value of a capacitor can be calculated by the following formula:

[0099] C=ε·A / d

[0100] Where C represents the capacitance value, ε represents the dielectric constant, A represents the area of ​​the capacitor plates, and d represents the dielectric thickness of the capacitor.

[0101] In view of the three methods of increasing the capacitance of capacitors in RF chips studied by the applicant in the background technology and their existing defects, the applicant has conducted in-depth research on how to prepare MIM capacitors with high capacitance density without increasing the number of masks and wasting wafer area in combination with the inherent procedures of chip manufacturing, and found a breakthrough in solving the corresponding technical problems, as follows:

[0102] The applicant found that in high-frequency applications, in order to ensure the normal reception and transmission of signals, RF chips usually use discontinuous die seal rings, but this will cause water vapor to easily penetrate into the chip, thus affecting its reliability. Therefore, RF chips have extremely high requirements for waterproofness. The RFSOI process usually adds an extra layer of mask to make a waterproof layer (WBL, water block layer) to protect the circuit and improve the reliability of the chip. Specifically, the waterproof layer is located on the periphery of the RF chip body and is arranged around the RF chip body. In the process of forming the waterproof layer, a waterproof layer groove must be formed first, and then the waterproof layer is filled, wherein the waterproof layer groove is a deep groove structure.

[0103] In view of this, the present invention proposes a method for preparing a MIM capacitor device, which may include:

[0104] A substrate is provided, on which a front-end semiconductor device and a first interlayer dielectric layer are formed, and a contact hole is formed in the first interlayer dielectric layer; wherein the substrate comprises a device region and an edge region, and the front-end semiconductor device is formed in the device region.

[0105] An interconnection layer is formed on the first interlayer dielectric layer; the interconnection layer includes a metal interconnection layer located in the device area and a first MIM capacitor lower plate located in the edge area; the metal interconnection layer is electrically connected to the contact hole, and the metal interconnection layer includes a multi-layer interconnection metal layer and an interconnection through hole electrically connected to adjacent interconnection metal layers; the first MIM capacitor lower plate includes a multi-layer lower plate metal layer and a lower plate through hole electrically connected to adjacent lower plate metal layers.

[0106] A waterproof layer groove of a preset depth is formed in the edge area of ​​the interconnection layer; and the lower electrode plate of the first MIM capacitor is located on the outer side of at least one side wall of the waterproof layer groove.

[0107] A waterproof layer is deposited on the surface of the interconnection layer, and the waterproof layer covers the surface of the interconnection layer, as well as the bottom and sidewalls of the waterproof layer groove.

[0108] A first MIM upper plate metal layer is formed at the bottom and sidewall of the waterproof layer groove, and the first MIM capacitor lower plate, the waterproof layer, and the first MIM upper plate metal layer constitute a first MIM capacitor.

[0109] It can be seen that the preparation method of the MIM capacitor device provided by the technical solution of the present invention utilizes the inherent waterproof layer in the preparation process of the RF chip and the preparation process of the waterproof layer groove corresponding to the waterproof layer, and uses the waterproof layer as the capacitor dielectric layer. An additional first MIM capacitor is prepared at the waterproof layer groove without adding a mask, thereby efficiently utilizing the wafer area; and because the waterproof layer groove is a deep groove, the area of ​​the MIM capacitor is greatly increased compared to the conventional MIM capacitor, thereby greatly improving the capacitance of the MIM capacitor.

[0110] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, the technical scheme of the present invention is described in detail below with reference to the accompanying drawings.

[0111] Figure 1 A flow chart of a method for preparing a MIM capacitor device provided in one embodiment of the present invention; Figures 2 to 19 A schematic diagram of the device structure corresponding to each step of the method for preparing a MIM capacitor device provided in one embodiment of the present invention.

[0112] Please refer to Figure 1 , and combined with reference Figures 2 to 19 In this embodiment, the number of interconnection layers is 3 as an example for illustration. The method for preparing a MIM capacitor device provided by the embodiment of the present invention may include:

[0113] S1: providing a substrate 10, on which a front-end semiconductor device and a first interlayer dielectric layer 104 are formed, and a contact hole 107 is formed in the first interlayer dielectric layer 104; wherein the substrate 10 comprises a device region 109 and an edge region 110, and the front-end semiconductor device is formed in the device region 109; Figure 2 shown.

[0114] The substrate 10 may be an SOI substrate. Specifically, the SOI substrate is a silicon-on-insulator substrate, that is, an insulating layer 102 is added between the top silicon 101 and the bottom substrate 103. SOI substrates are widely used in CMOS devices, radio frequency devices, and silicon photonic devices. Of course, the present invention is not limited thereto, and the substrate in the embodiment of the present invention may also be other types of substrates, such as a germanium-on-insulator substrate.

[0115] In one embodiment, the substrate 10 may include a plurality of device regions 109, each of which may be used to form a corresponding semiconductor device; the edge region 110 may be a region located at the periphery of the device region 109 and disposed around the device region 109. Specifically, for example, the outer side of the device region 109 is usually a sealing ring, the outer side of the sealing ring is a cutting tape, and the edge region 110 is located between the device region 109 and the sealing ring.

[0116] As a preferred method, Figure 2 In the example, the surface of the sidewall and the bottom of the contact hole 107 also has a contact hole barrier layer 106 to prevent the metal material in the contact hole 107 from diffusing into the first interlayer dielectric layer 104 .

[0117] Please continue to refer to Figure 2 In a preferred embodiment, a first barrier layer 108 is further formed on the first interlayer dielectric layer 104, and the first barrier layer 108 is used to prevent the metal material in the contact hole 107 from diffusing into the interconnection layer formed subsequently.

[0118] As an example, the first barrier layer 108 can be formed on the first interlayer dielectric layer 104 by chemical vapor deposition (CVD). Of course, the present invention is not limited thereto, and can also be formed by physical vapor deposition, heat treatment, etc., and those skilled in the art can select a suitable formation method as needed.

[0119] In one embodiment, the material of the first barrier layer 108 may be carbon nitride (NDC) or other nitride / carbide based composite material layers.

[0120] S2: forming an interconnection layer on the first interlayer dielectric layer; the interconnection layer comprises a metal interconnection layer located in the device area and a first MIM capacitor lower plate located in the edge area; the metal interconnection layer is electrically connected to the contact hole, the metal interconnection layer comprises a multi-layer interconnection metal layer and an interconnection through hole electrically connected to adjacent interconnection metal layers; the first MIM capacitor lower plate comprises a multi-layer lower plate metal layer and a lower plate through hole electrically connected to adjacent lower plate metal layers.

[0121] As an implementation manner, the method of forming an interconnection layer on the first interlayer dielectric layer 104 in step S2, for example, specifically includes:

[0122] S21: forming a first interconnect dielectric layer on the first interlayer dielectric layer 104, and forming a first interconnect metal layer and a first bottom plate metal layer in the first interconnect dielectric layer.

[0123] Please refer to Figure 3 to Figure 7 The specific formation process of step S21 is explained.

[0124] exist Figure 3 In the example, the first interconnect dielectric layer 201 is formed on the first barrier layer 108 .

[0125] The first interconnect dielectric layer 201 may be silicon oxide, silicon nitride, aluminum oxide, LK material, ULK material, HK (high dielectric constant) material, etc. The LK material may include organic silicon, silicon fluoride, polyimide, etc.

[0126] Preferably, the first interconnect dielectric layer 201 may be made of LK material or ULK material, so as to reduce the dielectric constant K of the metal interconnect interlayer insulating layer, thereby avoiding the increase of RC delay time, crosstalk noise, power consumption, etc.

[0127] Please continue to refer to Figure 3 After forming the first interconnect dielectric layer 201 , a first oxide layer 202 , a first hard mask layer 203 and a photoresist layer 301 may be sequentially formed on the first interconnect dielectric layer 201 .

[0128] In this embodiment, the first hard mask layer 203 is used to protect the functional layers below the first hard mask layer. The present invention does not specifically limit the material of the first hard mask layer, which can be any metal compound material that plays a protective role. In a specific embodiment, the material of the first hard mask layer 203 can be TiN.

[0129] In this embodiment, please refer to Figure 4 The photoresist layer 301 can be exposed and developed using a photomask to form a patterned photoresist layer 301 , that is, to form a mask layer 302 .

[0130] In this embodiment, the mask layer 302 includes a photolithography pattern, and the photolithography pattern includes a first interconnect metal layer pattern and a first lower plate metal layer pattern. The first interconnect metal layer pattern is located in the device area and corresponds to the contact hole; the first lower plate metal layer pattern is located in the edge area.

[0131] In this embodiment, please refer to Figure 5 , using the mask layer 302 as a mask and the surface of the first interlayer dielectric layer 104 as an etching stop layer, the first hard mask layer 203, the first oxide layer 202, the first interconnect dielectric layer 201 and the first barrier layer 108 are etched in sequence to form a first interconnect metal groove and a first lower plate metal groove.

[0132] In this embodiment, the first interconnect metal groove is located in the device region and exposes the top surface of the contact hole and a portion of the surface of the first interlayer dielectric layer 104. The first bottom plate metal groove is located in the edge region and exposes a portion of the surface of the first interlayer dielectric layer 104.

[0133] In this embodiment, after the etching is completed, the remaining mask layer 302 is removed.

[0134] In this embodiment, please refer to Figure 6, a second barrier layer 204 is deposited on the surface of the substrate 10 , and the second barrier layer 204 conformally covers the ground and sidewalls of the first interconnect metal groove and the first lower plate metal groove, and covers the remaining surface of the first hard mask layer 203 .

[0135] In this embodiment, continue to refer to Figure 6 , metal material can be filled into the first interconnect metal groove and the first lower plate metal groove to form a metal material layer 205.

[0136] In one embodiment, the metal material may be copper (Cu), so as to increase chip speed and reduce resistance. In other embodiments, the metal material is not limited, and the metal material may also be other metals, such as aluminum.

[0137] In one embodiment, when the metal material is copper (Cu), the material of the second barrier layer 204 can be tantalum (Ta), tantalum nitride (TaN), or a combination of tantalum (Ta) and tantalum nitride (TaN), which serves as an adhesion layer for copper and a barrier layer for preventing copper diffusion.

[0138] In this embodiment, please refer to Figure 7 , using the first interconnect dielectric layer 201 as a stop layer, the metal material layer 205 is ground until the first hard mask layer 203 and the first oxide layer 202 are removed, thereby forming the first interconnect metal layer 211 and the first lower electrode metal layer 221, wherein the surface of the first interconnect metal layer 211 and the surface of the first lower electrode metal layer 221 are flush with the surface of the first interconnect dielectric layer 201.

[0139] As an example, the grinding method is chemical mechanical polishing (CMP). In other embodiments, the present invention is not limited to this, and other grinding methods are also within the protection scope of the present invention.

[0140] For the convenience of description, the second barrier layer 204 is omitted in subsequent figures.

[0141] S22: at least one barrier layer and at least one second interconnect dielectric layer are sequentially formed on the first interconnect dielectric layer 201, wherein a first interconnect via, a second interconnect metal layer, a first lower electrode plate via and a second lower electrode plate metal layer are formed in the second interconnect dielectric layer; the first interconnect via penetrates the barrier layer, the first interconnect via electrically connects the second interconnect metal layer with the first interconnect metal layer, the first lower electrode plate via penetrates the barrier layer, and electrically connects the second lower electrode plate metal layer with the first lower electrode plate metal layer.

[0142] Please refer to Figure 8-Figure 9Now, taking the example of sequentially forming two barrier layers and two second interconnect dielectric layers on the first interconnect dielectric layer 201, the step S21 is described.

[0143] Please refer to Figure 8 A barrier layer 209 and a second interconnect dielectric layer 206 are sequentially formed on the first interconnect dielectric layer 201, and a first interconnect through hole 212, a second interconnect metal layer 213, a first lower electrode plate through hole 222 and a second lower electrode plate metal layer 223 are formed in the second interconnect dielectric layer 206; the first interconnect through hole 212 penetrates the barrier layer 209, and the first interconnect through hole 212 electrically connects the second interconnect metal layer 213 and the first interconnect metal layer 211, and the first lower electrode plate through hole 222 penetrates the barrier layer 209 and electrically connects the second lower electrode plate metal layer 223 and the first lower electrode plate metal layer 221.

[0144] In this embodiment, the material of the barrier layer 209 may be SiN. The present invention is not limited to this, and those skilled in the art may select a suitable barrier layer material as needed.

[0145] In this embodiment, the barrier layer 209 and the second interconnect dielectric layer 206 may be formed first, and after the second interconnect dielectric layer 206 is formed, the first interconnect through hole groove, the second interconnect metal groove, the first lower plate through hole groove and the second lower plate metal groove are formed in the second interconnect dielectric layer 206, and then the metal material is deposited and ground. The specific preparation process thereof refers to the preparation process of the first interconnect metal layer and the first lower plate metal layer, which will not be described in detail here.

[0146] In this embodiment, the metal forming the first interconnection through hole 212, the second interconnection metal layer 213, the first lower electrode plate through hole 222 and the second lower electrode plate metal layer 223 can be the same as the aforementioned first interconnection metal layer and the first lower electrode plate metal layer, and the material of the second interconnection dielectric layer 206 can also be the same as the aforementioned first interconnection dielectric layer 201.

[0147] In this embodiment, the barrier layer and the second interconnect dielectric layer are multiple layers. In this case, the multiple barrier layers and the multiple second interconnect dielectric layers are arranged at intervals, and each of the second interconnect dielectric layers is formed with a first interconnect through hole, a second interconnect metal layer, a first lower electrode plate through hole and a second lower electrode plate metal layer.

[0148] The first interconnection via is also electrically connected to a second interconnection metal layer adjacent to the second interconnection dielectric layer.

[0149] The first lower plate through hole is also electrically connected to the second lower plate metal layer of the adjacent second interconnect dielectric layer.

[0150] Specifically, please refer to Fig. 9 A second barrier layer 209 and a second second interconnect dielectric layer 206 are sequentially formed on the second interconnect dielectric layer 206, and a first interconnect through hole 212, a second interconnect metal layer 213, a first lower electrode through hole 222 and a second lower electrode metal layer 223 are formed in the second interconnect dielectric layer 206.

[0151] The first interconnection through-hole 212 is electrically connected to the second interconnection metal layer 213 adjacent to the second interconnection dielectric layer 206 , and the first lower plate through-hole 222 is also electrically connected to the second lower plate metal layer 223 adjacent to the second interconnection dielectric layer 206 .

[0152] It can be seen that in Fig. 9 In the example, an interconnection layer 20 is formed on the first interlayer dielectric layer 104; wherein the interconnection layer 20 includes the metal interconnection layer 210 and the first MIM capacitor lower plate 220; wherein the metal interconnection layer 210 is used to electrically connect to the contact hole 107; the first MIM capacitor lower plate 220 is located in the edge area 110; the metal interconnection layer includes multiple interconnection metal layers and interconnection through holes electrically connected to adjacent interconnection metal layers; the first MIM capacitor lower plate 220 includes multiple lower plate metal layers and lower plate through holes electrically connected to adjacent lower plate metal layers. Of course, it should be appreciated that the number of metal interconnection layers and the number of lower plate metal layers in this embodiment are only examples. According to actual conditions, the number of metal interconnection layers and lower plate metal layers can also be other values, such as four layers, five layers, etc., which are all within the scope of protection of the present invention.

[0153] In addition, by Fig. 9 As can be seen from the example, in this embodiment, the number of the first MIM capacitor bottom plates 220 is two. In practical applications, the number of the first MIM capacitor bottom plate 220 may also be one.

[0154] In the manufacturing process of the embodiment of the present invention, the height of the interconnection metal layer in each interconnection dielectric layer is the same as the height of the lower plate metal layer, and the height of the interconnection through hole in each interconnection dielectric layer is the same as the height of the lower plate through hole. It should be understood that the present invention does not limit the widths of the interconnection metal layer in each interconnection dielectric layer, the lower plate metal layer, the interconnection through hole, and the lower plate through hole.

[0155] In a preferred embodiment, the material of the interconnection through-hole, the material of the interconnection metal layer, the material of the lower plate through-hole and the material of the lower plate metal layer are the same.

[0156] Thus, the first MIM capacitor bottom plate of the present invention can be prepared while forming the interconnection layer, without the need for additional processes, saving the number of masks and further saving costs. Furthermore, since the material of the interconnection through hole and the material of the interconnection metal layer are copper metal, the resistance value of the first MIM capacitor bottom plate is greatly reduced, and the Q value of the first MIM capacitor obtained subsequently is improved.

[0157] In a preferred embodiment, when performing the preparation process corresponding to step S22, when forming the top interconnection metal layer in the multi-layer interconnection metal layer, the preparation method of the MIM capacitor device may further include:

[0158] S221: When forming the top interconnect metal layer in the multi-layer interconnect metal layer, forming the second MIM capacitor bottom plate metal layer 230; Fig. 9 shown.

[0159] In a preferred embodiment, the material of the second MIM capacitor lower plate metal layer 230 is the same as the material of the interconnect metal layer, thereby reducing the difficulty of the preparation process and also greatly reducing the resistance value of the second MIM capacitor lower plate, thereby improving the Q value of the subsequently obtained second MIM capacitor.

[0160] In one of the embodiments, after forming the top interconnect metal layer in the multi-layer interconnect metal layer, the method may further include:

[0161] A second hard mask layer 207 is formed on the interconnect layer. Fig.10 shown.

[0162] Specifically, the material of the second hard mask layer can be one of SiN / SiO2 or a combination of the two. In the embodiment of the present invention, the material of the second hard mask layer can also be set to be consistent with the waterproof layer. The second hard mask layer mainly plays a protective role, protecting the functional layers below the second hard mask layer.

[0163] Please continue to refer to Figure 1 , executing step S3: forming a waterproof layer groove of a preset depth in the edge area 110 of the interconnection layer; wherein the first MIM capacitor lower electrode plate 220 is located on the outside of at least one side wall of the waterproof layer groove.

[0164] As an embodiment, the method of forming a waterproof layer groove of a preset depth at the edge area 110 of the interconnection layer in step S3 may specifically include:

[0165] S31: forming a mask layer 303 on the interconnection layer, wherein the mask layer 303 comprises a waterproof layer pattern, and the waterproof layer pattern is located in the edge region; Fig.11 shown.

[0166] Specifically, a mask layer 303 is formed on the interconnection layer 20 after photolithography and development.

[0167] It should be noted that, since there are two first MIM capacitor lower plates 220 in this embodiment, the waterproof layer pattern is located between the two first MIM capacitor lower plates 220. It should be noted that if there is only one first MIM capacitor lower plate, the waterproof layer pattern can be located on one side of the first MIM capacitor lower plate.

[0168] It should be understood that Fig.11 The example is based on forming a second hard mask layer 207 on the interconnect layer. In actual implementation, other methods can also be used to form the mask layer 303 on the interconnect layer, that is, the second hard mask layer 207 can be excluded or other functional layers can be added, and the present invention is not limited thereto.

[0169] S32: using the mask layer 303 as a mask to etch the interconnect layer to form a waterproof layer groove of a preset depth; Fig.12 shown.

[0170] The bottom of the waterproof layer groove is lower than the bottom of the interconnect metal layer in the first interconnect dielectric layer. Of course, the present invention is not limited to this. In actual preparation, the interface between the substrate 10 and the first interlayer dielectric layer 104 can also be used as an etching stop layer, and etching can be performed in the edge area 110 of the interconnect layer to form the waterproof layer groove, that is, the bottom of the waterproof layer groove can contact the surface of the substrate 10.

[0171] exist Fig.12 In the example, the two first MIM capacitor lower plates 220 are respectively located on the outer sides of the two side walls of the waterproof layer groove. During preparation, the first MIM capacitor lower plate 220 should be close to the waterproof layer groove, and the distance between the first MIM capacitor lower plate 220 and the waterproof layer groove is greater than or equal to 0 microns and less than or equal to 0.5 microns.

[0172] Please continue to refer to Fig.13 , remove the mask layer 303.

[0173] exist Fig.13 Please continue to refer to Figure 1 , executing step S4: depositing a waterproof layer 208 on the surface of the interconnection layer, the waterproof layer 208 covers the surface of the interconnection layer 20, and the bottom and sidewalls of the waterproof layer groove; after the waterproof layer 208 is deposited, the device is as follows Fig.14 shown.

[0174] In a specific implementation, the waterproof layer 208 may be deposited by plasma enhanced chemical vapor deposition (PECVD). In the embodiment of the present invention, the waterproof layer 208 also serves as a dielectric layer of the MIM, and its thickness may range from tens of angstroms to thousands of angstroms.

[0175] As an example, the material of the waterproof layer 208 may be silicon nitride (SIN). Of course, the present invention is not limited to this, and the waterproof layer 208 may also be a dense layer of other materials, such as hafnium dioxide (HfO2), aluminum oxide, and the like.

[0176] Please continue to refer to Figure 1 , execute step S5: form a first MIM upper plate metal layer 240 located at the bottom and sidewall of the waterproof layer groove, wherein the first MIM capacitor lower plate 220, the waterproof layer 208, and the first MIM upper plate metal layer 240 constitute a first MIM capacitor.

[0177] Since the metal material forming the first MIM top plate metal layer 240 is easy to diffuse, it is necessary to form a third barrier layer 243 on the surface of the first MIM top plate metal layer 240 to prevent the diffusion of the metal material in subsequent processes.

[0178] On this basis, as a specific implementation, step S5 may specifically include:

[0179] S511: forming a MIM top plate metal material layer, a third barrier material layer 241 , and a photoresist layer in sequence on the surface of the substrate 10 .

[0180] S512 : patterning the photoresist layer to form a mask layer 304 .

[0181] S513: Using the mask layer 304 as a mask, etching the first portion of the MIM upper plate metal material layer and the first portion of the third barrier material layer 241 to form the first MIM upper plate metal layer 240, such as Fig.15 shown.

[0182] S514: removing the mask layer 304.

[0183] S515: depositing a third barrier layer material on the surface of the substrate 10 to form the third barrier layer 243 covering the surface and sidewalls of the first MIM upper plate metal layer 240, such as Fig.16 shown.

[0184] In a preferred embodiment, if the material of the first MIM upper electrode metal layer 240 is aluminum, then for the through hole connected to the MIM upper electrode formed in the subsequent process, the mobility of aluminum relative to the metal copper in the through hole is lower and it is not easy to diffuse. Therefore, it is no longer necessary to deposit the third barrier layer 243 on the surface of the first MIM upper electrode metal layer 240.

[0185] exist Fig.16 In the example, the first MIM upper plate metal layer 240 in the waterproof layer groove extends to the surface of the area on both sides of the waterproof layer groove. Of course, the first MIM upper plate metal layer 240 can be formed only on the bottom and sidewalls of the waterproof layer groove, such as Fig.17 As shown, the formation process thereof is prior art and will not be described in detail here.

[0186] It can be seen that the method provided by the embodiment of the present invention forms a first MIM capacitor lower plate outside the side wall of the waterproof layer groove, uses the waterproof layer as a capacitor dielectric layer, forms a first MIM upper plate metal layer at the bottom and side wall of the waterproof layer groove, and the first MIM capacitor lower plate, the waterproof layer, and the first MIM upper plate metal layer constitute a first MIM capacitor. Since the preparation of the waterproof layer is an inherent procedure of existing semiconductor devices, this method cleverly realizes the formation of the first MIM capacitor in the process of forming the waterproof layer, and realizes the preparation of an additional MIM capacitor at the waterproof layer groove without adding a photomask, which efficiently utilizes the wafer area; and since the waterproof layer groove is a deep groove, the area of ​​the MIM capacitor is greatly increased compared to conventional MIM capacitors, thereby greatly improving the capacitance of the MIM capacitor.

[0187] Please continue to refer to Fig.16 In a preferred embodiment, when a second MIM capacitor bottom plate metal layer 230 is also formed in the interconnect layer, the method may further include:

[0188] When the first MIM upper plate metal layer 240 is formed on the bottom and sidewall of the waterproof layer groove, the second MIM upper plate metal layer 242 is formed on the second MIM capacitor lower plate metal layer 230 .

[0189] The second MIM capacitor lower plate 230 , the waterproof layer 208 , and the second MIM upper plate metal layer 242 constitute a second MIM capacitor.

[0190] Specifically, the method of forming the first MIM upper plate metal layer 240 and the second MIM upper plate metal layer 242 may include:

[0191] S521: depositing an upper plate metal layer on the waterproof layer.

[0192] S522: forming a mask layer on the upper plate metal layer, wherein the mask layer includes a first MIM capacitor upper plate metal layer pattern and a second MIM upper plate metal layer pattern.

[0193] S523: using the mask layer as a mask, etching the upper plate metal layer to form a first MIM upper plate metal layer 240 and a second MIM upper plate metal layer 242; Fig.16 shown.

[0194] In this case, the second MIM capacitor and the first MIM capacitor can be connected in parallel, thereby further increasing the capacitance of the MIM capacitor, increasing the plate area of ​​the MIM capacitor without reducing the grain size, and thus realizing a MIM capacitor with a high capacitance value.

[0195] It should be understood that the present invention does not limit the material of the first MIM top plate metal layer 240 or the second MIM top plate metal layer 242, and the material may be titanium Ti, titanium nitride TiN, aluminum Al, tantalum nitride TaN, etc.

[0196] It can be seen that in one processing area (shot), the proportion of the layout area consumed by the MIM capacitor formed in the embodiment of the present invention is <0.008%, while the effective area (or plate area) of the MIM capacitor is increased by approximately 220,000 square microns, which is much larger than the effective area (or plate area) of the ordinary MIM capacitor formed in the prior art (approximately several hundred square microns to 10 square millimeters).

[0197] Of course, the preparation process of semiconductor devices also includes other processes. Fig.17 After the MIM capacitors, please continue to refer to Figure 18 to Figure 20 Provide explanation.

[0198] Please refer to Fig.18 , depositing a third interconnect dielectric layer 401 on the surface of the substrate 10 ; and performing surface planarization treatment on the third interconnect dielectric layer 401 .

[0199] Specifically, the third interconnect dielectric layer 401 can be silicon oxide, silicon nitride, aluminum oxide, LK material, ULK material, etc. Preferably, since the RF chip needs to increase the speed and reduce the parasitic capacitance to improve its performance, LK material or ULK material is often used as the interconnect dielectric layer. Among them, LK material includes organic silicon, silicon fluoride, polyimide, etc.

[0200] Please refer to Fig.19 , forming a through hole 402 at a preset position of the third interconnect dielectric layer 401 to connect the metal interconnect layer 210, the first MIM capacitor and the second MIM capacitor.

[0201] Please refer to Fig. 20 , a new barrier layer 410 and a fourth interconnection dielectric layer 403 are sequentially formed on the third interconnection dielectric layer 401, the fourth interconnection dielectric layer 403 includes a second metal interconnection layer 404, and the second metal interconnection layer 404 is electrically connected to the corresponding through hole 402; a fourth barrier layer 405 and a fifth interconnection dielectric layer 406 are sequentially formed on the fourth interconnection dielectric layer 403; the interface between the fourth barrier layer 405 and the second metal interconnection layer 404 is used as an etching stop layer, and the fifth interconnection dielectric layer 406 and the fourth barrier layer 405 are sequentially etched to form a second recess; a metal material is filled into the second recess to form a contact metal layer 407, and the contact metal layer 407 also extends to the surface of the fifth interconnection dielectric layer 406; a buffer layer 408 and a passivation layer 409 are sequentially formed on the surface of the substrate 10.

[0202] In summary, the embodiment of the present invention cleverly utilizes the waterproof layer 208 as a capacitor dielectric layer, and prepares additional MIM capacitors in the trenches of the waterproof layer without adding a photomask, thereby efficiently utilizing the wafer area and increasing the capacitance.

[0203] In addition, please continue to refer to Fig.15 The embodiment of the present invention further provides a MIM capacitor device, which may include:

[0204] A substrate 10 on which a front-end semiconductor device 105 and a first interlayer dielectric layer 104 are formed, and a contact hole 107 is formed in the first interlayer dielectric layer 104; wherein the substrate 10 includes a device region 109 and an edge region 110, and the front-end semiconductor device 105 is formed in the device region 109.

[0205] The interconnection layer 20 is located on the first interlayer dielectric layer 104, wherein the interconnection layer 20 includes a metal interconnection layer 210 located in the device area, a first MIM capacitor lower plate 220 located in the edge area, and a waterproof layer groove located in the edge area 110 of the interconnection layer 20; the metal interconnection layer 210 is electrically connected to the contact hole 107, and the metal interconnection layer 210 includes multiple layers of interconnection metal layers and interconnection through holes electrically connected to adjacent interconnection metal layers; the first MIM capacitor lower plate 220 is located on the outside of at least one side wall of the waterproof layer groove, including multiple layers of lower plate metal layers and lower plate through holes electrically connected to adjacent lower plate metal layers.

[0206] The waterproof layer 208 is located on the surface of the interconnection layer 20 , and covers the surface of the interconnection layer 20 , as well as the bottom and sidewalls of the waterproof layer groove.

[0207] The first MIM upper plate metal layer 240 is formed at the bottom and sidewall of the waterproof layer groove; wherein the first MIM capacitor lower plate 220, the waterproof layer 208, and the first MIM upper plate metal layer 240 constitute the first MIM capacitor.

[0208] The bottom of the waterproof layer groove is lower than the bottom of the interconnection metal layer in the first interconnection dielectric layer 201 .

[0209] It can be seen that the present invention uses the waterproof layer 208 as a capacitor dielectric layer, and prepares additional MIM capacitors in the trenches of the waterproof layer without adding a mask, which effectively utilizes the wafer area and increases the capacitance.

[0210] In a preferred embodiment, the material of the interconnection through-hole, the material of the interconnection metal layer, the material of the lower plate through-hole and the material of the lower plate metal layer are the same.

[0211] Therefore, the present invention does not require additional processes when forming the lower electrode metal layer, and uses the existing bottom metal as the lower electrode of the additional MIM capacitor, which not only reduces the resistance value and improves the Q value of the capacitor, but also saves the number of masks and reduces costs.

[0212] In a preferred embodiment, please continue to refer to Fig.15 , the MIM capacitor device may further include a second MIM capacitor, and the second MIM capacitor may include:

[0213] The second MIM capacitor bottom plate metal layer 230 is formed simultaneously with the top interconnect metal layer in the multi-layer interconnect metal layer.

[0214] The second MIM upper plate metal layer 242 is formed on the waterproof layer and covers the first portion of the second MIM capacitor lower plate metal layer 230 , and the second MIM upper plate metal layer 242 and the first MIM capacitor upper plate metal layer 240 are formed simultaneously.

[0215] The second MIM capacitor lower plate 230 , the waterproof layer 208 , and the second MIM upper plate metal layer 242 constitute the second MIM capacitor.

[0216] It can be seen that the additional MIM capacitor prepared in the waterproof layer groove of the present invention does not occupy the position of the original MIM capacitor, which effectively utilizes the wafer area and increases the capacitance.

[0217] Preferably, the material of the second MIM capacitor bottom plate metal layer 230 is the same as that of the interconnect metal layer, which reduces the difficulty of the manufacturing process.

[0218] In summary, the embodiment of the present invention forms a first MIM capacitor lower plate outside at least one side wall of the waterproof layer groove, uses the waterproof layer as a capacitor dielectric layer, forms a first MIM upper plate metal layer at the bottom and side wall of the waterproof layer groove, and the first MIM capacitor lower plate, the waterproof layer, and the first MIM upper plate metal layer constitute a first MIM capacitor. Since the preparation of the waterproof layer is an inherent procedure of existing semiconductor devices, this method cleverly realizes the formation of the first MIM capacitor in the process of forming the waterproof layer, and realizes the preparation of an additional MIM capacitor at the waterproof layer groove without adding a photomask, which efficiently utilizes the wafer area and increases the capacitance.

[0219] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a MIM capacitor device, characterized in that: include: A substrate is provided, on which a front-end semiconductor device and a first interlayer dielectric layer are formed, and a contact hole is formed in the first interlayer dielectric layer; wherein the substrate comprises a device region and an edge region, and the front-end semiconductor device is formed in the device region; An interconnection layer is formed on the first interlayer dielectric layer; the interconnection layer includes a metal interconnection layer located in the device area and a first MIM capacitor lower plate located in the edge area; the metal interconnection layer is electrically connected to the contact hole, the metal interconnection layer includes a multi-layer interconnection metal layer and an interconnection through hole electrically connected to adjacent interconnection metal layers; the first MIM capacitor lower plate includes a multi-layer lower plate metal layer and a lower plate through hole electrically connected to adjacent lower plate metal layers; A waterproof layer groove of a preset depth is formed in the edge area of ​​the interconnection layer; the lower electrode plate of the first MIM capacitor is located outside at least one side wall of the waterproof layer groove; Depositing a waterproof layer on the surface of the interconnection layer, wherein the waterproof layer covers the surface of the interconnection layer and the bottom and sidewalls of the trench of the waterproof layer; A first MIM upper plate metal layer is formed at the bottom and sidewall of the waterproof layer groove, and the first MIM capacitor lower plate, the waterproof layer, and the first MIM upper plate metal layer constitute a first MIM capacitor.

2. The method for preparing a MIM capacitor device according to claim 1, wherein: Forming an interconnection layer on the first interlayer dielectric layer, comprising: forming a first interconnect dielectric layer on the first interlayer dielectric layer, wherein a first interconnect metal layer and a first bottom plate metal layer are formed in the first interconnect dielectric layer; At least one barrier layer and at least one second interconnect dielectric layer are sequentially formed on the first interconnect dielectric layer, and a first interconnect through hole, a second interconnect metal layer, a first lower electrode plate through hole and a second lower electrode plate metal layer are formed in the second interconnect dielectric layer; the first interconnect through hole penetrates the barrier layer, the first interconnect through hole electrically connects the second interconnect metal layer with the first interconnect metal layer, and the first lower electrode plate through hole penetrates the barrier layer and electrically connects the second lower electrode plate metal layer with the first lower electrode plate metal layer.

3. The method for preparing a MIM capacitor device according to claim 2, wherein: The barrier layer and the second interconnect dielectric layer are multiple layers, the multiple barrier layers and the multiple second interconnect dielectric layers are arranged at intervals, and each of the second interconnect dielectric layers is formed with a first interconnect through hole, a second interconnect metal layer, a first lower plate through hole and a second lower plate metal layer; The first interconnection through hole is also electrically connected to a second interconnection metal layer of an adjacent second interconnection dielectric layer; The first lower plate through hole is also electrically connected to the second lower plate metal layer of the adjacent second interconnect dielectric layer.

4. The method for preparing a MIM capacitor device according to claim 1, wherein: The material of the interconnection through hole, the material of the interconnection metal layer, the material of the lower plate through hole and the material of the lower plate metal layer are the same.

5. The method for preparing a MIM capacitor device according to claim 1, wherein: Forming a waterproof layer groove of a preset depth in the edge area of ​​the interconnection layer, comprising: forming a mask layer on the interconnection layer, wherein the mask layer comprises a waterproof layer pattern, and the waterproof layer pattern is located in the edge area; The interconnection layer is etched using the mask layer as a mask to form a waterproof layer groove with a preset depth.

6. The method for preparing a MIM capacitor device according to claim 5, characterized in that: The bottom of the waterproof layer groove is lower than the bottom of the interconnection metal layer in the first interconnection dielectric layer.

7. The method for preparing a MIM capacitor device according to claim 1, wherein: The method further comprises: When forming the top interconnect metal layer in the multi-layer interconnect metal layer, forming a second MIM capacitor bottom plate metal layer; When the first MIM upper plate metal layer is formed on the bottom and sidewall of the waterproof layer groove, a second MIM upper plate metal layer is formed on the second MIM capacitor lower plate metal layer; The second MIM capacitor lower plate, the waterproof layer, and the second MIM upper plate metal layer constitute a second MIM capacitor.

8. The method for preparing a MIM capacitor device according to claim 7, characterized in that: Forming a first MIM upper plate metal layer and a second MIM upper plate metal layer, including: Depositing an upper plate metal layer on the waterproof layer; Forming a mask layer on the upper plate metal layer, the mask layer comprising a pattern opening of the first MIM capacitor upper plate metal layer and a pattern opening of the second MIM upper plate metal layer; The upper electrode plate metal layer is etched using the mask layer as a mask to form a first MIM upper electrode plate metal layer and a second MIM upper electrode plate metal layer.

9. A MIM capacitor device, characterized in that: include: A substrate, on which a front-end semiconductor device and a first interlayer dielectric layer have been formed, and a contact hole is formed in the first interlayer dielectric layer; wherein the substrate comprises a device region and an edge region, and the front-end semiconductor device is formed in the device region; An interconnection layer, located on the first interlayer dielectric layer, wherein the interconnection layer includes a metal interconnection layer located in the device area, a first MIM capacitor lower plate located in the edge area, and a waterproof layer groove located in the edge area of ​​the interconnection layer; the metal interconnection layer is electrically connected to the contact hole, and the metal interconnection layer includes a multi-layer interconnection metal layer and an interconnection through hole electrically connected to adjacent interconnection metal layers; the first MIM capacitor lower plate is located on the outer side of at least one side wall of the waterproof layer groove, including a multi-layer lower plate metal layer and a lower plate through hole electrically connected to adjacent lower plate metal layers; A waterproof layer, located on the surface of the interconnection layer, the waterproof layer covers the surface of the interconnection layer, and the bottom and sidewalls of the trench of the waterproof layer; The first MIM upper plate metal layer is formed at the bottom and sidewall of the waterproof layer groove; wherein the first MIM capacitor lower plate, the waterproof layer, and the first MIM upper plate metal layer constitute the first MIM capacitor.

10. The MIM capacitor device according to claim 9, characterized in that: The MIM capacitor device further includes a second MIM capacitor, wherein the second MIM capacitor includes: A second MIM capacitor bottom plate metal layer is formed simultaneously with a top interconnect metal layer in the multi-layer interconnect metal layer; A second MIM upper plate metal layer is formed on the waterproof layer and covers a first portion of the second MIM capacitor lower plate metal layer, and the second MIM upper plate metal layer is formed simultaneously with the first MIM capacitor upper plate metal layer; The second MIM capacitor lower plate, the waterproof layer, and the second MIM upper plate metal layer constitute the second MIM capacitor.

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