Laminated substrate for power package

Abstract

The invention relates to a laminated substrate (110) for a power package (100). The laminated substrate (110) includes an electrically insulating layer (120) and a plurality of conductive pads (131a to 131e) encapsulated in the electrically insulating layer (120). The conductive pads (131a to 131e) are arranged to form a staggered structure. The electrically conductive pad extends through the electrically insulating layer (120) from the first major surface (110a) to the second major surface (110b) of the insulating layer (120). The conductive pads (131a to 131e) are aligned along a first long axis on the second main surface (110b). The laminated substrate (110) includes a plurality of parallel conductors (132a to 132e) mounted on the second main surface (110b) of the electrically insulating layer (120). The parallel conductors (132a to 132e) are aligned along a second major axis on the second major surface (110b) of the electrically insulating layer (120). The first major axis is substantially perpendicular to the second major axis at a location on the second major surface (110b) of the electrically insulating layer (120), a respective pad (131a to 131e) electrically connecting a respective conductor (132a to 132e).

Description

Technical Field

[0001] The present invention relates to advanced laminated substrates and flip chip packaging technology for manufacturing power packages and components. In particular, the present invention relates to a laminated substrate for a power package, a power package including such a laminated substrate, and a method for manufacturing such a laminated substrate. Specifically, a laminated package for GaN with controlled isolation distance is disclosed. Background Art

[0002] In high-speed Gallium Nitride (GaN) packages, it is critical to minimize parasitic effects and maximize heat flow from the bare die to the printed circuit board (PCB) and cooling structure. Currently available high-speed / low parasitic GaN packages are face-down packages, in which the bare die is bonded to a laminate substrate or bonded to a half-etched lead frame or a simpler chip scale package (CSP) by flip chip (FC) technology. However, CSP and FC on half-etched lead frame packages are not suitable for complex multi-bare die packages, such as half-bridges with drivers. FC on laminate substrates can be used on multi-bare die packages, for example, as shown in US10,074,597B2, but the heat transfer and current carrying capacity from the bare die to the PCB are limited due to the thin copper (Cu) wiring and small size of plated microvias and plated through-holes (PTH) used to connect through the laminate substrate. Summary of the invention

[0003] The present invention provides a technical solution for a high-performance, low-parasitic package, which can be used as a single bare chip GaN package, a multi-bare chip GaN package, or other lateral current or even vertical current power device packages.

[0004] The above and other objects are achieved by the features of the independent claims. Other implementations are apparent from the dependent claims, the description and the drawings.

[0005] The embodiments described in this invention provide similar electrical and thermal performance and are also footprint compatible with existing half-etched leadframe flip chip variants, but with improved performance and reduced parasitic characteristics.

[0006] These embodiments provide an alternative and improved method to manufacture low parasitic GaN (or other lateral current power device) packages with good thermal performance due to the large cross-section of wiring and vias between the top and bottom of the package. In addition, these embodiments can properly address the multi-chip system problem in package integration, which is one of the most stringent limitations of current leadframe-based methods.

[0007] The package and manufacturing process described below may be based on the use of flip chip bonding on a build-up substrate and a simplified manufacturing process that enables the manufacture of substrates with thick copper wiring and large cross-section Cu vias through the package.

[0008] Embodiments described in the present invention may enable the production of complex (eg, intricate) multi-die packages, such as a half-bridge with a driver.

[0009] The embodiments described in the present invention are based on a laminate substrate instead of a lead frame. This has the advantage that intricate routing can be performed on the substrate. This allows several power bare chips and even driver bare chips to be integrated into one package. In a lead frame, all traces (leads) are connected to the frame, for example, "floating" wires cannot be used, unlike the disclosed embodiments that can use such "floating wires" to connect the bare chips. While in the lead frame process, all leads are visible at the edge of the package, the disclosed embodiments can use a laminate substrate, where all side walls can be isolated to improve creepage distances.

[0010] Another advantage of the disclosed technical solution is that processing can be performed on panels of larger size compared to lead frames. This allows panel-level processing, which reduces manufacturing costs because the processing time is shorter for parallel processing and the processing time of each component in sequential processing is also shorter due to shorter setup time, waiting time and startup time. The larger panel size also reduces material waste because the total processing area required to process multiple small panels is greater than the total processing area required to process one larger panel.

[0011] By using prefabricated build-up substrates, additional integration of passives and other components is very simple. Passives or other components can be easily placed in the ideal location of the package to ensure optimal electrical performance.

[0012] The present invention provides a package, substrate and structure for manufacturing a low parasitic single-die or multi-die GaN package, and a method for manufacturing a simplified build-up substrate on which the GaN power die can be mounted by flip-chip technology. The substrate can be manufactured by a build-up process using a commercially available molded interconnection substrate (MIS), a through-hole bar technology, or by a new simplified build-up substrate process, as described in detail below. If necessary, the back of the die can be exposed to improve thermal performance.

[0013] The disclosed embodiments can be used to manufacture single die and multi-die packages with or without integrated passive devices. Various structures are shown in conjunction with the examples described in the following figures, in which one or more GaN die have a structure with alternating source pads and gate pads. However, similar structures and design concepts can also be used for other types of gate-source configurations. Although the disclosed embodiments are mainly introduced for packaging GaN die, they can also be used for other types of lateral current power die, and even for vertical current die when using Cu clips to achieve back-side connection of the die.

[0014] Embodiments described in the present invention include: a single bare chip GaN package; a multi-bare chip GaN package, for example, a half-bridge with or without a driver and / or passive devices; a multi-bare chip GaN package, for example, parallel bare chips with or without a driver and / or passive devices; and two simplified process flows for manufacturing a laminate substrate.

[0015] As mentioned above, the embodiments of the present invention are not limited to GaN bare chips or GaN designs. It is understood that a conventional build-up substrate may also be used instead of the simplified build-up substrate described in the embodiments described below.

[0016] To describe the present invention in detail, the following terms, abbreviations and symbols will be used:

[0017] PCB Printed Circuit Board

[0018] GaN Gallium Nitride

[0019] FC Flip Chip

[0020] MIS Molded Interconnect Substrate

[0021] The present invention describes chip embedding technology. There are several different types of embedding processes: In a typical chip embedding process, electronic components (chips, capacitors, resistors, etc.) are either placed in openings in the center layer of a PCB or soldered on two or more layers of a PCB board. When the actual embedding is performed inside the final PCB board, FR4 prepreg or other polymer sheets can be laminated above and below the center layer that accommodates the components to be embedded. The electrical connection between the embedded component and the PCB metal layer can be formed by soldering the component terminals to the internal laminate layer and then uniformly laminating the PCB layers. In more advanced embedding techniques, the components can be electrically connected through current-filled micro-vias, which is a more stable connection because there is no solder remelting inside the package or circuit board, which must be taken into account when mounting other components to the outer layers of the PCB. The micro-vias are usually formed by laser drilling after lamination, specifically, the laser drilling is from the top surface through the thin laminate layer to the active chip pads or terminals of the embedded component package.

[0022] According to a first aspect, the present invention relates to a laminate substrate for a power package. The laminate substrate comprises: an electrical insulation layer having a first main surface and an opposite second main surface; a plurality of conductive pads encapsulated in the electrical insulation layer, wherein the plurality of conductive pads are arranged to form a staggered structure, the conductive pads extend from the first main surface to the second main surface through the electrical insulation layer, and the conductive pads are aligned along a first long axis on the second main surface of the electrical insulation layer; a plurality of parallel conductors mounted on the second main surface of the electrical insulation layer, wherein the parallel conductors are aligned along a second long axis on the second main surface of the electrical insulation layer, the first long axis is substantially perpendicular to the second long axis at a position on the second main surface of the electrical insulation layer, and corresponding pads are electrically connected to corresponding conductors.

[0023] "Substantially perpendicular" here means that the first major axis and the second major axis are at a 90° angle relative to each other, including slight positive or negative deviations from 90°, for example, deviations of less than 0.1°, 0.25°, 0.5°, 1°, 2°, 3°, 4° or 5°.

[0024] The advantage of this type of build-up substrate is that the build-up structure is simple, for example, the build-up substrate may have 1.5 layers, one of which is embedded with a pre-plated through-hole bar, for example, a conductive pad, which simplifies the structure and reduces the manufacturing cost.

[0025] Package designs with build-up substrates can be easily extended to multi-die packages and different voltage levels to improve clearance and creepage distances.

[0026] Embedded large via bars through the package substrate also define the component footprint or pads (depending on which side the routing is on). As a result, both electrical and thermal performance are improved compared to conventional laminate structures.

[0027] The build-up substrate does not use a lead frame, but the lead frame can be considered as a lead frame type package with isolated sidewalls. The advantage of this is that there is no Cu lead exposed on the package sidewall, thereby reducing the creepage distance.

[0028] In an exemplary implementation of the build-up substrate, the conductive pads are arranged in an interdigitated pattern.

[0029] This has the advantage that the available area of ​​the build-up substrate can be optimally utilized and the creepage distance can be specified efficiently.

[0030] In an exemplary implementation of the laminate substrate, a corresponding pad among the plurality of conductive pads is defined by a length and a width of the corresponding pad; the length of the corresponding pad is greater than the width of the corresponding pad; and the first major axis extends along the length direction of the corresponding pad.

[0031] This has the advantage that the source and drain pads and even the gate pads of the transistors can be arranged in a row, which helps to optimize the package footprint.

[0032] The thickness of the conductive pads may typically be between 80 μm and 150 μm, and in the range of about 40 μm to 250 μm. These conductive pads may be made of pre-plated embedded Cu strips or the like.

[0033] In one exemplary implementation of the build-up substrate, the plurality of conductive pads form through-holes that pass through the electrically insulating layer of the build-up substrate.

[0034] The benefit of this is that a simple laminate structure can be obtained at a reduced manufacturing cost. These through holes that pass through the package substrate can also define the package footprint. Compared with ordinary laminate structures, the through hole design improves electrical and thermal performance.

[0035] In an exemplary implementation of the build-up substrate, the plurality of conductive pads are formed according to a predetermined electrode pattern of at least one electronic chip included in the power package.

[0036] The advantage of this is that the conductive pads of the laminate substrate are aligned with the electrode patterns of the chip, thus achieving the mapping of the electrode pattern to the package footprint design.

[0037] In an exemplary implementation of the build-up substrate, the plurality of conductive pads and the plurality of parallel conductors are covered by the electrical insulation layer at an edge of the build-up substrate to provide lateral electrical insulation of the build-up substrate.

[0038] The advantage of this is that there are no exposed leads on the build-up substrate, allowing for optimal creepage design with controlled isolation distances, which is not possible with leadframe-based packages.

[0039] In an exemplary implementation of the laminate substrate, at least one of the multiple conductive pads is electrically isolated from at least one other of the multiple conductive pads by the electrical insulation layer; and / or at least one of the multiple conductors is electrically isolated from at least one other of the multiple conductors by the electrical insulation layer.

[0040] The advantage of this is that the design options are flexible.

[0041] The build-up substrate can be used to manufacture single die and multi-die packages with or without integrated passive devices. For example, the build-up substrate can be used for one or more GaN die with a structure where the source pads and gate pads are arranged alternately. Similar structures and the same design concept can also be used for other types of gate-source configurations.

[0042] Although the embodiments disclosed herein are primarily developed for packaging GaN die, they can also be used for other types of lateral current power die, and even for vertical current die when Cu clips are used for die backside connection, etc.

[0043] In an exemplary implementation of the build-up substrate, the electrically insulating layer comprises at least one or a combination of a laminate material or a molding material; and / or the plurality of conductive pads and the plurality of conductors comprise electroplated Cu structures.

[0044] The advantage of this is that the electrical and thermal performance are improved.

[0045] The thickness of the conductive pads may typically be between 80 μm and 150 μm, and in the range of about 40 μm to 250 μm. These conductive pads may be made of pre-plated embedded Cu strips or the like.

[0046] The thickness of the conductors may typically be between 20 μm and 35 μm, and in the range of about 10 μm to 150 μm. These conductors may be made of a Cu seed layer and electroplated Cu, etc.

[0047] According to a second aspect, the present invention relates to a power package. The power package comprises: a laminate substrate according to the first aspect; at least one electronic chip comprising a first main surface and a second main surface opposite to the first main surface, wherein the at least one electronic chip comprises at least one first terminal electrically connected to at least one of the plurality of conductive pads and at least one second terminal electrically connected to at least one other of the plurality of conductive pads; a sealant encapsulating at least a portion of the at least one electronic chip; or a bottom fill attaching the at least one electronic chip to the laminate substrate.

[0048] The advantage of this is that this package design with a build-up substrate can be easily extended to multi-die packages and different voltage levels to improve clearance and creepage distances.

[0049] Embedded large via bars through the package substrate also define the package footprint. As a result, both electrical and thermal performance are improved compared to conventional laminate structures.

[0050] The build-up substrate does not use a lead frame, but the lead frame can be considered as a lead frame type package with isolated sidewalls. The advantage of this is that there is no Cu lead exposed on the package sidewall, thereby reducing the creepage distance.

[0051] In an exemplary implementation of the power package, the second main surface of the at least one electronic chip faces the first main surface of the electrical insulation layer; the at least one first terminal and the at least one second terminal are arranged on the second main surface of the at least one electronic chip and are mounted on corresponding pads of the multiple conductive pads.

[0052] The advantage of this is that the design is flexible. The power package can be designed according to a first design option, wherein the chip is placed on the first main surface of the build-up substrate, that is, on the first main surface of the electrical insulation layer.

[0053] In an exemplary implementation of the power package, the second main surface of the at least one electronic chip faces the second main surface of the electrically insulating layer; the at least one first terminal and the at least one second terminal are arranged on the second main surface of the at least one electronic chip and are mounted on corresponding conductors among the multiple conductors.

[0054] The advantage of this is that the design is flexible. The power package can be designed according to a second design option, also known as flip chip mounting, in which the chip is placed on the second main surface of the build-up substrate, ie on the second main surface of the electrically insulating layer.

[0055] In an exemplary implementation of the power package, the at least one electronic chip includes a plurality of side surfaces arranged between the first main surface and the second main surface of the at least one electronic chip; and the sealant covers the first main surface and the side surfaces of the at least one electronic chip; or the first main surface of the at least one electronic chip is not covered by the sealant, and the sealant at least partially covers the side surfaces of the at least one electronic chip; or the first main surface of the at least one electronic chip is not covered by the bottom fill, and the bottom fill partially covers the side surfaces of the at least one electronic chip.

[0056] The advantage of this is that the design is flexible. The design can be based on an overmolding process, an overmolding process with the back side of the die exposed, or an underfill process.

[0057] In one exemplary implementation of the power package, the power package forms a single die GaN package or a multi-die GaN package in a half-bridge or parallel die configuration with or without drivers and / or passive devices.

[0058] The advantage of this is that the design is flexible and different types of single bare chip or multi-bare chip packages can be formed.

[0059] In an exemplary implementation of the power package, the power package includes: at least one first solder layer disposed between the at least one first terminal and the at least one pad among the plurality of conductive pads, wherein the at least one first solder layer electrically connects the at least one first terminal to the at least one pad among the plurality of conductive pads; and / or at least one second solder layer disposed between the at least one second terminal and the at least one other pad among the plurality of conductive pads, wherein the at least one second solder layer electrically connects the at least one second terminal to the at least one other pad among the plurality of conductive pads.

[0060] This has the advantage that the solder layer can be efficiently used to attach and electrically connect the chip to the build-up substrate.

[0061] In one exemplary implementation of the power package, the power package forms a leadframe-less package.

[0062] The advantage of this is that the leadframe-less package has improved creepage performance.

[0063] According to a third aspect, the present invention relates to a method for manufacturing a laminated substrate for a power package according to the first aspect. The method comprises: providing a carrier with a metal layer attached, wherein the metal layer has a first main surface and an opposite second main surface facing the carrier; processing a first photoresist layer on the first main surface of the metal layer and forming an opening in the first photoresist layer; performing metal electroplating on the opening in the first photoresist layer; removing the first photoresist layer to form the plurality of conductive pads; applying a laminate or a molding material on the first main surface of the metal layer and the plurality of conductive pads electroplated with the metal; removing the laminate or the molding material from the first main surface portion of the metal layer until the plurality of conductive pads electroplated with the metal are exposed, and removing the carrier from the second main surface of the metal layer; processing a second photoresist layer on the second main surface of the metal layer and forming an opening in the second photoresist layer; removing the metal layer from the opening of the second photoresist layer, and removing the second photoresist layer from the second main surface of the metal layer to form the plurality of conductors.

[0064] This method can be used to manufacture a build-up substrate at reduced manufacturing cost.

[0065] In a first process step, the metal foil can be attached to the carrier. Alternatively, this can also be done by the foil manufacturer and a carrier covered with the metal foil can be used in the first process step.

[0066] According to a fourth aspect, the present invention relates to a method for manufacturing a laminated substrate for a power package according to the first aspect. The method comprises: providing a carrier with a first metal layer attached thereto, wherein the first metal layer has a first main surface and an opposite second main surface facing the carrier; processing a first photoresist layer on the first main surface of the first metal layer and forming an opening in the first photoresist layer; performing metal electroplating on the opening in the first photoresist layer; removing the first photoresist layer from the first metal layer to form the plurality of conductive pads; applying a laminate material or a molding material on the first main surface of the first metal layer and the plurality of metal-plated conductive pads, and removing the laminate material or the molding material from a portion of the first main surface of the first metal layer until the plurality of metal-plated conductive pads are exposed; A second metal layer is applied on the exposed multiple metal-plated conductive pads and the partially removed laminate or molding material, wherein the second metal layer has a first main surface and an opposite second main surface, and the second main surface faces the exposed multiple metal-plated conductive pads and the partially removed laminate or molding material; a second photoresist layer is processed on the first main surface of the second metal layer, and an opening is formed in the second photoresist layer; the opening in the second photoresist layer is metal-plated; the second photoresist layer is removed from the first main surface of the second metal layer to form the multiple conductors; the second metal layer is removed from the laminate or molding material; and the carrier and the first metal layer are removed.

[0067] This method can be used to manufacture a build-up substrate at reduced manufacturing cost.

[0068] The embodiments described in the present invention introduce a new GaN package that is different from existing packages. As described in the present invention, an advanced build-up substrate is used instead of a half-etched lead frame of a conventional laminate substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] Other embodiments of the present invention will be described in conjunction with the following drawings, in which:

[0070] Figure 1a 1 shows a schematic cross section of a build-up substrate 110 for a power package 100 provided by the present invention;

[0071] Figure 1b Shows Figure 1a An exemplary package pad layout of the power package 100 is shown;

[0072] Figure 1c Shows Figure 1a An exemplary package footprint of the power package 100 is shown;

[0073] Figure 2a FIG. 4 shows a schematic cross section of an overmolded power package 100 with a build-up substrate 110 provided in a first embodiment;

[0074] Figure 2b 1 shows a schematic cross section of an overmolded and exposed power package 100 b with a build-up substrate 110 provided in a second embodiment;

[0075] Figure 2c FIG. 4 shows a schematic cross section of an underfill power package 100 c with a build-up substrate 110 provided in a third embodiment;

[0076] Figure 2d FIG. 4 shows a schematic cross section of an overmolded power package 100 d with a build-up substrate 110 provided in a fourth embodiment;

[0077] Figure 2e 1 shows a schematic cross section of an overmolded and exposed power package 100 e with a build-up substrate 110 provided in a fifth embodiment;

[0078] Figure 2f FIG. 4 shows a schematic cross section of an underfill power package 100 f with a build-up substrate 110 provided in a sixth embodiment;

[0079] Figure 3a to Figure 3f A schematic diagram showing an exemplary assembly process for manufacturing a power package using a build-up substrate provided by the present invention;

[0080] Figures 4a to 4c Schematic diagrams showing an exemplary bare chip pad layout 400a, an exemplary package pad layout 400b, and an exemplary package footprint 400c of a power package with a build-up substrate provided by the present invention;

[0081] Figure 4d to Figure 4f Schematic diagrams showing an alternative example of a bare die pad layout 400d, an alternative example of a package pad layout 400e, and an alternative example of a package footprint 400f of a power package with a build-up substrate;

[0082] Figure 4g and Figure 4h Schematic diagrams showing exemplary footprints 400c, 400h of a power package with a build-up substrate;

[0083] Figure 5 A top view of a multi-die GaN package 500 in a half-bridge configuration on a build-up substrate is shown according to one embodiment;

[0084] Figure 6a and Figure 6b Shows Figure 5A top view of a multi-die GaN package 500 in FIG. 5 , showing in detail the source and drain connections ( Figure 6a ) and the PGRD, VSWH, and VIN connections ( Figure 6b );

[0085] Figure 7 FIG. 1 shows a top view of a multi-die GaN package 700 integrating drivers and passive devices on a build-up substrate provided by one embodiment;

[0086] Figure 8 A top view of a multi-die GaN package 800 in a parallel die configuration on a build-up substrate is shown according to one embodiment;

[0087] Figure 9a and Figure 9b Shows Figure 8 A top view of a multi-die GaN package 800 in FIG. 8 , showing in detail the drain connection ( Figure 9a ) and source connection ( Figure 9b );

[0088] Figure 10a to Figure 10h A schematic diagram showing an exemplary process flow for manufacturing a build-up substrate provided by the first embodiment;

[0089] Figures 11a to 11k A schematic diagram of an exemplary process flow for manufacturing a build-up substrate provided by the second embodiment is shown. DETAILED DESCRIPTION

[0090] In the following detailed description, reference is made to the accompanying drawings which form a part of the present invention, wherein specific aspects of the present invention which may be practiced are illustrated by way of illustration. It should be understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following specific embodiments should not be understood in a restrictive sense, and the scope of the present invention is limited by the appended claims.

[0091] It should be understood that explanations related to a described method may also apply to a corresponding device or system for performing the method, and vice versa. For example, if a specific method step is described, the corresponding device may include a unit for performing the described method step, even if such a unit is not elaborated or illustrated in detail in the figure. In addition, it should be understood that the features of the various exemplary aspects described herein may be combined with each other unless otherwise explicitly stated.

[0092] Figure 1a FIG. 1 shows a schematic cross section of a build-up substrate 110 for a power package 100 provided by the present invention. Figure 1b An exemplary package pad layout of the power package 100 is shown. Figure 1c An exemplary package footprint of power package 100 is shown.

[0093] The build-up substrate 110 used in the power package 100 is as follows: Figure 1a The build-up substrate 110 includes an electrical insulating layer 120, a plurality of conductive pads 131a to 131e encapsulated in the electrical insulating layer 120, and a plurality of parallel conductors 132a to 132e.

[0094] like Figure 1a As shown, the electrically insulating layer 120 has a first major surface 110 a and an opposing second major surface 110 b .

[0095] The plurality of conductive pads 131a to 131e are arranged to form a staggered structure. The conductive pads 131a to 131e extend from the first main surface 110a to the second main surface 110b through the electrical insulating layer 120. Figure 1b As can be seen from the package pad layout shown, the conductive pads 131a to 131e are aligned along the first long axis on the second main surface 110b of the electrical insulation layer 120. Figure 1b In the example, the first major axis is shown as the vertical axis.

[0096] A plurality of parallel conductors 132a to 132e are mounted on the second major surface 110b of the electrical insulating layer 120. Figure 1c As can be seen from the package footprint shown, the parallel conductors 132a to 132e are aligned along the second major axis on the second major surface 110b of the electrically insulating layer 120. Figure 1c In the example of FIG. 1 , the second major axis is shown as the horizontal axis.

[0097] The first long axis is substantially perpendicular to the second long axis at a location on the second major surface 110b of the electrically insulating layer 120, and the respective pads 131a to 131e are electrically connected to the respective conductors 132a to 132e.

[0098] from Figure 1b It can be seen that the conductive pads 131a to 131e may be arranged in an interdigitated pattern.

[0099] A corresponding pad among the plurality of conductive pads 131a to 131e may be defined by a length and a width of the corresponding pad. Figure 1b It can be seen that the length of the corresponding pad can be greater than the width of the corresponding pad.

[0100] from Figure 1b It can be seen that the first major axis can extend along the length direction of the corresponding pad.

[0101] The thickness of the conductive pads 131a to 131e may be generally between 80 μm and 150 μm, and in the range of about 40 μm to 250 μm. These conductive pads 131a to 131e may be made of pre-plated embedded Cu strips or the like. Figure 4g and Figure 4h Describes more details.

[0102] from Figure 1a It can be seen that the plurality of conductive pads 131 a to 131 e may form through-holes that pass through the electrical insulation layer 120 of the build-up substrate 110 .

[0103] The plurality of conductive pads 131a to 131e may be formed according to a predetermined electrode pattern of at least one electronic chip 140 included in the power package 100, for example, as follows: Figure 2a to Figure 2f shown.

[0104] The plurality of conductive pads 131a to 131e and the plurality of parallel conductors 132a to 132e may be covered by an electrical insulation layer 120 at the edge of the build-up substrate 110 to provide lateral electrical insulation of the build-up substrate, for example, as Figure 1b and Figure 1c Therefore, the embodiment according to the present invention provides more freedom: the leads at the edge of the package can be exposed or electrically insulated. On the other hand, in the traditional lead frame method, the leads are always exposed.

[0105] At least one of the plurality of conductive pads 131 a to 131 e may be electrically isolated from at least one other of the plurality of conductive pads 131 a to 131 e by the electrical insulation layer 120 .

[0106] Additionally or alternatively, at least one conductor of the plurality of conductors 132a to 132e may be electrically isolated from at least one other conductor of the plurality of conductors 132a to 132e by the electrically insulating layer 120. An additional solder mask may be formed on the second major surface 110b, for example, as Figure 10g and Fig.10h This additional solder mask should only have openings in the footprint area.

[0107] The build-up substrate can be used to manufacture single die and multi-die packages with or without integrated passive devices. For example, the build-up substrate can be used for one or more GaN die with a structure where the source pads and gate pads are arranged alternately. Similar structures and the same design concept can also be used for other types of gate-source configurations.

[0108] Although the embodiments disclosed herein are primarily developed for packaging GaN die, they can also be used for other types of lateral current power die, and even for vertical current die when Cu clips are used for die backside connection, etc.

[0109] The electrically insulating layer 120 may include at least one or a combination of a laminate material or a molded material.

[0110] Additionally or alternatively, the plurality of conductive pads 131a to 131e and the plurality of conductors 132a to 132e may include a plated Cu structure.

[0111] The thickness of the conductive pads 131a to 131e may be typically between 80 μm and 150 μm, and in the range of about 40 μm to 250 μm. These conductive pads 131a to 131e may be made of pre-plated embedded Cu strips, etc. More details are described below.

[0112] The thickness of the conductors 132a to 132e may be generally between 20 μm and 35 μm, and in the range of about 10 μm to 150 μm. These conductors 132a to 132e may be made of a Cu seed layer and electroplated Cu, etc. More details are described below.

[0113] Figure 1a to Figure 1c Also shown is the power package 100 with a build-up substrate 110 .

[0114] The power package 100 includes a build-up substrate 110 as described above, at least one electronic chip 140, and an encapsulant 150 encapsulating at least a portion of the at least one electronic chip 140 or an underfill 151 attaching the at least one electronic chip 140 to the build-up substrate 110, for example, as described below in conjunction with Figure 2a to Figure 2f shown.

[0115] The at least one electronic chip 140 comprises a first main surface 140 a and a second main surface 140 b opposite the first main surface 140 a .

[0116] At least one electronic chip 140 includes at least one first terminal 141 electrically connected to at least one pad 131a of the plurality of conductive pads 131a to 131e and at least one second terminal 142 electrically connected to at least one other pad 131c of the plurality of conductive pads 131a to 131e, for example, as described below in conjunction with Figure 2a to Figure 2f shown.

[0117] The second main surface 140 b of the at least one electronic chip 140 may face the first main surface 110 a of the electrically insulating layer 120 .

[0118] At least one first terminal 141 and at least one second terminal 142 may be disposed on the second main surface 140 b of the at least one electronic chip 140 , and may be mounted on corresponding pads of the plurality of conductive pads 131 a to 131 e .

[0119] The second main surface 140 b of the at least one electronic chip 140 may face the second main surface 110 b of the electrically insulating layer 120 .

[0120] At least one first terminal 141 and at least one second terminal 142 may be disposed on the second main surface 140 b of the at least one electronic chip 140 , and may be mounted on respective conductors of the plurality of conductors 132 a to 132 e .

[0121] The at least one electronic chip 140 may include a plurality of side surfaces arranged between the first main surface 140 a and the second main surface 140 b of the at least one electronic chip 140 .

[0122] The encapsulant 150 may cover the first main surface 140 a and side surfaces of the at least one electronic chip 140 .

[0123] Alternatively, the first main surface 140 a of the at least one electronic chip 140 may not be covered by the encapsulant 150 , and the encapsulant 150 may at least partially cover the side surfaces of the at least one electronic chip 140 .

[0124] Alternatively, the first main surface 140 a of the at least one electronic chip 140 may not be covered by the underfill 151 , and the underfill 151 may partially cover the side surfaces of the at least one electronic chip 140 .

[0125] The power package 100 may form a single die GaN package or a multi-die GaN package in a half-bridge or parallel die configuration, etc., with or without drivers and / or passive devices.

[0126] The power package 100 may include at least one first solder layer 133a disposed between at least one first terminal 141 and at least one pad 131a of the plurality of conductive pads 131a to 131e, for example, as shown in FIG. Figure 2a to Figure 2c As shown. At least one first solder layer 133a can electrically connect at least one first terminal 141 to at least one pad 131a among the plurality of conductive pads 131a to 131e. Figure 2d to Figure 2f In the embodiment, the first solder layer 133a is not directly disposed between the first terminal 141 and the conductive pad 131a, but is indirectly disposed therebetween through the conductor 132a.

[0127] The power package 100 may include at least one second solder layer 133c disposed between the at least one second terminal 142 and at least one other pad 131c of the plurality of conductive pads 131a to 131e, for example, as shown in FIG. Figure 2a to Figure 2f At least one second solder layer 133c may electrically connect at least one second terminal 142 to at least one other pad 131c of the plurality of conductive pads 131a to 131e.

[0128] The power package 100 may form a leadframe-less package.

[0129] Figure 1a Different layers are described. Layer 101 represents a Cu metallization layer or a bump of Cu, nickel Ni, etc. The thickness of layer 101 can be between about 8 μm and 12 μm, or even between 3 μm and 80 μm, etc. Layer 101 can be made of a power metal on a bare chip or a non-solderable bump on top of aluminum copper (AlCu), etc.

[0130] Layer 102 represents a solder layer, etc. The thickness of layer 102 may be between about 20 μm and 80 μm, or even between 10 μm and 150 μm, etc. Layer 102 may be made of solder bumps, solder bumps and printed solder, or printed solder, etc.

[0131] Layer 103 represents the conductive pads 131a to 131e mentioned in the present invention, and layer 104 represents the parallel conductors 132a to 132e mentioned in the present invention. However, layer 103 can also be called a via bar, for example, a Cu via bar (for flip chip pads), and layer 104 can also be called a pad (for package base surface).

[0132] The thickness of the layer 103 may be between about 80 μm and 150 μm, or even between 40 μm and 250 μm, etc. The layer 103 may be made of pre-plated embedded Cu strips or the like.

[0133] The thickness of the layer 104 may be between about 20 μm and 35 μm, or even between 10 μm and 150 μm, etc. The layer 104 may be made of a Cu seed layer and electroplated Cu, or the like.

[0134] Figure 2a to Figure 2c as well as Figure 2d to Figure 2f Three different types of molding or underfill options are shown. Bare die can be protected by Figure 2a and Figure 2d Overmolding can be done as shown, for example, panel level overmolding or smaller size strip overmolding, and if better top cooling is required, the back side of the die can be exposed by grinding, etc. Figure 2b and Figure 2eOvermolding can also be avoided if a conventional underfill process is used, such as Figure 2c and Figure 2f shown.

[0135] Figure 2a The illustrated overmolded power package 100 with the build-up substrate 110 corresponds to the power package 100 described above in conjunction with FIG. 1 .

[0136] exist Figure 2a to Figure 2c In the embodiment, at least one electronic chip 140 is mounted on the build-up substrate 110 such that the second main surface 140b of the chip 140 faces the first main surface 110a of the build-up substrate 110. In these embodiments, the parallel conductors 132a to 132e are exposed at the bottom of the packages 100, 100b, 100c.

[0137] exist Figure 2d to Figure 2f In the embodiment, the opposite mounting technique is adopted, for example, flip chip mounting. That is, at least one electronic chip 140 is mounted on the build-up substrate 110 so that the second main surface 140b of the chip 140 faces the second main surface 110b of the build-up substrate 110. In these embodiments, the parallel conductors 132a to 132e are embedded in the sealant 150, and the conductive pads 131a to 131e are disposed and exposed at the bottom of the packages 100d, 100e, 100f.

[0138] Figure 3a to Figure 3f A schematic diagram showing an exemplary assembly process for manufacturing a power package using a build-up substrate provided by the present invention is shown.

[0139] The assembly process can be used to manufacture a single bare chip GaN package, for example, as described above in conjunction with Figure 2d and Figure 2e The power package 100 d or 100 f uses flip chip bonding and a build-up substrate 110 .

[0140] Figure 3a to Figure 3f The process option described in is to use a build-up substrate 110 (see Figure 3a ), wherein the base surface and the through holes 131a to 131e passing through the substrate 110 are large-area Cu strips, which can be produced by an electroplating process and then embedded in a molding material or a laminate material.

[0141] The solder pads of the GaN bare chip 140 are located on the top of the package. Solder 133a to 133e are printed or coated on the substrate 110 (see Figure 3b ), the bare chip 140 is picked up and placed on top of the solder 13a to 13e (see Figure 3c ), and then complete the connection by conventional reflow soldering (see Figure 3dAfter welding, the Figure 3e ) or bottom padding (see Figure 3f ) to protect the bare chip 140. The bare chip 140 has solder bumps or solderable bumps 104.

[0142] Figures 4a to 4c Schematic diagrams showing an exemplary bare chip pad layout 400a, an exemplary package pad layout 400b, and an exemplary package footprint 400c of a power package with a build-up substrate provided by the present invention. Figure 4d to Figure 4f Schematic diagrams showing an alternative example of a bare die pad layout 400d, an alternative example of a package pad layout 400e, and an alternative example of a package footprint 400f of a power package with a build-up substrate.

[0143] Figures 4a to 4f An example of a bare die, solder bumps, and the top and bottom of the package is shown. In this variation, the bare die has a structure with alternating source and drain lines. Typically, the distance and width of the source and drain lines on the bare die are too small to achieve the correct gap distance or large enough pad size and space for soldering / final assembly on the PCB. To convert the small L / S on the bare die to a suitable L / S on the bottom of the package, two or more layers are required.

[0144] Figures 4a to 4c A 2-layer design 400a to 400c (substrate top and bottom) is shown where the drain and source lines of the bare die are rotated 90 degrees through the package routing, allowing for increased clearance to meet voltage level requirements. If a 2-layer or 1.5-layer substrate is used (counting only routing layers), the source and drain lines on the substrate do not need to be rotated 90 degrees to increase line space and clearance.

[0145] like Figure 4d to Figure 4f As shown, depending on the substrate manufacturing process, alternative pad layouts 400e and footprint designs 400f may also be used, which are not achievable when using a lead frame.

[0146] It should be noted that Figures 4a to 4f For illustration only, the die design and package footprint design can be modified, for example, the size, shape, location and number of source and drain lines on the die and package can be modified. These figures also show a structure in which one or more GaN die have a structure with alternating source pads and gate pads, but similar packaging structures and the same design concepts can also be used for other types of gate-source configurations.

[0147] Although the embodiments disclosed herein are primarily developed for packaging GaN die, they can also be used for other types of lateral current power die, and even for vertical current die when Cu clips are used for die backside connection, etc.

[0148] Figure 4g and Figure 4h Schematic diagrams of exemplary footprints 400c, 400h of power packages with build-up substrates are shown.

[0149] The drain pad, source pad and gate pad on the package base surface can be as follows Figure 4g As shown, you can also set it up in rows as Figure 4f The setup shown is for individual pads.

[0150] exist Figure 4g At least 2 lines can be implemented. Figure 4g n rows are shown. The maximum number of rows may depend on the package size and voltage level. For example, for a package size of 5×6 mm and a voltage of 50 to 150 V, the maximum number of rows is 5.

[0151] Figure 4g An exemplary 5 rows and an exemplary 5 columns are shown. Figure 4g In the example, the minimum number of rows that can be achieved is 2. The maximum number of rows may depend on the package size and voltage level. For example, the maximum number of rows is 5 for a package size of 5×6mm and a voltage of 50 to 150V. Figure 4f In the example, a minimum of 2 columns can be realized. The maximum number of columns may depend on the package size. For example, if the package size is 5×6 mm, the maximum number of columns is 5.

[0152] exist Figure 4g In, W 1a Indicates the source line width or drain line width when the source or drain is in the same line as the gate. 1a May depend on package width and maximum package width. Figure 4g In, W 1b Indicates the source line width or drain line width when the source or drain is arranged in a row without a gate. W 1b May depend on package width and maximum package width. Typical values ​​may be 200μm to 400μm, etc., which is less than the package width. W 1b An exemplary range of may be 0 μm to 600 μm, which is less than the package width.

[0153] exist Figure 4g In FIG. 1 , W2 represents the width of 1 or 2 gate pads. The pad position can be located in a corner or in the middle according to the bare chip design. A typical value of W2 can be 400 μm to 600 μm, etc. An exemplary range of W2 can be 300 μm to 1200 μm, etc.

[0154] exist Figure 4h In FIG. 1 , W3 represents the width of the pad in the matrix, and the pad can be square, rectangular or circular. A typical value of W3 can be 400 μm to 600 μm, etc. An exemplary range of W3 can be 300 μm to 1200 μm, etc.

[0155] exist Figure 4g and Figure 4h In FIG. 1 , H represents the pad height. A typical value of H may be 400 μm to 600 μm, etc. An exemplary range of H may be 300 μm to 1200 μm.

[0156] exist Figure 4g In the figure, C represents the gap, which may depend on the voltage level. A typical value of C may be 0.6mm, etc.

[0157] Figure 5 A top view of an exemplary multi-die GaN package 500 in a half-bridge configuration on a build-up substrate is shown in accordance with one embodiment. The figure shows the die metallization, solder bumps (circles) on the die, and the package top metallization. Figure 5 In the example, the HS and LS die have the same size, this is just an example. The location and connections can be different, and the die size and shape can also be different.

[0158] In addition to the GaN die, the multi-die GaN package 500 may also include drivers and / or passive components.The manufacturing process and embodiments for the multi-die option are the same as those for the single die. Figure 5 The bare die metallization, solder bumps, and package top metallization are shown.

[0159] In the half-bridge package 500, the right bare chip 501 is rotated 180 degrees relative to the left bare chip 502, and the half-bridge connection is completed through package wiring. Figure 5 It can be seen how the source line 502a of the left die 502 is connected to the drain line 501b of the right die 501 through the solder bump 503. Both die 501, 502 use the same solder bump 503 design.

[0160] Figure 6a and Figure 6b Shows Figure 5 A top view of a multi-die GaN package 500 in FIG. 5 , showing in detail the source and drain connections ( Figure 6a ) and the PGRD, VSWH, and VIN connections ( Figure 6b ).

[0161] exist Figure 6a In the diagram, the electrical connector for the source line is on the left and the electrical connector for the drain line is on the right. Figure 6bThe three connections of PGRD, VSWH and VIN are shown in detail.

[0162] Figure 7 A top view of a multi-die GaN package 700 with integrated drivers and passives on a build-up substrate is shown, according to one embodiment. The figure shows the package top metallization 704, solder bumps 503 (circles) on the die, and the package bottom surface metallization 703.

[0163] Apart from Figure 5 , Figure 6a and Figure 6b In addition to the half-bridge configuration package 500 shown, Figure 7 In the embodiment, the driver 701 can also be integrated into the package 700. The base surface of the package 700 is marked by 702.

[0164] Figure 8 A top view of a multi-die GaN package 800 in a parallel die configuration on a build-up substrate is shown according to one embodiment.

[0165] Figure 8 It is shown that embodiments of the present invention can be used to manufacture packages with bare die connected in parallel. Connecting power bare die in parallel can reduce RDSon and reduce conduction losses. If the chip size is limited (e.g., SiC), paralleling can also achieve higher currents. The manufacturing process and embodiments of the multi-bare die option are the same as those for single bare die.

[0166] Figure 8 The connection between two bare chips 801, 802 is shown. As in the half-bridge package, in the parallel bare chip package, the right bare chip 801 is rotated 180 degrees relative to the left bare chip 802, and the connection between the bare chips is completed through the package wiring.

[0167] Figure 8 It shows how the source, drain and gate of two bare chips 801 and 802 are connected to each other through short wires 803a, 803b and 803c. Through proper footprint design, the connection of the gate, source and drain to the PCB can be balanced.

[0168] Figure 9a and Figure 9b Shows Figure 8 A top view of a multi-die GaN package 800 in FIG. 8 , showing in detail the drain connection ( Figure 9a ) and source connection ( Figure 9b ).

[0169] Figure 10a to Figure 10h FIG. 1 is a schematic diagram showing an exemplary process flow for manufacturing a build-up substrate 110 provided in the first embodiment.

[0170] These figures describe the fabrication and PCB structure to manufacture a build-up substrate 110 for GaN using a simplified and cost-optimized manufacturing process.

[0171] The process flow represents a simple process that can use existing processes, but all unnecessary process steps are skipped to reduce processing time and processing costs compared to the conventional process flow.

[0172] The process uses a carrier 1001 with a Cu seed layer 1010 (exemplary thickness of about 1 μm to 150 μm) attached to Fig.10a The temporary carrier 1011 is shown.

[0173] The first step after making the carrier (temporary carrier 1011 + Cu foil 1010) is Fig.10b The photolithography process 1002 is shown. Through the photolithography process, large-area openings 1013 are made in the photoresist 1012. These large-area openings 1013 form through-holes that pass through the package and the base surface of the substrate.

[0174] In progress Fig.10c After the Cu pattern shown in 1003 is electroplated, Fig.10d As shown, the 1004 resist is removed, and as Fig.10e As shown, PCB material 1014 is laminated 1005 or a molding material is molded over the electroplated Cu 131a to 131e.

[0175] from Fig.10f It can be seen that the electroplated Cu structure is exposed from the top by the grinding or milling process.

[0176] After the large-area electroplated Cu strips 131a to 131e are exposed, Fig.10f As shown, temporary carrier 1011 is removed 1006, and in Figure 10g After the photolithography step 1007 shown, the Cu carrier 1010 is etched 1008 to form Fig.10h Top or bottom of package shown. The final step is optional solder mask and surface finish (solderable surface, e.g., ENIG, etc.)

[0177] pass Figure 10a to Figure 10h The process shown in FIG. 1 and FIG. Figure 2a to Figure 2f The laminate substrate 110.

[0178] Figure 10a to Figure 10h The process flow shown may be described by a method 1000 of manufacturing a build-up substrate 110 for a power package 100, for example, as described above in conjunction with FIG. 1 and FIG. Figure 2a to Figure 2f The method 1000 comprises the following steps:

[0179] Providing 1001 a carrier 1011 having a metal layer 1010 attached thereto, wherein the metal layer 1010 has a first main surface 1010a and an opposite second main surface 1010b facing the carrier;

[0180] processing 1002 a first photoresist layer 1012 on a first major surface of the metal layer and forming an opening 1013 in the first photoresist layer;

[0181] Performing metal electroplating 1003 on the opening in the first photoresist layer;

[0182] removing 1004 the first photoresist layer to form a plurality of conductive pads 131 a to 131 e ;

[0183] applying 1005 a laminating material or molding material 1014 over the first major surface of the metal layer and the metal plated plurality of conductive pads 131a to 131e;

[0184] removing 1006 the laminate or molding material from the first major surface portion of the metal layer until the metal plated plurality of conductive pads 131a to 131e are exposed, and removing the carrier from the second major surface of the metal layer;

[0185] processing 1007 a second photoresist layer on the second major surface of the metal layer and forming an opening in the second photoresist layer;

[0186] The metal layer is removed 1008 from the openings of the second photoresist layer, and the second photoresist layer is removed from the second major surface of the metal layer to form a plurality of conductors 132a to 132e.

[0187] As a supplement or alternative to the conventional PCB patterning process (photolithography + etching + resist removal, where the resist is used as an etching mask) described in steps 1007 and 1008, a pattern plating process (photolithography + plating + resist removal + etching, where the resist is used as a plating mask and the plating pattern is used as an etching mask) can also be used.

[0188] In a first process step 1001, a metal foil 1010 may be attached to a carrier 1011. Alternatively, this may be done by the foil manufacturer and in the first process step 1001 a carrier 1011 covered with the metal foil 1010 may be used.

[0189] Figures 11a to 11k A schematic diagram of an exemplary process flow for manufacturing a build-up substrate provided by the second embodiment is shown.

[0190] These figures describe the fabrication and PCB structure to manufacture a build-up substrate 110 for GaN using a simplified and cost-optimized manufacturing process.

[0191] The process flow represents a simple process that can use existing processes, but all unnecessary process steps are skipped to reduce processing time and processing costs compared to the conventional process flow.

[0192] Figures 11a to 11k The process shown also uses a carrier 1101, where a Cu seed layer 1110 is attached to a temporary carrier 1111. The first step 1102 after manufacturing the 1101 carrier (temporary carrier 1111 + Cu foil 1110) is a photolithography process 1102. By the photolithography process 1102, large area openings 1113 are made in the photoresist 1112. These large area openings 1113 form through-holes that pass through the package and the substrate base surface.

[0193] After the Cu pattern plating 1103, the resist is removed 1104 and the PCB material is laminated 1105 or the molding material is molded on the plated Cu 131a to 131e. The plated Cu structures 131a to 131e are exposed from the top by a grinding or milling process, such as Fig.11e shown.

[0194] After exposing a large area of ​​electroplated Cu strip, such as Fig.11f As shown, a seed layer 1115 is sputtered 1106 on the exposed side of the panel. This is followed by a photolithography process 1107, a pattern plating process 1108, a resist removal process 1109, and a seed layer etching process 1120.

[0195] Before optional solder mask and surface treatment processes (solderable surface, e.g., ENIG, etc.), such as Figure 11k As shown, the temporary Cu carrier 1111 is removed 1121, and as Fig.11j As shown, the seed layer is etched or structured 1120 .

[0196] pass Figures 11a to 11k The process shown in FIG. 1 and FIG. Figure 2a to Figure 2f The laminate substrate 110.

[0197] Figures 11a to 11k The process flow shown may be described by a method 1100 of manufacturing a build-up substrate 110 for a power package 100, for example, as described above in conjunction with FIG. 1 and Figure 2a to Figure 2f The method 1100 comprises the following steps:

[0198] Providing 1101 a carrier 1111 having a first metal layer 1110 attached thereto, wherein the first metal layer has a first main surface and an opposite second main surface facing the carrier 1111 ;

[0199] processing 1102 a first photoresist layer 1112 on a first major surface of the first metal layer and forming an opening 1113 in the first photoresist layer;

[0200] Performing metal electroplating 1103 on the openings in the first photoresist layer;

[0201] removing 1104 the first photoresist layer from the first metal layer to form a plurality of conductive pads 131 a to 131 e ;

[0202] Applying 1105 a laminate or molding material 1114 on the first major surface of the first metal layer and the metal-plated plurality of conductive pads 131a to 131e, and removing the laminate or molding material from the first major surface of the first metal layer until the metal-plated plurality of conductive pads 131a to 131e are exposed;

[0203] applying 1106 a second metal layer 1115 on the exposed metal-plated plurality of conductive pads 131a to 131e and the partially removed laminate or molding material, wherein the second metal layer has a first major surface 1115a and an opposite second major surface 1115b, the second major surface 1115b facing the exposed metal-plated plurality of conductive pads 131a to 131e and the partially removed laminate or molding material;

[0204] processing 1107 a second photoresist layer 1116 on the first major surface of the second metal layer and forming an opening 1117 in the second photoresist layer;

[0205] performing metal electroplating 1108 on the openings in the second photoresist layer;

[0206] removing 1109 the second photoresist layer from the first major surface of the second metal layer to form a plurality of conductors 132a to 132e;

[0207] removing 1120 the second metal layer from the laminate or molded material;

[0208] The carrier and the first metal layer are removed 1121 .

[0209] For example, by photolithography and etching processes, the carrier and the first metal layer can also be at least partially retained in the final structure. This can be combined with the above Figure 10g and Fig.10h The process described is the same.

[0210] Although specific features or aspects of the present invention may have been disclosed in conjunction with only one of several implementations, such features or aspects may be combined with one or more features or aspects in other implementations, as long as it is necessary or advantageous for any given or specific application. In addition, to a certain extent, the terms "including", "having", "having" or other variations of these words are used in the detailed description or claims, and such terms are similar to the term "including" and are both intended to include. Similarly, the terms "exemplary" and "for example" are only represented as examples, rather than the best or optimal. The terms "coupled" and "connected" and derivatives may be used. It should be understood that these terms can be used to indicate that two elements cooperate or interact with each other, regardless of whether they are in direct physical contact or electrical contact, or they are not in direct contact with each other.

[0211] Although specific aspects have been illustrated and described herein, it will be appreciated by those skilled in the art that a variety of alternative and / or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the invention. This application is intended to cover any modifications or changes to the specific aspects discussed herein.

[0212] Although elements in the following claims are listed in a specific order with corresponding labels, these elements are not necessarily limited to being implemented in this specific order unless the claim recitation otherwise implies a specific order for implementing some or all of these elements.

[0213] According to the above guidance, many substitutions, modifications and changes are obvious to those skilled in the art. Of course, those skilled in the art will readily appreciate that in addition to the applications described herein, there are numerous other applications of the present invention. Although the present invention has been described in conjunction with one or more specific embodiments, those skilled in the art recognize that many changes may be made to the present invention without departing from the scope of the present invention. Therefore, it should be understood that within the scope of the appended claims and their equivalents, the present invention may be practiced in a manner different from that specifically described herein.

Claims

1. A build-up substrate (110) for a power package (100), characterized in that: The laminate substrate (110) comprises: an electrically insulating layer (120) having a first major surface (110a) and an opposing second major surface (110b); A plurality of conductive pads (131a to 131e) encapsulated in the electrical insulation layer (120), wherein the plurality of conductive pads (131a to 131e) are arranged to form a staggered structure, the conductive pads extend from the first main surface (110a) to the second main surface (110b) through the electrical insulation layer (120), and the conductive pads (131a to 131e) are aligned along a first long axis on the second main surface (110b) of the electrical insulation layer (120); a plurality of parallel conductors (132a to 132e) mounted on the second major surface (110b) of the electrical insulation layer (120), wherein the parallel conductors (132a to 132e) are aligned along a second long axis on the second major surface (110b) of the electrical insulation layer (120), The first long axis is substantially perpendicular to the second long axis at a position on the second major surface (110b) of the electrical insulating layer (120), and the corresponding pads (131a to 131e) are electrically connected to the corresponding conductors (132a to 132e).

2. The build-up substrate (110) according to claim 1, characterized in that: The conductive pads (131a to 131e) are arranged in an interdigitated pattern.

3. The build-up substrate (110) according to claim 1 or 2, characterized in that: A corresponding pad among the plurality of conductive pads (131a to 131e) is defined by a length and a width of the corresponding pad; The length of the corresponding pad is greater than the width of the corresponding pad; The first major axis extends along the length direction of the corresponding pad.

4. The laminate substrate (110) according to any one of the preceding claims, characterized in that: The plurality of conductive pads (131a to 131e) form through holes penetrating the electrical insulating layer (120) of the build-up substrate (110).

5. The laminate substrate (110) according to any one of the preceding claims, characterized in that: The plurality of conductive pads (131a to 131e) are formed according to a predetermined electrode pattern of at least one electronic chip (140) included in the power package (100).

6. The laminate substrate (110) according to any one of the preceding claims, characterized in that: The plurality of conductive pads (131a to 131e) and the plurality of parallel conductors (132a to 132e) are covered by the electrical insulation layer (120) at the edge of the build-up substrate (110) to provide lateral electrical insulation of the build-up substrate.

7. The laminate substrate (110) according to any one of the preceding claims, characterized in that: At least one of the plurality of conductive pads (131a to 131e) is electrically isolated from at least one other of the plurality of conductive pads (131a to 131e) by the electrical insulation layer (120); and / or At least one conductor of the plurality of conductors (132a to 132e) is electrically isolated from at least one other conductor of the plurality of conductors (132a to 132e) by the electrical insulation layer (120).

8. The laminate substrate (110) according to any one of the preceding claims, characterized in that: The electrical insulating layer (120) comprises at least one or a combination of a laminate material or a molded material; and / or The plurality of conductive pads (131a to 131e) and the plurality of conductors (132a to 132e) include a plated Cu structure.

9. A power package (100), characterized in that: include: A laminate substrate (110) according to any one of the preceding claims; At least one electronic chip (140) comprising a first main surface (140a) and a second main surface (140b) opposite to the first main surface (140a), wherein the at least one electronic chip (140) comprises at least one first terminal (141) electrically connected to at least one pad (131a) of the plurality of conductive pads (131a to 131e) and at least one second terminal (142) electrically connected to at least one other pad (131c) of the plurality of conductive pads (131a to 131e); as well as an encapsulant (150) encapsulating at least a portion of the at least one electronic chip (140); or an underfill (151) attaching the at least one electronic chip (140) to the build-up substrate (110).

10. The power package (100) according to claim 9, characterized in that: The second main surface (140b) of the at least one electronic chip (140) faces the first main surface (110a) of the electrical insulation layer (120); The at least one first terminal (141) and the at least one second terminal (142) are arranged on the second main surface (140b) of the at least one electronic chip (140) and are mounted on corresponding pads of the plurality of conductive pads (131a to 131e).

11. The power package (100) according to claim 9, characterized in that: The second main surface (140b) of the at least one electronic chip (140) faces the second main surface (110b) of the electrical insulation layer (120); The at least one first terminal (141) and the at least one second terminal (142) are disposed on the second main surface (140b) of the at least one electronic chip (140) and are mounted on corresponding conductors among the plurality of conductors (132a to 132e).

12. The power package (100) according to any one of claims 9 to 11, characterized in that: The at least one electronic chip (140) comprises a plurality of side surfaces arranged between the first main surface (140a) and the second main surface (140b) of the at least one electronic chip (140); and The sealant (150) covers the first main surface (140a) and the side surfaces of the at least one electronic chip (140); or The first main surface (140a) of the at least one electronic chip (140) is not covered by the sealant (150), and the sealant (150) at least partially covers the side surface of the at least one electronic chip (140); or The first main surface (140a) of the at least one electronic chip (140) is not covered by the bottom fill (151), and the bottom fill (151) partially covers the side surface of the at least one electronic chip (140).

13. The power package (100) according to any one of claims 9 to 12, characterized in that: Form single die GaN packages or multi-die GaN packages in half-bridge or parallel die configurations with or without drivers and / or passives.

14. The power package (100) according to any one of claims 9 to 13, characterized in that: include: At least one first solder layer (133a) is disposed between the at least one first terminal (141) and the at least one pad (131a) among the plurality of conductive pads (131a to 131e), wherein the at least one first solder layer (133a) electrically connects the at least one first terminal (141) to the at least one pad (131a) among the plurality of conductive pads (131a to 131e); and / or At least one second solder layer (133c) is arranged between the at least one second terminal (142) and the at least one other pad (131c) among the multiple conductive pads (131a to 131e), wherein the at least one second solder layer (133c) electrically connects the at least one second terminal (142) to the at least one other pad (131c) among the multiple conductive pads (131a to 131e).

15. The power package (100) according to any one of claims 9 to 14, characterized in that: A leadframe-less package is formed.

16. A method (1000) for manufacturing a build-up substrate (110) for a power package (100) according to any one of claims 1 to 7, characterized in that: The method comprises: Providing (1001) a carrier (1011) having a metal layer (1010) attached thereto, wherein the metal layer (1010) has a first main surface (1010a) and an opposite second main surface (1010b) facing the carrier; processing (1002) a first photoresist layer (1012) on the first major surface of the metal layer, and forming an opening (1013) in the first photoresist layer; Performing metal electroplating on the opening in the first photoresist layer (1003); removing (1004) the first photoresist layer to form the plurality of conductive pads (131a to 131e); applying (1005) a laminating or molding material (1014) on the first major surface of the metal layer and the plurality of metal-plated conductive pads (131a to 131e); removing (1006) the laminate or molding material from the first major surface portion of the metal layer until the plurality of metal-plated conductive pads (131a to 131e) are exposed, and removing the carrier from the second major surface of the metal layer; processing (1007) a second photoresist layer on the second major surface of the metal layer and forming an opening in the second photoresist layer; The metal layer is removed (1008) from the openings of the second photoresist layer, and the second photoresist layer is removed from the second major surface of the metal layer to form the plurality of conductors (132a to 132e).

17. A method (1100) for manufacturing a build-up substrate (110) for a power package (100) according to any one of claims 1 to 8, characterized in that: The method comprises: Providing (1101) a carrier (1111) having a first metal layer (1110) attached thereto, wherein the first metal layer has a first main surface and an opposite second main surface facing the carrier (1111); processing (1102) a first photoresist layer (1112) on the first major surface of the first metal layer, and forming an opening (1113) in the first photoresist layer; Performing metal electroplating on the opening in the first photoresist layer (1103); removing (1104) the first photoresist layer from the first metal layer to form the plurality of conductive pads (131a to 131e); Applying (1105) a laminate or molding material (1114) on the first major surface of the first metal layer and the plurality of metal-plated conductive pads (131a to 131e), and removing the laminate or molding material from the first major surface portion of the first metal layer until the plurality of metal-plated conductive pads (131a to 131e) are exposed; Applying (1106) a second metal layer (1115) on the exposed metal-plated plurality of conductive pads (131a to 131e) and the partially removed laminate or molding material, wherein the second metal layer has a first major surface (1115a) and an opposing second major surface (1115b), the second major surface (1115b) facing the exposed metal-plated plurality of conductive pads (131a to 131e) and the partially removed laminate or molding material; processing (1107) a second photoresist layer (1116) on the first major surface of the second metal layer and forming an opening (1117) in the second photoresist layer; performing metal electroplating on the opening in the second photoresist layer (1108); removing (1109) the second photoresist layer from the first major surface of the second metal layer to form the plurality of conductors (132a to 132e); removing (1120) the second metal layer from the laminate or molded material; The carrier and the first metal layer are removed (1121).

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