Foreground calibration system based on pseudo-random code injection pipeline analog-to-digital converter

Abstract

The invention belongs to the field of analog-to-digital converters, particularly relates to a foreground calibration system based on a pseudo-random code injection assembly line analog-to-digital converter, and aims to solve the problems that an existing calibration method of the analog-to-digital converter is not high enough in speed and too complex. The method comprises the steps that a calibration state machine controls generation of pseudo-random codes, pseudo-random code injection positions and the number of cycles; the stagei module to be calibrated receives the pseudo-random code and generates a thermometer code; the pseudo-random code changes the switching of the sampling switch differential capacitor pair; the rear-stage assembly line module receives the output of the stagei residual error amplifier as the input and outputs a digital code; the synchronized digital code is calibrated; multiplying each calibration result by the value of the pseudo-random code to obtain a product, and accumulating each product to obtain a product sum; extracting a mismatch error based on the product sum; the compensation value calculation module calculates an error compensation value; and the error compensation module compensates the output result. According to the invention, the problem of mismatch error of the capacitor can be solved.

Description

Background Art

[0002] In the pipeline analog-to-digital converter, MDAC realizes the functions of signal sampling and residual amplification, and its performance directly affects the overall performance of ADC. The main structure of the sub-DAC is the capacitor array. Due to non-ideal factors such as process deviation, there are mismatch errors in the capacitors, which in turn affect the linearity of the pipeline ADC and limit its application. Currently, the commonly used calibration technologies are mainly capacitor error averaging and capacitor trimming, which are implemented by modifying the analog circuit. These methods are often accompanied by an increase in the complexity of the clock and the complexity of the analog circuit, and the overall conversion speed will also be limited.

[0003] Therefore, the existing calibration method of analog-to-digital converter has the problems of insufficient conversion speed and overly complex circuit. Summary of the invention

[0004] In order to solve the above-mentioned problems in the prior art, that is, the existing calibration method of analog-to-digital converter has the problems of insufficient conversion speed and overly complex circuit, the present invention provides a calibration system of pipeline analog-to-digital converter based on pseudo-random code injection, the system comprising:

[0005] A calibration state machine is used to control the pseudo-random code generator to generate pseudo-random codes, the pseudo-random code injection position, and the number of cycles during the calibration phase;

[0006] The stagei module 1 to be calibrated is used to receive the pseudo-random code and generate a thermometer code; based on the pseudo-random code, the switch of the sampling switch differential capacitor pair in the MDAC in the stagei module 1 to be calibrated is changed, and the residual amplifier connected to the sampling switch capacitor pair in the MDAC outputs a differential residual voltage;

[0007] The rear-stage pipeline module 2 is used to receive the differential residual voltage output by the residual amplifier and use it as an input signal, then output a digital code, and pass the digital code to the timing synchronization module;

[0008] The timing synchronization module is used to synchronize the digital code and pass the synchronized digital code to the redundant bit digital calibration module; the redundant bit digital calibration module is used to perform redundant bit digital calibration on the synchronized digital code; then the result of each calibration is multiplied by the value of the pseudo-random code through a multiplier to obtain a product, and then each product is accumulated through an accumulator to obtain a product sum; based on the product sum, the mismatch error of the sampling switch differential capacitor pair injected by the pseudo-random code is extracted; the first register group is used to store the mismatch error of the sampling switch differential capacitor pair;

[0009] A compensation value calculation module, which calculates an error compensation value based on the thermometer code and the mismatch error; a second register group, which is used to store the error compensation value;

[0010] A multi-way selection module is used to determine the error value corresponding to the current input value based on the current digital code and the error compensation value after the calibration is completed; the error compensation module compensates the output result based on the error value. In a preferred embodiment, when the output of the sub-ADC thermometer code in the stagei module 1 to be calibrated is K bits, the MDAC circuit in the stagei module 1 to be calibrated includes (K+2) groups of sampling switch differential capacitor pairs, each differential capacitor pair has four switch paths; the (K+2) groups of sampling switch differential capacitor pairs include a first newly added sampling switch differential capacitor pair P1, a second newly added sampling switch differential capacitor pair P2 and K groups of ordinary sampling switch differential capacitor pairs; the K groups of sampling switch differential capacitor pairs related to the K-bit thermometer code output are recorded as Q i ; i∈[0,K-1];

[0011] The capacitance value of the first newly added sampling switch differential capacitor pair P1 is aC s The four switches are the first switch, the second switch, the third switch, and the fourth switch. The first switch is added to control the common mode voltage V CM The access is used to realize the sampling in the calibration phase and the normal working phase. The second switch, the third switch and the fourth switch are added to control the access of the signal in the residual amplification phase. The second switch is added to control the positive terminal V P and negative terminal V N The third switch is added to control the positive terminal V N and negative terminal V P The fourth switch is added to control the positive terminal 1 / 2V of the amplifier. P and the negative terminal of the amplifier 1 / 2V P The access of the newly added second switch, the newly added third switch, and the newly added fourth switch are controlled by the calibration state machine;

[0012] The capacitance value of the second newly added sampling switch differential capacitor pair P2 is 1 / 2aC s The four switches are the fifth switch, the sixth switch, the seventh switch, and the eighth switch. The fifth switch controls the common mode voltage V CM The sixth switch, the seventh switch, and the eighth switch control the access of the signal in the residual amplification stage, and the sixth switch controls the positive terminal V P and negative terminal V N The seventh switch controls the positive terminal V N and negative terminal V P The eighth switch controls the positive terminal of the amplifier to 1 / 2V P and negative terminal 1 / 2V P The fifth switch, the sixth switch, the seventh switch and the eighth switch are controlled by the calibration state machine and the pseudo-random code.

[0013] In a preferred embodiment, the K groups of common sampling switch differential capacitor pairs include:

[0014] K groups of common sampling switch differential capacitors Q i The capacitance value is aC s , the four switches are the first common switch 、 The second common switch, the third common switch, the fourth common switch, and the first common switch control voltage V CM The second common switch controls the positive terminal V INP and negative terminal V INN The third common switch controls the positive terminal V P and negative terminal V N The fourth common switch controls the positive terminal V N and negative terminal V P The third common switch and the fourth common switch are controlled by the calibration state machine and the pseudo-random code during the calibration phase; i∈[0,K-1]; i is a number;

[0015] The K groups of common sampling switch differential capacitor pairs correspond one-to-one to the K bits of the thermometer code.

[0016] In a preferred implementation, the switches in the K+2 groups of sampling switch differential capacitor pairs have non-overlapping clock signals during the sampling and residual amplification stages.

[0017] In a preferred embodiment, during the calibration phase, when the thermometer code output is K bits, the foreground calibration system divides the calibration time into K+1 time periods to extract mismatch errors, wherein each time period includes N cycles.

[0018] In a preferred embodiment, the pseudo-random code is generated by a linear shift feedback register, the number of which is related to the value of the number of cycles N in each time period; the number of cycles N in each time period is 2 x , the number of registers is x-1.

[0019] In a preferred implementation, in the first time period, the pseudo-random code is only injected into the second newly added sampling switch differential capacitor pair P2;

[0020] In the first time period, in the first newly added sampling switch differential capacitor pair P1, the first switch and the fourth switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling phase. CM ; During the residual amplification stage, the positive and negative terminals of the amplifier are connected to 1 / 2V P ;

[0021] In the second newly added sampling switch differential capacitor pair P2, the sixth switch and the seventh switch are controlled by the pseudo-random code PN; when the pseudo-random code PN=1, the fifth switch and the sixth switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling stage. CM ; During the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ; When PN = 0, the fifth switch and the seventh switch form a periodic non-overlapping clock to complete sampling and residual amplification. The sampling phase is connected to V CM ; During the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ;

[0022] For the common sampling switch differential capacitor pairs numbered from K / 2 to K-1, the first common switch and the fourth common switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling phase. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ;

[0023] For the sampling switch differential capacitor pairs numbered from 0th to K / 2-1th, the first common switch and the third common switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling phase. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ; The differential residual voltage output by the residual amplifier, i.e. the input of the subsequent pipeline module 2, is:

[0024] The post-stage pipeline module 2 generates a first digital code based on the input. After the first digital code is synchronized by the timing synchronization module, the redundant bit digital calibration module performs redundant bit digital calibration. The calibrated result and the value of the pseudo-random code are operated by the multiplier module and the accumulator module to obtain the product sum. Based on the product sum, the mismatch error of the second newly added differential capacitor pair is extracted:

[0025] Specifically:

[0026] The mismatch error of the second newly added differential capacitor pair is:

[0027] The fixed offsets are:

[0028] Where V p V ref , V n is 0, The mismatch value of the amplifier positive terminal capacitance in the newly added differential capacitor pair P2 is: is the mismatch value of the negative terminal capacitance of the amplifier in the newly added differential capacitor pair P2, a is the number of sampling capacitors in the sampling switch differential capacitor pair, b is the number of feedback capacitors, PN is the pseudo-random code, and σ is the remaining mismatch value that is not related to the pseudo-random code in the current stage.

[0029] In a preferred embodiment, in the 2nd to K / 2+1th time period, calculating the mismatch error includes:

[0030] Let L∈[2, K / 2+1]), L is any number between 2 and K / 2+1;

[0031] When calculating the mismatch error for the K+1-Lth group of sampling switch differential capacitor pairs:

[0032] In the first newly added sampling switch differential capacitor pair P1, the first switch and the third switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling phase. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ;

[0033] In the second newly added sampling switch differential capacitor pair P2, the sixth switch and the seventh switch are controlled by the pseudo-random code PN. When PN=1, the fifth switch and the seventh switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling stage. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ; When PN = 0, the fifth switch and the sixth switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected during the sampling phase. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ;

[0034] The third and fourth common switches in the K+1-Lth group of sampling switch differential capacitor pairs are controlled by the pseudo-random code PN. When PN=1, the first and third common switches in the K+1-Lth group of sampling switch differential capacitor pairs form a periodic non-overlapping clock to complete sampling and residual amplification. The sampling phase is connected to V CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V NWhen PN=0, the first common switch and the fourth common switch in the K+1-Lth group of sampling switch differential capacitor pairs form a periodic non-overlapping clock to complete sampling and residual amplification. The sampling phase is connected to V CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ;

[0035] For the first common switch and the fourth common switch in the common sampling switch differential capacitor pairs of the K / 2 to K-1 groups except the K+1-L groups, a periodic non-overlapping clock is formed to complete sampling and residual amplification. The sampling phase is connected to V CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ;

[0036] The first common switch and the third common switch in the sampling switch differential capacitor pair of the 0th to 1 / 2K-1th groups form a periodic non-overlapping clock to complete sampling and residual amplification. The sampling phase is connected to V CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ; The differential residual voltage output by the residual amplifier, i.e. the input of the subsequent pipeline module 2, is:

[0037] The rear-stage pipeline module 2 generates a second digital code based on the input. After the second digital code is synchronized by the timing synchronization module, the redundant bit digital calibration module performs redundant bit digital calibration. The calibrated result and the value of the pseudo-random code are operated by the multiplier module and the accumulator module to obtain a product sum. Based on the product sum and combined with the mismatch error value of the second newly added differential capacitor pair P2, the mismatch errors of the K / 2 to K-1 groups of common sampling switch differential capacitor pairs are extracted;

[0038] The mismatch error of the differential capacitor pairs of the K / 2th to K-1th groups of common sampling switches is:

[0039] The fixed offsets are:

[0040] Where V p V ref , V n is 0, The mismatch value of the amplifier positive terminal capacitance in the newly added differential capacitor pair P2 is: The mismatch value of the negative terminal capacitance of the amplifier in the newly added differential capacitor pair P2 is: is the mismatch value of the differential capacitor of the K+1-Lth group of common sampling switches to the positive terminal capacitor of the amplifier, is the mismatch value of the negative terminal capacitance of the amplifier of the K+1-Lth group of ordinary sampling switch differential capacitors, a is the number of sampling capacitors in the sampling switch differential capacitor pair, b is the number of feedback capacitors, PN is the pseudo-random code, and σ is the other mismatch values ​​that are not related to the pseudo-random code in the current stage.

[0041] In a preferred embodiment, in the K / 2+2th to K+1th stages, calculating the mismatch error includes:

[0042] Let M∈[K / 2+2, K+1], where M is any number from K / 2+2 to K+1;

[0043] For the first newly added sampling switch differential capacitor pair P1, the first switch and the second switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected during the sampling phase. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ;

[0044] For the second newly added sampling switch differential capacitor pair P2, the sixth switch and the seventh switch are controlled by the pseudo-random code PN; when PN=1, the fifth switch and the seventh switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling phase. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ; When PN = 0, the fifth switch and the sixth switch form a periodic non-overlapping clock to complete sampling and residual amplification. The sampling phase is connected to V CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ;

[0045] For the K+1-Mth group of sampling switch differential capacitor pairs, the third common switch and the fourth common switch are controlled by the pseudo-random code PN. When PN=1, the first common switch and the third common switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling stage. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ; When PN = 0, the first common switch and the fourth common switch form a periodic non-overlapping clock to complete sampling and residual amplification. The sampling phase is connected to V CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ;

[0046] The first common switch and the fourth common switch in the K / 2 to K-1 groups of sampling switch differential capacitor pairs form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling phase. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ;

[0047] For the first and third common switches in the common sampling switch differential capacitor pairs of the 0th to 1 / 2K-1th groups except the K+1-Mth groups, a periodic non-overlapping clock is formed to complete sampling and residual amplification. The common mode voltage V is connected in the sampling stage. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ;

[0048] The differential residual voltage output by the residual amplifier, i.e. the input of the subsequent pipeline module 2, is:

[0049] The rear-stage pipeline module 2 generates a third digital code based on the input. After the third digital code is synchronized by the timing synchronization module, the redundant bit digital calibration module performs redundant bit digital calibration. The calibrated result and the value of the pseudo-random code are operated by the multiplier module and the accumulator module to obtain a product sum. Based on the product sum and combined with the mismatch error value of the second newly added differential capacitor pair P2, the mismatch errors of the 0th to K / 2-1th common sampling switch differential capacitor pairs are extracted;

[0050] Specifically:

[0051] The mismatch error of the differential capacitor pair of the K+1-Mth group of common sampling switches is:

[0052] The fixed offsets are:

[0053] Where V p V ref , V n is 0, The mismatch value of the amplifier positive terminal capacitance in the newly added differential capacitor pair P2 is: The mismatch value of the negative terminal capacitance of the amplifier in the newly added differential capacitor pair P2 is: is the mismatch value of the differential capacitance of the K+1-Mth group of common sampling switches to the positive capacitance of the amplifier, is the mismatch value of the negative terminal capacitance of the amplifier of the K+1-Mth group of ordinary sampling switch differential capacitors, a is the number of sampling capacitors in the sampling switch differential capacitor pair, b is the number of feedback capacitors, PN is the pseudo-random code, and σ is the other mismatch values ​​that are not related to the pseudo-random code in the current stage.

[0054] In a preferred embodiment, the error compensation values ​​for different input ranges are calculated based on the thermometer code generated by the stage 1 module to be calibrated and the mismatch error, including:

[0055] When K+1 time periods are completed, the mismatch errors of K groups of common differential capacitor pairs are calculated and stored in the first register group. The mismatch errors of K groups of common differential capacitor pairs are Error x (x∈[0,K-1]);

[0056] Thermometer code is {B K-1 B K-2 ...B1B0}, then the compensation error value is:

[0057]

[0058] Among them, B x is the xth thermometer code, Error x is the mismatch error of the xth group of common differential capacitor pairs.

[0059] Beneficial effects of the present invention:

[0060] (1) The foreground calibration system of mismatched capacitors in the pipeline analog-to-digital converter of the present invention can effectively solve the problem of mismatch errors in capacitors and improve the linearity of the pipeline ADC. In the foreground calibration system of mismatched capacitors in the pipeline analog-to-digital converter of the present invention, a detailed control scheme is given for the switches in the sampling switch capacitor array during the calibration phase, and the formula is rigorously derived based on the random code injection method, so that the control scheme and algorithm are reasonable and feasible.

[0061] (2) In the foreground calibration system of mismatched capacitors in the pipeline analog-to-digital converter of the present invention, the mismatch error of the capacitor in a certain stage of the pipeline ADC is calculated, and the method is universal and highly portable. In the foreground calibration system of mismatched capacitors in the pipeline analog-to-digital converter of the present invention, after power-on, the calibration state machine controls the injection of random codes to automatically calculate the mismatch error and store it, without the need for human intervention.

[0062] (3) In the foreground calibration system of mismatched capacitors in the pipeline analog-to-digital converter of the present invention, two sets of sampling switch differential capacitor pairs are added to the MDAC circuit, thereby reducing the complexity of digital circuit design with relatively small hardware overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0064] Figure 1 is a schematic diagram of a calibration system for a pipeline analog-to-digital converter based on pseudo-random code injection according to an embodiment of the present invention;

[0065] Figure 2 is a schematic diagram of a sampling switch differential capacitor pair according to an embodiment of the present invention;

[0066] Figure 3 is a schematic diagram of the working timing of the first time period in an embodiment of the present invention;

[0067] Figure 4 is a schematic diagram of the working timing of the 2nd to K / 2+1 time periods in an embodiment of the present invention;

[0068] Figure 5 1 is a schematic diagram of the working timing of the K / 2+2th to K+1th time periods in an embodiment of the present invention. DETAILED DESCRIPTION

[0069] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the relevant invention are shown in the accompanying drawings.

[0070] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0071] The present invention provides a calibration system for a pipeline analog-to-digital converter based on pseudo-random code injection, the system comprising:

[0072] A calibration state machine is used to control the pseudo-random code generator to generate pseudo-random codes, the pseudo-random code injection position, and the number of cycles during the calibration phase;

[0073] The stagei module 1 to be calibrated is used to receive the pseudo-random code and generate a thermometer code; based on the pseudo-random code, the switch of the sampling switch differential capacitor pair in the MDAC in the stagei module 1 to be calibrated is changed, and the residual amplifier connected to the sampling switch capacitor pair in the MDAC outputs a differential residual voltage;

[0074] The rear-stage pipeline module 2 is used to receive the differential residual voltage output by the residual amplifier and use it as an input signal, then output a digital code, and pass the digital code to the timing synchronization module;

[0075] The timing synchronization module is used to synchronize the digital code and pass the synchronized digital code to the redundant bit digital calibration module; the redundant bit digital calibration module is used to perform redundant bit digital calibration on the synchronized digital code; then the result of each calibration is multiplied by the value of the pseudo-random code through a multiplier to obtain a product, and then each product is accumulated through an accumulator to obtain a product sum; based on the product sum, the mismatch error of the sampling switch differential capacitor pair injected by the pseudo-random code is extracted; the first register group is used to store the mismatch error of the sampling switch differential capacitor pair;

[0076] A compensation value calculation module, which calculates an error compensation value based on the thermometer code and the mismatch error; a second register group, which is used to store the error compensation value;

[0077] The multi-way selection module is used to determine the error value corresponding to the current input value based on the current digital code and the error compensation value after the calibration is completed; the error compensation module compensates the output result based on the error value.

[0078] In order to more clearly explain the calibration system based on pseudo-random code injection pipeline analog-to-digital converter of the present invention, the following is combined with Figure 1 Each module in the embodiment of the present invention is described in detail.

[0079] The calibration system based on pseudo-random code injection pipeline analog-to-digital converter of the first embodiment of the present invention, each module is described in detail as follows:

[0080] A calibration state machine is used to control the pseudo-random code generator to generate pseudo-random codes, the pseudo-random code injection position, and the number of cycles during the calibration phase;

[0081] The stagei module 1 to be calibrated is used to receive the pseudo-random code and generate a thermometer code; based on the pseudo-random code, the switch of the sampling switch differential capacitor pair in the MDAC in the stagei module 1 to be calibrated is changed, and the residual amplifier connected to the sampling switch capacitor pair in the MDAC outputs a differential residual voltage;

[0082] The rear-stage pipeline module 2 is used to receive the differential residual voltage output by the residual amplifier and use it as an input signal, then output a digital code, and pass the digital code to the timing synchronization module;

[0083] In this embodiment, when the output of the thermometer code in the stagei module 1 to be calibrated is K bits, the MDAC circuit in the stagei module 1 to be calibrated includes K+2 groups of sampling switch differential capacitor pairs, each differential capacitor pair has four switch paths; the K+2 groups of sampling switch differential capacitor pairs include a first newly added sampling switch differential capacitor pair P1, a second newly added sampling switch differential capacitor pair P2 and K groups of ordinary sampling switch differential capacitor pairs; the K groups of sampling switch differential capacitor pairs related to the K-bit thermometer code output are recorded as Q i ; i∈[0,K-1];

[0084] like Figure 2 As shown in FIG. 1 , there are K+2 sets of sampling switch differential capacitor pairs in the MDAC circuit. The capacitance value of the first newly added sampling switch differential capacitor pair P1 is aC s The four switches are the first switch, the second switch, the third switch, and the fourth switch. The first switch is added to control the common mode voltage V CM The access is used to realize the sampling in the calibration phase and the normal working phase. The second switch, the third switch and the fourth switch are added to control the access of the signal in the residual amplification phase. The second switch is added to control the positive terminal V P and negative terminal V N The third switch is added to control the positive terminal V N and negative terminal V P The fourth switch is added to control the positive terminal 1 / 2V of the amplifier. P and the negative terminal of the amplifier 1 / 2V P The access of the newly added second switch, the newly added third switch, and the newly added fourth switch are controlled by the calibration state machine;

[0085] The capacitance value of the second newly added sampling switch differential capacitor pair P2 is 1 / 2aC s The four switches are the fifth switch, the sixth switch, the seventh switch, and the eighth switch. The fifth switch controls the common mode voltage V CM The sixth switch, the seventh switch, and the eighth switch control the access of the signal in the residual amplification stage, and the sixth switch controls the positive terminal V P and negative terminal V N The seventh switch controls the positive terminal V N and negative terminal V P The eighth switch controls the positive terminal of the amplifier to 1 / 2V P and negative terminal 1 / 2V P The fifth switch, the sixth switch, the seventh switch and the eighth switch are controlled by the calibration state machine and the pseudo-random code.

[0086] In this embodiment, the K groups of common sampling switch differential capacitor pairs include: the K groups of common sampling switch differential capacitor pairs Qi have a capacitance value of aCs, the four switches are respectively a first common switch, a second common switch, a third common switch, and a fourth common switch, and the first common switch controls the voltage V CM The second common switch controls the positive terminal V INP and negative terminal V INN The third common switch controls the positive terminal V P and negative terminal V N The fourth common switch controls the positive terminal V N and negative terminal V P The third common switch and the fourth common switch are controlled by the calibration state machine and the pseudo-random code during the calibration phase; i∈[0,K-1]; i is a number;

[0087] The K groups of common sampling switch differential capacitor pairs correspond one-to-one to the K bits of the thermometer code.

[0088] In this embodiment, the switches in the K+2 groups of sampling switch differential capacitor pairs have non-overlapping clock signals in the sampling and residual amplification stages.

[0089] In this embodiment, the pseudo-random code is generated by a linear shift feedback register, and the number of linear shift feedback registers is related to the value of the number of cycles N in each time period; the value of the number of cycles N in each time period is 2 x , the number of registers is x-1.

[0090] The timing synchronization module is used to synchronize the digital code and pass the synchronized digital code to the redundant bit digital calibration module; the redundant bit digital calibration module is used to perform redundant bit digital calibration on the synchronized digital code; then the result of each calibration is multiplied by the value of the pseudo-random code through a multiplier to obtain a product, and then each product is accumulated through an accumulator to obtain a product sum; based on the product sum, the mismatch error of the sampling switch differential capacitor pair injected by the pseudo-random code is extracted; the first register group is used to store the mismatch error of the sampling switch differential capacitor pair;

[0091] In this embodiment, when the thermometer code output is K bits, the foreground calibration system divides the calibration time into K+1 time periods to extract the mismatch error, wherein each time period includes N cycles.

[0092] In this embodiment, in the first time period, the pseudo-random code is only injected into the second newly added sampling switch differential capacitor pair P2;

[0093] In the first time period, in the first newly added sampling switch differential capacitor pair P1, the first switch and the fourth switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling phase. CM ; During the residual amplification stage, the positive and negative terminals of the amplifier are connected to 1 / 2V P ;

[0094] like Figure 3 As shown, in the second newly added sampling switch differential capacitor pair P2, the sixth switch and the seventh switch are controlled by the pseudo-random code PN; when the pseudo-random code PN=1, the fifth switch and the sixth switch form a periodic non-overlapping clock to complete sampling and residual amplification, and the common mode voltage V is connected in the sampling stage. CM ; During the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ; When PN = 0, the fifth switch and the seventh switch form a periodic non-overlapping clock to complete sampling and residual amplification. The sampling phase is connected to V CM ; During the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ;

[0095] For the common sampling switch differential capacitor pairs numbered from K / 2 to K-1, the first common switch and the fourth common switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling phase. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ;

[0096] For the sampling switch differential capacitor pairs numbered from 0th to K / 2-1th, the first common switch and the third common switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling phase. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ;

[0097] The differential residual voltage output by the residual amplifier, i.e. the input of the subsequent pipeline module 2, is:

[0098] The post-stage pipeline module 2 generates a first digital code based on the input. After the first digital code is synchronized by the timing synchronization module, the redundant bit digital calibration module performs redundant bit digital calibration. The calibrated result and the value of the pseudo-random code are operated by the multiplier module and the accumulator module to obtain the product sum. Based on the product sum, the mismatch error of the second newly added differential capacitor pair is extracted:

[0099] Specifically:

[0100] The mismatch error of the second newly added differential capacitor pair P2 is:

[0101] The fixed offsets are:

[0102] Where V p V ref , V n is 0, The mismatch value of the amplifier positive terminal capacitance in the newly added differential capacitor pair P2 is: is the mismatch value of the negative terminal capacitance of the amplifier in the newly added differential capacitor pair P2, a is the number of sampling capacitors in the sampling switch differential capacitor pair, b is the number of feedback capacitors, PN is the pseudo-random code, and σ is the remaining mismatch value that is not related to the pseudo-random code in the current stage.

[0103] In this embodiment, if Figure 4 As shown, in the time period from 2 to K / 2+1, the calculation of the mismatch error includes:

[0104] Let L∈[2, K / 2+1]), L is any number between 2 and K / 2+1;

[0105] When calculating the mismatch error for the K+1-Lth group of sampling switch differential capacitor pairs:

[0106] In the first newly added sampling switch differential capacitor pair P1, the first switch and the third switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling phase. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ;

[0107] In the second newly added sampling switch differential capacitor pair P2, the sixth switch and the seventh switch are controlled by the pseudo-random code PN. When PN=1, the fifth switch and the seventh switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling stage. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ; When PN = 0, the fifth switch and the sixth switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected during the sampling phase. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ;

[0108] The third and fourth common switches in the K+1-Lth group of sampling switch differential capacitor pairs are controlled by the pseudo-random code PN. When PN=1, the first and third common switches in the K+1-Lth group of sampling switch differential capacitor pairs form a periodic non-overlapping clock to complete sampling and residual amplification. The sampling phase is connected to V CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N。 When PN=0, the first common switch and the fourth common switch in the K+1-Lth group of sampling switch differential capacitor pairs form a periodic non-overlapping clock to complete sampling and residual amplification. The sampling phase is connected to V CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ;

[0109] For the first common switch and the fourth common switch in the common sampling switch differential capacitor pairs of the K / 2 to K-1 groups except the K+1-L groups, a periodic non-overlapping clock is formed to complete sampling and residual amplification. The sampling phase is connected to V CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ;

[0110] The first common switch and the third common switch in the sampling switch differential capacitor pair of the 0th to 1 / 2K-1th groups form a periodic non-overlapping clock to complete sampling and residual amplification. The sampling phase is connected to V CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ;

[0111] The differential residual voltage output by the residual amplifier, i.e. the input of the subsequent pipeline module 2, is:

[0112] The rear-stage pipeline module 2 generates a second digital code based on the input. After the second digital code is synchronized by the timing synchronization module, the redundant bit digital calibration module performs redundant bit digital calibration. The calibrated result and the value of the pseudo-random code are operated by the multiplier module and the accumulator module to obtain a product sum. Based on the product sum and combined with the mismatch error value of the second newly added differential capacitor pair P2, the mismatch errors of the K / 2 to K-1 groups of common sampling switch differential capacitor pairs are extracted;

[0113] The mismatch error of the differential capacitor pairs of the K / 2th to K-1th groups of common sampling switches is:

[0114] The fixed offsets are:

[0115] Where V p V ref , V n is 0, The mismatch value of the amplifier positive terminal capacitance in the newly added differential capacitor pair P2 is: The mismatch value of the negative terminal capacitance of the amplifier in the newly added differential capacitor pair P2 is: is the mismatch value of the differential capacitor of the K+1-Lth group of common sampling switches to the positive terminal capacitor of the amplifier, is the mismatch value of the negative terminal capacitance of the amplifier of the K+1-Lth group of ordinary sampling switch differential capacitors, a is the number of sampling capacitors in the sampling switch differential capacitor pair, b is the number of feedback capacitors, PN is the pseudo-random code, and σ is the other mismatch values ​​that are not related to the pseudo-random code in the current stage.

[0116] like Figure 5 As shown, in this embodiment, in the K / 2+2th to K+1th time stages, calculating the mismatch error includes:

[0117] Let M∈[K / 2+2, K+1], where M is any number from K / 2+2 to K+1;

[0118] For the first newly added sampling switch differential capacitor pair P1, the first switch and the second switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected during the sampling phase. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ;

[0119] For the second newly added sampling switch differential capacitor pair P2, the sixth switch and the seventh switch are controlled by the pseudo-random code PN; when PN=1, the fifth switch and the seventh switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling phase. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ; When PN = 0, the fifth switch and the sixth switch form a periodic non-overlapping clock to complete sampling and residual amplification. The sampling phase is connected to V CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ;

[0120] For the K+1-Mth group of sampling switch differential capacitor pairs, the third common switch and the fourth common switch are controlled by the pseudo-random code PN. When PN=1, the first common switch and the third common switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling stage. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ; When PN = 0, the first common switch and the fourth common switch form a periodic non-overlapping clock to complete sampling and residual amplification. The sampling phase is connected to V CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ;

[0121] The first common switch and the fourth common switch in the K / 2 to K-1 groups of sampling switch differential capacitor pairs form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling phase. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ;

[0122] For the first and third common switches in the common sampling switch differential capacitor pairs of the 0th to 1 / 2K-1th groups except the K+1-Mth groups, a periodic non-overlapping clock is formed to complete sampling and residual amplification. The common mode voltage V is connected in the sampling stage. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ;

[0123] The differential residual voltage output by the residual amplifier, i.e. the input of the subsequent pipeline module 2, is:

[0124] The rear-stage pipeline module 2 generates a third digital code based on the input. After the third digital code is synchronized by the timing synchronization module, the redundant bit digital calibration module performs redundant bit digital calibration. The calibrated result and the value of the pseudo-random code are operated by the multiplier module and the accumulator module to obtain a product sum. Based on the product sum and combined with the mismatch error value of the second newly added differential capacitor pair P2, the mismatch errors of the 0th to K / 2-1th groups of common sampling switch differential capacitor pairs are extracted;

[0125] The mismatch error of the 0th to K / 2-1th groups of common sampling switch differential capacitor pairs is:

[0126] The fixed offsets are:

[0127] Where V p V ref , V n is 0, The mismatch value of the amplifier positive terminal capacitance in the newly added differential capacitor pair P2 is: The mismatch value of the negative terminal capacitance of the amplifier in the newly added differential capacitor pair P2 is: is the mismatch value of the differential capacitor of the K+1-Lth group of common sampling switches to the positive terminal capacitor of the amplifier, is the mismatch value of the negative terminal capacitance of the amplifier of the K+1-Lth group of ordinary sampling switch differential capacitors, a is the number of sampling capacitors in the sampling switch differential capacitor pair, b is the number of feedback capacitors, PN is the pseudo-random code, and σ is the other mismatch values ​​that are not related to the pseudo-random code in the current stage.

[0128] A compensation value calculation module, which calculates an error compensation value based on the thermometer code and the mismatch error; a second register group, which is used to store the error compensation value;

[0129] The multi-way selection module is used to determine the error value corresponding to the current input value based on the current digital code and the error compensation value after the calibration is completed; the error compensation module compensates the output result based on the error value.

[0130] In this embodiment, the error compensation values ​​for different input ranges are calculated based on the thermometer code and the mismatch error, including:

[0131] When K+1 time periods are completed, the mismatch errors of K groups of common differential capacitor pairs are calculated and stored in the first register group. The mismatch errors of K groups of common differential capacitor pairs are Error x (x∈[0,K-1]);

[0132] Thermometer code is {B K-1 B K-2 ...B1B0}, then the compensation error value is:

[0133]

[0134] Among them, B x is the xth thermometer code, Error x is the mismatch error of the xth group of common differential capacitor pairs.

[0135] It should be noted that the calibration system of the pipeline analog-to-digital converter based on pseudo-random code injection provided in the above embodiment is only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the modules or steps in the embodiments of the present invention can be decomposed or combined. For example, the modules in the above embodiment can be combined into one module, or further divided into multiple sub-modules to complete all or part of the functions described above. The names of the modules and steps involved in the embodiments of the present invention are only for distinguishing the modules or steps, and are not regarded as improper limitations of the present invention.

[0136] A second embodiment of the present invention provides a calibration method for a pipeline analog-to-digital converter based on pseudo-random code injection, the method comprising:

[0137] In the calibration stage, the calibration state machine controls the generation of pseudo-random codes, the injection position of pseudo-random codes, and the number of cycles; the module 1 of the stage i to be calibrated receives the pseudo-random codes and generates thermometer codes; the pseudo-random codes change the switches of the sampling switch differential capacitor pair in the MDAC; the residual amplifier connected to the sampling switch capacitor pair in the MDAC outputs a differential residual voltage; the post-stage pipeline module 2 receives the output of the residual amplifier in the module 1 of the stage i to be calibrated as input, outputs a digital code, and passes the digital code to the timing synchronization module; the timing synchronization module synchronizes the digital code and passes the synchronized digital code to the redundant bit digital calibration module; the redundant bit digital calibration module synchronizes the digital code to the redundant bit digital calibration module. The redundant bit digital calibration is performed on the digital code after the step; then the result of each calibration is multiplied by the value of the pseudo-random code through a multiplier to obtain a product, and then each product is accumulated through an accumulator to obtain a product sum; based on the product sum, the mismatch error of the sampling switch differential capacitor pair injected by the pseudo-random code is extracted; then the mismatch error of the sampling switch differential capacitor pair is stored in the first register group; the compensation value calculation module calculates the error compensation value based on the thermometer code and the mismatch error and saves it to the second register group; after the calibration is completed, the multi-way selection module determines the error value corresponding to the current input value based on the current digital code and the error compensation value; the error compensation module compensates the output result based on the error value.

[0138] Although the various steps in the above embodiment are described in the above-mentioned order, those skilled in the art can understand that in order to achieve the effect of this embodiment, different steps do not have to be executed in such an order. They can be executed simultaneously (in parallel) or in a reverse order. These simple changes are within the scope of protection of the present invention.

[0139] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process and related instructions of the system described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0140] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. A calibration system for pipeline analog-to-digital converters based on pseudo-random code injection, characterized in that: The system comprises: A calibration state machine is used to control the pseudo-random code generator to generate pseudo-random codes, the pseudo-random code injection position, and the number of cycles during the calibration phase; The stagei module 1 to be calibrated is used to receive the pseudo-random code and generate a thermometer code; based on the pseudo-random code, the switch of the sampling switch differential capacitor pair in the MDAC in the stagei module 1 to be calibrated is changed, and the residual amplifier connected to the sampling switch capacitor pair in the MDAC outputs a differential residual voltage; The rear-stage pipeline module 2 is used to receive the differential residual voltage output by the residual amplifier and use it as an input signal, then output a digital code, and pass the digital code to the timing synchronization module; The timing synchronization module is used to synchronize the digital code and pass the synchronized digital code to the redundant bit digital calibration module; the redundant bit digital calibration module is used to perform redundant bit digital calibration on the synchronized digital code; then the result of each calibration is multiplied by the value of the pseudo-random code through a multiplier to obtain a product, and then each product is accumulated through an accumulator to obtain a product sum; based on the product sum, the mismatch error of the sampling switch differential capacitor pair injected by the pseudo-random code is extracted; the first register group is used to store the mismatch error of the sampling switch differential capacitor pair; A compensation value calculation module, which calculates an error compensation value based on the thermometer code and the mismatch error; a second register group, which is used to store the error compensation value; The multi-way selection module is used to determine the error value corresponding to the current input value based on the current digital code and the error compensation value after the calibration is completed; the error compensation module compensates the output result based on the error value.

2. The calibration system for pipeline analog-to-digital converter based on pseudo-random code injection according to claim 1, characterized in that: The thermometer code output in the stagei module 1 to be calibrated is K bits, and the MDAC circuit in the stagei module 1 to be calibrated includes K+2 groups of sampling switch differential capacitor pairs, each differential capacitor pair has four switch paths; the K+2 groups of sampling switch differential capacitor pairs include a first newly added sampling switch differential capacitor pair P1, a second newly added sampling switch differential capacitor pair P2 and K groups of common sampling switch differential capacitor pairs; the K groups of sampling switch differential capacitor pairs related to the K-bit thermometer code output are recorded as Q i ; i∈[0,K-1]; The capacitance value of the first newly added sampling switch differential capacitor pair P1 is aC s The four switches are the first switch, the second switch, the third switch, and the fourth switch. The first switch is added to control the common mode voltage V CM The access is used to realize the sampling in the calibration phase and the normal working phase. The second switch, the third switch and the fourth switch are added to control the access of the signal in the residual amplification phase. The second switch is added to control the positive terminal V P and negative terminal V N The third switch is added to control the positive terminal V N and negative terminal V P The fourth switch is added to control the positive terminal 1 / 2V of the amplifier. P and the negative terminal of the amplifier 1 / 2V P The access of the newly added second switch, the newly added third switch, and the newly added fourth switch are controlled by the calibration state machine; The capacitance value of the second newly added sampling switch differential capacitor pair P2 is 1 / 2aC s The four switches are the fifth switch, the sixth switch, the seventh switch, and the eighth switch. The fifth switch controls the common mode voltage V CM The sixth switch, the seventh switch, and the eighth switch control the access of the signal in the residual amplification stage, and the sixth switch controls the positive terminal V P and negative terminal V N The seventh switch controls the positive terminal V N and negative terminal V P The eighth switch controls the positive terminal of the amplifier to 1 / 2V P and negative terminal 1 / 2V P The fifth switch, the sixth switch, the seventh switch and the eighth switch are controlled by the calibration state machine and the pseudo-random code.

3. The calibration system for pipeline analog-to-digital converter based on pseudo-random code injection according to claim 2, characterized in that: The K groups of common sampling switch differential capacitor pairs include: K groups of common sampling switch differential capacitors Q i The capacitance value is aC s , the four switches are first common switches 、 The second common switch, the third common switch, the fourth common switch, and the first common switch control voltage V CM The second common switch controls the positive terminal V INP and negative terminal V INN The third common switch controls the positive terminal V P and negative terminal V N The fourth common switch controls the positive terminal V N and negative terminal V P The third common switch and the fourth common switch are controlled by the calibration state machine and the pseudo-random code during the calibration phase; i∈[0,K-1]; i is a number; The K groups of common sampling switch differential capacitor pairs correspond one-to-one to the K bits of the thermometer code.

4. The calibration system based on pseudo-random code injection pipeline analog-to-digital converter according to claim 3, characterized in that: The switches in the K+2 groups of sampling switch differential capacitor pairs are non-overlapping clock signals in the sampling and residual amplification stages.

5. The calibration system for pipeline analog-to-digital converter based on pseudo-random code injection according to claim 4, characterized in that: In the calibration phase, when the thermometer code output is K bits, the foreground calibration system divides the calibration time into K+1 time periods to extract the mismatch error, wherein each time period includes N cycles.

6. The calibration system for pipeline analog-to-digital converter based on pseudo-random code injection according to claim 5, characterized in that: The pseudo-random code is generated by a linear shift feedback register, the number of which is related to the value of the number of cycles N in each time period; the number of cycles N in each time period is 2 x , the number of registers is x-1.

7. The calibration system for pipeline analog-to-digital converter based on pseudo-random code injection according to claim 6, characterized in that: In the first time period, the pseudo-random code is only injected into the second newly added sampling switch differential capacitor pair P2; In the first time period, in the first newly added sampling switch differential capacitor pair P1, the first switch and the fourth switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling phase. CM ; During the residual amplification stage, the positive and negative terminals of the amplifier are connected to 1 / 2V P ; In the second newly added sampling switch differential capacitor pair P2, the sixth switch and the seventh switch are controlled by the pseudo-random code PN; when the pseudo-random code PN=1, the fifth switch and the sixth switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling stage. CM ; During the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ; When PN = 0, the fifth switch and the seventh switch form a periodic non-overlapping clock to complete sampling and residual amplification. The sampling phase is connected to V CM ; During the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ; For the common sampling switch differential capacitor pairs numbered from K / 2 to K-1, the first common switch and the fourth common switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling phase. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ; For the sampling switch differential capacitor pairs numbered from 0th to K / 2-1th, the first common switch and the third common switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling phase. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ; The differential residual voltage output by the residual amplifier, i.e. the input of the subsequent pipeline module 2, is: The post-stage pipeline module 2 generates a first digital code based on the input. After the first digital code is synchronized by the timing synchronization module, the redundant bit digital calibration module performs redundant bit digital calibration. The calibrated result and the value of the pseudo-random code are operated by the multiplier module and the accumulator module to obtain the product sum. Based on the product sum, the mismatch error of the second newly added differential capacitor pair is extracted: Specifically: The mismatch error of the second newly added differential capacitor pair P2 is: The fixed offset is Where V p V ref , V n is 0, The mismatch value of the amplifier positive terminal capacitance in the newly added differential capacitor pair P2 is: is the mismatch value of the negative terminal capacitance of the amplifier in the newly added differential capacitor pair P2, a is the number of sampling capacitors in the sampling switch differential capacitor pair, b is the number of feedback capacitors, PN is the pseudo-random code, and σ is the remaining mismatch value that is not related to the pseudo-random code in the current stage.

8. The calibration system for pipeline analog-to-digital converter based on pseudo-random code injection according to claim 7, characterized in that: In the 2nd to K / 2+1 time period, the mismatch error is calculated including: Let L∈[2, K / 2+1]), L is any number between 2 and K / 2+1; When calculating the mismatch error for the K+1-Lth group of sampling switch differential capacitor pairs: In the first newly added sampling switch differential capacitor pair P1, the first switch and the third switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling phase. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ; In the second newly added sampling switch differential capacitor pair P2, the sixth switch and the seventh switch are controlled by the pseudo-random code PN. When PN=1, the fifth switch and the seventh switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling stage. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ; When PN = 0, the fifth switch and the sixth switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected during the sampling phase. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ; The third and fourth common switches in the K+1-Lth group of sampling switch differential capacitor pairs are controlled by the pseudo-random code PN. When PN=1, the first and third common switches in the K+1-Lth group of sampling switch differential capacitor pairs form a periodic non-overlapping clock to complete sampling and residual amplification. The sampling phase is connected to V CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N。 When PN=0, the first common switch and the fourth common switch in the K+1-Lth group of sampling switch differential capacitor pairs form a periodic non-overlapping clock to complete sampling and residual amplification. The sampling phase is connected to V CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ; For the first common switch and the fourth common switch in the common sampling switch differential capacitor pairs of the K / 2 to K-1 groups except the K+1-L groups, a periodic non-overlapping clock is formed to complete sampling and residual amplification. The sampling phase is connected to V CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ; The first common switch and the third common switch in the sampling switch differential capacitor pair of the 0th to 1 / 2K-1th groups form a periodic non-overlapping clock to complete sampling and residual amplification. The sampling phase is connected to V CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ; The differential residual voltage output by the residual amplifier, i.e. the input of the subsequent pipeline module 2, is: The rear-stage pipeline module 2 generates a second digital code based on the input. After the second digital code is synchronized by the timing synchronization module, the redundant bit digital calibration module performs redundant bit digital calibration. The calibrated result and the value of the pseudo-random code are operated by the multiplier module and the accumulator module to obtain a product sum. Based on the product sum and the mismatch error value of the second newly added differential capacitor pair P2, the mismatch errors of the K / 2th to K-1th common sampling switch differential capacitor pairs are extracted; The mismatch error of the K+1-Lth group of common sampling switch differential capacitor pairs is: The fixed offsets are: Where V p V ref , V n is 0, The mismatch value of the amplifier positive terminal capacitance in the newly added differential capacitor pair P2 is: The mismatch value of the negative terminal capacitance of the amplifier in the newly added differential capacitor pair P2 is: is the mismatch value of the differential capacitor of the K+1-Lth group of common sampling switches to the positive terminal capacitor of the amplifier, is the mismatch value of the negative terminal capacitance of the amplifier of the K+1-Lth group of ordinary sampling switch differential capacitors, a is the number of sampling capacitors in the sampling switch differential capacitor pair, b is the number of feedback capacitors, PN is the pseudo-random code, and σ is the other mismatch values ​​that are not related to the pseudo-random code in the current stage.

9. The calibration system based on pseudo-random code injection pipeline analog-to-digital converter according to claim 8, characterized in that: In the K / 2+2th to K+1th stages, the mismatch error is calculated including: Let M∈[K / 2+2, K+1], where M is any number from K / 2+2 to K+1; For the first newly added sampling switch differential capacitor pair P1, the first switch and the second switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected during the sampling phase. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ; For the second newly added sampling switch differential capacitor pair P2, the sixth switch and the seventh switch are controlled by the pseudo-random code PN; when PN=1, the fifth switch and the seventh switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling stage. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ; When PN = 0, the fifth switch and the sixth switch form a periodic non-overlapping clock to complete sampling and residual amplification. The sampling phase is connected to V CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ; For the K+1-Mth group of sampling switch differential capacitor pairs, the third common switch and the fourth common switch are controlled by the pseudo-random code PN. When PN=1, the first common switch and the third common switch form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling stage. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ; When PN = 0, the first common switch and the fourth common switch form a periodic non-overlapping clock to complete sampling and residual amplification. The sampling phase is connected to V CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ; The first common switch and the fourth common switch in the K / 2 to K-1 groups of sampling switch differential capacitor pairs form a periodic non-overlapping clock to complete sampling and residual amplification. The common mode voltage V is connected in the sampling phase. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V N , the negative terminal is connected to V P ; For the first and third common switches in the common sampling switch differential capacitor pairs of the 0th to 1 / 2K-1th groups except the K+1-Mth groups, a periodic non-overlapping clock is formed to complete sampling and residual amplification. The common mode voltage V is connected in the sampling stage. CM , in the residual amplification stage, the positive terminal of the amplifier is connected to V P , the negative terminal is connected to V N ; The differential residual voltage output by the residual amplifier, i.e., the input signal of the subsequent pipeline module 2, is: The rear-stage pipeline module 2 generates a third digital code based on the input. After the third digital code is synchronized by the timing synchronization module, the redundant bit digital calibration module performs redundant bit digital calibration. The calibrated result and the value of the pseudo-random code are operated by the multiplier module and the accumulator module to obtain a product sum. Based on the product sum and the mismatch error value in the second newly added differential capacitor pair P2, the mismatch errors of the 0th to K / 2-1th common sampling switch differential capacitor pairs are extracted; The mismatch error of the differential capacitor pair of the K+1-Mth group of common sampling switches is: The fixed offsets are: Where V p V ref , V n is 0, The mismatch value of the amplifier positive terminal capacitance in the newly added differential capacitor pair P2 is: The mismatch value of the negative terminal capacitance of the amplifier in the newly added differential capacitor pair P2 is: is the mismatch value of the differential capacitance of the K+1-Mth group of common sampling switches to the positive capacitance of the amplifier, is the mismatch value of the negative terminal capacitance of the amplifier of the K+1-Mth group of ordinary sampling switch differential capacitors, a is the number of sampling capacitors in the sampling switch differential capacitor pair, b is the number of feedback capacitors, PN is the pseudo-random code, and σ is the other mismatch values ​​that are not related to the pseudo-random code in the current stage.

10. The calibration system based on pseudo-random code injection pipeline analog-to-digital converter according to claim 9, characterized in that: The error compensation values ​​for different input ranges calculated based on the thermometer code and mismatch error include: When K+1 time periods are completed, the mismatch errors of K groups of common differential capacitor pairs are calculated and stored in the first register group. The mismatch errors of K groups of common differential capacitor pairs are Error x (x∈[0,K-1]); Thermometer code is {B K-1 B K-2 ...B1B0}, then the compensation error value is: Different thermometer codes correspond to different compensation error values, and the compensation error values ​​are stored in the second register group; Among them, B x is the xth thermometer code, Error x is the mismatch error of the xth group of common differential capacitor pairs.

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