Semiconductor assembly and manufacturing method thereof

Abstract

The invention discloses a semiconductor assembly and a manufacturing method thereof, and the method mainly comprises the steps: forming a metal gate on a substrate, a contact hole etching stop layer beside the metal gate, and an interlayer dielectric layer surrounding the gate structure, carrying out a first etching technology to remove the interlayer dielectric layer, and carrying out a second etching technology to remove the interlayer dielectric layer; a second etching process is performed to remove the contact hole etch stop layer to form a first contact hole, a first contact plug is formed in the first contact hole, and the width of the first contact plug adjacent to the contact hole etch stop layer is smaller than that of the first contact plug below the contact hole etch stop layer.

Description

Technical Field

[0001] The invention relates to a method for manufacturing a semiconductor component, and in particular to a method for forming a contact hole by segmented etching. Background Art

[0002] In recent years, as the size of field effect transistors (FETs) components continues to shrink, the development of existing planar field effect transistor components has faced the limit of manufacturing process. In order to overcome the limitation of manufacturing process, it has become the current mainstream development trend to replace planar transistor components with non-planar field effect transistor components, such as fin field effect transistor (Fin FET) components. Since the three-dimensional structure of the fin field effect transistor component can increase the contact area between the gate and the fin structure, the gate can further increase the control of the carrier channel area, thereby reducing the drain induced barrier lowering (DIBL) effect faced by small-sized components and suppressing the short channel effect (SCE). Furthermore, since the fin field effect transistor component has a wider channel width at the same gate length, it can obtain double the drain drive current. Even more, the threshold voltage of the transistor component can be regulated by adjusting the work function of the gate.

[0003] In the current manufacturing process of fin field effect transistor components, a metal gate replacement process is usually used to convert the polysilicon gate into a metal gate, and then a photolithography and etching process is used to directly remove part of the interlayer dielectric layer next to the metal gate to form a contact hole, and then a conductive material is filled in the contact hole to form a contact plug. However, the process of forming the contact hole in this way is prone to cause epitaxial layer loss and affect the subsequent operation of the component. Therefore, how to improve the existing fin field effect transistor manufacturing process and architecture is an important issue today. Summary of the invention

[0004] An embodiment of the present invention discloses a method for manufacturing a semiconductor component, which mainly forms a metal gate on a substrate, a contact hole etch stop layer next to the metal gate, and an interlayer dielectric layer surrounding the gate structure, performs a first etching process to remove the interlayer dielectric layer, performs a second etching process to remove the contact hole etch stop layer to form a first contact hole, and then forms a first contact plug in the first contact hole, wherein the width of the first contact plug adjacent to the contact hole etch stop layer is smaller than the width of the first contact plug below the contact hole etch stop layer.

[0005] Another embodiment of the present invention discloses a semiconductor component, which mainly includes a metal gate arranged on a substrate, a contact hole etch stop layer arranged next to the metal gate, an interlayer dielectric layer surrounding the contact hole etch stop layer, and a first contact plug arranged in the interlayer dielectric layer, wherein the width of the first contact plug adjacent to the contact hole etch stop layer is smaller than the width of the first contact plug below the contact hole etch stop layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1 to 7 The figure is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0007] Explanation of symbols

[0008] 12: Base

[0009] 14: Fin structure

[0010] 16: Shallow Trench Isolation

[0011] 18: Gate structure

[0012] 20: Gate structure

[0013] 22: Gate structure

[0014] 26: Gate dielectric layer

[0015] 28: Gate material layer

[0016] 30: Gap wall

[0017] 32: Source / drain region

[0018] 34: Epitaxial layer

[0019] 36: Contact hole etching stop layer

[0020] 38: Interlayer dielectric layer

[0021] 40: Dielectric layer

[0022] 42 High dielectric constant dielectric layer

[0023] 44: Work function metal layer

[0024] 46: Low impedance metal layer

[0025] 48:Metal Gate

[0026] 50: Hard shield

[0027] 52: Hard shield

[0028] 54: Patterned shielding

[0029] 56:ODL

[0030] 58:SHB layer

[0031] 60: Patterned photoresist

[0032] 62: Opening

[0033] 64: Patterned shielding

[0034] 66:ODL

[0035] 68:SHB layer

[0036] 70: Patterned photoresist

[0037] 72: Opening

[0038] 74:Contact hole

[0039] 76:Contact hole

[0040] 78: protrusion

[0041] 80: protrusion

[0042] 84: Contact plug

[0043] 86: Contact plug DETAILED DESCRIPTION

[0044] Please refer to Figures 1 to 7 , Figures 1 to 7 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor component according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, and then at least one fin structure 14 is formed on the substrate 12, wherein the number of the fin structures 14 can be adjusted according to the manufacturing process or product requirements, but is not limited thereto.

[0045] According to a preferred embodiment of the present invention, the fin structure 14 is preferably obtained by sidewall pattern transfer (SIT) and other technologies, and the procedure generally includes: providing a layout pattern to a computer system, and defining the corresponding pattern in a photomask through appropriate calculations. Subsequently, a plurality of equidistant and equal-width patterned sacrificial layers can be formed on the substrate through photolithography and etching processes, so that their individual appearances are strip-shaped. Thereafter, deposition and etching processes are sequentially performed to form spacers on each sidewall of the patterned sacrificial layer. Subsequently, the patterned sacrificial layer is removed, and an etching process is performed under the coverage of the spacers, so that the pattern formed by the spacers is transferred to the substrate, and then the desired patterned structure, such as a strip-shaped patterned fin structure, is obtained by a fin structure cutting process (fin cut).

[0046] In addition, the formation method of the fin structure 14 may include first forming a patterned mask (not shown) on the substrate 12, and then performing an etching process to transfer the pattern of the patterned mask to the substrate 12 to form the fin structure 14. In addition, the formation method of the fin structure 14 may also include first forming a patterned hard mask layer (not shown) on the substrate 12, and using an epitaxial process to grow a semiconductor layer such as silicon germanium on the substrate 12 exposed from the patterned hard mask layer, and this semiconductor layer can serve as the corresponding fin structure 14. These embodiments of forming the fin structure 14 are all within the scope of the present invention.

[0047] Then, a shallow trench isolation (STI) 16 is formed to surround the fin structure 14. In the present embodiment, the shallow trench isolation 16 can be formed by first using a flowable chemical vapor deposition (FCVD) process to form a silicon oxide layer on the substrate 12 and completely cover the fin structure 14. Then, a chemical mechanical polishing (CMP) process is used in combination with an etching process to remove a portion of the silicon oxide layer, so that the remaining silicon oxide layer is flush with or slightly lower than the surface of the fin structure 14 to form the shallow trench isolation 16.

[0048] Then, a gate structure 18, 20, 22 or a dummy gate is formed on the fin structure 14. In the present embodiment, the gate structures 18, 20, 22 can be fabricated by a gate first fabrication process, a gate last fabrication process of a high-k first fabrication process, or a gate last fabrication process of a high-k last fabrication process according to the fabrication process requirements. Taking the post-high-k dielectric layer manufacturing process of the present embodiment as an example, a gate dielectric layer 26 or a dielectric layer, a gate material layer 28 composed of polycrystalline silicon, and a selective hard mask can be sequentially formed on the substrate 12, and a patterned photoresist (not shown) is used as a mask to perform a pattern transfer manufacturing process, and a portion of the gate material layer 28 and a portion of the gate dielectric layer 26 are removed by a single etching or successive etching steps, and then the patterned photoresist is stripped off to form gate structures 18, 20, 22 each composed of a patterned gate dielectric layer 26 and a patterned gate material layer 28 on the fin structure 14.

[0049] Then, at least one spacer 30 is formed on the sidewalls of the gate structures 18, 20, and 22, respectively, and then a source / drain region 32 and / or an epitaxial layer 34 are formed in the fin structure 14 and / or the substrate 12 on both sides of the spacer 30, and a metal silicide (not shown) is selectively formed on the surface of the source / drain region 32 and / or the epitaxial layer 34. Since the source / drain region 32 is only provided in the substrate 12 on both sides of the gate structure 20, the gate structure 20 is preferably an active gate and the gate structures 18 and 22 on both sides are virtual gates. In the present embodiment, the spacer 30 may be a single spacer or a composite spacer, for example, it may include an offset spacer and a main spacer in detail. The offset spacer and the main spacer may include the same or different materials, and both may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide. The source / drain regions 32 may include different dopants according to the conductivity type of the transistor to be prepared, for example, may include P-type dopants or N-type dopants, and the epitaxial layer 34 may include silicon germanium, silicon carbide or silicon phosphide.

[0050] In a preferred embodiment of the present invention, the epitaxial layer 34 may have different materials according to different types of MOS transistors. For example, if the MOS transistor is a P-type transistor (PMOS), the epitaxial layer 34 may include silicon germanium (SiGe), silicon germanium boron (SiGeB) or silicon germanium tin (SiGeSn). In another embodiment of the present invention, if the MOS transistor is an N-type transistor (NMOS), the epitaxial layer 34 may include silicon carbide (SiC), silicon carbon phosphide (SiCP) or silicon phosphide (SiP). In addition, the selective epitaxial manufacturing process may be formed in a single layer or multi-layer manner, and its heterogeneous atoms (such as germanium atoms or carbon atoms) may also be changed in a gradual manner, but it is preferred to make the surface of the epitaxial layer 34 lighter or without germanium atoms to facilitate the subsequent formation of a metal silicide layer.

[0051] According to one embodiment of the present invention, the source / drain region 32 can be selectively formed on a part or all of the epitaxial layer 34. In one embodiment, the formation of the source / drain region 32 can also be performed simultaneously (in-situ) with the selective epitaxial growth process. For example, when the metal oxide semiconductor conductor is a PMOS, the formation of a germanium silicide epitaxial layer, a germanium boron silicide epitaxial layer or a germanium tin silicide epitaxial layer can be accompanied by the injection of P-type dopants; or when the metal oxide semiconductor conductor is an NMOS, the formation of a carbon silicide epitaxial layer, a carbon phosphorus silicide epitaxial layer or a phosphorus silicide epitaxial layer can be accompanied by the injection of N-type dopants. In this way, the subsequent use of additional ion implantation steps to form the source / drain region 32 of the P-type / N-type transistor can be omitted. In addition, in another embodiment, the dopants of the source / drain region 32 can also be formed in a gradual manner.

[0052] Next, a contact hole etch stop layer 36 is formed to cover the gate structures 18, 20, 22 and the surface of the shallow trench isolation 16, and then an interlayer dielectric layer 38 is formed on the contact hole etch stop layer 36. Then, a planarization process is performed, such as using chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 38 and part of the contact hole etch stop layer 36 and expose the gate material layer 28 composed of polysilicon material, so that the upper surface of the gate material layer 28 is flush with the upper surface of the interlayer dielectric layer 38.

[0053] like Figure 2 As shown, a metal gate replacement process is then performed to convert the gate structures 18, 20, and 22 into metal gates. For example, a selective dry etching or wet etching process may be performed first, such as using an etching solution such as ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 28 and even the gate dielectric layer 26 in the gate structures 18, 20, and 22 to form a groove in the interlayer dielectric layer 38 (not shown).

[0054] Then, a selective dielectric layer 40 or gate dielectric layer, a high dielectric constant dielectric layer 42, a work function metal layer 44 and a low impedance metal layer 46 are sequentially formed in the groove, and then a planarization process is performed, such as using CMP to remove part of the low impedance metal layer 46, part of the work function metal layer 44 and part of the high dielectric constant dielectric layer 42 to form a metal gate 48. Taking the gate structure manufactured by the post high dielectric constant dielectric layer manufacturing process in this embodiment as an example, each formed metal gate 48 preferably includes a dielectric layer 40 or gate dielectric layer, a U-shaped high dielectric constant dielectric layer 42, a U-shaped work function metal layer 44 and a low impedance metal layer 46.

[0055] In the present embodiment, the high-k dielectric layer 42 comprises a dielectric material having a dielectric constant greater than 4, for example, selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalum oxide (strontium bismuth tantalum oxide), and strontium tantalum oxide (strontium bismuth tantalum oxide). tantalate,SrBi2Ta2O9,SBT), lead zirconate titanate (leadzirconate titanate,PbZr x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- x TiO3, BST), or a combination thereof.

[0056] The work function metal layer 44 is preferably used to adjust the work function of the metal gate so that it is suitable for an N-type transistor (NMOS) or a P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer 44 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl) or TiAlC (titanium aluminum carbide), etc., but not limited thereto; if the transistor is a P-type transistor, the work function metal layer 44 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN) or tantalum carbide (TaC), etc., but not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 44 and the low resistance metal layer 46, wherein the barrier layer may be made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. The low resistance metal layer 46 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., or a combination thereof.

[0057] Next, a portion of the high-k dielectric layer 42, a portion of the work function metal layer 44, and a portion of the low-resistance metal layer 46 may be removed to form a groove (not shown), and then a hard mask 50 is filled into the groove and made flush with the surface of the interlayer dielectric layer 38, wherein the hard mask 50 may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride.

[0058] Subsequently, another hard mask 52 may be formed all over the metal gate 48 and the top surface of the interlayer dielectric layer 38, and then a patterned mask 54 may be formed on the hard mask 52. In the present embodiment, the hard mask 52 preferably comprises silicon oxide such as tetraethyl orthosilicate (TEOS), and the patterned mask 54 comprises a multi-layer mask consisting of an organic dielectric layer (ODL) 56, a silicon-containing hard mask bottom anti-reflective coating (SHB) layer 58, and a patterned photoresist 60, wherein the patterned photoresist 60 preferably comprises an opening 62 to expose the SHB layer 58 directly above each metal gate 48.

[0059] like Figure 3As shown, an etching process is then performed using the patterned photoresist 60 as a mask to remove a portion of the SHB layer 58, a portion of the ODL 56, a portion of the hard mask 52, and even a portion of the hard mask 50 directly above each metal gate 48 and expose the hard mask 50 directly above the metal gate 48. Subsequently, the patterned mask 54 is removed to expose the hard mask 52 and the surface of the hard mask 50.

[0060] Then as Figure 4 As shown, another patterned mask 64 is formed on the hard mask 52, wherein the patterned mask 64 also includes an organic dielectric layer (ODL) 66, a silicon-containing hard mask and anti-reflective (SHB) layer 68 and a patterned photoresist 70, and the patterned photoresist 70 preferably includes an opening 72 to expose the SHB layer 68 directly above the source / drain region 32 or the epitaxial layer 34.

[0061] like Figure 5 As shown, an etching process is then performed using the patterned photoresist 70 as a mask to remove a portion of the SHB layer 68, a portion of the ODL 66, a portion of the hard mask 52, and a portion of the interlayer dielectric layer 38 directly above the source / drain region 32, and expose and stop at the surface of the contact hole etching stop layer 36. The patterned mask 64 is then removed and the surfaces of the hard mask 50 and the hard mask 52 above the metal gate 48 are exposed again.

[0062] like Figure 6 As shown, another etching process is then performed to simultaneously remove the hard mask 50 directly above the metal gate 48 and the portion of the contact hole etch stop layer 36 directly above the source / drain region 32, thereby forming a contact hole 74 to expose the top surface of the metal gate 48 and a contact hole 76 to expose the surface of the source / drain region 32. Since the hard mask 50 and the contact hole etch stop layer 36 are both made of silicon nitride, it is preferred to directly remove the portion of the hard mask 50 and the portion of the contact hole etch stop layer 36 by etching at this stage without additionally forming a patterned mask, wherein the etching process preferably does not remove any metal gate 48 when removing the portion of the hard mask 50, and preferably removes the portion of the epitaxial layer 34 downward when removing the portion of the contact hole etch stop layer 36.

[0063] It should also be noted that since the contact holes 74 and 76 are formed by a two-stage etching method in this stage, after removing part of the hard mask 50 and part of the contact hole etch stop layer 36, the side walls of each contact hole 74 and 76 preferably have a discontinuous side wall profile, wherein the side wall of the contact hole 74 directly above the metal gate 48 preferably has a protruding protrusion 78 that protrudes outward from the side wall portion of the bottom hard mask 50, and the contact hole 76 directly above the source / drain region 32 or the epitaxial layer 34 has a protrusion 80 on the side wall of the contact hole etch stop layer 36, and the width of the contact hole 76 adjacent to the contact hole etch stop layer 36 or between the contact hole etch stop layers 36 on both sides is preferably slightly smaller than the width of the contact hole 76 in the epitaxial layer 34 or below the contact hole etch stop layer 36.

[0064] like Figure 7 As shown, each contact hole 74, 76 is then filled with the required metal material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., or a combination thereof. A planarization process is then performed, such as chemical mechanical polishing to remove part of the metal material to form a contact plug 84 in the contact hole 74 to connect the metal gate 48 and a contact plug 86 in the contact hole 74 to electrically connect the source / drain region 34. At this point, the manufacturing of the semiconductor device of the preferred embodiment of the present invention is completed.

[0065] Please refer to Figure 7 , Figure 7 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is also disclosed. Figure 7 As shown, the semiconductor device mainly includes a metal gate 48 disposed on a substrate 12, a hard mask 50 disposed on the metal gate 48, a contact hole etch stop layer 36 disposed beside the metal gate 48, an interlayer dielectric layer 38 surrounding the contact hole etch stop layer 36, another hard mask 52 disposed on the hard mask 50 and the interlayer dielectric layer 38, a contact plug 84 disposed directly above the metal gate 48, and another contact plug 86 disposed in the interlayer dielectric layer 38 beside the metal gate 48.

[0066] In this embodiment, the sidewall of the contact plug 84 directly above the metal gate 48 and the sidewall of the contact plug 86 beside the metal gate 48 each include an uneven surface. In detail, the contact plug 84 between the hard shields 50 includes a first width close to the metal gate 84 and a second width close to the hard shield 52, wherein the second width is smaller than the first width. In other words, the second width disposed between the protrusions 78 on the sidewall of the hard shield 50 is preferably smaller than the first width disposed below the protrusions 78.

[0067] In addition, in the contact plug 86 portion, the width of the contact plug 86 adjacent to the contact hole etch stop layer 36 is preferably smaller than the width of the contact plug 86 below the contact hole etch stop layer 36, and the width of the contact plug 86 adjacent to the contact hole etch stop layer 36 is also smaller than the width of the contact plug 86 above the contact hole etch stop layer 36. In other words, the width of the contact plug 86 located between two contact hole etch stop layers 36 or protrusions 80 is preferably smaller than the width of the contact plug 86 below and above the contact hole etch stop layer 36.

[0068] In summary, the present invention mainly converts the polysilicon gate into a metal gate by using a metal gate replacement process, and then uses a first etching process to remove part of the interlayer dielectric layer beside the metal gate and stop at the surface of the contact hole etching stop layer, and then uses a second etching process to simultaneously remove part of the hard shield just above the metal gate and part of the contact hole etching stop layer beside the metal gate and expose the metal gate and the source / drain region or the surface of the epitaxial layer, and then fills the conductive material in each contact hole to form a contact plug. According to the preferred embodiment of the present invention, the use of this segmented etching method to produce the contact plug can greatly reduce the damage and loss of the epitaxial layer in the manufacturing process and improve the overall component performance.

[0069] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor component, characterized in that: Include: Forming a metal gate on the substrate, a contact hole etching stop layer beside the metal gate and an interlayer dielectric layer surrounding the gate structure; Performing a first etching process to remove the interlayer dielectric layer; as well as A second etching process is performed to remove the contact hole etching stop layer to form a first contact hole.

2. The method of claim 1, further comprising: forming a gate structure on the substrate; forming a source / drain region next to the gate structure; forming the contact hole etching stop layer beside the gate structure; forming the interlayer dielectric layer to surround the contact hole etching stop layer; Performing a metal gate replacement process to convert the gate structure into the metal gate; forming a first hard shield on the metal gate; forming a second hard mask on the first hard mask and the interlayer dielectric layer; Performing the first etching process to remove the second hard mask and the interlayer dielectric layer; Performing the second etching process to remove the contact hole etching stop layer and the first hard mask to form the first contact hole and the second contact hole; as well as A first contact plug is formed in the first contact hole and a second contact plug is formed in the second contact hole. 3 . The method according to claim 2 , wherein a width of the first contact plug adjacent to the contact hole etch stop layer is smaller than a width of the first contact plug below the contact hole etch stop layer. 4 . The method according to claim 2 , wherein a width of the first contact plug adjacent to the contact hole etch stop layer is smaller than a width of the first contact plug above the contact hole etch stop layer. The method of claim 2 , wherein the first contact plug sidewall comprises an uneven surface.

6. The method of claim 2, wherein the second contact plug disposed between the first hard shields comprises: A first width, close to the metal gate; and A second width is proximate to the second hard shield. The method of claim 6 , wherein the second width is smaller than the first width.

8. The method of claim 2, wherein the second contact plug sidewall comprises an uneven surface.

9. A semiconductor component, characterized in that: Include: A metal gate is disposed on the substrate; A contact hole etching stop layer is disposed beside the metal gate; An interlayer dielectric layer and an etch stop layer surrounding the contact hole; as well as The first contact plug is disposed in the interlayer dielectric layer, wherein the width of the first contact plug adjacent to the contact hole etching stop layer is smaller than the width of the first contact plug below the contact hole etching stop layer. 10 . The semiconductor device as claimed in claim 9 , wherein a width of the first contact plug adjacent to the contact hole etch stop layer is smaller than a width of the first contact plug above the contact hole etch stop layer. 11 . The semiconductor device as claimed in claim 9 , wherein a sidewall of the first contact plug comprises an uneven surface.

12. The semiconductor device according to claim 9, further comprising: A first hard shield is disposed on the metal gate, wherein a top surface of the first hard shield is aligned with a top surface of the interlayer dielectric layer; a second hard shield disposed on the first hard shield; as well as The second contact plug is disposed on the metal gate.

13. The semiconductor device of claim 12, wherein the second contact plug disposed between the first hard shields comprises: A first width, close to the metal gate; and A second width is proximate to the second hard shield. The semiconductor device as claimed in claim 13 , wherein the second width is smaller than the first width. 15 . The semiconductor device as claimed in claim 12 , wherein the second contact plug sidewall comprises an uneven surface.

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