Thin film transistor, preparation method thereof and display panel

Abstract

The invention provides a thin film transistor and a preparation method thereof, an array substrate and a display panel. The thin film transistor includes a substrate, and an active layer and a first gate electrode on the substrate. The active layer comprises a first film layer and a second film layer which are stacked on the substrate, the second film layer is located between the first film layer and the first gate electrode, the first film layer and the second film layer are semiconductor film layers, the mobility of the second film layer is lower than that of the first film layer, and the etching rate of the second film layer is lower than that of the first film layer. In the thin film transistor, the first film layer has relatively high mobility, so that when the thin film transistor works, carriers are gathered on the surface, facing the first gate electrode, of the first film layer, and the second film layer with low etching rate can protect the surface so as to avoid surface defects, thereby improving the performance of the thin film transistor.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular, to a thin film transistor and a method for preparing the same, and a display panel. Background Art

[0002] With the development of information technology, the usage rate of electronic display products in daily life is increasing. Thin film transistors are the main switching elements of the driving circuits in electronic display products. However, the active layer in current thin film transistors is limited by its own structural design and formation process. It is difficult to ensure high mobility and high stability while ensuring the film formation effect, thus limiting the further improvement of the performance of thin film transistors. Summary of the invention

[0003] In a first aspect, the present disclosure provides a thin film transistor, which includes a substrate, an active layer and a first gate electrode located on the substrate. The active layer includes a first film layer and a second film layer stacked on the substrate, the second film layer is located between the first film layer and the first gate electrode, the first film layer and the second film layer are semiconductor film layers, the mobility of the second film layer is lower than the mobility of the first film layer, and the etching rate of the second film layer is lower than the etching rate of the first film layer.

[0004] In the above scheme, the first film layer has a relatively high mobility. Therefore, when the thin film transistor is working, the carriers will gather on the surface of the first film layer facing the first gate electrode, and the second film layer with a low etching rate can improve the surface to avoid surface defects, thereby improving the performance of the thin film transistor.

[0005] In a specific embodiment of the first aspect of the present disclosure, the first film layer and the second film layer are composed of semiconductor film layers deposited by physical vapor deposition, and the power of physical vapor deposition corresponding to the semiconductor film layer used to constitute the first film layer is greater than the power of physical vapor deposition corresponding to the semiconductor film layer used to constitute the second film layer, so that the etching rate of the second film layer is less than the etching rate of the first film layer.

[0006] In another specific embodiment of the first aspect of the present disclosure, the first film layer is composed of a semiconductor film layer deposited by physical vapor deposition, and the second film layer is composed of a semiconductor film layer deposited by atomic layer deposition, so that the etching rate of the second film layer is less than the etching rate of the first film layer.

[0007] In a specific embodiment of the first aspect of the present disclosure, the material of the first film layer includes at least two of In, Ga, Zn, and Sn. For example, optionally, the material of the first film layer is one of IGZO, IGZTO, IZO, and IGO. For example, further, the mobility of the first film layer is not less than 20cm2 / Vs.

[0008] In a specific embodiment of the first aspect of the present disclosure, the material of the second film layer includes at least one of In, Ga, and Zn. For example, optionally, the material of the second film layer is IGZO. For example, further, the mobility of the second film layer is not greater than 15 cm 2 / Vs.

[0009] For example, optionally, the etching rate of the first film layer is not less than 20 angstroms / second, and the etching rate of the second film layer is not more than 10 angstroms / second.

[0010] For example, optionally, the first film layer and the second film layer are made of the same material.

[0011] In a specific embodiment of the first aspect of the present disclosure, the orthographic projection of the first film layer on the substrate coincides with the orthographic projection of the second film layer on the substrate. For example, optionally, the first film layer is in direct contact with the second film layer.

[0012] In a specific embodiment of the first aspect of the present disclosure, the active layer is located between the first gate electrode and the substrate, that is, the thin film transistor can be a top-gate thin film transistor. For example, optionally, the thickness of the second film layer is less than the thickness of the second film layer. For example, further optionally, the thickness of the first film layer is 50 to 500 angstroms, and / or the thickness of the second film layer is 10 to 100 angstroms.

[0013] In another specific embodiment of the first aspect of the present disclosure, the first gate electrode is located between the active layer and the substrate, that is, the thin film transistor can be a bottom-gate thin film transistor. For example, optionally, the orthographic projection of the active layer on the substrate is located within the orthographic projection of the first gate electrode on the substrate.

[0014] In a specific embodiment of the first aspect of the present disclosure, the active layer may further include a third film layer, the third film layer is located on a side of the first film layer away from the first gate electrode, and the third film layer includes a semiconductor material. The mobility of the third film layer is lower than the mobility of the first film layer, and the etching rate of the third film layer is lower than the etching rate of the first film layer. For example, optionally, the first film layer is in direct contact with the third film layer.

[0015] In a specific embodiment of the first aspect of the present disclosure, the active layer further includes a third film layer, which is located on a side of the first film layer away from the first gate electrode and is made of a semiconductor material. The mobility of the third film layer is lower than the mobility of the first film layer, and the etching rate of the third film layer is lower than the etching rate of the first film layer.

[0016] In the above solution, the third film layer and the second film layer can protect the first film layer from both sides to prevent harmful ions in other dielectric layers from invading the first film layer.

[0017] For example, optionally, the first film layer and the third film layer are composed of semiconductor film layers deposited by physical vapor deposition, and the power of physical vapor deposition corresponding to the semiconductor film layer used to constitute the first film layer is less than the power of physical vapor deposition corresponding to the semiconductor film layer used to constitute the third film layer, so that the etching rate of the third film layer is less than the etching rate of the first film layer; or, the first film layer is composed of a semiconductor film layer deposited by physical vapor deposition, and the third film layer is composed of a semiconductor film layer deposited by atomic layer deposition, so that the etching rate of the third film layer is less than the etching rate of the first film layer; further preferably, the etching rate of the third film layer is less than 10 angstroms / second.

[0018] For example, optionally, the material of the third film layer includes at least one of In, Ga, and Zn. For example, further optionally, the material of the third film layer is IGZO; further preferably, the mobility of the second film layer is not greater than 15 cm 2 / Vs.

[0019] In a specific embodiment of the first aspect of the present disclosure, the orthographic projection of the first film layer on the substrate coincides with the orthographic projection of the third film layer on the substrate.

[0020] In a specific embodiment of the first aspect of the present disclosure, the thin film transistor may further include a second gate electrode, the second gate electrode being located on a side of the active layer away from the first gate electrode. For example, optionally, the thin film transistor may further include a second gate insulating layer, the second gate insulating layer being located between the second gate electrode and the active layer.

[0021] A second aspect of the present disclosure provides a display panel, which includes the thin film transistor in the first aspect.

[0022] A third aspect of the present disclosure provides a method for preparing a thin film transistor, which comprises: providing a substrate; depositing a first semiconductor material film layer having a first mobility on the substrate at a first film forming rate, and depositing a second semiconductor material film layer having a second mobility at a second film forming rate, wherein the first mobility is greater than the second mobility, and the first film forming rate is greater than the second film forming rate, so that an etching rate of the second semiconductor material film layer is less than an etching rate of the first semiconductor material film layer; patterning the first semiconductor material film layer and the second semiconductor material film layer to form a first film layer and a second film layer, respectively; depositing a first conductive material thin film on the substrate, and composing the first conductive material thin film to form a first gate electrode, wherein the second film layer is formed between the first film layer and the first gate electrode.

[0023] In a specific embodiment of the third aspect of the present disclosure, the steps of depositing a first semiconductor material film layer having a first mobility at a first film forming rate on a substrate, and depositing a second semiconductor material film layer having a second mobility at a second film forming rate, may include: forming the first semiconductor material film layer and the second semiconductor material film layer respectively by physical vapor deposition, wherein the power of the physical vapor deposition for forming the first semiconductor material film layer is greater than the power of the physical vapor deposition for forming the second semiconductor material film layer, so that the first film forming rate is greater than the second film forming rate, and the etching rate of the second film layer is less than the etching rate of the first film layer. For example, optionally, the power of the physical vapor deposition for forming the first semiconductor material film layer is 4KW to 6KW, and the power of the physical vapor deposition for forming the second semiconductor material film layer is 2KW to 4KW.

[0024] In another specific embodiment of the third aspect of the present disclosure, the step of depositing a first semiconductor material film layer having a first mobility at a first film formation rate on a substrate, and depositing a second semiconductor material film layer having a second mobility at a second film formation rate may include: forming the first semiconductor material film layer by physical vapor deposition, and forming the second semiconductor material film layer by atomic layer deposition, so that the first film formation rate is greater than the second film formation rate, and the etching rate of the second film layer is less than the etching rate of the first film layer. For example, optionally, the first film formation rate is 80 angstroms / second to 120 angstroms / second, and the second film formation rate is 20 angstroms / second to 60 angstroms / second.

[0025] In a specific embodiment of the third aspect of the present disclosure, the preparation method may further include: depositing an insulating material between the first gate electrode and the active layer to form a first gate insulating layer, wherein the first gate insulating layer separates the first gate electrode and the active layer.

[0026] For example, optionally, the preparation method also includes: depositing a conductive material film layer on the side of the active layer away from the substrate, and patterning the conductive material film layer to form a source electrode and a drain electrode, wherein the source electrode and the drain electrode are respectively connected to two ends of the active layer.

[0027] In a specific embodiment of the third aspect of the present disclosure, the preparation method may further include: depositing a third semiconductor material film layer having a third mobility at a third rate, wherein the first mobility is greater than the third mobility, and the first film formation rate is greater than the third rate, so that the etching rate of the third semiconductor material film layer is less than the etching rate of the first semiconductor material film layer; and patterning the third semiconductor material film layer to form a third film layer.

[0028] In a specific embodiment of the third aspect of the present disclosure, the second mobility is equal to the third mobility.

[0029] In a specific embodiment of the third aspect of the present disclosure, the second film forming rate is equal to the third rate, so that the etching rates of the first film layer and the third film layer are equal.

[0030] In a specific embodiment of the third aspect of the present disclosure, the preparation method may also include: after depositing the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer, simultaneously performing a composition process on the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer to form a first film layer, a second film layer and a third film layer, and making the orthographic projection of the first film layer on the substrate, the orthographic projection of the second film layer on the substrate and the orthographic projection of the third film layer on the substrate coincide with each other.

[0031] In another specific embodiment of the third aspect of the present disclosure, the first gate electrode is formed on a side of the active layer facing away from the substrate, and the preparation method also includes: before forming the active layer and the first gate electrode, depositing a second conductive material film on the substrate, and composing the second conductive material film to form a second gate electrode.

[0032] For example, optionally, the preparation method may further include: before forming the active layer and the first gate electrode and after forming the second gate electrode, depositing an insulating material on the substrate to form a second gate insulating layer to cover the second gate electrode.

[0033] In another specific embodiment of the third aspect of the present disclosure, the first gate electrode is formed between the active layer and the substrate, and the preparation method may further include: after forming the first gate electrode and the active layer on the substrate, depositing a second conductive material film on the substrate, and composing the second conductive material film to form a second gate electrode, wherein the second gate electrode is formed on a side of the active layer away from the first gate electrode.

[0034] For example, optionally, the preparation method further includes: after forming the active layer and the first gate electrode and before forming the second gate electrode, depositing an insulating material on the substrate to form a second gate insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 FIG. 1 is a cross-sectional view of a thin film transistor provided by an embodiment of the present disclosure;

[0036] Figure 2 A cross-sectional view of another thin film transistor provided according to an embodiment of the present disclosure.

[0037] Figure 3 A cross-sectional view of another thin film transistor provided according to an embodiment of the present disclosure.

[0038] Figure 4 A cross-sectional view of another thin film transistor provided according to an embodiment of the present disclosure.

[0039] Figure 5 A cross-sectional view of an array substrate provided in accordance with an embodiment of the present disclosure.

[0040] Figure 6 A schematic diagram of a planar structure of a display panel provided in one embodiment of the present disclosure.

[0041] Figure 7 for Figure 6 The shown display panel is a cross-sectional view along line MN.

[0042] Figure 8 A flowchart of a method for preparing a thin film transistor provided by an embodiment of the present disclosure.

[0043] Figures 9 to 13 A process diagram of a method for preparing a thin film transistor provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of this specification to clearly and completely describe the technical solutions in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this specification.

[0045] In thin film transistors, the quality of the channel surface affects the mobility. If there are defects on the channel surface, the electrical properties and reliability of the channel will be degraded. In addition, when preparing dielectric layers in thin film transistors, if harmful ions invade the channel, it will also affect the electrical properties and reliability of the channel.

[0046] The embodiments of the present disclosure provide a thin film transistor and a method for preparing the same, and a display panel to at least solve the above technical problems. The thin film transistor includes a substrate, an active layer and a first gate electrode located on the substrate. The active layer includes a first film layer and a second film layer stacked on the substrate, the second film layer is located between the first film layer and the first gate electrode, the first film layer and the second film layer are semiconductor film layers, the mobility of the second film layer is lower than the mobility of the first film layer, and the etching rate of the second film layer is lower than the etching rate of the first film layer. In this design, the first film layer has a relatively high mobility, so when the thin film transistor is working, the carriers will gather on the surface of the first film layer facing the first gate electrode, and the second film layer with a low etching rate can improve the surface to avoid surface defects, thereby improving the performance of the thin film transistor; in addition, the second film layer with a low etching rate has a strong blocking effect on ions, so that the first film layer can be protected.

[0047] Below, the thin film transistor and its preparation method, and the structure involved in the display panel according to at least one embodiment of the present disclosure are described in conjunction with the accompanying drawings. In these embodiments, a spatial rectangular coordinate system is established based on the surface where the substrate in the thin film transistor is located (for example, or the display surface of the display panel) to describe the position of each structure in the thin film transistor, the array substrate, and the display panel. In this spatial rectangular coordinate system, the X-axis and the Y-axis are parallel to the substrate, and the Z-axis is perpendicular to the substrate.

[0048] like Figure 1 As shown, the thin film transistor 100 includes an active layer 120 and a first gate electrode 131, and the first gate electrode 131 is spaced apart from the active layer 120. The substrate 110 is used to support the active layer 120 and the first gate electrode 131. By controlling the voltage on the first gate electrode 131, the active layer 120 can be caused to generate voltage floating to generate carriers, thereby forming a current channel, so that the switch of the thin film transistor 100 and the degree of opening can be controlled.

[0049] The active layer 120 includes a first film layer 121 and a second film layer 122 stacked together. The first film layer 121 is formed of a semiconductor material with high mobility, and the second film layer 122 is formed of a semiconductor material with low mobility, so that the surface of the first film layer 121 in contact with the second film layer 122 serves as the main channel for the two-dimensional electron gas (carriers). The etching rate of the second film layer 121 is lower than the etching rate of the first film layer 121, and the etching rate of the second film layer 121 will be lower than the first film layer 121. During the film formation process, the surface of the second film layer 122 with a low etching rate has a high degree of flatness, which can improve the surface defects of the first film layer 121 to ensure the electrical properties and stability of the active layer. In addition, the second film layer 122 with a low etching rate has a better ion blocking effect, thereby protecting the first film layer 121.

[0050] It should be noted that in the embodiments of the present disclosure, when the atoms, molecules or lattice structures in the film layer are densely arranged, the film layer has a strong ability to resist etching and a low etching rate. Accordingly, the film layer has fewer surface defects and thus has higher barrier properties.

[0051] For example, Figure 1As shown, the thin film transistor 100 may further include an electrode 141 and a drain electrode 142, and the source electrode 141 and the drain electrode 142 are connected to the active layer 120. The active layer 120 may be divided into a channel region, a source region, and a drain region, the channel region is located between the source region and the drain region, and the channel region corresponds to the first gate electrode 131, that is, the orthographic projection of the channel region on the substrate is located within the orthographic projection of the first gate electrode 131 on the substrate, or the orthographic projection of the channel region on the substrate coincides with the orthographic projection of the first gate electrode 131 on the substrate. The source region and the drain region may be located at both ends of the active layer 120, the source region is used to connect to the source electrode 141 (electrically connected, such as ohmic contact), and the drain region is used to connect to the drain electrode 142 (electrically connected, such as ohmic contact). For example, after a voltage is applied to the first gate electrode 131 , the channel is opened (depending on the material of the active layer, the channel state is opposite in this case, possibly from open to closed), and the current (electrical signal) on the source electrode 141 is conducted to the drain electrode 142 through the active layer 120 .

[0052] For example, in at least one embodiment of the present disclosure, Figure 1 As shown, the thin film transistor 100 may further include a first gate insulating layer 151 and an interlayer dielectric layer 160 to define various structures in the thin film transistor 100. For example, the first gate insulating layer 151 is located between the first gate electrode 131 and the active layer 120 to separate the first gate electrode 131 and the active layer 120, and the interlayer dielectric layer 160 is located between the source-drain electrode layer (including the source electrode 141 and the drain electrode 142) and the active layer 120 to separate the source-drain electrode layer and the active layer 120.

[0053] For example, in at least one embodiment of the present disclosure, Figure 1 As shown, the thin film transistor 100 may further include a buffer layer 170 located between the substrate 110 and the active layer 120 . The buffer layer 170 may block harmful ions intruding from the substrate 110 into the active layer 120 .

[0054] It should be noted that in the embodiments of the present disclosure, as long as the etching rate of the second film layer is lower than the etching rate of the first film layer and the mobility of the second film layer is higher than the mobility of the first film layer, the specific preparation process and specific materials of the first film layer and the second film layer are not limited. Below, the preparation process of the first film layer and the second film layer and different selections of specific materials and the structure of the thin film transistor under the corresponding selections are exemplified.

[0055] In some embodiments of the present disclosure, the first film layer and the second film layer are composed of semiconductor film layers formed by physical vapor deposition, and the power of physical vapor deposition corresponding to the semiconductor film layer used to form the first film layer is greater than the power of physical vapor deposition corresponding to the semiconductor film layer used to form the second film layer, so that the etching rate of the second film layer is less than the etching rate of the first film layer. The film formation rate of the film layer formed by physical vapor deposition under low power is low, so that the film layer can have a higher etching rate. Therefore, by controlling the power of physical vapor deposition, the difference in etching rate between the first film layer and the second film layer can be controlled. For example, the power of physical vapor deposition to form the first semiconductor material film layer can be 4KW~6KW, and the power of physical vapor deposition to form the second semiconductor material film layer can be 2KW~4KW.

[0056] In other embodiments of the present disclosure, the first film layer is composed of a semiconductor film layer deposited by physical vapor deposition, and the second film layer is composed of a semiconductor film layer deposited by atomic layer deposition, so that the etching rate of the second film layer is less than the etching rate of the first film layer. For example, the rate of forming the first film layer by physical vapor deposition is 80 angstroms / second to 120 angstroms / second, and the rate of forming the second film layer by atomic layer deposition is 20 angstroms / second to 60 angstroms / second.

[0057] Atomic layer deposition (ALD) is a surface deposition technology that can prepare high-quality nanomaterials by depositing atomically thick films layer by layer on the surface of the material. The technical advantages of ALD include: high-precision control; control of the thickness and composition of each layer, thereby accurately controlling the thickness and properties of the film; forming a uniform film on the surface of the structure, thereby improving the quality and stability of the film; and being carried out at low temperatures, reducing the generation of impurities, thereby improving the purity of the film. Therefore, the film layer formed by ALD has good uniformity, a uniform film surface, and a low risk of surface defects.

[0058] For example, the etching rate of the first film layer is not less than 20 angstroms / second, and the etching rate of the second film layer may be not more than 10 angstroms / second. It should be noted that the actual etching rates of the first film layer and the second film layer can be designed according to specific process requirements and are not limited to the above numerical range.

[0059] For example, in the embodiment of the present disclosure, when the first film layer has high mobility and low etching rate, the material of the first film layer is not limited and can be determined according to actual process requirements. For example, the material of the first film layer includes at least two of In, Ga, Zn, and Sn. For example, optionally, the material of the first film layer is one of IGZO, IGZTO, IZO, and IGO. For example, further, the mobility of the first film layer is not less than 20 cm 2 / Vs.

[0060] For example, in the embodiment of the present disclosure, when the second film layer has low mobility and high etching rate, the material of the second film layer is not limited and can be determined according to actual process requirements. For example, the material of the second film layer includes at least one of In, Ga, and Zn. For example, optionally, the material of the second film layer is IGZO. For example, further, the mobility of the second film layer is not greater than 15 cm 2 / Vs.

[0061] For example, Figure 1 As shown, the first film layer 121 and the second film layer 122 are in contact with each other, and the first film layer 121 and the second film layer 122 can be prepared under the same composition process to reduce the preparation process flow of the active layer 120. In this case, the patterns of the first film layer 121 and the second film layer 122 roughly overlap, that is, the orthographic projection of the first film layer 121 on the substrate 110 overlaps with the orthographic projection of the second film layer 122 on the substrate 110.

[0062] For example, the first film layer 121 and the second film layer 122 may be made of the same material to ensure that the second film layer 122 can better protect the first film layer 121 in different etching environments (or environments invaded or corroded by the same substance).

[0063] It should be noted that in the embodiments of the present disclosure, when the first film layer is a semiconductor layer and the thin film transistor includes only one gate electrode (first gate electrode), the thin film transistor can be set as a top-gate thin film transistor, or it can be set as a bottom-gate thin film transistor, as follows.

[0064] For example, in some embodiments of the present disclosure, Figure 1 As shown, when the first film layer 121 is a semiconductor layer, the first film layer 121 is located between the second film layer 122 and the substrate 110, that is, the thin film transistor 100 is a top-gate thin film transistor.

[0065] It should be noted that both ends of the first film layer need to be doped (for example, heavily doped) for conductorization, so as to ensure the electrical connection between the active layer and the source electrode and the drain electrode. When the thin film transistor is a top-gate thin film transistor, the design thickness of the second film layer can be reduced to ensure that the setting of the second film layer does not have an adverse effect on the doping of the first film layer. For example, the thickness of the second film layer is less than the thickness of the second film layer.

[0066] For example, the thickness of the first film layer is 50 to 500 angstroms, such as 100 angstroms, 200 angstroms, 300 angstroms, 400 angstroms, etc., and / or the thickness of the second film layer is 10 to 100 angstroms, such as 20 angstroms, 40 angstroms, 60 angstroms, 80 angstroms, etc.

[0067] For example, in some other embodiments of the present disclosure, Figure 2 As shown, when the first film layer 121 is a semiconductor layer, the second film layer 122 is located between the first film layer 121 and the substrate 110, that is, the thin film transistor 100 is a bottom-gate thin film transistor.

[0068] For example, Figure 2 As shown, in the case where the thin film transistor 100 is a bottom-gate thin film transistor, the positive projection of the active layer 120 on the substrate 110 is located within the positive projection of the first gate electrode 131 on the substrate 110. In this way, the setting of the first gate electrode 131 can avoid adverse effects on the flatness of the active layer 120; in addition, the first gate electrode 131 can block the light passing through one side of the substrate 110 to reduce the problem of photogenerated carriers in the active layer 120; in addition, the first gate electrode 131 can block harmful ions invading from the substrate 110 to the active layer 120.

[0069] In at least one embodiment of the present disclosure, Figure 3 As shown, the active layer 120 may further include a third film layer 123, which is located on the side of the first film layer 121 away from the first gate electrode 131, and the third film layer 123 is a semiconductor material. The mobility of the third film layer 123 is lower than that of the first film layer 121, and the etching rate of the third film layer 123 is lower than that of the first film layer 121. In this way, the third film layer 123 and the second film layer 122 can protect the first film layer 121 from both sides to prevent harmful ions in other dielectric layers (such as the gate insulating layer) from invading the first film layer 121.

[0070] It should be noted that the mobility of the third film layer is lower than that of the first film layer, and therefore, the first film layer is still used to form the channel.

[0071] In some embodiments of the present disclosure, the first film layer and the third film layer are composed of semiconductor film layers formed by physical vapor deposition, and the power of physical vapor deposition corresponding to the semiconductor film layer used to form the first film layer is greater than the power of physical vapor deposition corresponding to the semiconductor film layer used to form the third film layer, so that the etching rate of the third film layer is lower than the etching rate of the first film layer. The film formation rate of the film layer formed by physical vapor deposition under low power is low, so that the film layer can have a higher etching rate. Therefore, by controlling the power of physical vapor deposition, the difference in etching rates between the first film layer and the third film layer can be controlled.

[0072] In other embodiments of the present disclosure, the first film layer is composed of a semiconductor film layer deposited by physical vapor deposition, and the third film layer is composed of a semiconductor film layer deposited by atomic layer deposition, so that the etching rate of the third film layer is lower than the etching rate of the first film layer.

[0073] For example, the etching rate of the third film layer may be less than 10 angstroms / second.

[0074] For example, in the embodiment of the present disclosure, when the third film layer has low mobility and high etching rate, the material of the third film layer is not limited and can be determined according to actual process requirements. For example, the material of the third film layer includes at least one of In, Ga, and Zn. For example, optionally, the material of the third film layer is IGZO. For example, further, the mobility of the third film layer is not greater than 15 cm 2 / Vs.

[0075] For example, in some embodiments of the present disclosure, Figure 3 As shown, the third film layer 123 and the first film layer 121 can be prepared under the same patterning process to reduce the preparation process flow of the active layer 120. In this case, the orthographic projection of the third film layer 123 on the substrate 110 coincides with the orthographic projection of the first film layer 121 on the substrate 110. For example, further, the orthographic projections of the first film layer 121, the second film layer 122, and the third film layer 123 on the substrate 110 coincide, that is, the first film layer 121, the second film layer 122, and the third film layer 123 are formed under the same patterning process, so that the first film layer 121 can be prevented from contacting with other materials (such as photoresist) and being contaminated (such as ion invasion).

[0076] In at least one embodiment of the present disclosure, Figure 4 As shown, the thin film transistor 100 can be designed as a dual-gate thin film transistor to improve the response speed of the thin film transistor. For example, the thin film transistor 100 can include a second gate electrode 132 , and the second gate electrode 132 is located on a side of the active layer 120 away from the first gate electrode 131 .

[0077] It should be noted that, for the first gate electrode and the second gate electrode, the area of ​​one side located between the active layer and the substrate should be larger than the area of ​​the active layer to shield the active layer and ensure the flatness of the active layer. Figure 4 As shown, the second gate electrode 132 is located between the active layer 120 and the substrate 110 , and the orthographic projection of the active layer 120 on the substrate 110 is located within the orthographic projection of the second gate electrode 132 on the substrate 110 .

[0078] For example, Figure 4 As shown, in the case where the second gate electrode 132 is provided, the thin film transistor 100 may further include a second gate insulating layer 152 located between the active layer 120 and the second gate electrode 132 .

[0079] At least one embodiment of the present disclosure provides an array substrate, such as Figure 5As shown, the array substrate may include a driving circuit layer 10, the driving circuit layer includes a plurality of pixel driving circuits, each pixel driving circuit includes a plurality of thin film transistors 100, and at least one thin film transistor is the thin film transistor in the above embodiment.

[0080] For example, the pixel driving circuit may include a plurality of transistors TFT (thin film transistor), capacitors, etc., for example, in various forms such as 2T1C (i.e., 2 transistors (TFT) and 1 capacitor (C)), 3T1C or 7T1C. The pixel driving circuit is connected to a light emitting device (see the light emitting device 200 in the following embodiment) to control the switching state and light emitting brightness of the light emitting device.

[0081] For example, in at least one embodiment of the present disclosure, Figure 5 As shown, the array substrate may further include a planar layer 180 and an anode 210 located on the planar layer 180, wherein a via is provided in the planar layer 180, a pixel driving circuit is provided corresponding to the anode 210, and a source electrode or a drain electrode of a thin film transistor in the pixel driving circuit is connected to the corresponding anode 210 through the via.

[0082] At least one embodiment of the present disclosure provides a display panel such as Figure 6 and Figure 7 As shown, the display panel includes a display function layer 20 and the array substrate 10 in the above embodiment. The display panel can be divided into a display area 1 and a frame area 2 located on at least one side of the display area, and a plurality of sub-pixels R, G, and B are arranged in the display area 1. The display function layer 20 is located on the array substrate 10 and includes a plurality of light-emitting devices 200, and the light-emitting devices 200 are physical light-emitting structures of sub-pixels R, G, and B. For example, the light-emitting devices 200 respectively located in the sub-pixels R, G, and B are respectively designed to emit red light (R), green light (G), and blue light (B). For example, the light-emitting devices 200 are connected to the pixel driving circuit in the array substrate 100.

[0083] The light emitting device 200 may include an anode 210, a light emitting functional layer 230, and a cathode 220 sequentially stacked on an array substrate, and the light emitting functional layer 230 may include a first common layer 231, a light emitting layer 232, and a second common layer 233 sequentially stacked on the anode 210. For example, the first common layer 231 may include a hole injection layer, a hole transport layer, and may further include an electron blocking layer, etc. For example, the second common layer 233 may include an electron injection layer, an electron transport layer, and may further include a hole blocking layer, etc.

[0084] For example, Figure 7As shown, the display panel may further include a pixel defining layer 300 , wherein the pixel defining layer 300 includes a plurality of openings to define the positions of the light emitting devices, for example, the light emitting layer of each light emitting device 200 is located in the opening.

[0085] For example, Figure 7 As shown, the display panel may further include an encapsulation layer 30 to cover the display function layer 20 to protect the light emitting device 200. For example, the encapsulation layer 30 may include a first inorganic encapsulation layer 31, an organic encapsulation layer 32, and a second inorganic encapsulation layer 33 sequentially stacked on the display function layer 20.

[0086] For example, in an embodiment of the present disclosure, the display panel may further include functional structures such as a touch function layer, a polarizer, a lens layer, and a cover plate located on the display side (eg, on the encapsulation layer).

[0087] For example, in the embodiments of the present disclosure, the display panel may be any product or component having a display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, a navigator, or the like.

[0088] At least one embodiment of the present disclosure provides a method for preparing a thin film transistor as mentioned in the above embodiments, such as Figure 8 As shown, the preparation method may include the following steps S100 to S300.

[0089] S100, providing a substrate; depositing a first semiconductor material film layer having a first mobility on the substrate at a first film forming rate, and depositing a second semiconductor material film layer having a second mobility at a second film forming rate, wherein the first mobility is greater than the second mobility, and the first film forming rate is greater than the second film forming rate, so that an etching rate of the second semiconductor material film layer is less than an etching rate of the first semiconductor material film layer.

[0090] S200 , patterning the first semiconductor material film layer and the second semiconductor material film layer to form a first film layer and a second film layer respectively.

[0091] S300, depositing a first conductive material film on a substrate, and patterning the first conductive material film to form a first gate electrode, wherein a second film layer is formed between the first film layer and the first gate electrode.

[0092] In this preparation method, the first film layer has a relatively high mobility. Therefore, when the thin film transistor is working, the carriers will gather on the surface of the first film layer facing the first gate electrode, and the second film layer with a low etching rate can improve the surface to avoid surface defects, thereby improving the performance of the thin film transistor.

[0093] For example, in some embodiments of the present disclosure, the above-mentioned step S100 may include: forming a first semiconductor material film layer and a second semiconductor material film layer respectively by physical vapor deposition, wherein the power of the physical vapor deposition for forming the first semiconductor material film layer is greater than the power of the physical vapor deposition for forming the second semiconductor material film layer, so that the first film formation rate is greater than the second film formation rate, and the etching rate of the second film layer is less than the etching rate of the first film layer. Under this design, the specific materials of the first film layer and the second film layer and the formation environment can refer to the relevant description in the above-mentioned embodiments, and will not be repeated here.

[0094] For example, in some other embodiments of the present disclosure, the above step S100 may include: forming a first semiconductor material film layer by physical vapor deposition, and forming a second semiconductor material film layer by atomic layer deposition, so that the first film formation rate is greater than the second film formation rate, and the etching rate of the second film layer is less than the etching rate of the first film layer. Under this design, the specific materials of the first film layer and the second film layer and the formation environment can refer to the relevant description in the above embodiments, and will not be repeated here.

[0095] For example, in at least one embodiment of the present disclosure, the preparation method may further include: depositing an insulating material between the first gate electrode and the active layer to form a first gate insulating layer, wherein the first gate insulating layer separates the first gate electrode and the active layer. The positional relationship between the first gate insulating layer, the first gate electrode, and the active layer formed in this manner can be referred to the relevant description in the aforementioned embodiment, and will not be described in detail here.

[0096] For example, the preparation method further includes: depositing a conductive material film layer on the side of the active layer away from the substrate, and patterning the conductive material film layer to form a source electrode and a drain electrode, wherein the source electrode and the drain electrode are respectively connected to two ends of the active layer. The positional relationship between the source electrode, the drain electrode, the first gate electrode, and the active layer formed in this manner can be referred to the relevant description in the aforementioned embodiment, and will not be described in detail here.

[0097] For example, in at least one embodiment of the present disclosure, the preparation method may further include: depositing a third semiconductor material film layer having a third mobility at a third rate, wherein the first mobility is greater than the third mobility, and the first film forming rate is greater than the third rate, so that the etching rate of the third semiconductor material film layer is less than the etching rate of the first semiconductor material film layer; and patterning the third semiconductor material film layer to form a third film layer. Under this design, the specific material and formation environment of the third film layer can refer to the relevant description in the aforementioned embodiment, and will not be repeated here.

[0098] In the preparation method provided by at least one embodiment of the present disclosure, the second mobility is equal to the third mobility. For example, the second film forming rate is equal to the third rate, so that the etching rates of the first film layer and the third film layer are equal. The mobility and etching rate of the second film layer and the third film layer are equal, for example, the materials of the second film layer and the third film layer can also be the same, so as to reduce the preparation cost of the thin film transistor.

[0099] In at least one embodiment of the present disclosure, the preparation method may further include: after depositing the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer, the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer are simultaneously patterned to form the first film layer, the second film layer and the third film layer, and the orthographic projection of the first film layer on the substrate, the orthographic projection of the second film layer on the substrate and the orthographic projection of the third film layer on the substrate are overlapped. In this way, the preparation process cost of the active layer can be simplified. In addition, the second semiconductor material layer and the third semiconductor material layer can protect the first semiconductor material layer, thereby reducing the risk of contamination of the active layer, especially the first film layer therein, during the preparation process.

[0100] In at least one embodiment of the present disclosure, the preparation method may further include: depositing a second conductive material film on the substrate, and patterning the second conductive material film to form a second gate electrode, wherein the second gate electrode is formed on a side of the active layer away from the first gate electrode. Regarding the structure of the thin film transistor formed as a dual-gate thin film transistor, please refer to the relevant description in the aforementioned embodiment, which will not be repeated here. In addition, based on the different choices of whether the first gate electrode is located above or below the active layer, the preparation method of the second gate electrode can have different choices, as follows.

[0101] For example, in some embodiments of the present disclosure, a first gate electrode is formed on a side of the active layer facing away from the substrate, and the preparation method further includes: before forming the active layer and the first gate electrode, depositing a second conductive material film on the substrate, and composing the second conductive material film to form a second gate electrode.

[0102] For example, in some other embodiments of the present disclosure, the preparation method may further include: before forming the active layer and the first gate electrode and after forming the second gate electrode, depositing an insulating material on the substrate to form a second gate insulating layer to cover the second gate electrode.

[0103] In at least one embodiment of the present disclosure, the preparation method may further include: after forming the active layer and the first gate electrode and before forming the second gate electrode, depositing an insulating material on the substrate to form a second gate insulating layer. The positional relationship between the second gate insulating layer formed in this manner and other structures in the thin film transistor can be referred to the relevant description in the aforementioned embodiment, and will not be repeated here.

[0104] Next, prepare Figure 4 Taking the thin film transistor shown in FIG. 1 as an example, the process of the method for preparing the thin film transistor in at least one embodiment of the present disclosure is described. For details, refer to the following Figures 9 to 13 The process steps are shown.

[0105] like Fig. 9 As shown, a substrate 110 is provided and an insulating material film layer and a conductive material film (the second conductive material film mentioned above) are sequentially deposited on the substrate 110 , and the insulating material film layer forms a buffer layer 170 ; the conductive material film is patterned to form a second gate electrode 132 .

[0106] In an embodiment of the present disclosure, the patterning process may be a photolithography patterning process, which may include, for example, coating a photoresist on a structure layer to be patterned, exposing the photoresist using a mask, developing the exposed photoresist to obtain a photoresist pattern, etching the structure layer using the photoresist pattern (optionally wet etching or dry etching), and then optionally removing the photoresist pattern. It should be noted that, in the case where the material of the structure layer includes a photoresist, the structure layer may be directly exposed through a mask to form a desired pattern.

[0107] like Figures 9 and 10 As shown, an insulating material film layer is deposited on the substrate 110 formed with the second gate electrode 132 to form a second gate insulating layer 152; then a third semiconductor material film layer 123a, a first semiconductor material film layer 121a, and a second semiconductor material film layer 122a are sequentially deposited on the second gate insulating layer 152. The second semiconductor material film layer 122a and the third semiconductor material film layer 123a can be formed by atomic layer deposition, and the etching rate thereof can be less than 10 angstroms / second, and the thickness thereof can be 10 to 100 angstroms; the first semiconductor material film layer 121a can be formed by physical vapor deposition, and the etching rate thereof can be not less than 20 angstroms / second, and the thickness thereof can be 50 to 500 angstroms.

[0108] like Figure 10 to Figure 11 As shown, the first semiconductor material film layer 121a, the second semiconductor material film layer 122a and the third semiconductor material film layer 123a are subjected to a composition process to form a first film layer 121, a second film layer 122 and a third film layer 123 respectively. The first film layer 121, the second film layer 122 and the third film layer 123 stacked together constitute an active layer 120.

[0109] For example, in Fig.11 In the steps shown, the two ends of the first film layer 121 (the source region and the drain region respectively connected to the source electrode and the drain electrode) can be doped through the second film layer 122 to make the two ends of the first film layer 121 conductive.

[0110] It should be noted that, in some embodiments of the present disclosure, a gate electrode (for example, the gate electrode described below) may be formed on the side of the active layer facing away from the substrate. Fig.12 After forming the first gate electrode 131 as shown, the active layer is doped using the gate electrode as a mask.

[0111] like Figure 11 to Figure 12 As shown, an insulating material is deposited on the active layer 120 to form a first gate insulating layer 151 ; then a conductive material film (the first conductive material film mentioned above) is deposited on the first gate insulating layer 151 , and a patterning process is performed on the conductive material film to form a first gate electrode 131 .

[0112] like Figure 12 to Figure 13 As shown, an insulating material film layer is deposited on the substrate 110 formed with the first gate electrode 131 to form an interlayer dielectric layer 160 .

[0113] like Fig.13 and Figure 4 As shown, the interlayer dielectric layer 160 is patterned to form vias; a conductive material film is deposited on the interlayer dielectric layer 160, and the conductive material film is patterned to form a source electrode 141 and a drain electrode 142, and the source electrode 141 and the drain electrode 142 are connected to the active layer 120 through the vias in the interlayer dielectric layer 160.

[0114] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, etc. made within the spirit and principles of this specification should be included in the protection scope of this specification.

Claims

1. A thin film transistor, characterized in that: A method for manufacturing a semiconductor device comprising a substrate and an active layer and a first gate electrode located on the substrate, wherein the active layer comprises a first film layer and a second film layer stacked on the substrate, and the second film layer is located between the first film layer and the first gate electrode, and The first film layer and the second film layer are semiconductor film layers, the mobility of the second film layer is lower than the mobility of the first film layer, and the etching rate of the second film layer is lower than the etching rate of the first film layer.

2. The thin film transistor according to claim 1, characterized in that: The material of the first film layer includes at least two of In, Ga, Zn, and Sn. Preferably, the material of the first film layer is one of IGZO, IGZTO, IZO, and IGO. Further preferably, the mobility of the first film layer is not less than 20 cm 2 / Vs; and / or The material of the second film layer includes at least one of In, Ga, and Zn. Preferably, the material of the second film layer is IGZO. Further preferably, the mobility of the second film layer is not greater than 15 cm 2 / Vs; Preferably, the etching rate of the first film layer is not less than 20 angstroms / second, and the etching rate of the second film layer is not more than 10 angstroms / second; Preferably, the first film layer and the second film layer are made of the same material.

3. The thin film transistor according to claim 1, characterized in that: The orthographic projection of the first film layer on the substrate coincides with the orthographic projection of the second film layer on the substrate; Preferably, the first film layer is in direct contact with the second film layer.

4. The thin film transistor according to any one of claims 1 to 3, characterized in that: The active layer is located between the first gate electrode and the substrate. Preferably, the thickness of the second film layer is less than that of the first film layer. Further preferably, the thickness of the first film layer is 50 to 500 angstroms, and / or the thickness of the second film layer is 10 to 100 angstroms; or The first gate electrode is located between the active layer and the substrate. Preferably, the orthographic projection of the active layer on the substrate is located within the orthographic projection of the first gate electrode on the substrate.

5. The thin film transistor according to any one of claims 1 to 3, characterized in that: Also includes: a first gate insulating layer, located between the first gate electrode and the active layer; Preferably, the thin film transistor may further include a source electrode and a drain electrode, wherein the source electrode and the drain electrode are located on a side of the active layer away from the substrate, and two ends of the active layer are connected to the source electrode and the drain electrode respectively.

6. The thin film transistor according to any one of claims 1 to 3, characterized in that: The active layer further comprises: A third film layer, located on a side of the first film layer away from the first gate electrode, the third film layer comprising a semiconductor material; Wherein, the mobility of the third film layer is lower than the mobility of the first film layer, and the etching rate of the third film layer is lower than the etching rate of the first film layer; Preferably, the first film layer is in direct contact with the third film layer; Preferably, the material of the third film layer includes at least one of In, Ga, and Zn; further preferably, the material of the third film layer is IGZO; further preferably, the mobility of the third film layer is not greater than 15 cm 2 / Vs; Preferably, the etching rate of the third film layer is less than 10 angstroms / second; Preferably, the orthographic projection of the first film layer on the substrate coincides with the orthographic projection of the third film layer on the substrate.

7. The thin film transistor according to claim 6, characterized in that: Also comprising a second gate electrode, wherein the second gate electrode is located on a side of the active layer away from the first gate electrode; Preferably, the thin film transistor further includes a second gate insulating layer, and the second gate insulating layer is located between the second gate electrode and the active layer.

8. A display panel, characterized in that: The invention comprises the thin film transistor according to any one of claims 1 to 7.

9. A method for preparing a thin film transistor, characterized in that: include: providing a substrate; Depositing a first semiconductor material film layer having a first mobility on the substrate at a first film-forming rate, and depositing a second semiconductor material film layer having a second mobility at a second film-forming rate, wherein the first mobility is greater than the second mobility, and the first film-forming rate is greater than the second film-forming rate, so that an etching rate of the second semiconductor material film layer is less than an etching rate of the first semiconductor material film layer; performing patterning on the first semiconductor material film layer and the second semiconductor material film layer to form a first film layer and a second film layer respectively; and A first conductive material film is deposited on the substrate, and the first conductive material film is patterned to form a first gate electrode, wherein the second film layer is formed between the first film layer and the first gate electrode.

10. The preparation method according to claim 9, characterized in that: The method of depositing a first semiconductor material film layer having a first mobility on the substrate at a first film forming rate, and depositing a second semiconductor material film layer having a second mobility at a second film forming rate, comprises: The first semiconductor material film layer and the second semiconductor material film layer are formed respectively by physical vapor deposition, wherein the power of the physical vapor deposition for forming the first semiconductor material film layer is greater than the power of the physical vapor deposition for forming the second semiconductor material film layer, so that the first film forming rate is greater than the second film forming rate, and the etching rate of the second film layer is less than the etching rate of the first film layer, preferably, the power of the physical vapor deposition for forming the first semiconductor material film layer is 4KW to 6KW, and the power of the physical vapor deposition for forming the second semiconductor material film layer is 2KW to 4KW; or The first semiconductor material film layer is formed by physical vapor deposition, and the second semiconductor material film layer is formed by atomic layer deposition, so that the first film formation rate is greater than the second film formation rate, and the etching rate of the second film layer is less than the etching rate of the first film layer, preferably, the first film formation rate is 80 angstroms / second to 120 angstroms / second, and the second film formation rate is 20 angstroms / second to 60 angstroms / second; Preferably, the material of the first film layer includes at least two of In, Ga, Zn, and Sn. Further preferably, the material of the first film layer is one of IGZO, IGZTO, IZO, and IGO. Further preferably, the mobility of the first film layer is not less than 20 cm 2 / Vs; and / or, the material of the second film layer includes at least one of In, Ga, and Zn. Further preferably, the material of the second film layer is IGZO. Further preferably, the mobility of the second film layer is not greater than 15cm 2 / Vs; Preferably, the etching rate of the first film layer is not less than 20 angstroms / second, and the etching rate of the second film layer is not more than 10 angstroms / second.

11. The preparation method according to claim 9 or 10, characterized in that: Also includes: depositing an insulating material between the first gate electrode and the active layer to form a first gate insulating layer; Preferably, the preparation method further includes: depositing a conductive material film layer on a side of the active layer away from the substrate, and patterning the conductive material film layer to form a source electrode and a drain electrode, wherein the source electrode and the drain electrode are respectively connected to two ends of the active layer.

12. The preparation method according to claim 9 or 10, characterized in that: Also includes: Depositing a third semiconductor material film layer having a third mobility at a third rate, wherein the first mobility is greater than the third mobility, and the first film formation rate is greater than the third rate, so that an etching rate of the third semiconductor material film layer is less than an etching rate of the first semiconductor material film layer; as well as Performing patterning on the third semiconductor material film layer to form a third film layer; Preferably, the second mobility is equal to the third mobility; Preferably, the second film forming rate is equal to the third rate, so that the etching rates of the second film layer and the third film layer are equal; Preferably, the material of the third film layer includes at least one of In, Ga, and Zn; further preferably, the material of the third film layer is IGZO; further preferably, the mobility of the third film layer is not greater than 15 cm 2 / Vs; Preferably, the etching rate of the third film layer is less than 10 angstroms / second; Preferably, after depositing the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer, the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer are simultaneously subjected to a patterning process to form the first film layer, the second film layer and the third film layer, and the orthographic projection of the first film layer on the substrate, the orthographic projection of the second film layer on the substrate and the orthographic projection of the third film layer on the substrate coincide with each other.

13. The preparation method according to claim 12, characterized in that: The first gate electrode is formed on a side of the active layer away from the substrate, and the preparation method further includes: before forming the active layer and the first gate electrode, depositing a second conductive material film on the substrate, and patterning the second conductive material film to form a second gate electrode. Preferably, the preparation method further includes: before forming the active layer and the first gate electrode and after forming the second gate electrode, depositing an insulating material on the substrate to form a second gate insulating layer to cover the second gate electrode; or The first gate electrode is formed between the active layer and the substrate, and the preparation method further includes: after forming the first gate electrode and the active layer on the substrate, depositing a second conductive material film on the substrate, and composing the second conductive material film to form a second gate electrode, wherein the second gate electrode is formed on a side of the active layer away from the first gate electrode. Preferably, the preparation method further includes: after forming the active layer and the first gate electrode and before forming the second gate electrode, depositing an insulating material on the substrate to form a second gate insulating layer.

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