Memory array integrated circuit based on multilayer magnetoelectric effect induction memristor

Abstract

The invention provides a high-performance memristor memory device structure. The structure is only composed of four layers of film materials, and the preparation process is very simple. The first layer of substrate film is Pt, and the second layer of substrate film is a NiO film. The third layer is a thin layer jointly formed by Co and NiO, the NiO part is square, the NiO thin film has two resistance change principles of an overall effect and a local effect and has strong resistance change and memorability, the Co part is a square ring with the same center as the NiO, Co has a GMR effect, and when a magnetic field changing in a certain direction appears around the memristor, the resistance change of the memristor is changed, and the resistance change of the memristor is changed. And the resistance value of the Co layer is changed accordingly, so that the overall electrical state of the memristor is changed. And the fourth layer of film is composed of a Cu top electrode. The structure can be controlled by an electric field and a magnetic field to generate four storage states, and has the characteristic of integrating storage and calculation.

Description

Technical Field

[0001] The present invention belongs to the field of storage-computation integrated memory, and in particular relates to a memory array integrated circuit composed of a unique non-volatile memory device based on a memristor. Background Art

[0002] With the continuous development of chip integration density technology, the famous Moore's Law has encountered unprecedented challenges. As the sub-size of semiconductor electronic components has been decreasing, the process size is gradually approaching the theoretical limit, the operation of electronics is difficult to control, the complexity increases and the reliability decreases, and the increase in process difficulty will make the investment cost high. At the same time, the number of components per unit area of ​​the integrated chip will reach the upper limit, at which time the physical and chemical properties of the material will change, and the semiconductor components using existing technology will not work properly. Microelectronics processes, ion implantation processes, optical lithography and other technologies will approach the physical limit and will not allow the component size to be further reduced. At the same time, with the continuous reduction of transistor size and the continuous increase of integration density, the number of transistors per unit area is also increasing, and power consumption is also increasing. The design cost and maintenance cost of processors and peripheral circuits will also increase. Existing data storage technology can be divided into volatile storage and non-volatile storage by distinguishing the storage capacity of data in the case of power failure. Non-volatile memory (NVM) has always been an important feature and key performance in data storage. Therefore, NVM technology needs to select components based on whether the device has data retention capabilities. Flash Memory (FM) is the most basic NVM technology. This technology is very mature and well optimized, and has now been put into large-scale commercial applications. Flash memory is based on a single transistor unit that connects the storage module and the selection module together. In recent years, NAND flash memory technology has developed rapidly and has surpassed dynamic random access memory technology (DRAM) in terms of storage density. Judging from the current development trend, NAND flash memory technology is still the mainstream development direction of high-density storage, but in the long run, its development will inevitably be affected by factors such as integration ratio, fault voltage between similar array lines and the size of logic circuits, and will encounter bottlenecks. As a type of non-volatile memory that is currently widely used, the size of Flash memory will soon reach its limit of reduction. Therefore, the industry urgently needs to adopt new processes or use new materials to develop new memories with better performance to meet the requirements of large capacity, high speed and low power consumption for massive information processing. Memristors are non-volatile, low-power, and compatible with CMOS processes, and have great potential for application in non-volatile memory, large-scale integrated circuits, artificial neural networks, pattern recognition, and image processing. Memristor-based non-volatile storage circuits have become a research hotspot for the next generation of non-volatile storage technology due to their fast storage speed (<10ns), high storage density, low energy consumption, high durability (up to 1015 write times), and high reliability. Summary of the invention

[0003] Since the development of memory structure in the background technology is still in its infancy, there are still various drawbacks. It usually only has electrical induction and can only sense voltage and current changes to change the storage state. This characteristic limits its application in many fields. The present invention proposes a high-performance memristor memory device structure. The structure is composed of only four layers of thin film materials, and the preparation process is very simple. The first layer of substrate film is Pt, and the second layer is NiO film. The third layer is a thin layer composed of Co and NiO, in which the NiO part is a square. The NiO film has two resistive switching principles of overall effect and local effect, and has strong resistive switching and memory. The Co part is a square ring with the same center as NiO. Co has a GMR effect. When a magnetic field with a certain direction change appears around this memristor, the resistance of the Co layer will change accordingly, thereby causing the overall electrical state of the memristor to change. The fourth layer of film is composed of Cu top electrode. This structure can be controlled by electric and magnetic fields, and has the characteristics of storage and calculation integration.

[0004] In order to achieve the above object, the technical solution of the present invention is as follows:

[0005] The key to the preparation of this memristor is that the preparation of the NiO film and the top electrode requires a certain pattern, which requires a photolithography step. When preparing the NiO film, a magnetron sputtering device is required. When using the device, O2 and Ar are mixed in a certain proportion and introduced into the vacuum chamber and the flow rate is kept constant to keep the vacuum degree of the vacuum chamber in dynamic balance. Then, the high-purity Ni metal target is directly sputtered by the reactive DC sputtering method, and NiO is generated by the reaction of Ni atoms with oxygen during the deposition process. Usually, the ratio of O2 to Ar flow used in the study is about 10%. When studying the performance of different devices, the gas composition will be adjusted accordingly. This method is used to directly prepare the NiO layer on the Pt / Ti / SiO2 / Si substrate with a Pt electrode. As for the preparation of Co, it only needs to be photolithographically processed once more on the current graphics, and then magnetron sputtering can be performed directly in an Ar environment. At the same time, it should be noted that after magnetron sputtering of Pt and Co, further annealing is required. Generally, the annealing process has three main functions: lattice recovery by moving internal defects in the crystal, while reducing residual stress; new grains are generated through grain recombination, changing the crystallization state; and grain growth increases the grain size and reduces grain boundaries, thereby improving the performance of the material. After the preparation of the first three layers of film is completed, further preparation of the top electrode should be carried out. Since the preparation of the top electrode is relatively complicated, the following steps will be listed separately, as shown below:

[0006] Step 1: Preparation of substrate. Before applying photoresist, it is necessary to evaporate the moisture on the substrate surface by baking, which is conducive to the application of photoresist. In this paper, the deposited NiO and Co films are used as substrates, and photolithography is performed on their surfaces.

[0007] Step 2, coating of photoresist. Before photolithography, the photoresist needs to be evenly and evenly distributed on the substrate surface. First, the substrate is adsorbed on the tray and photoresist is dripped on the substrate. By rotating it, it moves toward the periphery of the substrate under the action of centrifugal force and covers the entire substrate surface. Therefore, coating can also be called spinning. The thickness of the photoresist is different at different rotation speeds. Here, Yiban1 uses a speed of 1000 rpm for 5 seconds, and then 3000 rpm for 30 seconds.

[0008] Step 3, soft baking. After the photoresist is evenly distributed on the substrate, it is necessary to bake at a higher temperature to evaporate the residual solvent from the photoresist, thereby improving the purity and strength of the photoresist while ensuring its activity. This step is also called pre-baking. In this paper, the substrate is placed on a heating table and maintained at a temperature of 100°C for 60 seconds.

[0009] Step 4, exposure. Use ultraviolet light of a specific wavelength to selectively irradiate the photoresist covering the substrate, so that the irradiated area (photosensitive area) of the negative photoresist undergoes a cross-linking reaction, so that it is not dissolved by the developer. The chemical properties of the photoresist in the non-photosensitive area remain basically unchanged, and it can be dissolved in the developer to form a specific pattern during development. Here, the mask is first attached to the photoresist and exposed to ultraviolet light. The exposure time is usually 2 to 10 seconds.

[0010] Step 5, post-baking. Post-baking is the process of placing the exposed sample at a certain temperature to further cross-link the photoresist. The temperature of post-baking is generally controlled between 115 and 125°C. If the temperature is too low, sufficient cross-linking reaction cannot occur and it will be dissolved by the developer; if the temperature is too high, a thermal cross-linking reaction will occur, causing all areas of the photoresist to be cross-linked, and the developer cannot dissolve the photoresist, so the required photolithography pattern will not appear. This article uses 120°C for post-baking, with a holding time of 90s.

[0011] Step 6: Flood exposure. Flood exposure refers to exposing the entire sample in the photosensitive area, so that all areas of the sample are exposed twice. There are usually no very strict parameter regulations for flood exposure, and it is only necessary to ensure that sufficient energy is provided during the flood exposure process. In this paper, the sample is placed in the photosensitive area and exposed for 60 seconds.

[0012] Step 7. Development: By adding a developer after the exposure process, the non-photosensitive area of ​​the negative photoresist will dissolve in the developer to form a specific pattern.

[0013] Step 8. Hard drying: After the photoresist is developed, it needs to be dried to make the properties of the photoresist more stable. This step is also called hard film.

[0014] Step 9. Preparation of the top electrode. After preparing the photoresist protective layer by photolithography, the top electrode is prepared by magnetron sputtering. Here, the Cu electrode is prepared by radio frequency sputtering. The top electrode has a thickness of 150nm, and the size is determined by the photolithography plate, with an area range of 102μm2-106μm2.

[0015] Step 10. Removal of photoresist. After the top electrode is prepared, the non-electrode covered area no longer needs photoresist as a protective layer, and the photoresist needs to be stripped off. This step is referred to as stripping. In this paper, the completed substrate is placed in an acetone solution for ultrasonic treatment for about 1 minute to strip off the remaining photoresist, and the top electrode is prepared.

[0016] Furthermore, since the memristor has the characteristics of nanoscale size, non-volatility, high durability, low power consumption, fast conversion, stackability and compatibility with CMOS, it is the hope for manufacturing high-performance new memory. The main characteristics of the memristor are that it is non-volatile, and the change of its resistance state is controlled by the amplitude, polarity and time length of the externally applied voltage (current). After power failure, it will maintain the last memristor resistance state without change, so when positive and negative voltages are applied, the memristor can record the current 1 (0) state to achieve storage. Similarly, when encountering positive and negative magnetic fields, the storage of the 1 (0) state can also be achieved. Using this effect, a large memory read-write array can be formed to achieve storage functions. Compared with the prior art, the beneficial effects of the present invention are:

[0017] 1. The high-performance memristor memory device structure proposed by the present invention is composed of only four layers of thin film materials, and the storage of binary data "0" and "1" is realized through the non-volatile nature of the memristor itself. Compared with the prior art, the device preparation method of the present invention is simpler, lower in cost, and has a short production cycle.

[0018] 2. The structure proposed in the present invention uses a combination of NiO and Co thin films. While having the performance of electrically controlled storage, it also has a certain perception of magnetism. Appropriate changes in positive and negative electricity and magnetism will change its resistance. Compared with the original single resistance variable structure, it has 4 stable resistance states and can realize multi-state storage.

[0019] 3. The present invention uses a photolithography method to prepare the middle film and the top electrode, which have a physical size of micrometer level and can be well adapted to the CMOS process and the demand for miniaturization.

[0020] 4. The change of the resistance state of the memristor proposed in the present invention is controlled by the amplitude, polarity and duration of the externally applied voltage (current). After power failure, it will maintain the last memristor state without change, and the stored data is non-volatile.

[0021] 5. Due to the application of a specific graphic structure, the present invention can realize the controllability of the four resistance state positions. The resistance state positions can be controlled by adjusting the area ratio of the square NiO graphic to the area of ​​the square frame Co. Different from the general two-layer structure, the structure in the present invention has a higher degree of freedom in design, with multiple variables such as the area thickness of the NiO layer, and the area thickness of the NiO and Co mixed layers, so that the margins of each resistance state can be sufficient and equal. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a cross-sectional view of the structure of the high-performance memristor storage device of the present invention.

[0023] Figure 2 It is a side view of the structure of the high-performance memristor storage device of the present invention.

[0024] Figure 3 It is a schematic diagram of the data reading and writing function of the storage device of the present invention through the memory effect of the memristor.

[0025] Figure 4 It is a graph showing the IV curve test results of the memory device of the present invention.

[0026] Figure 5 It is the resistance value of the memristor in high and low resistance states caused by the voltage change under different areas.

[0027] Figure 6 It is a process flow chart of manufacturing the memristor device of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below in conjunction with the implementation modes and the accompanying drawings.

[0029] like Figure 1 As shown, the structure includes four layers of thin film structure, wherein 101 is a Pt bottom electrode, 102 is a second NiO thin layer, 103 and 104 are a third layer composed of Co and NiO, and 105 is a Cu top electrode with a thickness of 10-15nm.

[0030] A high-performance multi-layer electromagnetic effect induction memristor memory device structure, and a preparation method thereof as follows Figure 6 As shown in the flow chart, the following steps are included:

[0031] Step 1: Prepare the Pt electrode directly on the substrate.

[0032] Step 2: Prepare NiO on the substrate obtained in step 1 by direct current magnetron sputtering in an oxygen environment.

[0033] Step 3: Test the resistance change of Co due to the GMR effect under a certain magnetic field (the magnetic field change here needs to be based on the maximum magnetic field change range that the device can provide).

[0034] Step 4: Since the Co part is essentially in a series-parallel relationship with the NiO film, the graphic area of ​​Co required to make the margins of each resistance state sufficient and equal can be calculated using the series-parallel formula.

[0035] Step 5: Form the square pattern required by NiO by photolithography. Here we test the resistance values ​​of high and low resistance states under different areas (see Figure 5 ) and select an area as required.

[0036] Step 6: Form the square frame pattern required by Co by photolithography, based on the required frame area obtained in step 4.

[0037] Step 7: Grow a metal film on the surface of the film obtained in step 3 by RF magnetron sputtering. Here we choose Cu.

[0038] Example 1

[0039] A high-performance magnetoelectric coupling effect sensing memristor memory device structure storage mechanism, memristor resistance change:

[0040] The high-performance electromagnetic effect sensing memory device structure of the present invention constructs a memristor structure, and utilizes the fact that the change of the resistance state of the device is controlled by the amplitude, polarity and time length of the externally applied voltage (magnetic field). After power failure, it will maintain the last memristor state unchanged for storage. The resistance is changed by changing the voltage or magnetic field applied to both ends of the memristor. When the resistance is in a high resistance state, the memory device is set to logic "1", and when the resistance is in a low resistance state, the memory device is set to logic "0". Similarly, changes in the magnetic field will also cause changes in resistance, thus forming four resistance states of 00, 01, 10, and 11.

[0041] Taking this structure as an example, the resistance change is tested according to the method shown above, and the following is obtained: Figure 4 The voltage and current variation test results of the memristor are shown in Figure 5. From Figure 5, it can be seen that the high and low resistance values ​​of the memristor differ by 105 times in a smaller device area.

[0042] Example 2

[0043] A high-performance memristor that realizes read and write functions (taking electrical control as an example): Figure 3As shown, 302, 303, 304, and 305 constitute a high-performance memory device of the present invention. 301 is a current line for reading data, which is used to read the voltage of the memory device and obtain resistance. If it is in a high-resistance state, it is in a "1" state, and if it is in a low-resistance state, it is in a "0" state. 306 is a current line for writing data, which acts on the voltage at both ends of the memristor to produce a change in resistance and store binary numbers "1" and "0". 307 is a MOS tube used as a switch, which is used to control the data storage process. A high-performance memristor realizes the read and write function process as follows: Write process: When a data storage signal is received, the gate voltage of the MOS tube 307 increases, so that the MOS tube is turned on, and a write current is generated in the current path for writing data, so a voltage is generated at both ends of the memristor, and the resistance of the memristor is changed to realize the data storage process. Read process: When a data reading signal is received, a very small read current is generated in the read current path. The current flows through the memristor film, and a small voltage is generated between the upper and lower electrodes, thereby obtaining the resistance state of the resistor and realizing the data reading process.

[0044] Example 3

[0045] A high-performance memory device structure can be used in the simulation software Cadence Virtuoso, in which more complex memory circuits can be designed and circuit performance can be optimized.

[0046] First, after the physical preparation, the key parameters of the device unit are measured and integrated into a complete device model. The device can realize the operation of writing and reading data by utilizing the non-volatility of the memristor. The established model is converted into Verilog-A hardware description language based on mathematical formulas, and the corresponding basic device symbols are generated in Cadence Virtuoso software. The basic device is simulated and debugged to ensure that the established device model can accurately simulate the behavior and effect of the actual multilayer memristor. After the device model is established and verified, the corresponding peripheral circuits are designed for the device, mainly including storage array, data reading circuit, data writing circuit, address decoding circuit and logic control circuit. Among them, the storage array is composed of single memristor devices arranged in m rows and n columns; the data reading circuit is connected to the storage array to read data from the unit devices in the array; the data writing circuit is also connected to the storage array to write data to the unit devices in the array; the address decoding circuit selects the unit device to be read and written according to the external input address signal; the logic control circuit controls the read and write operation timing of the entire read and write circuit.

[0047] With the above four-port equivalent model, the circuit design becomes simpler and faster, saving both time and cost.

[0048] The above is a specific embodiment of the present invention. Without departing from the principle of the present invention, those skilled in the art may make many modifications and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A multi-layer electromagnetic effect induction memristor memory structure, characterized in that Multilayer memristor structure, the core of the device is a multilayer structure, the most important of which is the middle memristor material layer and the mixed layer of memristor and GMR material. A high-performance quantum memory device structure characterized by constructing a spin heterojunction, including four layers of thin film materials: the first layer is a bottom electrode, which is used to grow thin films, carry logic devices, and connect devices to circuits; The second layer is a memristor material film layer, located above the substrate layer; the third layer is a memristor and GMR material mixed layer, located above the magnetic film layer; and the fourth layer is a top metal layer, located above the magnetic film layer.

2. The multilayer electromagnetic effect induced memristor device structure according to claim 1, characterized in that: The memristor film layer is made of NiO film, and the memristor and MR material mixed layer is made of patterned materials with memristor properties (such as NiO, TiO2, etc.) and GMR properties (Co, Cr, etc.).

3. The multi-layer electromagnetic effect induced memristor device structure according to claim 1, characterized in that: The resistance of the device remains unchanged after power is removed, and the stored data is non-volatile.

4. The multi-layer electromagnetic effect induced memristor device structure according to claim 1, characterized in that: The heavy metal thin film layer can be made of one of Pt, PtBi alloy, Au, Ag, and Cu.

5. The multi-layer electromagnetic effect induced memristor device structure according to claim 1, characterized in that: By applying a specific graphic structure, the controllable positions of the four resistance states can be achieved. The controllable positions of the resistance states can be achieved by simply adjusting the area ratio of the square NiO graphic to the area ratio of the square frame Co. Unlike the general two-layer structure, the structure in the present invention has a higher degree of freedom in design, with multiple variables such as the area thickness of the NiO layer and the area thickness of the NiO and Co mixed layers, which can make the margins of each resistance state sufficient and equal.

Images