Method and apparatus for reducing inter-stage gain error in analog-to-digital converter

Abstract

An example analog-to-digital converter (ADC) (100) is provided that includes sample and hold circuitry (120) coupled to an analog input (VIN); a first sub-ADC (130) coupled to the sample and hold circuitry (120); a multiplicative digital-to-analog converter (M-DAC) (140) coupled to the first sub-ADC (130); summing circuitry (160) coupled to the sample and hold circuitry (120) and the M-DAC (140); an amplifier (170) coupled to the summing circuitry (160); a second sub-ADC (180) coupled to the amplifier (170); and a reference generation circuitry (150) coupled to the first sub-ADC (130), the M-DAC (140), and the second sub-ADC (180), the reference generation circuitry (150) including: a reference voltage circuitry coupled to the M-DAC (140); a first resistor coupled to the reference voltage circuitry; a second resistor coupled to the first resistor; and a capacitor coupled in parallel to the second resistor through a switch.

Description

Technical Field

[0001] This description relates generally to analog-to-digital conversion and, more particularly, to methods and apparatus for reducing inter-stage gain errors in analog-to-digital converters. Background Art

[0002] Digital signal processing typically uses an analog-to-digital converter (ADC) to convert an analog input (e.g., an external analog signal) into a digital output. The ADC requires time to perform this conversion, which typically limits digital signal processing. A pipeline ADC is capable of converting an analog input into a digital output at a relatively high speed with relatively high accuracy. The pipeline ADC may include a first stage that determines at least one of the most significant bits (MSBs) of the digital output and a second stage that determines the remaining bits of the digital output. Summary of the invention

[0003] For methods and apparatus for reducing inter-stage gain errors in an analog-to-digital converter, an example analog-to-digital converter (ADC) includes: a sample and hold circuit system coupled to an analog input; a first sub-ADC coupled to the sample and hold circuit system; a multiplying digital-to-analog converter (M-DAC) coupled to the first sub-ADC; a summing circuit system coupled to the sample and hold circuit system and the M-DAC; an amplifier coupled to the summing circuit system; a second sub-ADC coupled to the amplifier; and a reference generation circuit system coupled to the first sub-ADC, the M-DAC, and the second sub-ADC, the reference generation circuit system including: a reference voltage coupled to the M-DAC; a first resistor coupled to the reference voltage; a second resistor coupled to the first resistor; and a capacitor coupled in parallel to the second resistor through a switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a block diagram of an example pipelined analog-to-digital converter including reference generation circuitry configured to generate a high voltage reference and a low voltage reference.

[0005] Figure 2 for Figure 1 Schematic diagram of a reference generation circuit system configured to generate a low voltage reference using a high voltage reference.

[0006] Figure 3 is configured to use charge injection cancellation to reduce the Figure 1 and 2 Schematic diagram of the switch causing charge injection of the reference generation circuit system.

[0007] Figure 4 is a schematic diagram of an example input stage of a reference amplifier including offset compensation circuitry and temperature compensation circuitry, the input stage being configured to trim the Figure 1 and2 The reference generating circuit system generates a low voltage reference.

[0008] Figure 5 for Figure 4 Schematic diagram of an offset compensation circuit system, wherein the offset compensation circuit system is configured to generate an offset voltage to compensate for a direct current (DC) offset Figure 1 and 2 The reference generating circuit system generates a low voltage reference.

[0009] Figure 6 for Figure 4 Schematic diagram of a temperature compensation circuit system configured to generate a temperature compensation voltage to compensate for temperature changes caused by Figure 1 and 2 The reference generating circuit system generates a low voltage reference.

[0010] Figure 7 for Figure 1 and 2 A timing diagram of an example switching operation of a reference generation circuit system for generating a low voltage reference.

[0011] Figure 8 for Figure 1 and 2 A timing diagram of an example operation of a reference generation circuit system including a low voltage reference and a high voltage reference, the low voltage reference using Figure 7 The switching operation is generated.

[0012] Fig. 9 To represent that a hardware circuit system and / or a machine-readable instruction that can be executed and / or configured to implement Figure 1 and 2 Reference generation circuitry and / or more generally Figure 1 A flowchart of an example method for implementing pipelined ADC hardware.

[0013] Fig.10 is a block diagram of an example processing platform including processor circuitry configured to perform Fig. 9 Example machine readable instructions and / or example operations to implement Figure 1 and 2 Reference generating circuit system.

[0014] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar features (functionally and / or structurally). DETAILED DESCRIPTION

[0015] The drawings are not necessarily to scale. In general, the same reference numerals in one or more of the drawings and this description refer to the same or similar parts. Although the drawings show regions with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In practice, boundaries and / or lines may be unobservable, mixed, and / or irregular.

[0016] Digital signal processing may use an analog-to-digital converter (ADC) to convert an analog input signal (e.g., a signal from a sensor, a signal received from a transmitter, etc.) into a digital output signal. For example, a microcontroller may include an ADC to convert a voltage provided by a sensor into a digital value to allow the microcontroller to perform operations on the digital value using a processor circuit system. The ADC requires time to perform this conversion, which often limits digital signal processing. As digital signal processing becomes more advanced, some systems require an ADC that can convert analog inputs into digital outputs at relatively high speeds and resolutions.

[0017] The pipeline ADC converts an analog input signal into a digital output signal at a relatively high speed and resolution. The pipeline ADC may include a first stage that determines at least one of the most significant bits (MSBs) of the digital output and a second stage that determines the remaining bits of the digital output. The digital output of the pipeline ADC is a combination of the one or more MSBs determined by the first stage and the remaining bits determined by the second stage.

[0018] The first stage includes a first sub-ADC and a multiplying digital-to-analog converter (M-DAC). The first sub-ADC is a relatively low-resolution ADC such that the digital output of the sub-ADC produces fewer bits than the digital output of the pipeline ADC. The first sub-ADC determines at least one most significant bit (MSB) of the digital output of the pipeline ADC by comparing the input signal with a relatively large reference signal.

[0019] The first stage removes the voltage representing the MSB of the digital output from the analog input to reduce the voltage of the input to the second stage of the pipeline ADC. The MSB of the digital output corresponds to approximately half of the potential voltage of the analog input. For example, when the analog input is greater than or equal to approximately zero volts, the pipeline ADC capable of converting the analog input between positive / negative 48 volts sets the MSB equal to logic one. In such an example, when the analog input is less than zero volts, the digital output of the first sub-ADC sets the MSB equal to logic zero (e.g., logic "low" or 0), and when the analog input is greater than approximately zero volts, sets the MSB equal to logic one (e.g., logic "high" or 1). In addition, the first sub-ADC may determine one or more additional bits of the digital output to further reduce the voltage of the input to the second stage of the pipeline ADC.

[0020] The M-DAC generates an analog output based on one or more MSBs determined by the first sub-ADC. For example, when the analog input is greater than 24 volts, a pipeline ADC capable of converting the analog input between positive / negative 48 volts causes the M-DAC to generate an analog output of 36 volts. In this example, the first sub-ADC determines the two MSBs of the digital output to be logic ones, such that the MSB indicates that the analog input is greater than zero volts, and the second MSB indicates that the analog input is greater than 24 volts.

[0021] The M-DAC converts one or more MSBs from the first sub-ADC into an analog output using a first reference input. The M-DAC requires that the first reference input be supplied by a reference voltage equal to the voltage represented by the one or more MSBs to ensure that the M-DAC is able to produce an analog output equal to the analog voltage represented by the one or more MSBs of the pipeline ADC. For example, when the two MSBs of the digital output are logic one and the analog output of the M-DAC is 36 volts, the first stage of the pipeline ADC that determines the two MSBs of the digital output requires a 48 volt reference voltage. The pipeline ADC subtracts the analog output of the M-DAC from the analog input of the pipeline ADC to reduce the analog input by the analog output of the M-DAC. Advantageously, since the first stage reduces the analog input, the pipeline ADC can use relatively low voltage and higher speed circuitry in the second stage.

[0022] The second stage determines the remaining bits of the digital output using the second sub-ADC. The second sub-ADC determines the remaining bits of the analog input using a second reference input coupled to a second reference voltage that is less than the first reference voltage of the first stage. Advantageously, the lower voltage circuitry included in the second stage reduces the conversion time of the second sub-ADC and reduces power consumption.

[0023] The mismatch of the reference voltage between the first stage and the second stage causes inter-stage gain error. The inter-stage gain error is caused by not taking into account the difference in the reference voltage of the first stage and the second stage. The inter-stage gain error makes the digital output of the pipeline ADC inaccurate, for example, one or more bits are incorrect. The inter-stage gain error reduces the signal-to-noise ratio (SNR) and increases the harmonic distortion of the digital output, similar to the residual amplifier gain error.

[0024] Some systems prevent inter-stage gain errors by using the same reference input for the first and second stages. In this example, the second stage is supplied with a first reference voltage that is capable of generating an analog value representing one or more MSBs of a pipeline ADC, which requires the second stage to include a circuit system capable of using the first reference voltage. This relatively high voltage circuit system being supplied to the second stage increases the duration required to convert the analog input to a digital output and increases power consumption. Another method of preventing inter-stage gain errors is to use the reference voltage of the first stage as the first reference voltage for the least significant bit of the second stage. In this method, for the most significant bit, the second stage uses a second reference voltage that is relatively lower than the first reference voltage. This method increases the speed of the second stage and requires the second stage to include a circuit system capable of supporting the reference voltage of the first stage and reducing inter-stage redundancy. Both methods of reducing inter-stage gain errors can route the reference input of the first stage to the second stage to reduce the conversion speed and increase the possibility of coupling between components.

[0025] The examples described herein include a pipeline ADC, which includes a reference generation circuit system configured to reduce inter-stage gain error. In some described examples, the reference generation circuit system uses a relatively high voltage reference supplied to the first stage to generate a relatively low voltage reference for the second stage of the pipeline ADC. The reference generation circuit system supplies both a high voltage reference and a low voltage reference to the first stage and supplies a low voltage reference to the second stage. The reference generation circuit system uses a voltage divider across the high voltage reference to generate a low voltage reference so that the voltage sampled on the voltage divider is proportional to the high voltage reference. The reference generation circuit system uses a first switch and a first capacitor to sample the voltage divider. The first capacitor is configured to maintain the sampled voltage when the first switch is disconnected and the first capacitor is no longer coupled to the voltage divider. The reference generation circuit system uses a second switch and a second capacitor to sample the voltage maintained at both ends of the first capacitor to generate a low voltage reference. The capacitance of the second capacitor is greater than that of the first capacitor to reduce noise on the low voltage reference. Advantageously, generating the low voltage reference using the reference generation circuitry reduces inter-stage gain errors in the pipeline ADC in response to the low voltage reference being proportional to the high voltage reference.

[0026] Figure 1 is a block diagram of an example pipeline ADC 100. Figure 1 In the example of , the pipeline ADC 100 includes a buffer 110, a sampling and holding circuit system 120, a first sub-ADC 130, an M-DAC 140, a reference generation circuit system 150, a summing circuit system 160, an amplifier 170 and a second sub-ADC 180. The pipeline ADC 100 converts the analog input (V IN ) is converted to digital output (D OUT) (not shown) (eg, M+K bits long). The digital output of the pipeline ADC 100 is one or more MSBs (D OUT_MSB ) (eg, M bits) and the remaining bits (D OUT_LSB ) (eg, K bits). The pipeline ADC 100 includes a reference generation circuit system 150 to generate a reference voltage that is proportional to a high voltage reference (V REFH ) is proportional to the first low voltage reference (V REFL1 ) and a second low voltage reference (V REFL2 ).

[0027] exist Figure 1 In the example of FIG. 1 , the buffer 110 is coupled to the analog input (V IN ) and sample and hold circuitry 120. Buffer 110 prevents circuitry including pipeline ADC 100 from altering the analog input by isolating the circuitry configured to generate the analog input from pipeline ADC 100. Buffer 110 supplies the isolated analog input to sample and hold circuitry 120.

[0028] The sampling and holding circuit system 120 is coupled to the buffer 110, the first sub-ADC 130, and the summing circuit system 160. The sampling and holding circuit system 120 samples the isolated analog input from the buffer 110. The sampling and holding circuit system 120 resamples the isolated analog input from the buffer 110 after a duration. For example, the sampling and holding circuit system 120 samples the isolated analog input from the buffer 110 approximately every one hundred microseconds (μS). Alternatively, the sampling and holding circuit system 120 may sample the isolated analog input in response to an event (e.g., an alarm, an enable signal, etc.). The duration between sampling may be determined based on the speed of the analog-to-digital conversion of the pipeline ADC 100. The sampling and holding circuit system 120 holds the sampled analog input between sampling. The sampling and holding circuit system 120 supplies the sampled analog input to the first sub-ADC 130 and the summing circuit system 160.

[0029] The first sub-ADC 130 is coupled to the sampling and holding circuit system 120, the M-DAC 140, the reference generation circuit system 150, and the summing circuit system 160. The first sub-ADC 130 generates a first low voltage reference (V REFL1) to determine at least one of the one or more MSBs of the digital output of the pipeline ADC 100. The first sub-ADC 130 determines the one or more MSBs of the digital output by determining whether the sampled analog input is greater than or equal to approximately half of the voltage range of the pipeline ADC 100 (e.g., M bits, where M is greater than or equal to one). The voltage range of the pipeline ADC 100 includes all voltages that can be represented using the digital output of the pipeline ADC 100. For example, a voltage range equal to twice the high voltage reference corresponds to the digital output of the pipeline ADC 100 being able to be represented between the positive / negative high voltage reference. In such an example, the first low voltage reference may be approximately half of the high voltage reference (approximately one quarter of the voltage range) to determine the two MSBs of the digital output between the positive / negative half of the high reference voltage. The MSB of the digital output of the pipeline ADC 100 may represent the sign of the digital output. For example, in the case where the analog input has a voltage range between +X volts and -X volts, when the sampled analog input is greater than or equal to zero volts and the digital output of the pipeline ADC 100 can represent an analog input between the positive / negative high voltage reference, the first sub-ADC 130 determines that the MSB of the digital output of the pipeline ADC 100 is a logical one. The first sub-ADC 130 can scale the analog input by a gain less than one to reduce the low voltage reference. For example, the first sub-ADC 130 scales the analog input by half to represent a voltage equal to twice the low voltage reference. In such an example, the first low voltage reference can be one-quarter of the high voltage reference to represent a voltage between the positive / negative halves of the high voltage reference, such as the two MSBs of the digital output.

[0030] The first sub-ADC 130 may determine a plurality of MSBs of the digital output. For example, when the sampled analog input is greater than or equal to three-quarters of the high voltage reference, the first sub-ADC 130 determines three MSBs (e.g., M=3) of the digital output of the pipeline ADC 100 to be equal to a logical one. In this example, the first MSB indicates that the sampled analog input is greater than a common potential (e.g., ground or zero volts), the second MSB indicates that the sampled analog input is greater than half of the high voltage reference, and the third MSB indicates that the sampled analog input is greater than three-quarters of the high voltage reference. The first sub-ADC 130 supplies one or more MSBs (D-subs) of the digital output to the M-DAC 140. OUT_MSB ). Advantageously, the first low voltage reference enables the first sub-ADC 130 to include lower voltage and higher speed circuitry.

[0031] The M-DAC 140 is coupled to the first sub-ADC 130, the reference generation circuitry 150, and the summing circuitry 160. The M-DAC 140 generates a digital output signal based on one or more MSBs of the digital output from the first sub-ADC 130 and a high voltage reference (V REFH ) to generate an analog output. For example, when both MSBs of the output of the first sub-ADC 130 are logic ones, the analog output of the M-DAC 140 is equal to half of the high voltage reference. In this example, the MSB being logic one indicates that the sampled analog input is greater than a common potential (e.g., ground), and the second MSB being logic one indicates that the sampled analog input is greater than half of the high voltage reference. The analog output of the M-DAC 140 is an analog representation of one or more MSBs of the digital output from the first sub-ADC 130. For example, when the MSB of the digital output from the first sub-ADC 130 is logic one and any remaining bits of the output of the first sub-ADC 130 are zero, the analog output of the M-DAC 140 is approximately equal to the common potential (e.g., ground). In this example, the first sub-ADC 130 determines that the sampled analog input is greater than the common potential at a minimum value (e.g., where M=1), such that any future ADC operation requires a reference voltage of approximately half of the high voltage reference. The M-DAC 140 requires a high voltage reference greater than or equal to half the difference between the highest and lowest voltages that can be represented by one or more MSBs of the digital output. For example, when the two MSBs of the digital output are logic ones (corresponding to twenty-four volts), the high voltage reference needs to be at least twenty-four volts. In this example, the voltage range of the pipeline ADC 100 is positive / negative forty-eight volts, so that the MSB of the digital output corresponds to greater than the common potential, and the second MSB corresponds to greater than or equal to half the difference between the common potential and half the voltage range. The M-DAC 140 supplies an analog output to the summing circuitry 160.

[0032] The reference generation circuit system 150 is coupled to the first sub-ADC 130, the M-DAC 140, and the second sub-ADC 180. The reference generation circuit system 150 generates a high voltage reference (V REFH ) are proportional to the first low voltage reference and the second low voltage reference (V REFL1 and V REFL2 ). This generation of a low voltage reference reduces the inter-stage gain error between the M-DAC 140 and the second sub-ADC 180. Figure 2The reference generation circuitry 150 is further described. The reference generation circuitry 150 supplies a first low voltage reference to a first reference input of the first sub-ADC 130. The reference generation circuitry 150 supplies a high voltage reference to a second reference input of the M-DAC 140. The reference generation circuitry 150 supplies a second low voltage reference to a third reference input of the second sub-ADC 180.

[0033] Summing circuitry 160 is coupled to sample and hold circuitry 120, M-DAC 140, and amplifier 170. Summing circuitry 160 generates a subtracted analog output by subtracting the analog output of M-DAC 140 from the sampled analog input of sample and hold circuitry 120. For example, when the sampled analog input is twenty-eight volts and the analog output of M-DAC 140 is twenty-four volts (e.g., M=2 and the MSB is 11), the subtracted analog output is four volts. Summing circuitry 160 supplies the subtracted analog output to amplifier 170. The subtracted analog output may be referred to as a residual. Advantageously, summing circuitry 160 reduces the sampled analog input so that amplifier 170 and second sub-ADC 180 can include relatively low voltage circuitry that can have a relatively higher operating speed than the circuitry used by M-DAC 140.

[0034] The amplifier 170 is coupled to the summing circuit system 160 and the second sub-ADC 180. The amplifier 170 amplifies the subtracted analog output from the summing circuit system 160 by a designed gain (G). The amplifier 170 reduces the noise supplied by the second sub-ADC 180 by amplifying the subtracted analog output. For example, the noise generated by the second sub-ADC 180 in the range from plus one millivolt (mV) to minus one millivolt (mV) has a substantially greater effect on a ten millivolt (mV) signal than if the signal were amplified to ten volts (V). Advantageously, the amplifier 170 reduces the noise generated by the second sub-ADC 180.

[0035] When having a fixed resolution, the amplifier 170 may amplify the subtracted analog output to increase the number of bits that can be determined by the second sub-ADC 180. For example, the number of bits determined by a sub-ADC capable of ten millivolt (mV) accuracy may be increased to one millivolt (mV) accuracy by amplifying the subtracted analog input by a designed gain of ten. In such an example, the bits determined by the second sub-ADC 180 may be scaled to coincide with one or more MSBs determined by the first sub-ADC 130. Advantageously, the accuracy of the second sub-ADC 180 may be increased due to the amplifier 170 amplifying the subtracted analog input. The amplifier 170 supplies the amplified subtracted analog input to the second sub-ADC 180.

[0036] The second sub-ADC 180 is coupled to the reference generation circuit system 150 and the amplifier 170. The second sub-ADC 180 determines a plurality of bits of the digital output of the pipeline ADC 100 based on the second low voltage reference from the reference generation circuit system 150 and the amplified subtracted analog input from the amplifier 170. The M-DAC 140 and the summing circuit system 160 reduce the voltage range of the second sub-ADC 180 by greater than or equal to half of the voltage range of the analog input. For example, when the first sub-ADC 130 determines the two MSBs of the digital output, the circuit system including the second sub-ADC 180 needs to be able to have a voltage range between plus and minus twenty-five percent of the voltage range of the analog input. Advantageously, the circuit system including the second sub-ADC 180 can be a relatively low voltage circuit system capable of increasing speed compared to the circuit system including the first sub-ADC 130 and the M-DAC 140.

[0037] In an example operation of the pipeline ADC 100, the sample and hold circuit system 120 samples the isolated analog input and provides the sampled analog input to the first sub-ADC 130 and the summing circuit system 160 within the hold time. Such a hold time may be referred to as a hold phase. The first sub-ADC 130 uses a first low voltage reference to determine one or more MSBs of the digital output of the pipeline ADC 100. The first sub-ADC 130 supplies the determined one or more MSBs to the M-DAC 140. The M-DAC 140 converts the one or more MSBs into an analog output using a high voltage reference. As described in more detail below, the M-DAC 140 includes a circuit system (not illustrated) that causes a voltage swing in the high voltage reference. For example, charge injection from a switch inside the M-DAC 140 may cause the high voltage reference to swing above and / or below the average voltage being supplied. The voltage swing makes it impossible to take into account gain errors that may not be trimmed using a single trim. The voltage swing on the high voltage reference prevents the reference generation circuit system 150 from using a voltage divider to generate a low voltage reference. Combined with the following Figure 7 and 8 This voltage swing in the high voltage reference is further detailed and described. The voltage swing on the high voltage reference is stable over time. However, the voltage swing causes the average voltage supplied to the M-DAC 140 to vary.

[0038] The reference generation circuit system 150 reduces the inter-stage gain error produced by changes in the average voltage of the high voltage reference by proportionally matching such changes in the low voltage reference. The reference generation circuit system 150 uses the high voltage reference to generate a low voltage reference so that the low voltage reference is proportional to the high voltage reference. The reference generation circuit system 150 samples the low voltage reference from the high voltage reference near the end of the hold phase so that any voltage swing has begun to stabilize. At the end of the hold phase, the low voltage reference is proportional to the high voltage reference due to the stable voltage swing. This method of sampling the high voltage reference near the end of the hold phase reduces reference errors that may not be trimmed using a single trim due to variations in the voltage swing across process, voltage and temperature (PVT). Alternatively, the voltage swing on the low voltage reference can be mitigated using a large capacitor, which will substantially increase the system chip (SoC) size. The following is combined with Figure 2 Reference generation circuitry 150 is described in further detail.

[0039] The summing circuit system 160 subtracts the analog output of the M-DAC 140 from the sampled analog input. The summing circuit system 160 supplies the subtracted analog output to the amplifier 170. The amplifier 170 amplifies the subtracted analog output to reduce the noise contribution from the second sub-ADC 180. The second sub-ADC 180 converts the amplified subtracted analog output using the second low voltage reference to generate a plurality of LSBs of the digital output. Advantageously, the reference generation circuit system 150 reduces inter-stage gain errors caused by not taking into account the difference between the high voltage reference and the low voltage reference.

[0040] Figure 2 for Figure 1 A schematic diagram of the reference generation circuit system 150 is shown in FIG. Figure 2 In the example of FIG. 1 , the reference generation circuit system 150 includes a high voltage reference source 205, a first switch 210, a current source 215, a first resistor 220, a second resistor 225, a second switch 230, a first capacitor 235, a third switch 240, a second capacitor 245, a controller 250, a first reference amplifier 255, and a second reference amplifier 260. The reference generation circuit system 150 generates a high voltage reference (V REFH ) to generate the first low voltage reference (V REFL1 ) and a second low voltage reference (V REFL2 ).

[0041] exist Figure 2In an example of , the high voltage reference source 205 is coupled to the first switch 210 and a common potential (e.g., ground). Alternatively, the high voltage reference source 205 may be coupled to the first resistor 220. In such an example, the first switch 210 and the current source 215 may be removed from the reference generation circuit system 150. The high voltage reference source 205 generates a high voltage reference. The high voltage reference source 205 may be referred to as a reference voltage circuit system or a reference voltage generation circuit system, which is a circuit system capable of supplying a reference voltage. The high voltage reference source 205 may include a high voltage reference amplifier circuit system (not illustrated) configured to generate a coarse high voltage reference and a fine high voltage reference. In such a configuration, the high voltage reference source 205 may switch between supplying a coarse high voltage reference and a fine high voltage reference as a high voltage reference. For example, at a first time, the high voltage reference source 205 supplies a high voltage reference to the reference amplifier 150. Figure 1 At one time, the M-DAC 140 of the embodiment supplies a coarse high voltage reference, and at a second time, the high voltage reference source 205 supplies a fine high voltage reference to the M-DAC 140. In this example, the voltage swing caused by the M-DAC 140 affects the coarse high voltage reference, while the fine high voltage reference is used by the reference generation circuitry 150 to generate a low voltage reference with a reduced voltage swing. Advantageously, such switching of the high voltage reference source 205 between the coarse high voltage reference and the fine high voltage reference reduces input-related stability issues with respect to the fine high voltage reference caused by circuitry (e.g., the M-DAC 140) coupled to the coarse high voltage reference.

[0042] The first switch 210 is coupled to the high voltage reference source 205, the current source 215, the first resistor 220, and the controller 250. The first switch 210 couples the high voltage reference source 205 to the first resistor 220 based on the controller 250. The first switch 210 can be opened or closed by the controller 250. For example, the controller 250 can close the first switch 210 to couple the high voltage reference source 205 to the first resistor 220, or open the first switch 210 to prevent the high voltage reference source 205 from applying the high voltage reference across the first resistor 220. The first switch 210 can be a transistor configured to be turned on (e.g., conducting) and off (e.g., not conducting) by the controller 250. Advantageously, in response to the controller 250 being able to disable the low voltage reference by disabling the first switch 210, the first switch 210 increases the reliability of the high voltage reference and the low voltage reference. The first switch 210 may be coupled to the M-DAC 140 to enable the reference generation circuitry 150 to disable both the high voltage reference and the low voltage reference by disabling (turning off so that it is non-conductive) the first switch 210. For example, the first switch 210 may be coupled to the M-DAC 140 such that when the first switch 210 is open, the M-DAC 140 is disconnected from the high voltage reference source 205.

[0043] The current source 215 is coupled to the first switch 210, the first resistor 220, and the controller 250. The current source 215 supplies a compensation current (I) to the first resistor 220. The compensation current is generated by supplying enough current to generate a high voltage reference (V) across the combined resistance (R1+R2) of the resistors 220 and 225 that is equal to the high voltage reference source 205. REFH ) to correct the voltage difference across the first switch 210. The current supplied by the current source 215 is determined using the following formula (1). The current source 215 can be enabled (e.g., supply current) or disabled (e.g., not supply current) by the controller 250. Advantageously, the current source 215 reduces the change in the voltage from the high voltage reference source 205 caused by the internal resistance (not illustrated) of the first switch 210 across the resistors 220 and 225.

[0044]

[0045] The first resistor 220 is coupled to the switches 210 and 230, the current source 215, and the second resistor 225. The first resistor 220 is coupled between the first switch 210 and the second resistor 225. The first resistor 220 has a first resistance (R1). The second resistor 225 is coupled to the first resistor 220, the second switch 230, and a common potential (e.g., ground). The second resistor 225 is coupled between the first resistor 220 and the common potential. The second resistor 225 has a second resistance (R2). The resistors 220 and 225 are configured as a voltage divider. The resistors 220 and 225 may be referred to as a reference voltage circuit system, which is a circuit system configured to supply a reference voltage. Alternatively, the resistors 220 and 225 may be replaced with another method of generating a voltage based on a high voltage reference in the teachings described herein. The resistors 220 and 225 may be positioned relatively close to the M-DAC 140 to reduce errors caused by electrical traces such as parasitic inductance, resistance, etc. For example, a system-on-chip (SoC) implementation of pipeline ADC 100 may place resistors 220 and 225 based on the location of M-DAC 140 .

[0046] The resistances of resistors 220 and 225 are selected to produce a reference voltage (V REF ), and is used to determine the compensation current in the above formula (1). The reference voltage is approximately equal to the second resistance multiplied by the high voltage reference divided by the first resistance plus the second resistance. The reference voltage can be determined using the following formula (2). Advantageously, the reference voltage is generated using a high voltage reference and a voltage divider.

[0047]

[0048] The second switch 230 is coupled to the resistors 220 and 225, the first capacitor 235, the third switch 240, and the controller 250. The second switch 230 couples the reference voltage generated by the resistors 220 and 225 across the first capacitor 235 based on the controller 250. The second switch 230 can be opened (e.g., not conducting) or closed (e.g., conducting) by the controller 250. The controller 250 can be configured to generate a reference voltage at a sampling frequency (F S ) opens and closes the second switch 230. The sampling frequency corresponds to the time between when the controller 250 opens the second switch 230. The sampling frequency may be based on Figure 1 The second switch 230 is configured to set the voltage across the first capacitor 235 to be approximately (preferably exactly) equal to the reference voltage. This voltage across the first capacitor 235 may be referred to as a small capacitor reference (V REF_C1 ).

[0049] The first capacitor 235 is coupled to the switches 230 and 240 and the common potential. When the second switch 230 couples the first capacitor 235 to the resistors 220 and 225, the small capacitor reference of the first capacitor 235 is substantially equal to the reference voltage generated between the resistors 220 and 225. The first capacitor 235 has a first capacitance (C small ).

[0050] The third switch 240 is coupled to the second switch 230, the capacitors 235 and 245, the controller 250, and the reference amplifiers 255 and 260. The third switch 240 can be opened or closed by the controller 250. The third switch 240 sets the voltage across the second capacitor 245 to be equal to the voltage across the first capacitor 235 based on the controller 250. For example, after the controller closes the third switch 240, the voltage across the second capacitor 245 is substantially equal to the small capacitor reference. Such a voltage across the second capacitor 245 may be referred to as the large capacitor reference (V REF_C2 ).

[0051] The second capacitor 245 is coupled to the third switch 240, the reference amplifiers 255 and 260, and the common potential. After the third switch 240 couples the first capacitor 235 to the second capacitor 245, the large capacitor reference is substantially equal to the small capacitor reference. The second capacitor 245 has a second capacitance (C large) to reduce noise. For example, the second capacitance may be large enough to average the noise of the small capacitor reference. Advantageously, second capacitor 245 reduces errors caused by noise, and such relatively large capacitance of second capacitor 245 reduces coupling to relatively small parasitic capacitances (not illustrated) of the inputs of reference amplifiers 255 and 260. The capacitances of capacitors 235 and 245 modify the effective bandwidth and sampling bandwidth of reference generation circuitry 150, as described below. The sampling bandwidth corresponds to the small capacitor reference of first capacitor 235 generated by the high voltage reference of high voltage reference source 205. The effective bandwidth corresponds to the large capacitor reference of second capacitor 245 generated by the high voltage reference of high voltage reference source 205.

[0052] The effective bandwidth (BANDWIDTH) of the reference generation circuit system 150 eff ) can be determined using the following formula (3). The sampling bandwidth (BANDWIDTH) of the reference generation circuit system 150 Samp ) is configured to be greater than the bandwidth of amplifier 170 so that the voltage across first capacitor 235 can track the voltage generated by high voltage reference source 205. The sampling bandwidth of reference generation circuit system 150 is determined using the following formula (4). Advantageously, the difference between the bandwidths of reference generation circuit system 150 and amplifier 170 reduces the error between the voltage across first capacitor 235 and resistors 220 and 225.

[0053]

[0054] The controller 250 is coupled to the switches 210, 230, and 240 and the current source 215. The controller 250 enables the reference generation circuit system 150 by closing the first switch 210 and enabling the current source 215. The controller 250 uses the clock holding signal (CLK HOLD ) controls the second switch 230. The controller 250 uses the non-overlapping clock holding signal (CLK NOV_HOLD ) controls the third switch 240. Figure 7The clock hold signal and the non-overlapping clock hold signal are further described. The controller 250 may include a dedicated reference source configured to enable and disable switches 210, 230, and 240. The controller 250 closes the second switch 230 to couple the first capacitor 235 to the reference voltage generated by resistors 220 and 225. The controller 250 ensures that the third switch 240 is open during the time when the second switch 230 is closed. The controller 250 opens the second switch 230 to keep the small capacitor reference approximately equal to the reference voltage. The controller 250 closes the third switch 240 to couple the second capacitor 245 to the first capacitor 235. The controller 250 ensures that the second switch 230 remains open while the third switch 240 couples capacitors 235 and 245. The controller 250 opens the third switch 240 to keep the large capacitor reference approximately equal to the small capacitor reference.

[0055] Reference amplifiers 255 and 260 are coupled to third switch 240 and second capacitor 245. First reference amplifier 255 generates a first low voltage reference based on the voltage across second capacitor 245. First reference amplifier 255 includes first trimming circuitry 265. First trimming circuitry 265 modifies first reference amplifier 255 to compensate for temperature variations and direct current (DC) offsets of the voltage across second capacitor 245 and first reference amplifier 255. Figures 4 to 6 First trimming circuitry 265 is described. Advantageously, first trimming circuitry 265 reduces errors by reducing variations in the first low voltage reference caused by temperature variations and / or DC offsets.

[0056] The second reference amplifier 260 generates a second low voltage reference based on the voltage across the second capacitor 245. The first low voltage reference and the second low voltage reference are substantially equal to the large capacitor reference. The second reference amplifier 260 includes a second trimming circuit system 270. The second trimming circuit system 270 modifies the second reference amplifier 260 to compensate for temperature variations and DC offsets of the voltage across the second capacitor 245 and the second reference amplifier 260. The second trimming circuit system 270 is similar to the first trimming circuit system 265. Advantageously, the second trimming circuit system 270 reduces inter-stage gain errors by reducing variations in the first low voltage reference caused by temperature variations and / or DC offsets.

[0057] Figure 3 for Figure 2 The configuration uses charge injection cancellation to reduce the Figure 1 and 2 Schematic diagram of the second switch 230 causing charge injection due to the switching of the reference generation circuit system 150. Such charge injection may cause errors that may not be corrected by a single trim. Figure 3In the example of , the second switch 230 includes a first transistor 310, a second transistor 320, and a third transistor 330. The transistors 310 to 330 are p-channel transistors. Alternatively, with slight modifications to the second switch 230, the transistors may be n-channel transistors. The transistors 310 to 330 are configured as follows: Figure 2 The controller 250 is turned on (e.g., conducting) or off (e.g., not conducting). When the transistors 310 and 330 are turned off and the second transistor 320 is turned on, the second switch 230 is called closed. When the transistors 310 and 330 are turned on and the second transistor 320 is turned off, the second switch 230 is called open.

[0058] The control terminal (eg, gate) of the first transistor 310 is coupled to the controller 250 (eg, to receive the control signal CLK NOV_HOLD ), and a current terminal (e.g., source and / or drain) of the first transistor 310 is coupled to one of the current terminals of the second transistor 320. The first transistor 310 is controlled by the controller 250. The first transistor 310 is configured to be turned on when the second transistor 320 is turned off. The first transistor 310 stores a current supplied by the second transistor 320 after the second transistor 320 is turned off. This current supplied by the second transistor 320 may be due to the discharge of an internal capacitance (not illustrated) of the second transistor 320. The first transistor 310 supplies the stored current when turned off to charge the internal capacitance of the second transistor 320. The operation of collecting and storing such current may be referred to as charge injection cancellation. Advantageously, the first transistor 310 implements a method of charge cancellation to prevent changes in the reference voltage, and thereby prevent changes in the high voltage reference, caused by the current supplied by turning on and off the second transistor 320.

[0059] The control terminal of the second transistor 320 is coupled to the controller 250 (eg, to receive the control signal CLK HOLD ), and one of the current terminals is connected to the current terminal of transistor 310, and the other current terminal is connected to the current terminal of transistor 330. The second transistor 320 is controlled by the controller 250. The controller 250 is configured to turn on the second transistor 320 at substantially (preferably exactly) the same time as the transistors 310 and 330 are turned off. The controller 250 is configured to turn off the second transistor 320 at substantially (preferably exactly) the same time as the transistors 310 and 330 are turned on. For example, the controller 250 supplies a clock holding signal (CLK HOLD ) to control the second transistor 320 and supply an inverted version of the clock holding signal (CLK HOLD_INV) to control transistors 310 and 330. Second transistor 320 includes an internal capacitance (not illustrated) that is charged when second transistor 320 is turned on and discharged when second transistor 320 is turned off. This discharge of the internal capacitor causes current to be supplied to transistors 310 and 330. This current is referred to as charge injection. The charge injection caused by second transistor 320 can be reduced by reducing the size of second transistor 320 to reduce the internal capacitance. Transistors 310 and 330 are configured to store the current released by second transistor 320 when turned off, and to supply the collected current to second transistor 320 when turned on. Advantageously, the effect of charge injection caused by turning off second transistor 320 on reference generation circuit system 150 is reduced by transistors 310 and 330.

[0060] The control terminal of the third transistor 330 is coupled to the controller 250, and the current terminal of the third transistor 330 is coupled to one of the current terminals of the second transistor 320. The third transistor 330 is controlled by the controller 250. The third transistor 330 is configured to be turned on when the second transistor 320 is turned off. The third transistor 330 stores the current supplied by turning off the second transistor 320. The third transistor 330 supplies the stored current when turned off to charge the internal capacitance of the second transistor 320. Advantageously, the third transistor 330 implements a method of charge cancellation to prevent a small capacitor reference from responding to changes in the current supplied by turning on and off the second transistor 320.

[0061] like Figure 2 As described in , transistors 310, 320, and 330 can be implemented using metal oxide semiconductor field effect transistors (MOSFETs). Preferably, each of transistors 310, 320, and 330 is implemented using a p-channel MOSFET (pMOSFET). Alternatively, transistors 310, 320, and / or 330 can be a PNP bipolar junction transistor (BJT), an N-channel field effect transistor (FET), an N-channel insulated gate bipolar transistor (IGBT), an N-channel junction field effect transistor (JFET), an N-channel MOSFET, a P-channel FET, a P-channel IGBT, a P-channel JFET, or an NPN BJT. The clock holding signal controlling transistors 310 to 330 turns on transistors 310 to 320 using a common potential (AVSS) and turns off transistors 310 to 320 using a clean power supply voltage (AVDD). The clean power supply voltage is a voltage supply isolated from a switching component that can add noise to the clock holding signal. For example, the clean power supply voltage can be a voltage generated by a dedicated voltage source. Advantageously, cleaning the supply voltage reduces clock coupling of retention signals, which may not be trimmed.

[0062] exist Figure 3In the example of , the second switch 230 is illustrated. Alternatively, the use of transistors 310 to 330 to implement charge injection cancellation can be applied in the teachings described herein as including Figure 2 The circuitry of switches 210 and / or 240 may be modified to reduce charge injection caused by the switches. In some examples, the channel widths of transistors 310 and 330 are a fraction (eg, approximately half) of the channel width of transistor 320 .

[0063] Figure 4 for Figure 2 Schematic diagram of an example input stage 400 of the first reference amplifier 255. Figure 2 The input stage 400 of the first trimming circuit system 265 is configured to trim the Figure 1 and 2 The reference generation circuit system 150 generates a large capacitor reference (V REF_C2 ).exist Figure 4 In the example of , input stage 400 includes first trim circuitry 265, first transistor 405, first current source 410, and second transistor 415. Input stage 400 is configured to reduce gain errors caused by DC offset and / or temperature variations by compensating a large capacitor reference.

[0064] exist Figure 4 In the example of FIG. 4 , first trimming circuitry 265 includes third transistor 420, fourth transistor 425, second current source 430, offset compensation circuitry 435, fifth transistor 440, sixth transistor 445, third current source 450, and temperature compensation circuitry 455. First trimming circuitry 265 is configured to trim a large capacitor reference to compensate for DC offset and / or temperature variations.

[0065] The third transistor 420 is coupled to transistors 405, 425, and 440, a second current source 430, and an offset compensation circuit system 435. The first offset correction voltage (V CORRP ) is supplied by the offset circuitry 435 to the control terminal of the third transistor 420 and controls the third transistor 420. The offset compensation circuitry 435 generates a first offset correction voltage based on the determined DC offset. The determined DC offset may be determined as part of a calibration of the offset compensation circuitry 435 and / or using a large capacitor reference and a first low voltage reference (V REFL1 ) is determined by analog-to-digital conversion. The determined DC offset is described in further detail below. The third transistor 420 allows current to flow to the second current source 430 when turned on by the first offset correction voltage. The third transistor 420 prevents current from flowing to the second current source 430 when turned off.

[0066] The fourth transistor 425 is coupled to the transistors 415, 420 and 445, the second current source 430 and the offset compensation circuit system 435. The second offset correction voltage (V CORRM ) is supplied by the offset circuit system 435 to the control terminal of the fourth transistor 425, and controls the fourth transistor 425. The offset compensation circuit system 435 generates a second offset correction voltage based on the determined DC offset. The determined DC offset is the difference between the first offset correction voltage and the second offset correction voltage. The fourth transistor 425 allows current to flow to the second current source 430 when turned on by the second offset correction voltage. The fourth transistor 425 prevents current from flowing to the second current source 430 when turned off.

[0067] The second current source 430 supplies current from transistors 420 and / or 425 to the output of the input stage 400 of the reference amplifier 255. The magnitude of the second current source 430 may be divided by the first scalar value (N1) to reduce the noise added by transistors 420 and 425 and provide additional control over the DC offset. For example, when the first scalar value of the second current source 430 is equal to ten, a ten millivolt (mV) DC offset may be corrected by applying a one hundred millivolt (mV) difference between the first offset correction voltage and the second offset correction voltage. When the first scalar value is equal to one, the magnitude of the second current source 430 is approximately (preferably exactly) equal to the magnitude of the first current source 410. Advantageously, the magnitude of the noise supplied by the offset correction voltage is divided by the first scalar value.

[0068] The offset compensation circuitry 435 generates an offset correction voltage that is supplied to transistors 420 and 425. The potential difference between the offset correction voltages is configured to offset the large capacitor reference by a DC voltage, similar to adding the DC voltage directly to the large capacitor reference. The magnitude of the DC offset may be calibrated or determined. For example, an ADC (and / or other circuitry operable to provide such functionality) may be coupled to the large capacitor reference and the low voltage reference to determine the DC voltage contribution and configure the offset compensation circuitry 435 to generate a corresponding DC voltage. In such an example, the ADC may configure the second offset correction voltage to be three millivolts (mV) to compensate the large capacitor reference for having a three millivolt (mV) offset. Figure 5 Examples of offset compensation circuitry 435 are described in further detail.

[0069] The fifth transistor 440 is coupled to the transistors 405, 420 and 425, the third current source 450 and the temperature compensation circuit system 455. The first temperature correction voltage (V CORRP_T ) is supplied by the offset circuit system 455 to the control terminal of the fifth transistor 440, and controls the fifth transistor 440. The temperature compensation circuit system 455 generates a first temperature correction voltage based on the temperature-dependent circuit system. Figure 6The temperature compensation circuitry 455 is described in further detail. The fifth transistor 440 allows current to flow to the third current source 450 when turned on by the first temperature correction voltage. The fifth transistor 440 prevents current from flowing to the third current source 450 when turned off.

[0070] The sixth transistor 445 is coupled to the transistors 415, 425 and 440, the third current source 450 and the temperature compensation circuit system 455. The second temperature correction voltage (V CORRM_T ) is supplied by the offset circuit system 455 to the control terminal of the sixth transistor 445 and controls the sixth transistor 445. The temperature compensation circuit system 455 generates a second temperature correction voltage based on the temperature-dependent circuit system of the compensation circuit system 455. Figure 6 The temperature compensation circuitry 455 is described in further detail. The sixth transistor 445 allows current to flow to the third current source 450 when turned on by the second temperature correction voltage. The sixth transistor 445 prevents current from flowing to the third current source 450 when turned off.

[0071] The third current source 450 supplies current from transistors 440 and / or 445 to a common potential. The magnitude of the third current source 450 may be divided by a second scalar value (N2) to reduce noise added by transistors 440 and 445 and to provide additional control over temperature variations of the DC offset value. For example, when the second scalar value of the third current source 450 is equal to ten, approximately one hundred millivolts (mV) of temperature-dependent variation in the difference between the first temperature correction voltage and the second temperature correction voltage may be applied to correct for a ten millivolt (mV) temperature variation. When the second scalar value is equal to one, the magnitude of the third current source 450 is approximately (preferably exactly) equal to the magnitude of the first current source 410. Advantageously, the magnitude of the noise supplied by the temperature correction voltage is divided by the second scalar value.

[0072] Temperature compensation circuitry 455 generates a temperature correction voltage that is supplied to the control terminals of transistors 440 and 445. The potential difference between the temperature correction voltages is configured to offset the large capacitor reference by a voltage that represents the change in the circuitry of reference generation circuitry 150 and first reference amplifier 255 over temperature. The amount of temperature compensation is determined using temperature compensation circuitry 455. Figure 6 Examples of temperature compensation circuitry 455 are described in further detail.

[0073] exist Figure 4 In the example of FIG. 4 , the first transistor 405 is coupled to the first current source 410 and transistors 415, 420, and 440. The first transistor 405 is connected to the first current source 410 and transistors 415, 420, and 440. Figure 2The large capacitor reference generated across the second capacitor 245 controls the first transistor 405. The first transistor 405 allows current to flow to the first current source 410 when turned on by the second capacitor voltage. The first transistor 405 prevents current from flowing to the first current source 410 when turned off.

[0074] A first current source 410 is coupled to transistors 405 and 415. The first current source 410 is configured to supply current from transistors 405 and / or 415 to an output of the input stage 400 of the reference amplifier 255.

[0075] The second transistor 415 is coupled to the transistors 405, 425, and 445. The second transistor 415 is controlled by a feedback input. The feedback input may be coupled to the output of the first reference amplifier 255. The second transistor 415 allows current to flow to the first current source 410 when turned on by the feedback input. The second transistor 415 prevents current from flowing to the first current source 410 when turned off.

[0076] exist Figure 4 In the example of FIG. 2 , the first trimming circuit system 265 is illustrated. Alternatively, the input stage 400 including circuitry for compensating for DC offset and / or temperature variations may be applied in the teachings described herein as including Figure 2 The circuit system of the second trimming circuit system 270 is used to reduce gain errors caused by DC offset and / or temperature changes.

[0077] Figure 5 for Figure 4 Schematic diagram of an example implementation of an offset compensation circuit system 435 configured to generate an offset voltage to compensate for a DC offset caused by Figure 1 and 2 The reference generation circuit system 150 generates a low voltage reference. Figure 5 In the example of , the offset compensation circuit system 435 includes a current source 510, a first resistor 520, an example resistor ladder 530, a second resistor 540, and an example multiplexer 550. The offset compensation circuit system 435 uses the multiplexer 550 to select the voltage generated by the current source 510 and the resistor ladder 530 to generate the offset correction voltage (V CORRP and / or V CORRM ).

[0078] exist Figure 5 In the example of , the current source 510 is coupled to the first resistor 520 and supplies current to the first resistor 520. The magnitude of the current supplied by the current source 510 may be determined to produce a potential drop across the first resistor 520, the resistor ladder 530, and / or the second resistor 540.

[0079] A first resistor 520 is coupled to a current source 510, a resistor ladder 530, and a multiplexer 550. The resistor ladder 530 is coupled to resistors 520 and 540 and the multiplexer 550. The resistor ladder 530 is a resistor circuit configured to divide a potential difference into a plurality of divided voltages. For example, the resistor ladder 530 may be implemented by a plurality of coupled resistors. Examples of resistor ladders include the resistor ladders shown in commonly assigned U.S. Patents 8,618,971, 5,969,658, 4,467,286 (each of which is incorporated by reference in its entirety). A second resistor 540 is coupled to the resistor ladder 530 and the multiplexer 550.

[0080] Multiplexer 550 couples the voltage generated by resistor ladder 530 to the first offset correction voltage and / or the second offset voltage. Advantageously, multiplexer 550 may be configured to couple a voltage corresponding to the determined DC offset to the offset correction voltage. Multiplexer 550 may be implemented by an ADC (not illustrated) or by a Figure 2 Multiplexer 550 may be controlled by controller 250 of the present invention. For example, multiplexer 550 may be configured to be controlled by a digital value generated by an analog-to-digital conversion of a large capacitor reference. In such an example, multiplexer 550 may include circuitry for converting the digital value to configure the offset correction voltage. Alternatively, controller 250 may control multiplexer 550 to correct a DC offset determined as part of a calibration process. For example, a manufacturer may calibrate controller 250 and / or multiplexer 550 to generate the offset correction voltage as a calibrated value.

[0081] Figure 6 for Figure 4 Schematic diagram of an example implementation of a temperature compensation circuit system 455 configured to generate a temperature compensation voltage to compensate for temperature changes caused by Figure 1 and 2 The reference generation circuit system 150 and the first reference amplifier 255 generate a low voltage reference. Figure 6 In the example of FIG. 4 , the temperature compensation circuit system 455 includes a first variable current source 610, a first resistor 620, a fixed current source 630, a second variable current source 640, a second resistor 650, and a third resistor 660. The temperature compensation circuit system 455 generates a first temperature compensation voltage (V CORRP_T ) and the second temperature compensation voltage (V CORRM_T ).

[0082] exist Figure 6In an example of , a first variable current source 610 is coupled to a first resistor 620. The first variable current source 610 supplies current to the first resistor 620 to generate a first temperature correction voltage. The magnitude of the current supplied by the first variable current source 610 varies with temperature to compensate for temperature changes. The first variable current source 610 can be a current digital-to-analog converter (IDAC) configured to supply current based on a digital input. In such an example, a temperature sensor can be used to determine the digital input.

[0083] The first resistor 620 is coupled to the first variable current source 610, the fixed current source 630, and the resistors 650 and 660. The first resistor 620 generates a potential difference based on currents supplied by the first variable current source 610 and the third resistor 660 to set a first temperature correction voltage.

[0084] A fixed current source 630 is coupled to the resistors 620, 650, and 660. The fixed current source 630 supplies current to the third resistor 660 to produce a fixed potential difference. The magnitude of the current being supplied by the fixed current source 630 is determined to set the voltage difference across the third resistor 660.

[0085] The second variable current source 640 is coupled to the second resistor 650. The second variable current source 640 supplies current to the second resistor 650 to generate a second temperature correction voltage. The magnitude of the current being supplied by the second variable current source 640 varies with temperature to compensate for temperature changes. The second variable current source 640 can be an IDAC configured to supply current based on a digital input. In this example, a temperature sensor can be used to determine the digital input.

[0086] The second resistor 650 is coupled to the fixed current source 630, the second variable current source 640, and the resistors 620 and 660. The first resistor 620 generates a potential difference to set a first temperature correction voltage based on the current supplied by the first variable current source 610 and the third resistor 660. The third resistor 660 is coupled to the resistors 620 and 650 and the fixed current source 630. The third resistor 660 is configured to generate a voltage difference to equally offset the two temperature correction voltages.

[0087] Figure 7 for Figure 1 and 2 A timing diagram of an example switching operation of the reference generation circuit system 150 for generating a low voltage reference. Figure 7 In the example of FIG. 1 , the timing diagram illustrates the residual amplification / holding phase clock 710, the clock holding signal (CLK HOLD )720, non-overlapping clock hold signal (CLK NOV_HOLD )730 and a high voltage reference signal 740.

[0088] The residual amplification / holding phase clock 710 represents a clock configured to control Figure 1 For example, amplifier 170 amplifies the signal from the residual amplification / holding phase clock 710 at the rising edge of the residual amplification / holding phase clock 710. Figure 1 The sampled analog input of the sampling and holding circuit system 120 is Figure 1 The difference between the analog outputs of the M-DAC 140. In this example, Figure 1 The second sub-ADC 180 samples the output of the amplifier 170 at the falling edge of the residual amplification / holding phase clock 710. The residual amplification / holding phase clock 710 may be generated by the controller 250 or generated inside the amplifier 170.

[0089] The clock hold signal 720 indicates that Figure 2 The controller 250 generates to control Figure 3 and 4 The clock holding signal 720 indicates that the second switch 230 is closed to a logic high so as to turn on the Figure 3 The second transistor 320 is turned off Figure 3 The clock holding signal 720 indicates that the second switch 230 is turned off to a logic low, so as to turn off the second transistor 320 and turn on the transistors 310 and 330. Figure 7 In the example of , a logic high of the clock hold signal 720 corresponds to closing the second switch 230 , but a common potential (eg, ground, AVSS, etc.) (eg, a logic low or “0”) may be used to turn on the transistors including the second switch 230 .

[0090] The non-overlapping clock hold signal 730 represents the clock hold signal generated by the controller 250 to control Figure 3 The non-overlapping clock holding signal 730 indicates that the third switch 240 is closed to a logic high so as to turn on the second transistor 320 and turn off the transistors 310 and 330. The non-overlapping clock holding signal 730 indicates that the third switch 240 is opened to a logic low so as to turn off the second transistor 320 and turn on the transistors 310 and 330. Although Figure 7 In the example of , a logic high of the non-overlapping clock hold signal 730 corresponds to the third switch 240 being closed, but a common potential (eg, ground, AVSS, etc.) may be used to turn on the transistors including the third switch 240 .

[0091] High voltage reference signal 740 represents a high voltage reference (eg, V REFH). The high voltage reference signal 740 is supplied to the M-DAC 140. The high voltage reference signal 740 is stabilized to a voltage higher than the average value (AVG) of the high voltage reference signal 740. The reference generation circuitry 150 generates a reference signal at the end of the hold phase (e.g., when CLK HOLD The transition from logic high to logic low time 780) produces a low voltage reference proportional to the high voltage reference and decreases Figure 1 The reference generation circuit system 150 reduces the gain error by using the high voltage reference signal 740 to generate a low voltage reference. The high voltage reference signal 740 may be caused by switching inside the M-DAC 140. Figure 2 However, when the switching is completed and / or the high voltage reference source 205 is stable, the change of the high voltage reference signal 740 is minimized.

[0092] At a first time 750, the residual amplification / holding phase clock 710 transitions from a logic low to a logic high, indicating a residual amplification / holding phase. Figure 1 The sample and hold circuit system 120 resamples the analog input and holds the sampled analog input until the next rising edge. The amplifier 170 amplifies the subtracted analog output from the first time 750 until the next falling edge of the residual amplification / holding phase clock 710. At the first time 750, the high voltage reference signal 740 changes as the switching inside the M-DAC 140 adds noise and / or requires additional current from the high voltage reference source 205. In response to the components of the M-DAC 140 and the reference generation circuit system 150 being stable, this effect from the switching decreases over time.

[0093] At the second time 760, the non-overlapping clock holding signal 730 changes from logic high to logic low, indicating that the controller 250 turns off the third switch 240 to decouple Figure 2 The controller 250 may be configured to provide a plurality of capacitors 235 and 245. At the second time 760, the large capacitor reference is substantially equal to the low voltage reference. At the second time 760, the controller 250 ensures that the non-overlapping clock hold signal 730 is not logic high at the same time as the clock hold signal 720. For example, the falling edge of the non-overlapping clock hold signal 730 at the second time 760 may be generated to prepare for the rising edge of the clock hold signal 720. The rising edge of the non-overlapping clock hold signal 730 is configured to be delayed until after the falling edge of the clock hold signal 720.

[0094] At the third time 770, the clock hold signal 720 changes from logic low to logic high, indicating that the controller 250 closes the second switch 230, thereby Figure 2 The first capacitor 235 is coupled to the Figure 2The reference voltage is generated across the second resistor 225. At a third time 770, the high voltage reference signal 740 begins to stabilize and the large capacitor reference remains substantially equal to the low voltage reference.

[0095] At the fourth time 780, the clock hold signal 720 transitions from logic high to logic low, indicating that the controller 250 turns off the second switch 230. At the fourth time 780, the small capacitor reference is held by the first capacitor 235, and the small capacitor reference is a noisy version of the reference voltage generated by the resistors 220 and 225. The noise on the small capacitor reference is responsive to the capacitance of the first capacitor 235 being small enough to allow relatively high frequency changes to be held.

[0096] At a fifth time 790, the non-overlapping clock hold signal 730 transitions from a logic low to a logic high, indicating that the controller 250 closes the third switch 240, thereby coupling capacitors 235 and 245 in parallel. In response to the capacitance of the second capacitor 245 being greater than the capacitance of the first capacitor 235, the large capacitor reference is configured to filter the relatively high frequency noise of the small capacitor reference. The noise filtered by the second capacitor 245 can be determined based on the effective bandwidth of the reference generation circuit system 150. The effective bandwidth of the reference generation circuit system 150 can be determined using the above formula (3).

[0097] At the sixth time 795, the residual amplification / holding phase clock 710 transitions from a logic high to a logic low, thereby causing the amplifier 170 to stop amplifying the subtracted analog output when the sample and hold circuit system 120 resamples the analog input. The time between the fourth time 780 and the sixth time 795 is relatively small to ensure that the voltage across the first capacitor 235 is approximately equal to the reference voltage when the high voltage reference signal 740 has stabilized. Advantageously, turning off the second switch 230 near the end of the hold phase at time 795 reduces the inter-stage gain error by ensuring that the voltage across the first capacitor 235 is proportional to the high voltage reference after stabilization. Advantageously, the noise on the small capacitor reference is averaged by the second capacitor 245. Advantageously, the gain error caused by the noise is reduced by the second capacitor 245.

[0098] Figure 8 for Figure 1 and 2 Contains the use of Figure 7 A timing diagram of an example operation of the reference generation circuit system 150 for generating a low voltage reference and a high voltage reference by switching operation. Figure 8 In the example of , the timing diagram includes an example scaled high voltage reference signal 810 and an example low voltage reference signal 820 .

[0099] exist Figure 8 In the example of Figure 1 The scaled high voltage reference signal 810 is scaled to be approximately equal to the low voltage reference. For example, when Figure 2 When the resistances of resistors 220 and 225 are equal, the scaled high voltage reference signal 810 can be scaled by half. The low voltage reference signal 820 is a low voltage reference generated by the reference generation circuit system 150. Figure 8 In the example operation, if the reference signals 810 and 820 are Figure 1 When the second sub-ADC 180 samples the output of the amplifier 170, Figure 1 The inter-stage gain error between the first stage and the second stage of the pipeline ADC 100 is zero. The inter-stage gain error between the first stage and the second stage is determined by determining the difference between the scaled high voltage reference represented by the scaled high voltage reference signal 810 and the low voltage reference represented by the low voltage reference signal 820 at the end of the residual amplification / holding phase clock 710.

[0100] The first time 830 corresponds approximately to Figure 7 At the first time 750, the low voltage reference signal 820 follows the scaled high voltage reference signal 810. At the third time 850, Figure 7 The residual amplification / holding phase clock 710 transitions to logic low. The third time 850 is approximately equal to Figure 7 The inter-stage gain error of the pipeline ADC 100 contributes to a portion of the difference between the reference signals 810 and 820 at the third time 850. Figure 8 In the example of , the error between reference signals 810 and 820 is approximately equal to 9 microvolts (μV).

[0101] Fig. 9 To indicate that machine-readable instructions that can be executed and / or configured to implement Figure 1 and 2 The reference generation circuit system 150 and / or more generally Figure 1 Flowchart of an example method performed by the hardware of the pipeline ADC 100. Fig. 9 The method starts at block 910. At block 910, Figure 2 The controller 250 of the embodiment determines whether analog-to-digital conversion is required. For example, the controller 250 determines whether the example microcontroller (not shown) requires pipeline ADC 100. If the controller 250 determines that pipeline ADC 100 is not required, the method proceeds to the end. If the controller 250 determines that pipeline ADC 100 is required, the method proceeds to block 920.

[0102] At block 920, the controller 250 enables the reference generation circuitry 150. For example, the controller 250 enables the reference generation circuitry 150 by closing Figure 2 The first switch 210 is enabled Figure 2 When the first switch 210 is closed, the first switch 210 will Figure 2 The voltage source 205 is coupled to Figure 2 The first resistor 220 of . The current source 215 supplies current based on the above formula (1). The method proceeds to block 930.

[0103] At block 930, the reference generation circuitry 150 supplies a first reference voltage to the first stage of the pipeline ADC 100. For example, Figure 2 The voltage source 205 supplies a high voltage reference to the M-DAC 140. The method proceeds to block 940.

[0104] At block 940, the controller 250 closes the first switch to sample the second reference voltage using the first capacitor. Figure 2 The second switch 230 is configured to couple the reference voltage to the first capacitor 235. Figure 2 The reference voltage generated by resistors 220 and 225 is sampled. In this example, the controller 250 may shut down Figure 3 The transistors 310 and 330 are turned on, and the second transistor 320 is turned on to close the second switch 230. Block 940 corresponds to Figure 7 The method proceeds to block 950.

[0105] At block 950, the controller 250 turns off the first switch to maintain the second reference voltage on the first capacitor. For example, the controller 250 turns off the second switch 230 to maintain the reference voltage across the first capacitor 235. In this example, the controller 250 may turn on transistors 310 and 330 and turn off the second transistor 320 to turn off the second switch 230. The method proceeds to block 960.

[0106] At block 960, the controller 250 closes the second switch to sample the second reference voltage using the second capacitor. Figure 2 The method proceeds to block 970 .

[0107] At block 970 , the controller 250 opens the second switch to maintain the second reference voltage on the second capacitor. For example, the controller 250 opens the third switch 240 to maintain the large capacitor reference across the second capacitor 245 . Figure 2 The inputs of reference amplifiers 255 and 260 remain in a stable state after block 970. The method proceeds to block 980.

[0108] At block 980, reference amplifiers 255 and / or 260 supply a second reference voltage to the second stage of pipeline ADC 100. For example, reference amplifiers 255 and 260 generate a first low voltage reference and a second low voltage reference based on the large capacitor reference held on second capacitor 245 after block 970. The method proceeds to block 910 to determine whether pipeline ADC 100 is still needed.

[0109] Fig.10 is a block diagram of an example processing platform 1000 that is configured to execute and / or instantiate Fig. 9 100 to implement the pipeline ADC 100 of FIG. 100. The processor platform 1000 may be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cell phone, a smart phone, a tablet computer such as an iPad™), a personal digital assistant (PDA), an Internet appliance, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a game console, a personal video recorder, a set-top box, a head-mounted device (e.g., an augmented reality (AR) head-mounted device, a virtual reality (VR) head-mounted device, etc.) or other wearable device, or any other type of computing device.

[0110] The processor platform 1000 of the illustrated example includes a processor circuit system 1012. The processor circuit system 1012 of the illustrated example is hardware. For example, the processor circuit system 1012 may be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The processor circuit system 1012 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the processor circuit system 1012 may implement Figure 2 Controller 250.

[0111] The processor circuit system 1012 of the illustrated example includes a local memory 1013 (e.g., cache memory, registers, etc.). The processor circuit system 1012 of the illustrated example communicates with a main memory including a volatile memory 1014 and a non-volatile memory 1016 via a bus 1018. The volatile memory 1014 may be comprised of synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), Dynamic Random Access Memory The non-volatile memory 1016 may be implemented by flash memory and / or any other desired type of memory device. Access to the main memory 1014, 1016 of the illustrated example is controlled by a memory controller 1017. Alternatively, the controller 250 may be implemented using circuitry coupled to the bus 1018.

[0112] The processor platform 1000 of the illustrated example also includes an interface circuit system 1020. The interface circuit system 1020 can be implemented by hardware according to any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, and / or a peripheral component interconnect express (PCIe) interface.

[0113] In the illustrated example, one or more input devices 1022 are connected to the interface circuitry 1020. The one or more input devices 1022 permit a user to enter data and / or commands into the processor circuitry 1012. The one or more input devices 1022 may be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touch screen, a touch pad, a trackball, an isotropic device, and / or a speech recognition system.

[0114] One or more output devices 1024 are also connected to the interface circuitry 1020 of the illustrated example. The one or more output devices 1024 may be implemented, for example, by a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-situ switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. Thus, the interface circuitry 1020 of the illustrated example may include a graphics driver card, a graphics driver chip, and / or a graphics processor circuitry such as a GPU.

[0115] The interface circuitry 1020 of the illustrated example also includes communication devices, such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces to facilitate the exchange of data with external machines (e.g., any kind of computing device) over the network 1026. Communications may occur through, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a site wireless system, a cellular telephone system, an optical connection, etc.

[0116] The processor platform 1000 of the illustrated example also includes one or more mass storage devices 1028 for storing software and / or data. Examples of such mass storage devices 1028 include magnetic storage devices, optical storage devices, floppy disk drives, HDDs, CDs, Blu-ray disk drives, redundant array of independent disks (RAID) systems, solid-state storage devices such as flash memory devices and / or SSDs, and DVD drives.

[0117] can be Fig. 9 The machine-readable instructions 1032 implemented by the machine-readable instructions may be stored in the mass storage device 1028, in the volatile memory 1014, in the non-volatile memory 1016, and / or on a removable, non-transitory computer-readable storage medium such as a CD or DVD.

[0118] In this description, the term "and / or" (when used in the form of, for example, A, B, and / or C) refers to any combination or subset of A, B, C, such as: (a) A alone; (b) B alone; (c) C alone; (d) A and B; (e) A and C; (f) B and C; and (g) A and B and C. In addition, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to embodiments that include any of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0119] The term "coupled" is used throughout this specification. The term may encompass connections, communications, or signal paths that achieve a functional relationship consistent with this description. For example, if device A provides a signal to control device B to perform an action, then in the first instance, device A is coupled to device B, or in the second instance, if the intermediate component C does not substantially change the functional relationship between device A and device B, then device A is coupled to device B through the intermediate component C, so that device B is controlled by device A via the control signal provided by device A.

[0120] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) at the time of manufacture by the manufacturer to perform the function, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed by firmware and / or software programming of the device, by the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0121] As used herein, the terms "terminal", "node", "interconnect", "pin" and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to an interconnection or an end thereof between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components.

[0122] A circuit or device described herein as including certain components may actually be suitable for coupling to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be suitable for coupling to at least some of the passive elements and / or the sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0123] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively with little or no change to the remaining circuitry. For example, metal oxide silicon FETs ("MOSFETs") (e.g., n-channel MOSFETs (nMOSFETs) or p-channel MOSFETs (pMOSFETs)), bipolar junction transistors (BJTs, e.g., NPN or PNP), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in conjunction with the devices described herein. The transistors may be depletion mode devices, drain extended devices, enhancement mode devices, native transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0124] The circuit described herein can be reconfigured to include the replaced components to provide functions that are at least partially similar to the functions available before the component replacement. Unless otherwise stated, the components shown as resistors generally represent any one or more elements that are coupled in series and / or in parallel to provide the impedance amount represented by the displayed resistor. For example, the resistor or capacitor shown and described as a single component in this article may actually be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, the resistor or capacitor shown and described as a single component in this article may actually be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively. Although some elements of the described examples are included in the integrated circuit and other elements are outside the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features described as being outside the integrated circuit may be included in the integrated circuit, and / or some features described as being inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated into the same module; and / or (iv) are incorporated in / on the same printed circuit board. Although certain elements of the described examples are included in the integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features described as being external to the integrated circuit may be included in the integrated circuit, and / or some features described as being internal to the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated into the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0125] The use of the phrase "ground" in the foregoing description includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this description. Unless otherwise stated, "about," "substantially," or "substantially" preceding a value means + / - 10% of the value, or if the value is zero, means a reasonable range of values ​​around zero.

[0126] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

Claims

1. An analog-to-digital converter (ADC), comprising: a sample and hold circuit system coupled to the analog input; a first sub-ADC coupled to the sample and hold circuitry; a multiplying digital-to-analog converter (M-DAC) coupled to the first sub-ADC; summing circuitry coupled to the sample-and-hold circuitry and the M-DAC; an amplifier coupled to the summing circuitry; a second sub-ADC coupled to the amplifier; and a reference generation circuit system coupled to the first sub-ADC, the M-DAC and the second sub-ADC, the reference generation circuit system comprising: reference voltage circuitry coupled to the M-DAC; a first resistor coupled to the reference voltage circuitry; a second resistor coupled to the first resistor; and A capacitor is coupled in parallel to the second resistor through a switch.

2. The ADC of claim 1 , wherein the reference voltage circuit system is a first reference voltage circuit system, the first reference voltage circuit system is configured to generate a first voltage, the first resistor and the second resistor include a second reference voltage circuit system configured to generate a second voltage less than the first voltage, and the second reference voltage circuit system is to be coupled to the first sub-ADC and the second sub-ADC.

3. The ADC of claim 1, wherein the switch is a first switch and the capacitor is a first capacitor, the reference generation circuitry further comprising a second capacitor coupled to the first capacitor and the first switch through a second switch.

4. The ADC of claim 3, wherein the reference generation circuitry further comprises a reference amplifier coupled between the second capacitor and the first sub-ADC, the reference amplifier for supplying a voltage to the first sub-ADC.

5. The ADC of claim 3, wherein the ADC further comprises a controller coupled to the first switch and the second switch, the controller configured to: closing the first switch to set a first voltage across the first capacitor; turning off the first switch to maintain the first voltage across the first capacitor; and The second switch is closed to set a second voltage across the second capacitor to be substantially equal to the first voltage of the first capacitor.

6. The ADC of claim 1, wherein the summing circuitry is configured to supply the amplifier with the output of the sample and hold circuitry minus the output of the M-DAC.

7. The ADC of claim 1, wherein the first sub-ADC determines a most significant bit of a digital output of the ADC and the second sub-ADC determines a least significant bit of the digital output of the ADC.

8. The ADC of claim 1, wherein the switch is configured to couple the capacitor to the second resistor after enabling the amplifier until disabling the amplifier.

9. The ADC of claim 1, wherein a first duration during which the switch couples the capacitor to the second resistor has a first bandwidth, and a second duration during which the amplifier is enabled has a second bandwidth, the first bandwidth being configured to be greater than the second bandwidth.

10. An apparatus comprising: A pipelined analog-to-digital converter (ADC) comprising: a first sub-ADC comprising a first reference input; a second sub-ADC including a second reference input; a multiplying digital-to-analog converter (M-DAC) coupled between the first sub-ADC and the second sub-ADC, the M-DAC including a third reference input; and a reference generation circuitry coupled to the first reference input, the second reference input, and the third reference input, the reference generation circuitry comprising: a first resistor; a second resistor coupled to the first resistor at a first node; a first switch configured to couple the first node to a first capacitor; a second switch configured to couple the first capacitor to a second capacitor; and A reference amplifier has an input coupled to the second capacitor and has an output coupled to the second reference input.

11. The device of claim 10, wherein the first switch comprises: a first transistor coupled to the first resistor and the second resistor; a second transistor coupled to the first resistor, the second resistor, the second switch, the first capacitor, and the first transistor; and A third transistor is coupled to the second transistor, the second switch, and the first capacitor.

12. The device of claim 11, wherein the first transistor, the second transistor, and the third transistor are P-channel metal oxide semiconductor field effect transistors (pMOSFETs).

13. The apparatus of claim 10, wherein the reference generation circuitry further comprises a controller coupled to the first switch and the second switch, the controller configured to: closing the first switch to set the voltage of the first capacitor equal to a reference voltage; turning off the first switch to maintain the reference voltage on the first capacitor; and The second switch is closed to set the voltage of the second capacitor equal to the reference voltage on the first capacitor.

14. The apparatus of claim 10, wherein the reference generation circuitry further comprises: a transistor coupled between a voltage source and the first resistor, the transistor configured to enable the reference generation circuitry; and A current source is coupled to the transistor and the first resistor, the current source being configured to supply a current to set a voltage drop across the first resistor and the second resistor equal to a voltage generated by the voltage source.

15. The device of claim 10, wherein the second capacitor is configured to include a capacitance greater than the first capacitor.

16. The apparatus of claim 10, wherein the reference amplifier comprises trimming circuitry configured to compensate the voltage across the second capacitor for direct current (DC) offsets and temperature variations.

17. The device of claim 10, wherein the reference amplifier is a first reference amplifier, the input is a first input, and the output is a second output, the reference generation circuitry further comprising a second reference amplifier having a second input coupled to the second capacitor and having a second output coupled to the first reference input.

18. A method of operating an analog-to-digital converter (ADC), the method comprising: supplying a first reference voltage from a reference voltage generating circuit system to a multiplying digital-to-analog converter of a pipeline analog-to-digital converter (ADC); closing, by a controller, a first switch to supply a second reference voltage to the first capacitor, the second reference voltage being generated using the first reference voltage; turning off the first switch by the controller to maintain the second reference voltage on the first capacitor; closing, by the controller, a second switch to supply the second reference voltage to a second capacitor; turning off the second switch by the controller to maintain the second reference voltage on the second capacitor; and The second reference voltage is supplied to the sub-ADC by an amplifier.

19. The method of claim 18, wherein the amplifier is a first amplifier and the sub-ADC is a first sub-ADC, the method further comprising supplying the second reference voltage to a second sub-ADC by a second amplifier.

20. The method of claim 18, further comprising averaging the second reference voltage by the second capacitor.

21. The method of claim 18, further comprising reducing noise on the second reference voltage and coupling between the second capacitor and the amplifier by increasing capacitance of the second capacitor.

22. The method of claim 18, further comprising correcting an offset error of the second reference voltage using circuitry for trimming an input of the amplifier.

23. The method of claim 18, wherein the second reference voltage is sampled by the first switch before the second switch samples the first capacitor.

24. The method of claim 18, wherein opening the first switch is in response to supplying a potential to the transistor from a dedicated reference source.

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