Method for reducing warping degree of silicon wafer after epitaxy and silicon epitaxial wafer
By making a photoresist film layer and material layer on a silicon single-crystal substrate and baking it at high temperature, the problem of high warpage after the silicon wafer is solved, and the effect of reducing warpage and cost is achieved.
Patent Information
- Application Number
- CN202411803619.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-10
- Publication Date
- 2025-03-28
AI Technical Summary
In the high-temperature processes of semiconductor integrated circuits and other silicon devices, the warping phenomenon after the silicon wafer is one of the most important and difficult problems in the device process. The existing methods are costly and difficult to ensure high product yields.
Provided is a method including providing a silicon single-crystal substrate, making a photoresist film layer, forming a material layer by vapor deposition, and baking the epitaxial sheet at a temperature of 1000°C to 1300°C to reduce its warpage.
It effectively reduces the warpage of the silicon epitaxial sheet, meets expected needs, and reduces implementation costs, and is simple.
Smart Images
Figure CN119710938A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of semiconductor technology, in particular to a method for reducing the warpage of a silicon wafer after epitaxy and a silicon epitaxial wafer. Background Art
[0002] As integrated circuits develop towards high integration, in order to meet the requirements of high packaging density and low cost of semiconductor integrated circuits and other silicon devices, the outer edge of silicon wafers tends to be larger in size. At the same time, the increase in the number of wiring layers and the miniaturization of components require the surface of silicon wafer epitaxial wafers to have a higher flatness. However, in the high-temperature process of semiconductor integrated circuits and other silicon devices, the warping phenomenon that occurs after silicon wafer epitaxy is one of the most important and difficult problems in the device process. The warping of silicon epitaxial wafers causes the maximum distance and the minimum distance between the midline plane and the reference plane to have a non-zero difference, which brings difficulties to the photolithography process of complex circuit diagrams on silicon epitaxial wafers, affecting the device yield and performance.
[0003] The existing method of reducing the warpage of silicon epitaxial wafers is usually to control the warpage of the silicon wafer substrate, but the implementation cost is relatively high and it is difficult to ensure a high product yield; alternatively, the warpage is reduced during the process of growing epitaxial layers on silicon wafers to form epitaxial wafers. The existing process flow for reducing the warpage during silicon wafer epitaxy is: start → heating → deposition of single crystal layer → end. Although the warpage of silicon epitaxial wafers can be improved, the warpage of epitaxial wafers manufactured by existing processes is usually 40 microns to 70 microns, which is still difficult to meet the warpage requirements and does not meet expected needs. Summary of the invention
[0004] The purpose of the present invention is to provide a method for reducing the warpage of silicon wafers after epitaxy and a silicon epitaxial wafer, which can reduce the warpage of the silicon epitaxial wafer so that the warpage of the silicon epitaxial wafer meets the warpage requirements and meets the expected needs, while helping to reduce the implementation cost.
[0005] To achieve the above object, the present invention provides the following technical solutions:
[0006] In a first aspect, a method for reducing the warpage of a silicon wafer after epitaxy is provided, comprising:
[0007] Providing a silicon single wafer substrate, the silicon single wafer substrate serving as a base layer for silicon wafer epitaxy;
[0008] Making a photoresist film layer on the silicon single wafer substrate, wherein the photoresist film layer is used as a pattern transfer template to form a desired pattern;
[0009] Baking the photoresist film layer at a temperature of 100° C. to 150° C. for 3 minutes to 6 minutes;
[0010] A material layer is formed on the thin film layer by a vapor deposition method to manufacture an epitaxial wafer, wherein the material layer includes a required structure and circuit, and the silicon single crystal substrate, the photoresist thin film layer and the material layer constitute the epitaxial wafer;
[0011] Heating the epitaxial wafer to a temperature not lower than 1000° C.;
[0012] The epitaxial wafer is baked at a temperature of 1000°C-1300°C for 10 minutes-20 minutes to reduce the warping of the epitaxial wafer.
[0013] As a further solution of the present invention: providing a silicon single wafer substrate comprises:
[0014] Cleaning the surface of the silicon single wafer substrate, and drying the cleaned surface of the silicon single wafer substrate to ensure that there is no water mark on the surface of the silicon single wafer substrate, wherein the cleaning method comprises removing pollutants on the surface of the silicon single wafer substrate by a chemical method, a physical method or a combination of the two;
[0015] The physical method includes using ultraviolet rays or ozone to dry-clean the silicon single wafer substrate, and the chemical method includes using a mixed solution of sulfuric acid and hydrogen peroxide to clean and remove organic pollutants on the surface of the silicon single wafer substrate;
[0016] The ratio of the mixed solution of sulfuric acid and hydrogen peroxide is 4:1 by volume. The sulfuric acid solution can dehydrate and carbonize the organic pollutants on the surface of the silicon single wafer substrate. The carbonization product is further oxidized by the hydrogen peroxide solution to generate carbon monoxide or carbon dioxide gas, so that the organic pollutants finally generate gas and water and are separated from the surface of the silicon single wafer substrate. The relationship between the rotation speed and the film thickness is as follows:
[0017] Spi n=knT
[0018] In the formula, Spi n is the rotation speed; T is the film thickness; k and n are constants.
[0019] As a further solution of the present invention: the step of manufacturing a photoresist film layer on the silicon single wafer substrate comprises:
[0020] The photoresist is dripped on the silicon single wafer substrate, and the silicon single wafer substrate is rotated at a high speed. The photoresist dripped during the rotation is coated on the surface of the silicon single wafer substrate to obtain a photoresist film layer, and a patterned photoresist layer is produced by exposure, and the photoresist film layer is used as a template for pattern definition;
[0021] A mask plate and an ultraviolet light exposure system are used to selectively expose the photoresist film layer. After the exposure process is completed, the unexposed photoresist film layer undergoes a chemical reaction in a developer and is dissolved and removed, thereby forming a patterned photoresist layer on the photoresist film layer. The thickness of the photoresist film layer is 20 nanometers to 100 micrometers. By using a spin coating method to spin-coat the photoresist on the surface of the silicon single crystal substrate, the photoresist film layer can have the advantages of uniform film thickness, few defects, and good uniformity, which is beneficial to improving the coating performance of the photoresist film layer.
[0022] As a further solution of the present invention: the baking of the photoresist film layer comprises:
[0023] The photoresist film layer is subjected to a first baking, a second baking and a third baking, wherein the first baking adopts a baking temperature of 100° C.-110° C. and a baking duration of 1 minute-2 minutes. The first baking is used to remove the solvent in the photoresist film layer and reduce the solvent residue, which is beneficial to improving the adhesion between the photoresist and the silicon single wafer substrate;
[0024] The second baking adopts a baking temperature of 100°C-110°C and a baking duration of 1 minute-2 minutes. The second baking is used to bake the photoresist film layer after exposure, which can enhance the corrosion resistance of the photoresist film layer;
[0025] The third baking temperature is 110℃-150℃, and the baking time is 1 minute-2 minutes. The third baking is used to reduce the residual stress in the photoresist film layer to prevent affecting the subsequent etching or ion implantation process and avoid interlayer displacement or peeling in the etching or ion implantation process.
[0026] As a further solution of the present invention: the method of forming a material layer on the photoresist film layer by using a vapor deposition method comprises:
[0027] Under vacuum conditions, the target material is converted into gas or plasma by physical vapor deposition and then sputtered and deposited onto the surface of the photoresist film layer. The target material is silicon or silicon dioxide. The physical vapor deposition method is beneficial to forming a dense material layer and improving the electrical properties of the material layer.
[0028] As a further solution of the present invention: the method of forming a material layer on the photoresist film layer by using a vapor deposition method comprises:
[0029] The precursor gas is introduced into the reaction chamber to cause a chemical reaction, so that the product of the chemical reaction adheres and deposits on the surface of the photoresist film layer to form a material layer. Silicon carbide or silicon nitride gas is used as a precursor gas and introduced into the reaction chamber. Silicon carbide or silicon nitride gas is deposited on the surface of the photoresist film layer by using a laser.
[0030] As a further solution of the present invention: the step of heating the epitaxial wafer to a temperature not less than 1000° C. comprises:
[0031] The epitaxial wafer is heated by a radiation heat source of a specific wavelength, so that the temperature of the epitaxial wafer is uniformly increased to 1000° C.-1200° C. The wavelength of the radiation heat source is 0.3 micron-0.4 micron, which can heat the epitaxial wafer in minutes.
[0032] As a further solution of the present invention: the method of baking the epitaxial wafer at a temperature of 1000° C. to 1300° C. comprises:
[0033] The epitaxial wafer is continuously heated by a radiation heat source and then annealed and cooled by an RTP process, which is beneficial to repairing defects in the material layer during the annealing process, arranging impurity atoms and misaligned carriers in the material layer, and increasing the concentration of electrons and holes in the material layer and the mobility of carriers after annealing, thereby improving the conductivity.
[0034] In a second aspect, the present invention further provides a silicon epitaxial wafer, which is prepared by the method for reducing the warpage of silicon wafers after epitaxy as described in the above scheme. By heating the epitaxial wafer with a radiation heat source of a specific wavelength, the epitaxial wafer can be quickly heated to achieve secondary high-temperature heating of the epitaxial wafer, and after the high-temperature heating is completed, the subsequent parameter growth is not affected. At the same time, by repairing the defects of the material layer after the secondary high-temperature heating, the impurity atoms and the misaligned carriers in the material layer can be arranged, which greatly reduces the warpage of the epitaxial wafer, thereby effectively improving the anti-warping ability of the epitaxial wafer.
[0035] As a further solution of the present invention: the warpage of the silicon epitaxial wafer is 2 to 29, compared with the warpage of 35 to 60 of the epitaxial wafer manufactured by the traditional epitaxial wafer manufacturing method, the method provided by the present invention can effectively reduce the warpage of the epitaxial wafer, while having low cost and simple steps.
[0036] Compared with the prior art, the present invention has the following beneficial effects:
[0037] In the present invention, by adopting a radiation heat source of a specific wavelength to heat the epitaxial wafer, the epitaxial wafer can be quickly heated, and secondary high-temperature heating of the epitaxial wafer is achieved. After the high-temperature heating is completed, the subsequent parameter growth is not affected. At the same time, by repairing the defects of the material layer after the secondary high-temperature heating, the impurity atoms and the misaligned carriers in the material layer can be arranged, and the warping of the epitaxial wafer can be greatly reduced, thereby effectively improving the anti-warping ability of the epitaxial wafer. In addition, the implementation cost is low, the steps are simple, and the customer's expectations of the product warping can be improved, which has high commercial value. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figure 1 It is a flowchart of the method of the present invention;
[0039] Figure 2 A comparison chart of the process flow before and after the method for improving the warpage of silicon wafer after epitaxy;
[0040] Figure 3 This is a comparison diagram before and after the improvement of the warpage after epitaxial growth of the present invention. DETAILED DESCRIPTION
[0041] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0042] Example:
[0043] See also Figure 1 , a method for reducing the warpage of a silicon wafer after epitaxy is provided, comprising the following steps:
[0044] S1: providing a silicon single wafer substrate, the silicon single wafer substrate serving as a base layer for silicon wafer epitaxy;
[0045] S2: forming a photoresist film layer on a silicon single wafer substrate, the photoresist film layer being used as a pattern transfer template to form a desired pattern;
[0046] S3: baking the photoresist film layer at a temperature of 100° C. to 150° C. for 3 minutes to 6 minutes;
[0047] S4: forming a material layer on the thin film layer by a vapor deposition method to produce an epitaxial wafer, wherein the material layer includes a required structure and circuit, and the silicon single crystal substrate, the photoresist thin film layer and the material layer constitute the epitaxial wafer;
[0048] S5: heating the epitaxial wafer to a temperature not lower than 1000° C.;
[0049] S6: baking the epitaxial wafer at a temperature of 1000° C. to 1300° C. for 10 minutes to 20 minutes to reduce the warping of the epitaxial wafer.
[0050] Preferably, providing a silicon single wafer substrate comprises:
[0051] The surface of the silicon single wafer substrate is cleaned, and the surface of the cleaned silicon single wafer substrate is dried to ensure that there is no water mark on the surface of the silicon single wafer substrate. The cleaning method includes using a physical method or a combination of the two methods to remove pollutants on the surface of the silicon single wafer substrate. The physical method includes using ultraviolet rays or ozone to dry clean the silicon single wafer substrate. The chemical method includes using a mixed solution of sulfuric acid and hydrogen peroxide to clean and remove organic pollutants on the surface of the silicon single wafer substrate. The ratio of the mixed solution of sulfuric acid and hydrogen peroxide is a volume ratio of sulfuric acid solution to hydrogen peroxide solution of 4:1. The sulfuric acid solution can dehydrate and carbonize the organic pollutants on the surface of the silicon single wafer substrate. The carbonization product is further oxidized by the hydrogen peroxide solution to generate carbon monoxide or carbon dioxide gas, so that the organic pollutants finally generate gas and water and detach from the surface of the silicon single wafer substrate. The relationship between the rotation speed and the film thickness is as follows:
[0052] Spi n=knT
[0053] In the formula, Spi n is the rotation speed; T is the film thickness; k and n are constants.
[0054] Preferably, manufacturing a photoresist film layer on a silicon single wafer substrate comprises:
[0055] The photoresist is dripped on the silicon single crystal substrate, and the silicon single crystal substrate is rotated at a high speed. During the rotation process, the photoresist dripped is coated on the surface of the silicon single crystal substrate to obtain a photoresist film layer. A patterned photoresist layer is produced by exposure. The photoresist film layer is used as a template for graphic definition. A mask plate and an ultraviolet light exposure system are used to selectively expose the photoresist film layer. After the exposure process is completed, the unexposed photoresist film layer undergoes a chemical reaction in a developer and is dissolved and removed, thereby forming a patterned photoresist layer on the photoresist film layer. The thickness of the photoresist film layer is 20 nanometers to 100 micrometers. By using a spin coating method to spin-coat the photoresist on the surface of the silicon single crystal substrate, the photoresist film layer can have the advantages of uniform film thickness, few defects, and good uniformity, which is beneficial to improving the coating performance of the photoresist film layer.
[0056] Preferably, baking the photoresist film layer comprises:
[0057] The photoresist film layer is baked for the first time, the second time and the third time. The baking temperature used in the first baking is 100℃-110℃, and the baking duration is 1 minute-2 minutes. The first baking is used to remove the solvent in the photoresist film layer and reduce the solvent residue, which is beneficial to improve the adhesion between the photoresist and the silicon single wafer substrate. The baking temperature used in the second baking is 100℃-110℃, and the baking duration is 1 minute-2 minutes. The second baking is used to bake the photoresist film layer after exposure, which can enhance the corrosion resistance of the photoresist film layer. The baking temperature used in the third baking is 110℃-150℃, and the baking duration is 1 minute-2 minutes. The third baking is used to reduce the residual stress in the photoresist film layer to prevent affecting the subsequent etching or ion implantation process and avoid interlayer displacement or peeling in the etching or ion implantation process.
[0058] Preferably, forming a material layer on the photoresist film layer by vapor deposition method comprises:
[0059] Under vacuum conditions, the target material is converted into gas or plasma by physical vapor deposition, and then sputtered and deposited onto the surface of the photoresist film layer. The target material is silicon or silicon dioxide. The physical vapor deposition method is beneficial to form a dense material layer and improve the electrical properties of the material layer.
[0060] Preferably, forming a material layer on the photoresist film layer by vapor deposition method comprises:
[0061] The precursor gas is introduced into the reaction chamber to cause a chemical reaction, so that the product of the chemical reaction adheres and deposits on the surface of the photoresist film layer to form a material layer. Silicon carbide or silicon nitride gas is used as a precursor gas and introduced into the reaction chamber. Silicon carbide or silicon nitride gas is deposited on the surface of the photoresist film layer by using a laser.
[0062] Preferably, heating the epitaxial wafer to a temperature not less than 1000° C. comprises:
[0063] The epitaxial wafer is heated by a radiation heat source of a specific wavelength, so that the temperature of the epitaxial wafer is uniformly increased to 1000°C-1200°C. The wavelength of the radiation heat source is 0.3 micron-0.4 micron, which can heat the epitaxial wafer in minutes.
[0064] Preferably, baking the epitaxial wafer at a temperature of 1000° C. to 1300° C. comprises:
[0065] The epitaxial wafer is continuously heated by a radiation heat source and then annealed and cooled by an RTP process, which is beneficial to repairing defects in the material layer during the annealing process, arranging impurity atoms and misaligned carriers in the material layer, and increasing the concentration of electrons and holes in the material layer and the mobility of carriers after annealing, thereby improving the conductivity.
[0066] The present invention also provides a silicon epitaxial wafer (not shown), which is prepared by the method for reducing the warpage of silicon wafer after epitaxy as in the above scheme. By heating the epitaxial wafer with a radiation heat source of a specific wavelength, the epitaxial wafer can be quickly heated, and secondary high-temperature heating of the epitaxial wafer is achieved. After the high-temperature heating is completed, the subsequent parameter growth is not affected. At the same time, by repairing the defects of the material layer after the secondary high-temperature heating, the impurity atoms and the misaligned carriers in the material layer can be arranged, which greatly reduces the warpage of the epitaxial wafer, thereby effectively improving the anti-warping ability of the epitaxial wafer.
[0067] Preferably, the warpage of the silicon epitaxial wafer is 2 to 29, compared with the warpage of 35 to 60 of the epitaxial wafer manufactured by the traditional epitaxial wafer manufacturing method, the method provided by the present invention can effectively reduce the warpage of the epitaxial wafer, while having low cost and simple steps.
[0068] The above are only preferred specific implementation modes of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical solutions and inventive concepts of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.
Claims
1. A method for reducing the warpage of silicon wafers after epitaxy, characterized in that: Providing a silicon single wafer substrate; Fabricating a photoresist film layer on the silicon single wafer substrate; Baking the photoresist film layer at a temperature of 100° C. to 150° C. for 3 minutes to 6 minutes; forming a material layer on the thin film layer by a vapor deposition method to produce an epitaxial wafer; Heating the epitaxial wafer to a temperature not lower than 1000° C.; The epitaxial wafer is baked at a temperature of 1000°C-1300°C, and the baking time is 10 minutes-20 minutes.
2. The method for reducing the warpage of silicon wafer after epitaxy according to claim 1, characterized in that: Providing a silicon single wafer substrate comprises: The surface of the silicon single crystal substrate is cleaned, and the cleaned surface of the silicon single crystal substrate is dried to ensure that there is no water mark on the surface of the silicon single crystal substrate.
3. The method for reducing the warpage of silicon wafer after epitaxy according to claim 1, characterized in that: The step of manufacturing a photoresist film layer on the silicon single wafer substrate comprises: The photoresist dripped on the silicon single wafer substrate is rotated at high speed. During the rotation, the photoresist dripped is coated on the surface of the silicon single wafer substrate to obtain a photoresist film layer, and a patterned photoresist layer is produced by exposure.
4. The method for reducing the warpage of silicon wafer after epitaxy according to claim 3, characterized in that: The baking of the photoresist film layer comprises: The photoresist film layer is subjected to a first baking, a second baking and a third baking. The baking temperature used in the first baking is 100°C-110°C, and the baking duration is 1 minute-2 minutes. The first baking is used to remove the solvent in the photoresist film layer and reduce the solvent residue. The baking temperature used in the second baking is 100°C-110°C, and the baking duration is 1 minute-2 minutes. The second baking is used to bake the photoresist film layer after exposure. The baking temperature used in the third baking is 110°C-150°C, and the baking duration is 1 minute-2 minutes. The third baking is used to reduce the residual stress in the photoresist film layer.
5. The method for reducing the warpage of silicon wafer after epitaxy according to claim 1, characterized in that: The forming of a material layer on the photoresist film layer by using a vapor deposition method comprises: Under vacuum conditions, the target material is converted into gas or plasma by physical vapor deposition, and then sputtered and deposited onto the surface of the photoresist film layer.
6. The method for reducing the warpage of silicon wafer after epitaxy according to claim 1, characterized in that: The forming of a material layer on the photoresist film layer by using a vapor deposition method comprises: The precursor gas is introduced into the reaction chamber to cause a chemical reaction, so that the product of the chemical reaction is attached and deposited on the surface of the photoresist film layer to form a material layer.
7. The method for reducing the warpage of silicon wafer after epitaxy according to claim 1, characterized in that: The step of heating the epitaxial wafer to a temperature not lower than 1000° C. comprises: The epitaxial wafer is heated by a radiation heat source of a specific wavelength, so that the temperature of the epitaxial wafer is uniformly increased to 1000°C-1200°C.
8. The method for reducing the warpage of silicon wafer after epitaxy according to claim 7, characterized in that: The method of baking the epitaxial wafer at a temperature of 1000° C. to 1300° C. comprises: The epitaxial wafer is continuously heated by a radiation heat source and then annealed and cooled by an RTP process.
9. A silicon epitaxial wafer, characterized in that: The method for reducing the warpage of a silicon wafer after epitaxy is used to prepare the silicon wafer.
10. The silicon epitaxial wafer according to claim 9, characterized in that: The warpage of the silicon epitaxial wafer is 2-29.