Secondary electron emission structure for weak ion signal amplification based on silicon wafer and multiplier

Abstract

The invention belongs to the technical field of magnetic separation state cesium atomic clocks, and particularly relates to a secondary electron emission structure for weak ion signal amplification based on a silicon wafer and a multiplier. The secondary electron emission structure comprises a rectangular silicon wafer, electrode plates and an acceleration grid electrode, the electrode plates are fixed at two ends of the rectangular silicon wafer, and the acceleration grid electrode is connected with the electrode plates; the rectangular silicon wafer with the electrode plates at the two ends and the acceleration grid form a multiplication stage; wherein the surface of the rectangular silicon wafer is plated with a composite secondary electron emission film, and the composite secondary electron emission film is activated before use.

Description

Technical Field

[0001] The invention belongs to the technical field of magnetically selected cesium atomic clocks, and in particular relates to a secondary electron emission structure and a multiplier for amplifying weak ion signals based on a silicon wafer. Background Art

[0002] The magnetically selected cesium atomic microwave clock is a first-class frequency standard device that has been widely used in commercial applications, including timekeeping, frequency measurement, navigation communication, and scientific research. Further reducing the cost of magnetically selected cesium atomic clocks and improving their performance, lifespan, and reliability are the main technical approaches to achieve wider and more lasting applications. Among them, the box-grid multiplier is a key component of the magnetically selected cesium atomic clock, which has an important impact on the cost, performance, and lifespan of the magnetically selected cesium atomic clock.

[0003] The box-grid multiplier for magnetically selected cesium atomic clocks usually includes an arc-shaped dynode with a grid, a collector, a ceramic plate, a voltage divider resistor, etc. Among them, the secondary electron-emitting film is mainly MgO, and the current mainstream methods are silver-magnesium alloy oxidation and magnetron sputtering (Li Jie, Research on Performance Improvement Technology of Separated Dynode Electron Multiplier, Vacuum Electronic Technology, 2023; Wang Haodong, A Preparation Method for Magnesium Oxide Secondary Emitter). At present, the existing MgO box-grid multiplier has problems such as complex structure and manufacturing process, and high cost. Patents CN114395747B "A high emission coefficient bombardment resistant secondary electron emission film structure and preparation method", CN117524829A "A high gain electron multiplier and its manufacturing method", CN116978769A "A three-dimensionally arranged multi-stage dynode multiplication structure and electron multiplier containing the same", CN 114446762A "A long-life electron multiplier for cesium clock" etc. illustrate the complexity of MgO multilayer films. The difficulties include multilayer film design, mixed coating of oxides and metals, complex dynode structure, voltage divider resistor welding and lengthy process flow.

[0004] For example, the existing MgO box-grid multiplier requires to shorten the assembly time after magnetron sputtering coating as much as possible. Patent CN109243959B "A structure and assembly method of an electron multiplier" uses planar voltage divider resistors, planar transition electrodes and other methods to reduce welding work. Patent CN 112185784B "An assembly tool and assembly method of an electron multiplier dynode" designs the key dynode assembly tool. Patent CN110828259B "A tool for rapid and accurate assembly of an electron multiplier" designs the assembly tool of the overall structure. In addition, the MgO box-grid multiplier basically adopts the production method of making before use, and it is impossible to use batch production to reduce costs. For example, patent CN 115783519A "An electron multiplier storage device and storage method" shows the difference in secondary electron emission coefficients between atmospheric storage, storage in a storage device and a newly prepared MgO film. The best performance is still the newly prepared MgO film. Summary of the invention

[0005] The present application provides a secondary electron emission structure for weak ion signal amplification based on a silicon wafer and an electron multiplier thereof, which can solve the problems of complex structure and process and high cost of the multiplier for magnetically selected cesium atomic clocks.

[0006] The technical solution for implementing the present invention is as follows:

[0007] In the first aspect, an embodiment of the present application is a secondary electron emission structure for amplifying weak ion signals based on a silicon wafer, comprising a rectangular silicon wafer, an electrode sheet and an accelerating gate, wherein the electrode sheets are fixed at both ends of the rectangular silicon wafer, and the accelerating gate is connected to the electrode sheets; the rectangular silicon wafer with electrode sheets at both ends and the accelerating gate constitute a multiplication stage; wherein: a composite secondary electron emission film is coated on the surface of the rectangular silicon wafer, and the composite secondary electron emission film is activated before use.

[0008] Furthermore, the resistivity of the rectangular silicon wafer of the present invention is 2.3 x 10 5 The resistance between the electrodes at both ends is about 0.5MΩ~10MΩ.

[0009] Furthermore, one surface of the rectangular silicon wafer of the present invention is pre-polished to a roughness better than 2 nm and is used for coating a composite secondary electron emission film.

[0010] Furthermore, before the composite secondary electron emission film is plated on the rectangular silicon wafer of the present invention, the two ends of the fixed electrode sheet are pasted with polyimide films, and the polyimide films are torn off after the coating is completed.

[0011] Furthermore, the rectangular silicon wafer described in the present invention is coated with a full-metal composite secondary electron emission film on the polishing surface, which is, from the silicon crystal surface, a first layer of Mg film, a second layer of Ag film or Au film, and a third layer of Mg film; the thickness of the first layer of Mg film of the composite secondary electron emission film is 20 to 40 nm, the thickness of the second layer of Ag film or Au film is 20 to 30 nm, and the thickness of the third layer of Mg film is 20 to 40 nm.

[0012] Furthermore, before coating the composite secondary electron emission film, the rectangular silicon wafer of the present invention is pasted with polyimide film at both ends of the electrode sheet where it is needed to be fixed, and the polyimide film is torn off after coating to ensure that there is no composite secondary electron emission film on the mounting surface of the electrode sheet.

[0013] Furthermore, the composite secondary electron emission film of the present invention is activated before use, that is, maintained at 400-500° C. and 10-1000 Pa of CO 2 or O 2 for 1-12 hours.

[0014] Furthermore, the electrode sheet of the present invention is integrated with the accelerating grid.

[0015] In the second aspect, an embodiment of the present application is a multiplier for a magnetically selected cesium atomic clock that uses a secondary electron emission structure for amplifying weak ion signals on a silicon wafer, including multiple multiplier stages formed by the secondary electron emission structure, a collecting pole, a ceramic plate, a fixing stud, a magnetic shielding shell, a dynode electrode lead and a signal line. The multiple multiplier stages are sequentially installed between two ceramic plates, the ceramic plates are fixed with multiple fixing studs, and the outermost layer is wrapped with a magnetic shielding shell, leaving only the dynode electrode leads, the signal output line and the ion entrance hole.

[0016] Furthermore, in two adjacent secondary electron emission structures, the output accelerating gate in the previous emission structure is aligned with the input accelerating gate of the next emission structure, and the output electrode of the previous emission structure is connected to the input electrode of the next emission structure.

[0017] Beneficial effects:

[0018] First, the present application adopts silicon wafers and composite secondary electron emission films. The polishing cost of silicon wafers is low, and the surface roughness reaches the sub-nanometer level. It can effectively improve the roughness of the composite secondary electron emission film and increase the amplification factor. The resistance of the silicon wafer itself is used to form a voltage divider to reduce the use of discrete resistors, simplify the structure, and increase the operating temperature of the multiplier. The pre-plated composite secondary electron emission film is a layered structure of all-metal materials, which is simple to plate and activated before use. It solves the contradiction between batch production and single use of multipliers, shortens the exposure time of the multiplier to the atmosphere, improves performance and life, and the multiplier has a simple structure, can be assembled in batches, has high reliability, and greatly reduces costs.

[0019] Second, the secondary electron emission structure of the multiplier is not activated during assembly, so no special protection is required and multiple pieces can be manufactured and assembled in one batch. It is activated before being installed on the magnetically selected cesium atomic clock, greatly shortening the time the multiplier is exposed to the atmosphere before use. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 Schematic diagram of a silicon wafer-based secondary electron emission structure provided according to an embodiment of the present application, including (a) a coated silicon wafer with an electrode sheet, (b) an accelerating gate, (c) a silicon wafer dynode, and (d) a silicon wafer with a composite secondary electron emission film coated on the surface;

[0022] Figure 2 A pre-plated composite secondary electron emission thin film structure is provided according to an embodiment of the present application;

[0023] Figure 3 Schematic diagram of an electron multiplier based on a silicon wafer secondary electron emission structure provided according to an embodiment of the present application, including (a) a top view, (b) a bottom view and (c) a front view;

[0024] Figure 4 A schematic diagram of a secondary electron emission structure based on a silicon wafer and an accelerating gate integrated type and an integrated electron multiplier thereof provided according to an embodiment of the present application, including (a) a front view of the secondary electron emission structure integrated with a silicon wafer and an accelerating gate, (b) a top view of the secondary electron emission structure integrated with a silicon wafer and an accelerating gate, (c) a top view of the integrated electron multiplier, and (d) a bottom view of the integrated electron multiplier;

[0025] Figure 5 Silicon wafer with electrodes, (a) two-end electrodes, (b) three-electrode, (c) ring electrode, (d) two-end electrode equipotential lines, (e) three-electrode equipotential lines, (f) ring electrode equipotential lines;

[0026] Figure 6 It is a secondary electron emission structure of a silicon wafer substrate;

[0027] Figure 7 It is the secondary emission of electrons incident on the dynode of the silicon wafer substrate;

[0028] Figure 8 It is the secondary emission of electrons incident on the two-stage cascaded silicon wafer substrate dynode;

[0029] Fig. 9 Cesium ions are incident on a 10-stage cascade of silicon wafer substrate dynode multipliers.

[0030] In the figure: 1-rectangular silicon wafer, 2-electrode sheet, 3-accelerating grid, 4-connection between electrode sheet and accelerating grid, 5-polished surface of rectangular silicon wafer, 6-composite secondary electron emission film, 21-first layer of Mg film, 22-second layer of Ag or Au film, 23-third layer of Mg film, 31-first silicon wafer multiplication stage, 32-second silicon wafer multiplication stage, 33-third silicon wafer multiplication stage, 34-fourth silicon wafer multiplication stage, 35-fifth silicon wafer multiplication stage, 36-sixth silicon wafer multiplication stage, 37-seventh silicon wafer multiplication stage, 38-eighth silicon wafer multiplication stage, 39-ninth silicon wafer multiplication stage, 40-final silicon wafer multiplication stage, 41-collecting pole, 42-upper ceramic plate, 43-lower ceramic plate, 44-fixing stud, 45-magnetic shielding shell , 46-first-stage silicon wafer multiplication stage lead, 47-final silicon wafer multiplication stage lead, 48-signal line, 49-ion inflow perforation; 51-integrated acceleration gate; 61-first-stage silicon wafer integrated multiplication stage, 62-second-stage silicon wafer integrated multiplication stage, 63-third-stage silicon wafer integrated multiplication stage, 64-fourth-stage silicon wafer integrated multiplication stage, 65-fifth-stage silicon wafer integrated multiplication stage, 66-sixth-stage silicon wafer integrated multiplication stage, 67-seventh-stage silicon wafer integrated multiplication stage, 68-eighth-stage silicon wafer integrated multiplication stage, 69-ninth-stage silicon wafer integrated multiplication stage, 70-final silicon wafer integrated multiplication stage, 71-input lead, 72-input electrode, 73-silicon wafer, 74-output electrode, 75-output lead, 76-acceleration gate. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0032] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0033] In the present application, the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings. These terms are mainly used to better describe the present application and its embodiments, and are not used to limit the indicated devices, elements or components to have a specific orientation, or to be constructed and operated in a specific orientation.

[0034] In addition, some of the above terms may be used to express other meanings in addition to indicating orientation or positional relationship. For example, the term "on" may also be used to express a certain dependency or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in this application can be understood according to specific circumstances.

[0035] In addition, the term "plurality" shall mean two or more.

[0036] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0037] like Figure 1 As shown, the present application provides a secondary electron emission structure for weak cesium ion signal amplification based on a silicon wafer, namely a silicon wafer dynode, comprising a rectangular silicon wafer 1, an electrode sheet 2 and an accelerating gate 3, wherein: the substrate of the rectangular silicon wafer 1 is a silicon material with a resistivity of 2.3 x 10 5Ω·cm, and the resistance formed between the electrode sheets 2 at both ends is 0.5MΩ~10MΩ; the rectangular silicon wafer 1 is polished on one side to form a polished surface 5, and then a composite secondary electron emission film 6 is plated on the polished surface 5 by magnetron sputtering; before the rectangular silicon wafer 1 is plated with the composite secondary electron emission film 6, it is necessary to stick a polyimide film near the two ends of the electrode sheet 2, and the polyimide film is torn off after the coating is completed to ensure that there is no composite secondary electron emission film 6 on the mounting surface near the electrode sheet 2. The rectangular silicon wafer 1 and the electrode sheet 2 can be connected and fixed by laser welding, brazing and other forms, and are suitable for working and using under vacuum and high temperature conditions.

[0038] like Figure 2 As shown, the composite secondary electron emission film 6 includes three layers, namely, a first layer of Mg film 21, a second layer of Ag film or Au film 22, and a third layer of Mg film 23; the thickness of the first layer of Mg film 21 is 20-40nm, the thickness of the second layer of Ag film or Au film 22 is 20-30nm, and the thickness of the third layer of Mg film 23 is 20-40nm; the composite secondary electron emission film is a metal film, which can be used for assembly and long-term storage after plating, and activated before use. The activation method is to maintain (1-12) hours under the conditions of 400℃-500℃, 10Pa-1000Pa CO2 or O2 or even CO2 / O2 combination atmosphere; wherein, when using CO2, it is recommended to maintain 400℃, 1000Pa, and maintain for 12 hours, or when using O2, it is recommended to maintain 500℃, 100Pa, and maintain for 1 hour.

[0039] Specifically, the embodiment of the present application also provides a 10-stage magnetically selected cesium atomic clock multiplier using a secondary electron emission structure for amplifying weak ion signals based on a silicon wafer, such as Figure 3 As shown, it includes 10 silicon wafer multiplier stages (31-40) formed by a secondary electron emission structure, a collecting electrode 41, an upper ceramic plate 42, a lower ceramic plate 43, a fixing stud 44, a magnetic shielding shell 45, a first silicon wafer multiplier stage lead 46, a last silicon wafer multiplier stage lead 47 and a signal line 48. Multiple silicon wafer multiplier stages are sequentially installed between the upper ceramic plate 42 and the lower ceramic plate 43. Holes are opened on the ceramic plate for inserting the various pins extending from the electrode sheet 2. The ceramic plate is fixed with multiple fixing studs, and the outermost layer is wrapped with a magnetic shielding shell, leaving only the first silicon wafer multiplier stage lead 46, the last silicon wafer multiplier stage lead 47, the signal output line 48 and the ion inflow perforation 49.

[0040] Furthermore, the secondary electron emission structure of the 10-stage multiplier is not activated when it is stored before assembly and use, so no special protection is required and multiple pieces can be manufactured and assembled in one batch. When in use, it needs to be installed in front of the magnetically selected cesium atomic clock for activation, which greatly shortens the time the multiplier is directly exposed to the atmosphere before use, improves the amplification factor and its attenuation, and enhances the performance and life of the multiplier for the magnetically selected cesium atomic clock.

[0041] Furthermore, the multiplier based on the silicon wafer multiplier can be designed in stages according to the required magnification. For example, for the ion flow signal, the magnification of the first silicon wafer multiplier is calculated as 0.8, and the magnification of the second silicon wafer multiplier is calculated as 4 times, so 10 stages can reach about 210,000 times. If the required magnification is 50,000 times, a 9-stage silicon wafer multiplier can be selected, the last silicon wafer multiplier of the 10-stage silicon wafer multiplier can be reduced, and the collector can be installed at the original last silicon wafer multiplier position.

[0042] The present application also provides another embodiment of a 10-stage magnetically selected cesium atomic clock multiplier based on a secondary electron emission structure for amplifying weak ion signals of a silicon wafer, such as Figure 4 As shown, the coated silicon wafer 1 with electrode sheets, the electrode sheet 2 and the integrated accelerating gate 51 are integrated together to form an integrated dynode based on a silicon wafer. Compared with the ordinary accelerating gate 3, the structure of the integrated accelerating gate 51 can be fixedly connected by welding the electrode sheets, and there is no extended pin similar to the electrode sheet 2. The number of fixing holes on the ceramic plate required for further assembly to form a multiplier is reduced by half, and the number of connections between the integrated dynodes is also reduced by half, which has the advantages of higher integration and better consistency.

[0043] More specifically, the embodiments of the present application provide a secondary electron emission structure for amplifying weak ion signals based on a silicon wafer and a multiplier using the structure. The silicon wafer realizes the voltage divider resistor function to increase the operating temperature of the multiplier. The silicon wafer has been batch polished and has good roughness. The composite secondary electron emission film is a metal material before activation and can be batch plated and stored for a long time. It is only activated before use. Therefore, the silicon wafer multiplier can be mass-produced without voltage divider resistors and complex components, effectively reducing costs. The entire multiplier has a compact structure, good consistency, and high reliability, which improves the performance and life of the multiplier for magnetically selected cesium atomic clocks.

[0044] The present invention is explained by taking the design of a silicon wafer electron multiplier for a cesium atomic clock as an example.

[0045] Usually, the electron multiplier used in cesium atomic clocks is a box-grid structure composed of 9 1 / 4 arc-surface stainless steel dynodes (i.e., the secondary electron emission structure mentioned above). Each dynode is either made of stainless steel as the base material, with a secondary electron emission film plated on its surface, or made of silver-magnesium alloy or beryllium-copper alloy as the base material, with a surface secondary electron emission film formed through an oxidation process. Each stage is connected by a 6M~8MΩ discrete resistor, with a total gain of ≥100,000 times, which can amplify a 1pA current signal to 100nA. Therefore, a gain of 100,000 times is set as the design goal of silicon chip electron multipliers.

[0046] Silicon wafers are semiconductor materials that can form resistors themselves. Therefore, the electron multiplier that uses high-resistance silicon wafers as the base material to form the dynode does not require discrete resistors. R represents resistance, ρ represents resistivity, S represents cross-sectional area (= thickness × width), and L represents length. The resistance calculation formula of silicon wafers is R = ρL / S. The resistivity range of high-resistance silicon wafers is relatively wide, usually within 1 x 10 3 ~1ⅹ10 6 Ω·cm, the resistivity range of the silicon wafer selected for making the electron multiplier in the present invention is 1×10 5 Ω·cm~1ⅹ10 6 Ω·cm. For example, suppose the resistivity of a high-resistance silicon wafer is 2.3×10 5 Ω·cm, thickness is 0.775mm, width is 10mm, then the length is 20mm to obtain a resistance of 5.93MΩ. The actual resistance can be directly measured between the electrodes of the silicon wafer using a multimeter.

[0047] The gate and base of the stainless steel or silver-magnesium alloy dynode are both metal and equipotential, with almost no electric field inside, which will not deflect, converge or diverge the atomic beam. Unlike the stainless steel or silver-magnesium alloy base itself, the dynode formed with the silicon wafer as the base has a potential difference, forming an internal electric field. At the same time, it is necessary to design an electrode on the back of the silicon wafer (the front of the silicon wafer is a plated secondary electron emission functional film) to apply voltage and form a current flowing through the silicon wafer.

[0048] The present invention proposes the following three silicon wafer electrode shapes, positions and potential equipotential lines: Figure 5 As shown. Among them, the equipotential lines are horizontal when there are two-end electrodes, the equipotential lines are also horizontal and symmetrical when there are three electrodes, and the equipotential lines are annular when there are annular electrodes; according to the analysis of the equipotential lines, it can be inferred that the annular electrode has a strong effect on the convergence of the electron beam to the center, and the three electrodes have a strong effect on the divergence of the electron beam to the two ends. When there are two-end electrodes, the electron beam is biased toward the output electrode. The deflection, convergence or divergence of the electron beam by the silicon wafer dynode inside the electron multiplier will have a beneficial effect on the life and gain of the secondary electron emission film, and improve the performance of the electron multiplier. Here, the two-end electrodes are taken as an example for the next step of design.

[0049] In order to accelerate the incident electrons or ions, the dynode can also include an accelerating grid. For the cesium atomic clock, the accelerating grid of the silicon wafer dynode can only be connected to the input electrode. Here, a silicon wafer with electrodes at both ends is used. The three-dimensional diagram of the dynode with the accelerating grid is shown in Figure 6 As shown,

[0050] The dynodes of stainless steel or silver-magnesium alloy substrates are all metal, and all surfaces are equipotential. However, on the dynodes of silicon wafer substrates, the accelerating grid and the input electrode connected to it are equipotential, and the voltages of the silicon wafer surface are different except for the surface with electrodes. The potential of the input electrode is low (large absolute value), and the potential of the output electrode is high (small absolute value). The potential on the surface of the silicon wafer changes linearly from the input electrode potential to the output electrode potential.

[0051] The front of the silicon wafer is coated with a secondary electron emission film. When the electron beam is incident on the accelerating grid of a silicon wafer dynode, the electrons tend to fall to the output electrode side with a larger potential difference, which has a deflection and convergence effect on the incident electron beam, and at the same time, multiple secondary electrons are generated on the secondary electron emission film on the front of the silicon wafer. According to the test, one electron can generate 4 to 5 secondary electrons under a 200V voltage difference. Figure 7 shown.

[0052] Furthermore, two silicon wafer dynodes are cascaded, that is, the output acceleration gate of the previous dynode is directly opposite to the input acceleration gate of the next dynode, and the output electrode of the previous dynode is connected to the input electrode of the next stage with a wire, such as Figure 8 As shown, after two levels of amplification, the incident beam can be amplified 16 to 25 times.

[0053] By analogy, with each additional cascade stage, the gain is amplified by 4 to 5 times, so theoretically, 10 stages can reach at least 4 10 = 1048576 times, using secondary emission to amplify 1pA current to 1μA current, which is much smaller than the current flowing through the silicon wafer (200V / 5.93MΩ=33.7μA). 10-stage cascade silicon wafer multiplier can be used Fig. 9 It means that the resistance voltage division of the silicon chip itself is used, and the position of the electrodes on the silicon chip is relied upon to deflect, converge or diverge the electron beam, thereby improving the performance indicators such as the gain and life of the electron multiplier.

[0054] The purpose of the present invention is to address the deficiencies of the above-mentioned technologies, and to reduce the manufacturing cost of the multiplier while keeping the performance basically unchanged from the perspectives of simplifying the secondary electron multiplier structure, the multilayer MgO mixed film structure and the simultaneous production of multiple pieces.

[0055] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A secondary electron emission structure for amplifying weak ion signals based on a silicon wafer, characterized in that: It includes a rectangular silicon wafer, an electrode sheet and an accelerating grid, wherein the electrode sheets are fixed at both ends of the rectangular silicon wafer, and the accelerating grid is connected to the electrode sheets; the rectangular silicon wafer with electrode sheets at both ends and the accelerating grid constitute a multiplication stage; wherein: the surface of the rectangular silicon wafer is coated with a composite secondary electron emission film, and the composite secondary electron emission film is activated before use.

2. The secondary electron emission structure for amplifying weak ion signals based on a silicon wafer according to claim 1, characterized in that: The resistivity of the rectangular silicon wafer is 2.3 x 10 5 The resistance between the electrodes at both ends is about 0.5MΩ~10MΩ.

3. The secondary electron emission structure for amplifying weak ion signals based on a silicon wafer according to claim 1, characterized in that: One surface of the rectangular silicon wafer is pre-polished to a roughness better than 2 nm and is used for coating a composite secondary electron emission film.

4. The secondary electron emission structure for amplifying weak ion signals based on a silicon wafer according to claim 1, characterized in that: Before the rectangular silicon wafer is plated with the composite secondary electron emission film, the two ends of the electrode sheet are fixed with polyimide films, and the polyimide films are torn off after the coating is completed.

5. The secondary electron emission structure for amplifying weak ion signals based on a silicon wafer according to claim 1, characterized in that: The rectangular silicon wafer is plated with a full metal composite secondary electron emission film on the polished surface, which is sequentially arranged from the silicon crystal surface with a first layer of Mg film, a second layer of Ag film or Au film, and a third layer of Mg film; the first layer of Mg film of the composite secondary electron emission film has a thickness of 20 to 40 nm, the second layer of Ag film or Au film has a thickness of 20 to 30 nm, and the third layer of Mg film has a thickness of 20 to 40 nm.

6. The secondary electron emission structure for amplifying weak ion signals based on a silicon wafer according to claim 1, characterized in that: Before coating the composite secondary electron emission film on the rectangular silicon wafer, polyimide film is pasted on the two ends of the electrode sheet where it is needed to be fixed. After coating, the polyimide film is torn off to ensure that there is no composite secondary electron emission film on the mounting surface of the electrode sheet.

7. The secondary electron emission structure for amplifying weak ion signals based on a silicon wafer according to claim 1, characterized in that: The composite secondary electron emission film is activated before use, that is, maintained at 400-500° C. and 10-1000 Pa of CO 2 or O 2 for 1-12 hours.

8. The secondary electron emission structure for amplifying weak ion signals based on a silicon wafer according to claim 1, characterized in that: The electrode sheet is integrated with the accelerating grid.

9. A multiplier based on a secondary electron emission structure for amplifying weak ion signals of a silicon wafer, using the secondary electron emission structure as claimed in any one of claims 1 to 8, characterized in that: It includes multiple multiplier stages formed by secondary electron emission structure, collecting poles, ceramic plates, fixing studs, magnetic shielding shells, multiplier electrode leads and signal lines. The multiple multiplier stages are installed in sequence between two ceramic plates. The ceramic plates are fixed with multiple fixing studs. The outermost layer is wrapped with a magnetic shielding shell, leaving only the multiplier electrode leads, signal output lines and ion entrance holes.

10. The multiplier based on the secondary electron emission structure for amplifying weak ion signals of silicon wafer according to claim 9, characterized in that: In two adjacent secondary electron emission structures, the output accelerating gate in the previous emission structure is aligned with the input accelerating gate in the next emission structure, and the output electrode of the previous emission structure is connected to the input electrode of the next emission structure.

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