PPP-B2b-based high-precision time service method
By using the combination of PPP-B2b technology and constant temperature crystal oscillator + DDS clock adjustment module in the Beidou satellite navigation system, a high-precision timing method for forming a closed loop is solved, and the problem of high-precision timing in the existing technology depends on GPS and the Internet, achieving high-precision timing at nanosecond level and reducing hardware costs.
Patent Information
- Application Number
- CN202411672528.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-21
- Publication Date
- 2025-03-28
AI Technical Summary
The prior art relies on GPS systems and the Internet to obtain precise correction information in high-precision timing. The hardware design is complex and expensive, and the traditional timing methods have problems of quantization error and inherent error.
The PPP-B2b technology of the Beidou satellite navigation system is adopted, combined with the constant temperature crystal oscillator and DDS clock adjustment module, and a high-precision timing method of a closed loop is formed. The high-precision time difference information output by the PPP solution module and the frequency adjustment of DDS are achieved to achieve fine clock and frequency adjustment.
It realizes nanosecond-level high-precision timing that does not rely on GPS and the Internet, reduces hardware costs, avoids quantization errors in second pulse output, and improves timing accuracy and stability.
Smart Images
Figure CN119717474A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of Global Navigation Satellite System (GNSS), and relates to a high-precision time service method based on Precise Point Positioning (PPP) technology. The invention specifically describes a high-precision time service method which uses Beidou Navigation Satellite System (BDS) observations and BDS-B2b precision correction information to perform PPP solution, and forms a closed loop with a constant temperature crystal oscillator + DDS clock adjustment module. Background Art
[0002] GNSS is a satellite-based navigation and positioning system that can provide users with 3D coordinates, speed and time information on the Earth's surface or near-Earth space. It mainly includes China's BDS, the United States' Global Positioning System (GPS), the European Union's Galileo Satellite Navigation System (Galileo) and Russia's GLONASS Satellite Navigation System (GLONASS). The single point positioning (SPP) service accuracy provided by major satellite navigation systems is generally within 10 meters. Limited by the single point positioning accuracy, the timing accuracy can generally only reach within 20ns, which can no longer meet the application requirements of some occasions. Unlike single point positioning, PPP positioning technology can achieve higher positioning accuracy. At present, high-precision timing terminals based on PPP positioning technology have appeared, but generally need to use the Internet to obtain correction information such as precise ephemeris and precise clock error.
[0003] The BeiDou-3 global satellite navigation system (BDS-3) independently developed by my country was officially launched on July 31, 2020. The B2b frequency geostationary orbit (GEO) satellite can provide real-time PPP services for China and surrounding areas. After 30 minutes of convergence time, the positioning accuracy can reach decimeter level, which makes it possible to achieve timing accuracy within nanoseconds. For a long time, GPS has taken the lead in satellite navigation applications. Most high-precision positioning algorithms and timing algorithms are based on GPS. It is of great significance to study high-precision positioning algorithms and timing algorithms based on pure BDS.
[0004] The improvement of timing accuracy has brought higher requirements to hardware design solutions, clock adjustment strategies and pulse-per-second output control. Atomic clocks have good clock characteristics. Some high-precision timing terminals use atomic clocks as clock input sources, but their cost is high, so it is necessary to seek lower-cost solutions. In addition, the baseband working clock of traditional satellite navigation timing terminals will not be infinitely high, which will introduce quantization errors, and high-precision timing must consider its impact. Conventional timing methods generally use the time difference information output by the positioning timing solution module to directly adjust the pulse-per-second output module. On the one hand, the time difference information is not filtered, resulting in the burr of the time difference being directly transmitted to the pulse-per-second output; on the other hand, the hysteresis of the pulse-per-second output module adjustment is not considered, that is, the time difference output by the positioning timing solution module is the time difference at the current moment. The time difference is given to the pulse-per-second output, which is actually the next pulse-per-second effective. As a result, the receiver clock frequency deviation is incorrectly converted to part of the device zero value. In essence, the conventional method is a first-order phase-locked loop structure that can track frequency step signals, but there are inherent errors. Summary of the invention
[0005] Traditional PPP-based high-precision timing terminals mostly rely on the GPS system and require the Internet to receive precise correction information. Atomic clocks are generally used as the system clock source, and the hardware design is complex and costly.
[0006] To solve the above problems, the present invention is achieved through the following technical solutions:
[0007] A high-precision timing method based on PPP-B2b, comprising the following steps:
[0008] Step 1: The BeiDou-3 baseband chip captures and tracks the B1C, B2a and B2b frequency signals, parses the message and locks the observations, and sends the CNAV-1 ephemeris, the carrier, pseudorange and Doppler observations of B1C+B2a, and the orbit correction, clock correction and inter-code deviation correction provided by the B2b PPP service to the PPP solution module. The PPP solution module performs iterative calculations to obtain the position, velocity, clock error and frequency deviation.
[0009] Step 2: Before the PPP solution module converges, it outputs rough frequency deviation and clock difference to adjust the DDS and second pulse output control module, and then outputs precise clock difference and frequency deviation to the loop filter; after the PPP solution module converges, it reduces the bandwidth of the loop filter, and the loop filter generates a frequency adjustment amount and outputs it to the DDS. The DDS generates a working clock according to the frequency adjustment amount and outputs it to the second pulse output control unit;
[0010] Step 3: The pulse-per-second output control unit uses the clock difference output by the PPP solution module and the working clock output by the DDS to output the precise local time of the receiver and the pulse-per-second that is aligned with the UTC time after being corrected by the BDT-UTC parameters.
[0011] Among them, the PPP solution module is equivalent to the frequency and phase detector, the constant temperature crystal oscillator + DDS combination is equivalent to the digital control oscillator, the loop filter is equivalent to the loop filter in the carrier loop, and a second-order frequency-locked loop is used to assist a third-order phase-locked loop structure.
[0012] Furthermore, step 2 specifically includes the following process:
[0013] Step 2.1, coarse frequency modulation stage: the PPP solution module converts the coarse frequency deviation unit into the DDS adjustment amount and outputs it to the DDS, gradually controlling the DDS output clock frequency within the set range;
[0014] Step 2.2, coarse phase adjustment stage: the PPP solution module outputs a rough clock error to adjust the second pulse output control unit, and aligns the second pulse to the Beidou time by adjusting the second pulse count;
[0015] Step 2.3, smooth transition stage: the PPP solution module outputs the clock error and frequency deviation to the loop filter, and the loop filter uses the clock error and frequency deviation to generate a frequency adjustment value and output it to the DDS; and the pulse-per-second output control unit period is set to a fixed value;
[0016] Step 2.4, stable tracking stage: After the PPP solution module converges, the bandwidth of the loop filter is reduced. After the bandwidth is reduced, the loop filter re-outputs the frequency adjustment amount to the DDS. The DDS generates a working clock according to the frequency adjustment amount and outputs it to the second pulse output control unit.
[0017] Compared with the prior art, the present invention has the following beneficial effects:
[0018] 1) The present invention does not rely on GPS and the Internet to achieve high-precision timing within nanoseconds.
[0019] 2) The present invention uses a clock solution of a constant temperature crystal oscillator + DDS, which not only reduces the cost, but also can achieve fine adjustment of the clock and frequency, avoiding the quantization error problem of the second pulse output.
[0020] 3) The present invention introduces the delay locked loop theory to form a closed loop, thereby improving the timing accuracy and stability. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 The figure is a block diagram of the PPP-B2b high-precision timing principle according to an embodiment of the present invention.
[0022] Figure 2 This is a block diagram of the third-order phase-locked loop principle assisted by a second-order frequency-locked loop according to an embodiment of the present invention. DETAILED DESCRIPTION
[0023] The present invention will be further explained below in conjunction with the accompanying drawings.
[0024] The principle block diagram of a high-precision timing method based on PPP-B2b described in the present invention is as follows Figure 1 As shown, the clock source of the scheme of the present invention is a constant temperature crystal oscillator, which has the same short-term stability characteristics as the rubidium atomic clock, but at a relatively low price. The main disadvantage of the constant temperature crystal oscillator compared to the rubidium atomic clock is the long-term stability, while the high-precision time difference information output by the PPP solution module can ensure the long-term stability of the system. In order to solve the quantization error problem output by the second pulse output control unit, a DDS chip that can achieve small step precision adjustment of the clock is adopted. The traditional timing scheme adjusts the delay by increasing or decreasing the second pulse count, which is essentially the adjustment of time. DDS finely adjusts the frequency of the clock source through digital frequency synthesis technology, which is essentially the adjustment of frequency, and realizes the adjustment of time by integrating the frequency over time. After the PPP solution module converges stably, the clock error will be a small range jitter near zero. Because the adjustment of time is achieved by adjusting the frequency through the DDS chip, it is no longer necessary to adjust the second pulse output module, thereby avoiding the quantization error problem.
[0025] In addition, the scheme of the present invention also adopts a filtering algorithm similar to a delay locked loop, the PPP solution module is similar to a frequency detector, the clock combination of a constant temperature crystal oscillator + DDS is similar to a numerically controlled oscillator (NCO), and the theory of loop filtering is introduced to form a closed loop, which can not only filter out certain noise items, but also consider the influence of high-order items of clock frequency on timing accuracy. The phase-locked loop and the frequency-locked loop have different characteristics. The phase-locked loop has high tracking accuracy but the loop is fragile, while the frequency-locked loop has slightly poor tracking accuracy but high loop robustness. Combining the two can give play to the advantages of both parties. Because the frequency difference output by the frequency-locked loop filter must be integrated before it can become the phase difference output by the phase-locked loop filter, the first-order frequency-locked loop is usually used to assist the second-order phase-locked loop, and the second-order frequency-locked loop is usually used to assist the third-order phase-locked loop. According to the relevant theory of phase-locked loop, the N-order phase-locked loop can accurately track the signal whose phase changes according to the N-1 power of time or lower power, and can also track the signal whose phase changes according to the N power of time, but it will produce a constant phase tracking error, but it cannot track the signal whose phase changes according to the N+1 power of time. In order to stably track the frequency ramp excitation, the scheme of the present invention adopts a second-order frequency-locked loop to assist the third-order phase-locked loop structure, and its principle block diagram is as follows Figure 2 As shown in the figure. s is the loop update period, w nf and w np are the characteristic frequencies of the second-order frequency-locked loop and the third-order phase-locked loop respectively, and a2, a3 and b3 are the corresponding loop parameters.
[0026] The optimal value scheme for loop filter parameters is shown in Table (1). In loop design, the noise bandwidth B is first determined based on loop performance and dynamic requirements.L Then, the various filtering parameters are determined according to Table (1). According to the Nyquist sampling theorem, the selection of the loop bandwidth must at least satisfy the following formula:
[0027]
[0028] In this article, T s The value is 1 second, so B L ≤0.5. Noise bandwidth B L The selection of is crucial to the tracking loop. Too high noise bandwidth will increase the noise entering the loop and affect the tracking performance. Too low noise bandwidth will lead to poor dynamic adaptability of the loop and easy loss of lock. The present invention adopts a variable bandwidth tracking strategy. When the PPP solution has not converged and the loop is in a smooth transition stage, a relatively large noise bandwidth is used, and B is selected. L =0.2; After the loop has been stably tracked for a period of time, it switches to narrow bandwidth tracking parameters and takes B L =0.08.
[0029] Table 1 Optimal value scheme for loop filter parameters
[0030]
[0031] The PPP solution module can stably output rough position and clock error, as well as relatively accurate speed and frequency deviation before convergence, but PPP convergence generally takes a long time. In order to quickly enter a stable tracking state after PPP convergence, it is necessary to apply rough clock error and frequency deviation to adjust the time and frequency to a relatively accurate state before PPP convergence. The specific time adjustment is divided into the following steps:
[0032] Step 1: The BeiDou-3 baseband chip captures and tracks the B1C, B2a and B2b frequency signals, parses the message and locks the observations, and sends the CNAV-1 ephemeris, the carrier, pseudorange and Doppler observations of B1C+B2a, and the orbit correction, clock correction and inter-code deviation correction provided by the B2b PPP service to the PPP solution module. The PPP solution module performs iterative calculations to obtain the position, velocity, clock error and frequency deviation.
[0033] Step 2: Before the PPP solution module converges, it outputs rough frequency deviation and clock difference to adjust the DDS and second pulse output control module, and then outputs precise clock difference and frequency deviation to the loop filter; after the PPP solution module converges, it reduces the bandwidth of the loop filter, and the loop filter generates a frequency adjustment amount and outputs it to the DDS. The DDS generates a working clock according to the frequency adjustment amount and outputs it to the second pulse output control unit; the specific control strategy is divided into the following steps:
[0034] Step 2.1, coarse frequency modulation stage. The PPP solution module can output a frequency deviation with an accuracy equivalent to 0.2m / s, and convert the frequency deviation unit into a DDS adjustment amount and give it to the DDS chip. Since the working clock of the Beidou-3 baseband chip is provided by the DDS chip, excessive frequency adjustment will cause the baseband tracking loop to lose lock or abnormality, so it is necessary to limit the amplitude of a single adjustment. Through a single small step, the DDS output clock frequency is gradually controlled to a range equivalent to 0.2m / s. Due to the error in the frequency deviation, the clock frequency deviation will oscillate slightly around the zero value.
[0035] Step 2.2, rough phase adjustment stage. After step 2.1, the DDS output frequency is close to the ideal frequency, and now it is time to adjust the second pulse output control unit. The PPP solution module outputs a rough clock deviation, and the second pulse can be aligned to the Beidou time by adjusting the second pulse count. Since there is still an error in the frequency, the second pulse adjustment amount will become approximately periodic. The second pulse output control unit is based on the limited working clock of the baseband chip and has granularity, so the output second pulse timing error will be a periodic sawtooth shape.
[0036] Step 2.3, smooth transition stage. After step 2.2, the DDS output frequency and pulse-per-second output time have been roughly aligned to the Beidou time. The PPP solution module is also close to convergence, and the smooth transition stage is started at this time. The pulse-per-second output control unit period is set to a fixed value and is no longer adjusted. The loop filter receives the more accurate clock error and frequency deviation information output by PPP, and outputs the frequency adjustment amount to the DDS. At this time, PPP has not fully converged, and the loop bandwidth is 0.2.
[0037] Step 2.4, stable tracking phase. The PPP convergence time based on the BDS-3 system is about 30 minutes. After PPP works for 30 minutes, the loop filter bandwidth is reduced to 0.08 to output a frequency adjustment with higher accuracy. After the bandwidth is reduced, the loop filter re-outputs the frequency adjustment to the DDS, and the DDS generates a working clock based on the frequency adjustment and outputs it to the pulse-per-second output control unit.
[0038] Step 3: The pulse-per-second output control unit uses the clock difference output by the PPP solution module and the working clock output by the DDS to output, on the one hand, the precise local time of the receiver, and on the other hand, the pulse-per-second that is aligned with the UTC (NTSC) time after being corrected by the BDT-UTC parameters.
[0039] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, it is apparent to those skilled in the art that several modifications and improvements may be made without departing from the principles of the present invention, and these modifications and improvements should also be considered to fall within the scope of protection of the present invention.
Claims
1. A high-precision timing method based on PPP-B2b, characterized in that: The following steps are included: Step 1: The BeiDou-3 baseband chip captures and tracks the B1C, B2a and B2b frequency signals, parses the message and locks the observations, and sends the CNAV-1 ephemeris, the carrier, pseudorange and Doppler observations of B1C+B2a, and the orbit correction, clock correction and inter-code deviation correction provided by the B2b PPP service to the PPP solution module. The PPP solution module performs iterative calculations to obtain the position, velocity, clock error and frequency deviation. Step 2: Before the PPP solution module converges, it outputs rough frequency deviation and clock difference to adjust the DDS and second pulse output control module, and then outputs precise clock difference and frequency deviation to the loop filter; after the PPP solution module converges, it reduces the bandwidth of the loop filter, and the loop filter generates a frequency adjustment amount and outputs it to the DDS. The DDS generates a working clock according to the frequency adjustment amount and outputs it to the second pulse output control unit; Step 3: The pulse-per-second output control unit uses the clock difference output by the PPP solution module and the working clock output by the DDS to output the precise local time of the receiver and the pulse-per-second that is aligned with the UTC time after being corrected by the BDT-UTC parameters.
2. According to claim 1, a high-precision timing method based on PPP-B2b is characterized in that: The PPP solution module is equivalent to a frequency detector and phase detector, the constant temperature crystal oscillator + DDS combination is equivalent to a digitally controlled oscillator, the loop filter is equivalent to the loop filter in the carrier loop, and a second-order frequency-locked loop is used to assist a third-order phase-locked loop structure.
3. According to the high-precision timing method based on PPP-B2b as claimed in claim 1, it is characterized in that: Step 2 specifically includes the following processes: Step 2.1, coarse frequency modulation stage: the PPP solution module converts the coarse frequency deviation unit into the DDS adjustment amount and outputs it to the DDS, gradually controlling the DDS output clock frequency within the set range; Step 2.2, coarse phase adjustment stage: the PPP solution module outputs a rough clock error to adjust the second pulse output control unit, and aligns the second pulse to the Beidou time by adjusting the second pulse count; Step 2.3, smooth transition stage: the PPP solution module outputs the clock error and frequency deviation to the loop filter, and the loop filter uses the clock error and frequency deviation to generate a frequency adjustment value and output it to the DDS; and the pulse-per-second output control unit period is set to a fixed value; Step 2.4, stable tracking stage: After the PPP solution module converges, the bandwidth of the loop filter is reduced. After the bandwidth is reduced, the loop filter re-outputs the frequency adjustment amount to the DDS. The DDS generates a working clock according to the frequency adjustment amount and outputs it to the second pulse output control unit.