Apparatus and method for adjusting skew between data and clock

Abstract

An apparatus and a method for adjusting skew between data and a clock are provided. An apparatus driven by a supply voltage includes a clock circuit that adjusts skew between data and a clock. The clock circuit performs a first loop operation through a first loop and a second loop operation through a second loop based on a phase difference between data and a clock. A first loop operation is performed until there is no phase difference between the data and the clock, and a second loop operation is performed until a first slope indicating a change in delay of the data with respect to the power supply voltage level and a second slope indicating a change in delay of the clock become the same as each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0129554 filed in the Korean Intellectual Property Office on September 26, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device, and more particularly, to an apparatus and method for adjusting a skew between data and a clock according to fluctuations in a power supply voltage. Background Art

[0004] Due to the increasing demand for the increased operating speed, increased data capacity and reduced power consumption of electronic systems, semiconductor memories that can be accessed faster, store more data and consume less power are being continuously developed. Semiconductor memories are usually controlled by providing commands, addresses and clocks to memory devices. Various commands, addresses and clocks can be provided by, for example, a memory controller. The commands can control the memory device to perform various memory operations, for example, a read operation for retrieving data from the memory device and a write operation for storing data in the memory device. The data associated with the command can be provided between the memory controller and the memory device at a known timing relative to the reception and / or transmission of the memory device.

[0005] The clock (e.g., DQS) provided to the memory device may be used to generate an internal clock signal that controls the timing of various internal circuits during memory operations. The memory device may capture signals received from the memory controller in response to the DQS clock (e.g., command, address, and / or data DQ), and synchronize the data DQ to be sent to the memory controller with the DQS clock. As the frequency of the DQS clock provided from the memory controller increases in accordance with the demand for high data transfer rates, it is important for the memory device to accurately capture the transmitted data DQ.

[0006] The memory device may capture data DQ sent from the memory controller in response to the received DQS clock. At this time, in order to prevent the data capture operation from malfunctioning due to external power supply noise, the memory device may be designed to perform the data capture operation using an internal voltage different from the external power supply. The memory device may generate an internal voltage derived from the external power supply by using an internal voltage generation circuit.

[0007] However, when a memory device captures data DQ in response to a DQS clock by using an internal voltage, the data capture operation may fail when internal voltage noise occurs. In addition, the memory device may consume power used to generate the internal voltage. Therefore, a data capture method that is safe from external power supply noise even when an external power supply is used instead of an internal voltage is needed. Summary of the invention

[0008] The present disclosure provides an apparatus and method for adjusting a skew between data and a clock according to fluctuations in a power supply voltage.

[0009] According to one aspect of the present invention, a device driven by a power supply voltage includes: a clock circuit, which includes: a clock delay scheduler; a first counting logic circuit; and a scheduler controller, wherein the clock circuit is configured to receive a clock signal and adjust the skew between a data signal and the clock signal; and a data input circuit, the data input circuit including a sampler circuit, the sampler circuit configured to receive the data signal and latch the data signal in response to a second clock signal provided by the clock delay scheduler, wherein a first loop includes the clock delay scheduler, the sampler circuit and the first counting logic circuit, and a second loop includes the scheduler controller and the clock delay scheduler, wherein the first counting logic circuit is configured to receive the data signal from the sampler circuit and generate a first counting code based on a phase difference between the clock signal and the data signal, wherein the clock delay scheduler is configured to adjust the delay of the clock signal based on a second counting code and generate the second clock signal, wherein the scheduler controller is configured to adjust the delay of the clock signal based on the first adjustment code and the second counting code The second counting code is generated by a second adjustment code, and wherein the clock circuit is further configured to: based on identifying a phase difference between the data signal and the clock signal, perform one or more first loop operations through the first loop until the phase difference is eliminated, obtain a first value of the first counting code by performing one or more of the one or more first loop operations when the level of the power supply voltage is a first power supply voltage level, and store the first value as the first adjustment code, obtain a second value of the first counting code by performing one or more of the one or more first loop operations when the level of the power supply voltage is a second power supply voltage level higher than the first power supply voltage level, and store the second value as the second adjustment code, and based on identifying a difference between a first slope representing a change in delay of the data signal relative to the first power supply voltage level and the second power supply voltage level and a second slope representing a change in delay of the clock signal, perform one or more second loop operations through the second loop until the first slope and the second slope are the same.

[0010] According to one aspect of the present invention, a device driven by a power supply voltage includes: a data input circuit, which includes a sampler circuit configured to receive a data signal and latch the data signal in response to a clock signal provided by a clock delay scheduler; a clock circuit, which includes: the clock delay scheduler; a clock buffer; a duty cycle corrector; a first logic circuit; and a scheduler controller, wherein the clock circuit is configured to: receive a first clock signal having a first swing width through the clock buffer, convert the first clock signal into a second clock signal amplified to a second swing width greater than the first swing width, and adjust a skew between the data signal and the second clock signal, wherein a first loop includes the clock delay scheduler, the duty cycle corrector, the sampler circuit, and a first counting logic circuit, and a second loop includes the scheduler controller and the clock delay scheduler, wherein the duty cycle corrector is configured to receive the first clock signal from the clock buffer and adjust the first clock signal based on a first counting code. A duty cycle of a first clock signal, wherein the first counting logic circuit is configured to receive the data signal from the sampler circuit and generate the first counting code based on a phase difference between the second clock signal and the data signal, wherein the clock delay scheduler is configured to receive the first clock signal from the duty cycle corrector and adjust the first clock signal based on a second counting code, wherein the scheduler controller is configured to generate the second counting code based on a first adjustment code and a second adjustment code, and wherein the clock circuit is further configured to: when the level of the power supply voltage is a first power supply voltage level, obtain a first value of the first counting code by causing one or more first loop operations to be performed through the first loop, and store the first value as a first adjustment code, and obtain a second value of the first counting code by causing one or more of the one or more first loop operations to be performed through the first loop when the level of the power supply voltage is a second power supply voltage level higher than the first power supply voltage level, and store the second value as a second adjustment code. and performing one or more second loop operations through the second loop until the first slope and the second slope are the same based on identifying a difference between a first slope representing a change in delay of the data signal relative to the first power supply voltage level and the second power supply voltage level and a second slope representing a change in delay of the clock signal.

[0011] According to one aspect of the present disclosure, a method for adjusting a skew between a data signal and a clock signal of a device, the device being driven by a power supply voltage and including a sampler circuit that latches a data signal in response to a clock signal, the method comprising: receiving a data signal through a data buffer of the device; receiving the clock signal through a clock buffer of the device; repeatedly performing one or more first loop operations through a first loop of the device based on identifying a phase difference between the data signal and the clock signal until the phase difference is eliminated, wherein the first loop includes the sampler circuit and a first counting logic circuit; when the level of the power supply voltage is the first power supply voltage level, performing the one or more first loop operations through the first loop to obtain a first adjustment code by one or more of the first and second adjustment codes; to obtain a second adjustment code, the second adjustment code being obtained by causing one or more of the one or more first loop operations to be performed when the level of the power supply voltage is a second power supply voltage level higher than the first power supply voltage level; storing the first adjustment code and the second adjustment code in a scheduler controller of the device; and based on identifying a difference between a first slope representing a change in delay of a data signal relative to the first and second power supply voltage levels and a second slope representing a change in delay of a clock signal, performing one or more second loop operations through a second loop of the device until the first slope and the second slope are the same, wherein the second loop includes a scheduler controller and a clock delay scheduler of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Embodiments of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a block diagram of an apparatus according to an embodiment;

[0014] Figure 2 , 3A , 3B and 3C are used to describe Figure 1 A diagram of a typical clock training method for a memory device;

[0015] Figure 4 is a block diagram illustrating a memory device according to one or more embodiments;

[0016] Figure 5 is a diagram for describing a voltage regulator according to one or more embodiments;

[0017] Fig. 6A and 6B is a diagram for describing a first delay circuit having a positive delay according to one or more embodiments;

[0018] Fig. 7A , Figure 7B and Figure 7C is a diagram for describing a second delay circuit having a negative delay according to one or more embodiments;

[0019] Figure 8 , Fig. 9 , Fig.10 , Fig.11A , Fig. 11B and Fig. 11C is a diagram for describing an operating method of a memory device according to one or more embodiments;

[0020] Fig.12 , 13 , 14 and 15 are block diagrams for describing memory devices according to one or more embodiments;

[0021] Fig.16A and 16B is a diagram illustrating a multi-phase clock signal used in a memory device according to one or more embodiments;

[0022] Fig.17 is a cross-sectional view of a memory device having a bonded vertical NAND (B-VNAND) structure according to an embodiment; and

[0023] Fig.18 is a block diagram for describing a system of an electronic device including a device according to one or more embodiments. DETAILED DESCRIPTION

[0024] Figure 1 is a block diagram of an apparatus according to an embodiment.

[0025] refer to Figure 1 , the device 100 includes a first device 110 and a second device 120. The device 100 may be implemented to be included in a personal computer (PC) or a mobile electronic device. The mobile electronic device may be implemented as a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or a portable navigation device (PND), a handheld game console, a mobile Internet device (MID), a wearable computer, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, or a drone.

[0026] For example, the device 110 may be implemented by an integrated circuit (IC), a system on chip (SoC), an application processor (AP), a mobile AP, a chipset, or a group of chips. For example, the first device 110 may be a semiconductor device that performs a memory control function, and the first device 110 may be a component included in a test device. The first device 110 may include a memory controller, a random access memory (RAM), a central processing unit (CPU), a graphics processing unit (GPU), and / or a test CPU.

[0027] The second device 120 may be implemented as a memory device. The second device 120 may be implemented as a non-volatile memory device, but the present disclosure is not limited thereto. For example, the second device 120 may include a NAND flash memory. According to another embodiment, the second device 120 may include a phase change random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), or a memory similar thereto.

[0028] The second device 120 may also be implemented as a volatile memory device. For example, the second device 120 may correspond to a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate LPDD (LPDDR) SDRAM, a graphic double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), etc. Alternatively, the second device 120 may be implemented by a high bandwidth memory (HBM) or a processor in memory (PIM)-HBM.

[0029] Hereinafter, for convenience of explanation, the first device 110 will be referred to as a memory controller, and the second device 120 will be referred to as a memory device. Although the memory device 120 is shown as a single semiconductor chip, in practice, the memory device 120 may include n memory devices (where n is a non-zero integer).

[0030] The memory device 120 may be coupled to a bus (or channel) 130 that carries commands, addresses, data, and clocks. The memory controller 110 and the memory device 120 may communicate with each other through various buses 130. For example, commands and addresses may be received by the memory device 120 through a data bus 134, and data may be provided between the memory controller 110 and the memory device 120 via the data bus 134. The data bus 134 may include one or more signal lines, e.g., 8 signal lines, 16 signal lines, etc., through which signals representing commands, addresses, or data are provided.

[0031] A clock signal DQS may be provided between the memory controller 110 and the memory device 120 via a clock bus 132. The clock bus 132 may include a signal line for sending a data strobe signal DQS provided by the memory controller 110 to the memory device 120 or for sending a data strobe signal DQS provided by the memory device 120 to the memory controller 110. The DQS signal may be used to provide and receive the timing of commands and addresses on the data bus 134, or may be used to provide the timing of data. The clock bus 132 includes two signal lines for providing clock signals DQS_t and DQS_c between the memory controller 110 and the memory device 120, and the clock signals DQS_t and DQS_c are complementary to each other. When the rising edge of the first clock signal DQS_t occurs simultaneously with the falling edge of the second clock signal DQS_c and when the rising edge of the second clock signal DQS_c occurs simultaneously with the falling edge of the first clock signal DQS_t (i.e., when the phase difference is 180 degrees), the clock signals DQS are complementary. Hereinafter, for convenience of explanation, the clock signals DQS_t and DQS_c may be referred to as DQS clocks or DQS clock signals. In addition, commands, addresses, or data on the data bus 134 may be referred to as DQ data.

[0032] The memory controller 110 may provide commands to the memory device 120 to perform memory operations. Non-limiting examples of memory commands include access commands for accessing memory, such as read commands for performing read operations, write (or program) commands for performing write (or program) operations, and training commands.

[0033] During a read operation, when a read command and an associated address are provided to the memory device 120 by the memory controller 110, the memory device 120 may receive the read command and the associated address and perform a read operation, thereby outputting read data DQ from a memory location corresponding to the associated address. The read data DQ may be provided by the memory device 120 to the memory controller 110 according to a timing associated with the receipt of the read command. When the memory controller 110 provides a write (or program) command and an associated address to the memory device 120, the memory device 120 may receive the write (or program) command and the associated address and perform a write (or program) operation, thereby writing the write data DQ from the memory controller 110 to the memory location corresponding to the associated address. The write data DQ may be provided by the memory controller 110 to the memory device 120 according to a timing associated with the receipt of the write (or program) command.

[0034] The timing that is important in these operations may be based on the alignment of the DQ data edges corresponding to the DQS clock edges. The memory controller 110 may include a training circuit 112 that performs memory training on the memory device 120. The training circuit 112 may perform a clock training operation with respect to the DQS clock in response to a training command. The DQ data edges may be aligned in response to the DQS clock edges through clock training.

[0035] The memory device 120 may include a clock circuit 122 and a data input / output circuit 124. The clock circuit 122 may provide a timing-adjusted DQS clock by adjusting the skew between the DQ data and the DQS clock. The clock circuit 122 may perform a first loop operation through a first loop and a second loop operation through a second loop based on a phase difference between the DQ data and the DQS clock. The first loop operation may be performed until there is no phase difference between the DQ data and the DQS clock, and the second loop operation may be performed until a first slope representing a delay variation of the DQ data becomes the same as a second slope representing a delay variation of the DQS clock relative to a level of a power supply voltage.

[0036] In one or more embodiments, the clock circuit 122 may receive a first clock signal having a first swing width, convert the first clock signal into a second clock signal amplified to a second swing width greater than the first swing width, and adjust the skew between the DQ data and the second clock signal. The clock circuit 122 may generate multi-phase clock signals by dividing the received first clock signal using a frequency divider circuit, and perform duty cycle adjustment on each of the multi-phase clock signals.

[0037] The data input / output circuit 124 may transmit read DQ data synchronized to the timing-adjusted DQS clock to the memory controller 110, and receive write DQ data synchronized to the timing-adjusted DQS clock from the memory controller 110. The DQ data transmitted and received by the data input / output circuit 124 may have a data width of 8 bits. However, this is merely an example and is not intended to limit the present disclosure.

[0038] Figure 2 , Figure 3A , Figure 3B and Figure 3C is used to describe Figure 1 Figure 2 shows a typical clock training method for memory devices.

[0039] refer to Figure 2, the memory device 120 is driven by a power supply voltage VCCQ, and may include a clock buffer 121, a clock circuit 122, a data buffer 123, and a data input / output circuit 124. The clock buffer 121 may receive a DQS clock on a clock bus 132 and provide the DQS clock to the clock circuit 122. The clock circuit 122 may include a variable delay circuit 127, a clock path 128, and a logic circuit 129. The DQS clock output from the clock buffer 121 may be provided to the variable delay circuit 127 and the clock path 128, and may be output after being delayed for a specific time. The variable delay circuit 127 is provided to reduce the timing deviation of the DQS clock and may output a DQS clock with adjusted timing. An example deviation of the clock timing may be a deviation due to a timing skew between the DQ data and the DQS clock or a distortion of the duty cycle (i.e., 50% duty cycle) of the DQS clock.

[0040] The data buffer 123 may receive the DQ data on the data bus 134 and provide the DQ data to the data input / output circuit 124. The data input / output circuit 124 may include a data path 125 and a sampler circuit 126. The DQ data output from the data buffer 123 may be provided to the sampler circuit 126 via the data path 125. The sampler circuit 126 may latch the DQ data of the data path 125 in response to the DQS clock of the clock path 128. The sampler circuit 126 may use an edge-triggered flip-flop. The sampler circuit 126 may experience timing skew (sometimes referred to as clock skew) due to factors including differences between wire lengths, capacitive coupling, clock jitter, temperature variations, and power supply voltage fluctuations. To reduce the timing deviation of the DQS clock, the logic circuit 129 can output the phase difference between the DQ data latched on the DQS clock edge in the sampler circuit 126 as a code, and the variable delay circuit 127 can delay the DQS clock according to the code output from the logic circuit 129, thereby outputting a timing-adjusted DQS clock.

[0041] The memory device 120 may be affected by changes that randomly affect the entire system, such as changes in the power supply voltage VCCQ. For example, the level of the power supply voltage VCCQ may become lower than a target level (indicated as a “first voltage level VCCQ_LV”) or higher than a target level (indicated as a “second voltage level VCCQ_HV”). The first voltage level VCCQ_LV and the second voltage level VCCQ_HV may belong to an allowable voltage range of the power supply voltage VCCQ provided to the memory device 120. Figure 3A1 , at a first voltage level VCCQ_LV, a DQS clock edge A of the clock path 128 latches the DQ data by using an effective window (or eye opening) EO1 of the DQ data on the data path 125 and the sampler circuit 126. The DQS clock edge A may vary at a central portion of the effective window EO1. At a second voltage level VCCQ_HV, an effective window EO2 of the DQ data on the data path 125 and the DQS clock edge B of the clock path 128 may be seen, wherein the DQS clock edge B may vary at an edge portion of the effective window EO2. When the power supply voltage VCCQ of the memory device 120 changes between the first voltage level VCCQ_LV and the second voltage level VCCQ_HV, the DQS clock provided to the sampler circuit 126 may have a first skew SKEW1 relative to the DQ data. In order for the memory device 120 to operate normally, the first skew SKEW1 needs to be reduced.

[0042] To reduce the first skew SKEW1, the memory device 120 may use the logic circuit 129 and the variable delay circuit 127 to output the timing-adjusted DQS clock edges C and D. Figure 3B In the embodiment, the DQS clock edge C with timing adjustment may appear at the first voltage level VCCQ_LV within the effective window EO1, and the DQS clock edge D with timing adjustment may appear at the second voltage level VCCQ_HV within the effective window EO2. Figure 3A The DQS clock edge A is at a first voltage level VCCQ_LV relative to Figure 3B The DQS clock edge C timing changes, and Figure 3A The DQS clock edge B is at the second voltage level VCCQ_HV relative to Figure 3B The DQS clock edge D timing is changed. Even when the skew according to the change of the power supply voltage VCCQ is reduced, the timing-adjusted DQS clock still has the second skew SKEW2. The method of reducing the skew refers to arithmetically adjusting the delay change of the DQS clock according to the change of the power supply voltage VCCQ, such as Figure 3C shown. Figure 3C FIG. 1 shows that a change in DQ data (sometimes referred to as a slope) according to a change in the power supply voltage VCCQ and a change in the DQS clock according to a change in the power supply voltage VCCQ are different from each other, wherein the difference between the slope of the DQ data and the slope of the DQS clock may be related to skew adjustment. When the slope of the DQ data and the slope of the DQS clock according to a change in the power supply voltage VCCQ may be adjusted to be the same as each other (for example, Fig. 11C ), reducing the skew between DQ data and DQS clock will be beneficial.

[0043] Figure 4 is a block diagram illustrating a memory device according to one or more embodiments. Figure 5 is a diagram for describing a voltage regulator according to one or more embodiments. Fig. 6A and 6B is a diagram for describing a first delay circuit having a positive delay according to one or more embodiments. Fig. 7A , Figure 7B and Figure 7C is a diagram for describing a second delay circuit having a negative delay according to one or more embodiments.

[0044] Figure 4 The memory device 120a may be connected to Figure 1 The memory device 120 of FIG. 1 functions in the same manner. Hereinafter, letters attached to reference numerals (e.g., a of 120a, b of 120b, etc.) are used to identify multiple circuits having the same function. Figure 2 The same ones given Figure 4 Description of the storage device 120a.

[0045] refer to Figure 4 , the memory device 120a may include switches 151 and 152, which provide the first power supply voltage VCCQ_LV or the second power supply voltage VCCQ_HV to the power supply voltage VCCQ line. However, this is merely an example and is not intended to limit the present disclosure. According to an embodiment, the memory device 120a may not include switches 151 and 152. In this embodiment, the first power supply voltage VCCQ_LV or the second power supply voltage VCCQ_HV may be provided to the power supply voltage VCCQ line in an operation of testing the memory device 120a.

[0046] According to one or more embodiments, the memory device 120a may be configured to store Figure 5A voltage regulator is used to generate a first power supply voltage VCCQ_LV or a second power supply voltage VCCQ_HV. The voltage regulator may be referred to as a low dropout (LDO) regulator. The LDO regulator may include an amplifier AMP, a transistor M0, a first resistor Ra, and a second resistor Rb. The amplifier AMP may have a first input terminal (e.g., a + input terminal) for receiving a reference voltage Vref and a second input terminal (e.g., a - input terminal) for receiving a feedback voltage Vfb between the first resistor Ra and the second resistor Rb, and amplify the difference between the reference voltage Vref and the feedback voltage Vfb. The transistor M0 may be a PMOS transistor connected between the power supply voltage VCCQ line and the first resistor Ra, wherein the output of the amplifier AMP is applied to the gate of the PMOS transistor. The connection node between the transistor M0 and the first resistor Ra may output the first power supply voltage VCCQ_LV or the second power supply voltage VCCQ_HV as the output of the LDO regulator. Here, when the level of the reference voltage Vref is set to the first power supply voltage level VCCQ_LV, the output of the LDO regulator may be output at the first power supply voltage level VCCQ_LV. When the level of the reference voltage Vref is set to the second power supply voltage level VCCQ_HV, the output of the LDO regulator may be output at the second power supply voltage level VCCQ_HV.

[0047] exist Figure 4 , the memory device 120a may include a clock buffer 121 driven by a first power supply voltage VCCQ_LV or a second power supply voltage VCCQ_HV sent to a power supply voltage VCCQ line, a clock circuit 122a, a data buffer 123, and a data input / output circuit 124a. The clock circuit 122a may include a variable delay circuit 127a, a clock delay scheduler 128a, a first counter logic circuit 129a, and a scheduler controller 140. The variable delay circuit 127a may be configured to receive a DQS clock received by the clock buffer 121 as an input and delay the DQS clock in response to a first count code FCC output from the first counter logic circuit 129a.

[0048] According to one or more embodiments, the variable delay circuit 127a may include a delay unit that is turned on / off according to the first count code FCC of the first counter logic circuit 129a. The delay unit turned on by the first count code FCC of the first counter logic circuit 129a has a certain delay amount. On the other hand, the delay unit turned off by the first count code FCC of the first counter logic circuit 129a may be bypassed.

[0049] The clock delay scheduler 128a may delay the DQS clock until the slope of the DQ data and the slope of the DQS clock according to the change of the power supply voltage VCCQ become identical to each other. The clock delay scheduler 128a may be configured to receive the delayed DQS clock output from the variable delay circuit 127 as an input, and delay the DQS clock in response to the second count code SCC output from the scheduler controller 140.

[0050] According to one or more embodiments, the clock delay scheduler 128a may include a plurality of first delay circuits PSC considered to have positive delays and a plurality of second delay circuits NSC considered to have negative delays to increase or decrease the amount of delay affecting the delay of the DQS clock. The first delay circuits PSC and the second delay circuits NSC may be connected in series.

[0051] The first delay circuit PSC is configured so that when the level of the power supply voltage VCCQ changes, the delay amount changes according to the increased level of the power supply voltage VCCQ, which can be represented by the first delay circuit PSC having "positive sensitivity". The second delay circuit NSC is configured so that when the level of the power supply voltage VCCQ changes, the delay amount does not change according to the increased level of the power supply voltage VCCQ. Since the DQS clock is not delayed unlike the first delay circuit PSC, the second delay circuit NSC can be represented by "negative sensitivity".

[0052] refer to Fig. 6A , the first delay circuit PSC includes PMOS transistors M1, M2 and M3 and NMOS transistors M4, M5 and M6 connected between the power supply voltage VCCQ line and the ground voltage VSS line. Transistors M3 and M4 can each be designed as an inverter having a DQS clock (expressed as "input signal IN") and its inverted output (expressed as "output signal OUT"). Transistors M1 and M2 can be connected in parallel between the power supply voltage VCCQ line and one end of transistor M3. A first bias voltage VBP1 can be applied to the gate of transistor M1, and a ground voltage VSS can be applied to the gate of transistor M2. Transistors M5 and M6 can be connected in parallel between one end of the M4 transistor and the ground voltage VSS. A second bias voltage VBN1 can be applied to the gate of transistor M5, and the power supply voltage VCCQ can be applied to the gate of transistor M6.

[0053] like Figure 6BAs shown, each of the first bias voltage VBP1 and the second bias voltage VBN1 can be maintained at a constant voltage level even when the level of the power supply voltage VCCQ increases or decreases. The level of the first bias voltage VBP1 can be set to be lower than the level of the second bias voltage VBN1. When the level of the power supply voltage VCCQ is the first power supply voltage level VCCQ_LV, the first delay circuit (PSC) can operate with the first drive current provided by the transistors M1 and M2, and when the level of the power supply voltage VCCQ is the second power supply voltage level VCCQ_HV, the first delay circuit (PSC) can operate with the second drive current. Here, the first drive current will be less than the second drive current. Therefore, when the level of the power supply voltage VCCQ is the first power supply voltage level VCCQ_LV, the first delay circuit PSC can exhibit an increased delay amount, and when the level of the power supply voltage VCCQ is the second power supply voltage level VCCQ_HV, the first delay circuit PSC can exhibit a reduced delay amount. In other words, the first delay circuit PSC has positive sensitivity in which the delay amount varies according to the level of the power supply voltage VCCQ. However, this is merely an example and is not intended to limit the present disclosure.

[0054] refer to Fig. 7A , the second delay circuit NSC may include Fig. 7A The first delay circuit PSC is similarly configured with PMOS transistors M11, M12 and M13 and NMOS transistors M14, M15 and M16. Transistors M11 and M12 can be connected in parallel between the power supply voltage VCCQ line and one end of transistor M13 transistor, transistors M13 and M14 are designed as inverters with input signal IN and output signal OUT, the output signal OUT is an inverted signal of the input signal IN, and transistors M15 and M16 transistors can be connected in parallel between one end of transistor M14 and ground voltage VSS. A third bias voltage VBP2 can be applied to the gate of transistor M11, and a ground voltage VSS can be applied to the gate of transistor M12. A fourth bias voltage VBN2 can be applied to the gate of transistor M15, and the power supply voltage VCCQ can be applied to the gate of transistor M16.

[0055] The third bias voltage VBP2 and the fourth bias voltage VBN2 can be respectively Figure 7BThe first voltage generating circuit 710 and the second voltage generating circuit 720 generate. The first voltage generating circuit 710 may include variable resistors R1, R2, R3, and R4 connected between the power supply voltage VCCQ line and the ground voltage VSS line, and a transistor M17 as an NMOS transistor. The connection node between the resistor R1 and the resistor R2 connected in series between the power supply voltage VCCQ line and the ground voltage VSS line may be connected to the gate of the transistor M17, the resistor R3 may be connected between the power supply voltage VCCQ line and one end of the transistor M17, and the resistor R4 may be connected between the other end of the transistor M17 and the ground voltage VSS line. The voltage of the connection node between the resistor R3 and the transistor M17 may be output at the level of the fourth bias voltage VBN2.

[0056] The second voltage generating circuit 720 may include variable resistors R5, R6, R7, and R8 connected between the power supply voltage VCCQ line and the ground voltage VSS line, and a transistor M18 as a PMOS transistor. A connection node between the resistor R5 and the resistor R6 connected in series between the power supply voltage VCCQ line and the ground voltage VSS line may be connected to the gate of the transistor M18, the resistor R7 may be connected between the power supply voltage VCCQ line and one end of the transistor M18, and the resistor R8 may be connected between the other end of the transistor M17 and the ground voltage VSS line. The voltage of the connection node between the resistor R3 and the transistor M18 may be output at the level of the third bias voltage VBP2.

[0057] For example, assuming that when the level of the power supply voltage VCCQ changes, the third bias voltage VBP2 and the fourth bias voltage VBN2 have the following Figure 7C In addition, it is assumed that the fourth bias voltage VBN2 is Figure 7B However, this is merely an example and is not intended to limit the present disclosure. Figure 7C It is shown that as the level of the power supply voltage VCCQ increases, the third bias voltage VBP2 increases to an incremental voltage level. When the level of the power supply voltage VCCQ is the first power supply voltage level VCCQ_LV, the level of the third bias voltage VBP2 may decrease, and when the level of the power supply voltage VCCQ is the second power supply voltage level VCCQ_HV, the level of the third bias voltage VBP2 may increase.

[0058] In the second delay circuit NSC, when the level of the power supply voltage VCCQ is reduced to the first power supply voltage level VCCQ_LV, the level of the third bias voltage VBP2 may also be reduced. When the level of the power supply voltage VCCQ is increased to the second power supply voltage level VCCQ_HV, the level of the third bias voltage VBP2 may also be increased. This means that for the first power supply voltage VCCQ_LV and the second power supply voltage VCCQ_HV, the same drive current is provided by transistors M11 and M12. Therefore, the second delay circuit NSC can present the same (substantially constant) delay amount for both the first power supply voltage VCCQ_LV and the second power supply voltage VCCQ_HV. In other words, the second delay circuit NSC has negative sensitivity, in which the delay amount does not change according to the level of the power supply voltage VCCQ (is substantially insensitive to changes in the power supply voltage VCCQ). However, this is merely an example and is not intended to limit the present disclosure.

[0059] Return to reference Figure 4 , the clock delay scheduler 128a can delay the DQS clock by using a plurality of first delay circuits PSC and a plurality of second delay circuits NSC connected in series. The problem with the variable delay circuit 127a before the clock delay scheduler 128a is that, as described above with reference to Figure 3A , Figure 3B and Figure 3C As described, even when the skew according to the change in the power supply voltage VCCQ is reduced, the timing-adjusted DQS clock still has a second skew SKEW2 for the DQ data. The clock delay scheduler 128a is required to completely remove the skew. The clock delay scheduler 128a can change the function of the second delay circuit NSC with negative sensitivity to have positive sensitivity like the first delay circuit PSC. Changing the function of the second delay circuit NSC to be similar to the first delay circuit PSC means that, as a result, the number of first delay circuits PSC with positive sensitivity increases. In other words, as more first delay circuits PSC are added to the clock delay scheduler 128a, the slope of the DQS clock can be adjusted according to the change in the power supply voltage VCCQ. The slope of the DQ data and the slope of the DQS clock according to the change in the power supply voltage VCCQ can be adjusted to be the same as each other (for example, Fig. 11C ), thereby reducing the skew between DQ data and DQS clock.

[0060] The DQ data received through the data buffer 123 and the data path 125a may be provided to the sampler circuit 126a. The sampler circuit 126a may latch the DQ data in response to the DQS clock output from the clock delay scheduler 128a. The sampler circuit 126a may output a phase difference between the DQS clock and the DQ data and provide the phase difference to the first counter logic circuit 129a. The first counter logic circuit 129a may generate a first count code FCC by calculating the phase difference between the DQS clock and the DQ data. The first count code FCC is provided to the variable delay circuit 127a, and the variable delay circuit 127a may delay the DQS clock by using a delay unit that is turned on / off according to the bit of the first count code FCC. The first loop LOOP1 may be formed in the order of the variable delay circuit 127a, the clock delay scheduler 128a, the sampler circuit 126a, and the first counter logic circuit 129a. Several repetitive loops may be performed through the first loop LOOP1 until there is no phase difference between the DQS clock and the DQ data. According to another embodiment, the order of the circuits forming the first loop LOOP1 may be changed. However, this is merely an example and is not intended to limit the present disclosure.

[0061] According to one or more embodiments, the first count code FCC of the first counter logic circuit 129a may be divided corresponding to (depending on) two or more levels of the power supply voltage VCCQ. When the power supply voltage VCCQ of the memory device 120a is at the first power supply voltage level VCCQ_LV, the first count code FCC obtained as a result of several repeated calculations through the first loop LOOP1 may be referred to as the first adjustment code LVC. When the power supply voltage VCCQ of the memory device 120a is at the second power supply voltage level VCCQ_HV, the first count code FCC obtained as a result of several repeated calculations through the first loop LOOP1 may be referred to as the second adjustment code HVC. Although the present embodiment describes that the first count code FCC includes the first adjustment code LVC and the second adjustment code HVC, the present disclosure is not limited thereto, and the first count code FCC may include a plurality of adjustment codes corresponding to a plurality of power supply voltage levels.

[0062] Based on the first adjustment code LVC and the second adjustment code HVC of the first counter logic circuit 129a, the scheduler controller 140 can generate a second count code SCC for controlling the slope of the DQS clock according to the change of the power supply voltage VCCQ to become the same as the slope of the DQ data. The scheduler controller 140 may include a register 142, a comparator 144, and a second counter logic circuit 146. The register 142 may store the bits of the first adjustment code LVC and the bits of the second adjustment code HVC output from the first counter logic circuit 129a. The comparator 144 may compare the bits of the first adjustment code LVC and the bits of the second adjustment code HVC, and the second counter logic circuit 146 may generate a second count code SCC based on the difference between the bits of the first adjustment code LVC and the bits of the second adjustment code HVC. The second count code SCC is provided to the clock delay scheduler 128a, and the clock delay scheduler 128a may change the function of the second delay circuit NSC with negative sensitivity to have positive sensitivity like the first delay circuit PSC based on the bits of the second count code SCC.

[0063] According to one or more embodiments, changing the negative sensitivity of the second delay circuit NSC to the positive sensitivity means that the third bias voltage VBP2 (eg, Figure 7C ) is fixed to a level similar to the first bias voltage level VBP1 (eg, Figure 6B )'s level. Figure 7B The second voltage generating circuit 720 may be configured to fix the resistance values ​​of the variable resistors R5, R6, R7, and R8 based on the bits of the second counting code SCC, thereby outputting the third bias voltage VBP2 having a constant voltage level regardless of the change in the power supply voltage VCCQ. In this embodiment, the clock delay scheduler 128a may be reorganized so that the number of first delay circuits PSC increases significantly with the increase in the number of second delay circuits NSC, and the negative sensitivity of the second delay circuit NSC becomes positive sensitivity due to the bits of the second counting code SCC.

[0064] The second loop LOOP2 may be formed in the order of the scheduler controller 140 and the clock delay scheduler 128a. Several repetitive loops are performed by the second loop LOOP2, which may be performed until the first adjustment code LVC and the second adjustment code HVC become identical to each other.

[0065] According to one or more embodiments, by adjusting the slope of the DQS clock according to the change of the power supply voltage VCCQ based on the first adjustment code LVC and the second adjustment code HVC of the first counting code FCC and the second counting code SCC passing through the second loop LOOP2, the reorganization of the clock delay scheduler 128a can be updated until the slope of the DQ data and the slope of the DQS clock according to the change of the power supply voltage VCCQ become the same as each other. Therefore, the skew between the DQ data and the DQS clock caused by the change of the power supply voltage VCCQ can be reduced.

[0066] Figure 8 , 9 , 10 , 11A, 11B, and 11C are diagrams for describing a method of operating a memory device according to one or more embodiments. Fig.11A Shows the adoption or implementation of Figure 8 , 9 and 10 before the clock skew (e.g., Figure 3A The first deflection SKEW1). Fig. 11B Shows the adoption or implementation of Figure 8 , 9 and 10 methods after zero clock skew, and Fig. 11C The matching between the slope of the DQ data and the slope of the DQS clock according to the change of the power supply voltage VCCQ that can be achieved by the embodiments is shown.

[0067] According to one or more embodiments, Figure 8 , 9 The method of 10 (eg, operation S700) may be performed by Figure 4 The memory device 120a shown in FIG. utilizes or performs. In this embodiment, the memory device 120a performs an operation to reduce the skew between the DQ data and the DQS clock according to the change of the power supply voltage VCCQ during the clock training performed between the memory controller 110 and the memory device 120a. However, this is only an example and is not intended to limit the present disclosure.

[0068] refer to Figure 4 and Figure 8, in operation S810, the first loop LOOP1 may be performed until there is no phase difference between the DQS clock and the DQ data for each level of the power supply voltage VCCQ of the memory device 120a. According to one or more embodiments, the first loop LOOP1 may be a loop in the order of the variable delay circuit 127a, the clock delay scheduler 128a, the sampler circuit 126a, and the first counter logic circuit 129a. The first count code FCC obtained as a result of several repeated calculations of the first loop LOOP1 at the first power supply voltage level VCCQ_LV may be stored in the scheduler controller 140 as a first adjustment code LVC. The first count code FCC obtained as a result of several repeated calculations of the first loop LOOP1 at the second power supply voltage level VCCQ_HV may be stored in the scheduler controller 140 as a second adjustment code HVC.

[0069] like Fig. 9 As shown, the memory device 120a can set the power supply voltage VCCQ to the first power supply voltage level VCCQ_LV (operation S902), compare the phase of the DQS clock with the phase of the DQ data through the first loop LOOP1 (operation S904), determine whether there is no phase difference between them (operation S906), update the first counting code FCC when there is a phase difference (operation S908), and repeat operations S904, S906 and S908, and store the first counting code FCC obtained when there is no phase difference between the DQS clock and the DQ data as the first adjustment code LVC in the scheduler controller 140 (operation S910). The memory device 120a may set the power supply voltage VCCQ to a second power supply voltage level VCCQ_HV (operation S912), compare the phase of the DQS clock with the phase of the DQ data through the first loop LOOP1 (operation S914), determine whether there is no phase difference therebetween (operation S916), update the first counting code FCC when there is a phase difference (operation S918), and repeatedly perform operations S904, S906, and S908, and store the first counting code FCC obtained when there is no phase difference between the DQS clock and the DQ data as the second adjustment code HVC in the scheduler controller 140 (operation S920).

[0070] In operation S820, the second loop LOOP2 may be performed until the slope of the DQ data becomes the same as the slope of the DQS clock for each level of the power supply voltage VCCQ of the memory device 120a. According to one or more embodiments, the second loop LOOP2 may be a loop in the order of the scheduler controller 140 and the clock delay scheduler 128a. Fig.10As shown, the memory device 120a performs several repetitive loops through the second loop LOOP2 (operation S820), compares the first adjustment code LVC and the second adjustment code HVC (operation S1002) by using the scheduler controller 140, determines whether the bit of the first adjustment code LVC is the same as the bit of the second adjustment code HVC (operation S830), and when there is a difference between them, updates the second count code SCC based on the difference (operation S1004). The memory device 120a can delay the DQS clock by changing the function of the second delay circuit NSC of the clock delay scheduler 128a from negative sensitivity to positive sensitivity based on the second count code SCC. In this embodiment, the clock delay scheduler 128a can be reorganized to add more positive sensitivity first delay circuits PSC.

[0071] In operation S830, an operation of determining whether the first adjustment code LVC and the second adjustment code HVC are identical to each other for each level of the power supply voltage VCCQ of the memory device 120a may be performed. According to one or more embodiments, when the first adjustment code LVC and the second adjustment code HVC are identical to each other, clock training of the memory device 120a may be terminated. This may remove DQS clock skew with respect to DQ data to prevent the influence of changes in the power supply voltage VCCQ ( Fig. 11B ), and equalizes the slope of the DQ data and the slope of the DQS clock according to the change of the power supply voltage VCCQ ( Fig. 11C According to one or more embodiments, when the first adjustment code LVC and the second adjustment code HVC are different from each other, the memory device 120a may repeatedly perform operations S810 and S820 a plurality of times.

[0072] Fig.12 , 13 , 14 and 15 are block diagrams for describing a memory device according to an embodiment. Fig.16A and 16B A multi-phase clock signal used in a memory device according to an embodiment is shown.

[0073] Reference Fig.12 ,and Figure 4 Compared with the memory device 120a of FIG. 1 , in the memory device 120b, the variable delay circuit 1227a is included in the DQ data line instead of the DQS clock signal line and is part of the data input / output circuit 124b. Hereinafter, the same description as that given above for the memory device 120a will be omitted.

[0074] In the memory device 120b, the first loop LOOP1 may be formed in the order of the variable delay circuit 127a, the data path 125a, the sampler circuit 126a, and the first counter logic circuit 129a. The variable delay circuit 127a may be configured to receive the DQ data received by the data buffer 123 as an input, and delay the DQ data in response to the first count code FCC output from the first counter logic circuit 129a. Several repeated loops may be performed by the first loop LOOP1 until there is no phase difference between the DQS clock and the DQ data. The memory device 120b may store a first adjustment code LVC for a first power supply voltage level VCCQ_LV and a second adjustment code HVC for a second power supply voltage level VCCQ_HV obtained as a result of performing several repeated calculations by the first loop LOOP1 in the scheduler controller 140. The memory device 120b may perform several repetitive loops through the second loop LOOP2 in the order of the scheduler controller 140 and the clock delay scheduler 128a based on the first adjustment code LVC and the second adjustment code HVC until the slope of the DQ data and the slope of the DQS clock become the same as each other. When the first adjustment code LVC and the second adjustment code HVC are different from each other, the function of the second delay circuit NSC of the clock delay scheduler 128a may be changed from negative sensitivity to positive sensitivity to delay the DQS clock. Therefore, the memory device 120b can reduce the skew between the DQ data and the DQS clock due to the change in the power supply voltage VCCQ.

[0075] Reference Fig.13 ,and Figure 4 Compared with the memory device 120a, in the memory device 120c, Figure 4 The data path 125a is not included in the data input / output circuit 124c. The data path 125a may include circuit elements for transmitting DQ data, including but not limited to buffers, drivers and / or triggers. The circuit elements of the data path 125a may be related to the determination of the trade-off between performance and power. For example, as more buffers (or other circuits) are added, more power may be consumed, but the DQ data signaling characteristics may be improved. For example, the logic level of the DQ data may be accurately distinguished under a poor DQ data line environment (e.g., interference distortion, reflection noise and / or crosstalk). By eliminating circuit elements in the data path 125a, the amount of power consumption may be limited.

[0076] The memory device 120c may store a first adjustment code LVC about a first power supply voltage level VCCQ_LV and a second adjustment code HVC about a second power supply voltage level VCCQ_HV, which is obtained as a result of several repeated calculations performed in the order of the variable delay circuit 127a, the clock delay scheduler 128a, and the first counter logic circuit 129a through the first loop LOOP1 until there is no phase difference between the DQS clock and the DQ data. The memory device 120c may perform several repeated loops through the second loop LOOP2 in the order of the scheduler controller 140 and the clock delay scheduler 128a based on the first adjustment code LVC and the second adjustment code HVC until the slope of the DQ data and the slope of the DQS clock become the same as each other. When the first adjustment code LVC and the second adjustment code HVC are different from each other, the function of the second delay circuit NSC of the clock delay scheduler 128a may be changed from negative sensitivity to positive sensitivity to delay the DQS clock. Therefore, the memory device 120c may reduce the skew between the DQ data and the DQS clock due to the change of the power supply voltage VCCQ.

[0077] refer to Fig.14 , the memory device 120d may use a signal swinging at a current mode logic (CML) level for a high-speed signal input / output (I / O) interface (e.g., a transmitter / receiver). The CML level refers to a scheduled direct current (DC) level or an average level determined according to a specific standard. A signal swinging at a CML level is a signal switched at an amplitude or swing range based on a DC level called a CML level. The swing width of a CML level signal is relatively small compared to a complementary metal oxide semiconductor (CMOS) level, which is a digital signal level for an internal signal of a semiconductor device. A CMOS level signal fully swings from a power supply voltage VDD level to a ground voltage VSS level. Since the swing width of a CML level signal is smaller than that of a CMOS level signal, a CML level signal can operate with a relatively low power supply and high-speed switching.

[0078] and Figure 4 Compared with the memory device 120a of FIG. 1 , in the memory device 120d, the data path 125a is not included in the data input / output circuit 124d, and the clock circuit 122d includes a CML buffer 1402 and a duty cycle corrector 1404. Figure 4 Compared to the memory device 120a, in the memory device 120d, the clock delay scheduler 1428 includes a CMS to CMOS converter (C2C) and a plurality of second delay circuits NSC.

[0079] According to one or more embodiments, the CML buffer 1402 may include an amplifier circuit that amplifies a voltage difference between a voltage level of a DQS clock received through the clock buffer 121 and a reference voltage level. The duty cycle corrector 1404 may adjust the duty cycle of the DQS clock provided from the CML buffer 1402 to an ideal value, i.e., 50%, and may be configured to correct the duty cycle of the DQS clock to a 50% duty cycle in response to a first count code FCC output from the first counter logic circuit 129a. The CML to CMOS converter C2C may be configured to maintain data invariance when the DQS clock of the CML level is converted into a digital signal of the CMOS level. The CML to CMOS converter C2C may also be referred to as a level converter.

[0080] The memory device 120d may store a first adjustment code LVC about the first power supply voltage level VCCQ_LV and a second adjustment code HVC about the second power supply voltage level VCCQ_HV obtained as a result of several repeated calculations performed in the order of the duty cycle corrector 1404, the clock delay scheduler 1428, and the first counter logic circuit 129a through the first loop LOOP1 until there is no phase difference between the DQS clock and the DQ data. The memory device 120d may perform several repeated loops through the second loop LOOP2 in the order of the scheduler controller 140 and the clock delay scheduler 128a based on the first adjustment code LVC and the second adjustment code HVC until the slope of the DQ data and the slope of the DQS clock become the same as each other. When the first adjustment code LVC and the second adjustment code HVC are different from each other, the function of the second delay circuit NSC of the clock delay scheduler 128a may be changed from negative sensitivity to positive sensitivity to delay the DQS clock. Therefore, the memory device 120d may reduce the skew between the DQ data and the DQS clock due to the change of the power supply voltage VCCQ.

[0081] refer to Fig.15 ,and Fig.14 Compared with the memory device 120d of FIG. 1 , the memory device 120e includes a frequency divider circuit 1521 instead of the clock buffer 121. Hereinafter, the same description as that given above with respect to the memory device 120d will be omitted.

[0082] The frequency divider circuit 1521 can receive the DQS clock on the clock bus 132 and output multi-phase clock signals DQS0, DQS90, DQS180, and DQS270 derived from the received DQS clock ( Fig.16A and 16B). According to one or more embodiments, the clock signal DQS0 may have a phase difference of 0 degrees (no phase difference) with the DQS clock, the clock signal DQS90 may have a phase difference of 90 degrees with the DQS clock, the clock signal DQS180 may have a phase difference of 180 degrees with the DQS clock, and the clock signal DQS270 may have a phase difference of 270 degrees with the DQS clock. The multi-phase clock signals DQS0, DQS90, DQS180, and DQS270 affect the operation sequence and pace of the memory device 120e, and may have a relatively low frequency compared to the DQS clock having a high frequency. This means that sufficient time is provided for the memory device 120e to operate by using the multi-phase clock signals.

[0083] The memory device 120e can store a first adjustment code LVC about the first power supply voltage level VCCQ_LV and a second adjustment code HVC about the second power supply voltage level VCCQ_HV, which are obtained as a result of repeated calculations through the first loop LOOP1 several times until there is no clock difference between each of the multi-phase clock signals DQS0, DQS90, DQS180 and DQS270 and the DQ data in the scheduler controller 140, wherein the first loop LOOP1 follows the order of the duty cycle corrector 1404, the clock delay scheduler 1428, the sampler circuit 126a and the first counter logic circuit 129a. The memory device 120e may perform several repetitive loops through the second loop LOOP2 in the order of the scheduler controller 140 and the clock delay scheduler 128a based on the first adjustment code LVC and the second adjustment code HVC until the slope of the DQ data and the slope of each of the multi-phase clock signals DQS0, DQS90, DQS180, and DQS270 become the same as each other. When the first adjustment code LVC and the second adjustment code HVC are different from each other, the function of the second delay circuit NSC of the clock delay scheduler 128a may be changed from negative sensitivity to positive sensitivity to delay the DQS clock. Therefore, the memory device 120e can reduce the skew between the DQ data and the DQS clock due to the change in the power supply voltage VCCQ.

[0084] Fig.17 5 is a cross-sectional view of a memory device 500 having a bonded vertical NAND (B-VNAND) structure according to an embodiment. The memory device 500 may be partially or completely combined with the above reference Figures 1 to 16B Embodiment described.

[0085] Fig.17 is a diagram illustrating a memory device 500 according to one or more embodiments of the present invention.

[0086] refer to Fig.17, the memory device 500 may have a chip-to-chip (C2C) structure. At least one upper chip including a cell area and a lower chip including a peripheral circuit area PERI may be manufactured separately, and then, at least one upper chip and a lower chip may be connected to each other by a bonding method to realize a C2C structure. For example, the bonding method may mean a method of electrically or physically connecting a bonding metal pattern formed in the uppermost metal layer of the upper chip to a bonding metal pattern formed in the uppermost metal layer of the lower chip. For example, in the case where the bonding metal pattern is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. Alternatively, the bonding metal pattern may be formed of aluminum (Al) or tungsten (W).

[0087] The memory device 500 may include at least one upper chip, and the at least one upper chip includes a cell region. Fig.17 As described in , the memory device 500 may include two upper chips. However, the number of upper chips is not limited thereto. In the case where the memory device 500 includes two upper chips, a first upper chip including a first cell area CELL1, a second upper chip including a second cell area CELL2, and a lower chip including a peripheral circuit area PERI may be manufactured separately, and then the first upper chip, the second upper chip, and the lower chip may be connected to each other by a bonding method to manufacture the memory device 500. The first upper chip may be flipped over and then connected to the lower chip by a bonding method, and the second upper chip may also be flipped over and then connected to the first upper chip by a bonding method. Hereinafter, before flipping each of the first and second upper chips, the upper and lower portions of each of the first and second upper chips will be defined based on the upper and lower portions of each of the first and second upper chips. In other words, in Fig.17 In the embodiment, the upper portion of the lower chip may refer to the upper portion defined based on the +Z axis direction, and the upper portion of each of the first and second upper chips may refer to the upper portion defined based on the -Z axis direction. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, one of the first upper chip and the second upper chip may be flipped and then connected to the corresponding chip by a bonding method.

[0088] Each of the peripheral circuit region PERI and the first and second cell regions CELL1 and CELL2 of the memory device 500 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

[0089] The peripheral circuit region PERI may include a first substrate 210 and a plurality of circuit elements 220a, 220b, and 220c formed on the first substrate 210. An interlayer insulating layer 215 including one or more insulating layers may be provided on the plurality of circuit elements 220a, 220b, and 220c, and a plurality of metal lines electrically connected to the plurality of circuit elements 220a, 220b, and 220c may be provided in the interlayer insulating layer 215. For example, the plurality of metal lines may include first metal lines 230a, 230b, and 230c connected to the plurality of circuit elements 220a, 220b, and 220c, and second metal lines 240a, 240b, and 240c formed on the first metal lines 230a, 230b, and 230c. The plurality of metal lines may be formed of at least one of various conductive materials. For example, the first metal lines 230 a , 230 b , and 230 c may be formed of tungsten having a relatively high resistivity, and the second metal lines 240 a , 240 b , and 240 c may be formed of copper having a relatively low resistivity.

[0090] In the present embodiment, the first metal lines 230a, 230b and 230c and the second metal lines 240a, 240b and 240c are shown and described. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, one or more additional metal lines may be formed on the second metal lines 240a, 240b and 240c. In this case, the second metal lines 240a, 240b and 240c may be formed of aluminum, and at least some of the additional metal lines formed on the second metal lines 240a, 240b and 240c may be formed of copper having a resistivity lower than the resistivity of the aluminum of the second metal lines 240a, 240b and 240c.

[0091] The interlayer insulating layer 215 may be disposed on the first substrate 210 and may include an insulating material such as silicon oxide and / or silicon nitride.

[0092] Each of the first cell region CELL1 and the second cell region CELL2 may include at least one memory block. The first cell region CELL1 may include a second substrate 310 and a common source line 320. A plurality of word lines 330 (331 to 338) may be stacked on the second substrate 310 in a direction perpendicular to the top surface of the second substrate 310 (i.e., the Z-axis direction). A string selection line and a ground selection line may be disposed above and below the word line 330, and a plurality of word lines 330 may be disposed between the string selection line and the ground selection line. Similarly, the second cell region CELL2 may include a third substrate 410 and a common source line 420, and a plurality of word lines 430 (431 to 438) may be stacked on the third substrate 410 in a direction perpendicular to the top surface of the third substrate 410 (i.e., the Z-axis direction). Each of the second substrate 310 and the third substrate 410 may be formed of at least one of various materials, and may be, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, or a substrate having a single crystal epitaxial layer grown on a single crystal silicon substrate. A plurality of channel structures CH may be formed in each of the first cell region CELL1 and the second cell region CELL2 .

[0093] In one or more embodiments, as shown in region "A1", the channel structure CH may be disposed in the bit line bonding region BLBA and may extend in a direction perpendicular to the top surface of the second substrate 310 to penetrate the word line 330, the string selection line, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a filling insulating layer. The channel layer may be electrically connected to the first metal line 350c and the second metal line 360c in the bit line bonding region BLBA. For example, the second metal line 360c may be a bit line and may be connected to the channel structure CH through the first metal line 350c. The bit line 360c may extend in a first direction (e.g., a Y-axis direction) parallel to the top surface of the second substrate 310.

[0094] In one or more embodiments, as shown in region "A2", the channel structure CH may include a lower channel LCH and an upper channel UCH connected to each other. For example, the channel structure CH may be formed by a process of forming the lower channel LCH and a process of forming the upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the top surface of the second substrate 310 to penetrate the common source line 320 and the lower word lines 331 and 332. The lower channel LCH may include a data storage layer, a channel layer, and a filling insulating layer, and may be connected to the upper channel UCH. The upper channel UCH may penetrate the upper word lines 333 to 338. The upper channel UCH may include a data storage layer, a channel layer, and a filling insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 350c and the second metal line 360c. As the length of the channel increases, it may be difficult to form a channel with a substantially uniform width due to the characteristics of the manufacturing process. The memory device 500 according to an embodiment of the present invention may include channels having improved width uniformity due to the lower channel LCH and the upper channel UCH formed by processes performed sequentially.

[0095] In the case where the channel structure CH includes a lower channel LCH and an upper channel UCH as shown in area "A2", a word line located near the boundary between the lower channel LCH and the upper channel UCH may be a dummy word line. For example, word lines 332 and 333 adjacent to the boundary between the lower channel LCH and the upper channel UCH may be dummy word lines. In this case, data may not be stored in the memory cells connected to the dummy word lines. Alternatively, the number of pages corresponding to the memory cells connected to the dummy word lines may be less than the number of pages corresponding to the memory cells connected to the universal word lines. The level of the voltage applied to the dummy word line may be different from the level of the voltage applied to the general word line, and thus the effect of the uneven channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device may be reduced.

[0096] In the region "A2", the number of lower word lines 331 and 332 penetrated by the lower channel LCH is less than the number of upper word lines 333 to 338 penetrated by the upper channel UCH. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the number of lower word lines penetrated by the lower channel LCH may be equal to or greater than the number of upper word lines penetrated by the upper channel UCH. In addition, the structural features and connection relationship of the channel structure CH disposed in the second cell region CELL2 may be substantially the same as the structural features and connection relationship of the channel structure CH disposed in the first cell region CELL1.

[0097] In the bit line bonding area BLBA, a first through electrode THV1 may be disposed in the first cell area CELL1, and a second through electrode THV2 may be disposed in the second cell area CELL2. Fig.17As shown, the first through electrode THV1 may penetrate the common source line 320 and the plurality of word lines 330. In some embodiments, the first through electrode THV1 may further penetrate the second substrate 310. The first through electrode THV1 may include a conductive material. Alternatively, the first through electrode THV1 may also include a conductive material surrounded by an insulating material. The second through electrode THV2 may have the same shape and structure as the first through electrode THV1.

[0098] In one or more embodiments, the first through electrode THV1 and the second through electrode THV2 may be electrically connected to each other through the first through metal pattern 372d and the second through metal pattern 472d. The first through metal pattern 372d may be formed at the bottom end of the first upper chip including the first cell area CELL1, and the second through metal pattern 472d may be formed at the top end of the second upper chip including the second cell area CELL2. The first through electrode THV1 may be electrically connected to the first metal line 350c and the second metal line 360c. The lower through hole 371d may be formed between the first through electrode THV1 and the first through metal pattern 372d, and the upper through hole 471d may be formed between the second through electrode THV2 and the second through metal pattern 472d. The first through metal pattern 372d and the second through metal pattern 472d may be connected to each other by a bonding method.

[0099] In addition, in the bit line bonding area BLBA, the upper metal pattern 252 may be formed in the uppermost metal layer of the peripheral circuit area PERI, and the upper metal pattern 392 having the same shape as the upper metal pattern 252 may be formed in the uppermost metal layer of the first cell area CELL1. The upper metal pattern 392 of the first cell area CELL1 and the upper metal pattern 252 of the peripheral circuit area PERI may be electrically connected to each other by a bonding method. In the bit line bonding area BLBA, the bit line 360c may be electrically connected to the page buffer included in the peripheral circuit area PERI. For example, some circuit elements 220c of the peripheral circuit area PERI may constitute a page buffer, and the bit line 360c may be electrically connected to the circuit element 220c constituting the page buffer through the upper bonding metal pattern 370c of the first cell area CELL1 and the upper bonding metal pattern 270c of the peripheral circuit area PERI.

[0100] Continue to refer Fig.17In the word line bonding area WLBA, the word lines 330 of the first cell area CELL1 may extend in a second direction (e.g., an X-axis direction) parallel to the top surface of the second substrate 310, and may be connected to a plurality of cell contact plugs 340 (341 to 347). The first metal line 350b and the second metal line 360b may be sequentially connected to the cell contact plugs 340 connected to the word lines 330. In the word line bonding area WLBA, the cell contact plugs 340 may be connected to the peripheral circuit area PERI through the upper bonding metal pattern 370b of the first cell area CELL1 and the upper bonding metal pattern 270b of the peripheral circuit area PERI.

[0101] The cell contact plug 340 may be electrically connected to a row decoder included in the peripheral circuit region PERI. For example, some circuit elements 220b of the peripheral circuit region PERI may constitute a row decoder, and the cell contact plug 340 may be electrically connected to the circuit element 220b constituting the row decoder through the upper bonding metal pattern 370b of the first cell region CELL1 and the upper bonding metal pattern 270b of the peripheral circuit region PERI. In one or more embodiments, the operating voltage of the circuit element 220b constituting the row decoder may be different from the operating voltage of the circuit element 220c constituting the page buffer. For example, the operating voltage of the circuit element 220c constituting the page buffer may be greater than the operating voltage of the circuit element 220b constituting the row decoder.

[0102] Likewise, in the word line bonding area WLBA, the word lines 430 of the second cell area CELL2 may extend in a second direction (e.g., X-axis direction) parallel to the top surface of the third substrate 410, and may be connected to a plurality of cell contact plugs 440 (441 to 447). The cell contact plugs 440 may be connected to the peripheral circuit area PERI through the upper metal pattern of the second cell area CELL2 and the lower and upper metal patterns of the first cell area CELL1 and the cell contact plugs 348.

[0103] In the word line bonding area WLBA, the upper bonding metal pattern 370b may be formed in the first cell area CELL1, and the upper bonding metal pattern 270b may be formed in the peripheral circuit area PERI. The upper bonding metal pattern 370b of the first cell area CELL1 and the upper bonding metal pattern 270b of the peripheral circuit area PERI may be electrically connected to each other by a bonding method. The upper bonding metal pattern 370b and the upper bonding metal pattern 270b may be formed of aluminum, copper, or tungsten.

[0104] In the external pad bonding area PA, a lower metal pattern 371e may be formed in a lower portion of the first cell area CELL1, and an upper metal pattern 472a may be formed in an upper portion of the second cell area CELL2. The lower metal pattern 371e of the first cell area CELL1 and the upper metal pattern 472a of the second cell area CELL2 may be connected to each other by a bonding method in the external pad bonding area PA. Similarly, an upper metal pattern 372a may be formed in an upper portion of the first cell area CELL1, and an upper metal pattern 272a may be formed in an upper portion of the peripheral circuit area PERI. The upper metal pattern 372a of the first cell area CELL1 and the upper metal pattern 272a of the peripheral circuit area PERI may be connected to each other by a bonding method.

[0105] Common source line contact plugs 380 and 480 may be disposed in the external pad bonding area PA. Common source line contact plugs 380 and 480 may be formed of a conductive material such as a metal, a metal compound, and / or doped polysilicon. The common source line contact plug 380 of the first cell area CELL1 may be electrically connected to the common source line 320, and the common source line contact plug 480 of the second cell area CELL2 may be electrically connected to the common source line 420. The first metal line 350a and the second metal line 360a may be sequentially stacked on the common source line contact plug 380 of the first cell area CELL1, and the first metal line 450a and the second metal line 460a may be sequentially stacked on the common source line contact plug 480 of the second cell area CELL2.

[0106] The input / output pads 205, 405, and 406 may be disposed in the external pad bonding area PA. Fig.17 , a lower insulating layer 201 may cover the bottom surface of the first substrate 210, and a first input / output pad 205 may be formed on the lower insulating layer 201. The first input / output pad 205 may be connected to at least one of a plurality of circuit elements 220a disposed in the peripheral circuit region PERI through a first input / output contact plug 203, and may be separated from the first substrate 210 by the lower insulating layer 201. In addition, a side insulating layer may be disposed between the first input / output contact plug 203 and the first substrate 210 to electrically isolate the first input / output contact plug 203 from the first substrate 210.

[0107] An upper insulating layer 401 covering the top surface of the third substrate 410 may be formed on the third substrate 410. Second input / output pads 405 and / or third input / output pads 406 may be disposed on the upper insulating layer 401. The second input / output pads 405 may be connected to at least one of the plurality of circuit elements 220a disposed in the peripheral circuit region PERI through second input / output contact plugs 403 and 303, and the third input / output pads 406 may be connected to at least one of the plurality of circuit elements 220a disposed in the peripheral circuit region PERI through third input / output contact plugs 404 and 304.

[0108] In one or more embodiments, the third substrate 410 may not be disposed in a region where the input / output contact plug is disposed. For example, as shown in region "B", the third input / output contact plug 404 may be separated from the third substrate 410 in a direction parallel to the top surface of the third substrate 410, and may penetrate the interlayer insulating layer 415 of the second cell region CELL2 so as to be connected to the third input / output pad 406. In this case, the third input / output contact plug 404 may be formed by at least one of various processes.

[0109] In one or more embodiments, as shown in region "B1", the third input / output contact plug 404 may extend in a third direction (e.g., Z-axis direction), and the diameter of the third input / output contact plug 404 may gradually increase toward the upper insulating layer 401. In other words, the diameter of the channel structure CH described in region "A1" may gradually decrease toward the upper insulating layer 401, but the diameter of the third input / output contact plug 404 may gradually increase toward the upper insulating layer 401. For example, the third input / output contact plug 404 may be formed after the second cell region CELL2 and the first cell region CELL1 are bonded to each other by a bonding method.

[0110] In some embodiments, as shown in region "B2", the third input / output contact plug 404 may extend in a third direction (e.g., Z-axis direction), and the diameter of the third input / output contact plug 404 may gradually decrease toward the upper insulating layer 401. In other words, like the channel structure CH, the diameter of the third input / output contact plug 404 may gradually decrease toward the upper insulating layer 401. For example, the third input / output contact plug 404 may be formed together with the cell contact plug 440 before the second cell region CELL2 and the first cell region CELL1 are bonded to each other.

[0111] In some embodiments, the input / output contact plug may overlap the third substrate 410. For example, as shown in region "C", the second input / output contact plug 403 may penetrate the interlayer insulating layer 415 of the second cell region CELL2 in a third direction (e.g., Z-axis direction), and may be electrically connected to the second input / output pad 405 through the third substrate 410. In this case, the connection structure of the second input / output contact plug 403 and the second input / output pad 405 may be implemented by various methods.

[0112] In one or more embodiments, as shown in the region “C1”, an opening 408 may be formed to penetrate the third substrate 410, and the second input / output contact plug 403 may be directly connected to the second input / output pad 405 through the opening 408 formed in the third substrate 410. In this case, as shown in the region “C1”, the diameter of the second input / output contact plug 403 may gradually increase toward the second input / output pad 405. However, the embodiments of the present disclosure are not limited thereto, and in some embodiments, the diameter of the second input / output contact plug 403 may gradually decrease toward the second input / output pad 405.

[0113] In some embodiments, as shown in region “C2”, an opening 408 penetrating the third substrate 410 may be formed, and a contact 407 may be formed in the opening 408. One end of the contact 407 may be connected to the second input / output pad 405, and the other end of the contact 407 may be connected to the second input / output contact plug 403. Therefore, the second input / output contact plug 403 may be electrically connected to the second input / output pad 405 through the contact 407 in the opening 408. In this case, as shown in region “C2”, the diameter of the contact 407 may gradually increase toward the second input / output pad 405, and the diameter of the second input / output contact plug 403 may gradually decrease toward the second input / output pad 405. For example, the second input / output contact plug 403 may be formed together with the cell contact plug 440 before the second cell region CELL2 and the first cell region CELL1 are bonded to each other, and the contact 407 may be formed after the second cell region CELL2 and the first cell region CELL1 are bonded to each other.

[0114] In some embodiments shown in region "C3", compared to the embodiment of region "C2", a barrier 409 may also be formed on the bottom end of the opening 408 of the third substrate 410. The barrier 409 may be a metal line formed in the same layer as the common source line 420. Alternatively, the barrier 409 may be a metal line formed in the same layer as at least one of the word lines 430. The second input / output contact plug 403 may be electrically connected to the second input / output pad 405 through the contact 407 and the barrier 409.

[0115] Similar to the second and third input / output contact plugs 403 and 404 of the second cell region CELL2 , a diameter of each of the second and third input / output contact plugs 303 and 304 of the first cell region CELL1 may gradually decrease toward the lower metal pattern 371 e or may gradually increase toward the lower metal pattern 371 e .

[0116] In one or more embodiments, the slit 411 may be formed in the third substrate 410. For example, the slit 411 may be formed at a specific position of the external pad bonding area PA. For example, as shown in area "D", when viewed in a plan view, the slit 411 may be located between the second input / output pad 405 and the cell contact plug 440. Alternatively, when viewed in a plan view, the second input / output pad 405 may be located between the slit 411 and the cell contact plug 440.

[0117] In one or more embodiments, as shown in region "D1", the slit 411 may be formed to penetrate the third substrate 410. For example, when the opening 408 is formed, the slit 411 may be used to prevent fine cracks from occurring in the third substrate 410. However, the embodiments of the present disclosure are not limited thereto, and in some embodiments, the slit 411 may be formed to have a depth in the range of about 60% to about 70% of the thickness of the third substrate 410.

[0118] In some embodiments, as shown in region "D2", a conductive material 412 may be formed in the slit 411. For example, the conductive material 412 may be used to discharge leakage current occurring when driving the circuit elements in the external pad bonding region PA to the outside. In this case, the conductive material 412 may be connected to an external ground line.

[0119] In some embodiments, as shown in the region "D3", an insulating material 413 may be formed in the slit 411. For example, the insulating material 413 may be used to electrically isolate the second input / output pad 405 and the second input / output contact plug 403 disposed in the external pad bonding region PA from the word line bonding region WLBA. Since the insulating material 413 is formed in the slit 411, it is possible to prevent a voltage provided through the second input / output pad 405 from affecting a metal layer on the third substrate 410 disposed in the word line bonding region WLBA.

[0120] In one or more embodiments, the first to third input / output pads 205, 405, and 406 may be selectively formed. For example, the memory device 500 may be implemented to include only the first input / output pad 205 disposed on the first substrate 210, only the second input / output pad 405 disposed on the third substrate 410, or only the third input / output pad 406 disposed on the upper insulating layer 401.

[0121] In one or more embodiments, at least one of the second substrate 310 of the first cell region CELL1 or the third substrate 410 of the second cell region CELL2 may be used as a sacrificial substrate and may be completely or partially removed before or after the bonding process. Additional layers may be stacked after the substrate is removed. For example, the second substrate 310 of the first cell region CELL1 may be removed before or after the bonding process of the peripheral circuit region PERI and the first cell region CELL1, and then, an insulating layer covering the top surface of the common source line 320 or a conductive layer for connection may be formed. Similarly, the third substrate 410 of the second cell region CELL2 may be removed before or after the bonding process of the first cell region CELL1 and the second cell region CELL2, and then, an upper insulating layer 401 covering the top surface of the common source line 420 or a conductive layer for connection may be formed.

[0122] Fig.18 is a block diagram for describing a system 2000 of an electronic device including a device according to one or more embodiments.

[0123] Reference Fig.18 , the system 2000 may include a camera 2100, a display 2200, an audio processor 2300, a modem 2400, DRAMs 2500a and 2500b, flash memories 2600a and 2600b, I / O devices 2700a and 2700b, and an application processor (AP) 2800. The system 2000 may be implemented as a laptop computer, a mobile phone, a smart phone, a tablet PC, a wearable device, a healthcare device, or an Internet of Things (IoT) device. In addition, the system 2000 may be implemented as a server or a PC.

[0124] The camera 2100 can capture still images or videos according to the control of the user, and can store the captured image / video data or send the captured image / video data to the display 2200. The audio processor 2300 can process the audio data or network content included in the flash memory 2600a and 2600b. The modem 2400 can send a modulated signal for wired / wireless data transmission / reception to the receiver, and the modulated signal can be demodulated by the receiver to restore the original signal. The I / O devices 2700a and 2700b may include devices that provide digital input functions and / or digital output functions, such as universal serial bus (USB), storage devices, digital cameras, secure digital (SD) cards, digital versatile disks (DVD), network adapters, touch screens, etc.

[0125] The AP 2800 may control the overall operation of the system 2000. The AP 2800 may include a controller 2810, an accelerator block or an accelerator chip 2820, and an interface block 2830. The AP 2800 may control the display 2200 so that a portion of the content stored in the flash memories 2600a and 2600b is displayed on the display 2200. When a user input is received through the I / O devices 2700a and 2700b, the AP 2800 may perform a control operation corresponding to the user input. The AP 2800 may include an accelerator block that is a circuit dedicated to calculating artificial intelligence (AI) data, or may include an accelerator chip 2820 that is separate from the AP 2800. The DRAM 2500b may be additionally provided in the accelerator block or the accelerator chip 2820. The accelerator block is a functional block dedicated to performing specific functions of the AP2800, and may include a GPU as a functional block dedicated to processing graphic data, a neural processing unit (NPU) as a block dedicated to AI calculation and reasoning, and a data processing unit (DPU) as a block dedicated to data transmission.

[0126] The system 2000 may include a plurality of DRAMs 2500a and 2500b. The AP 2800 may establish a DRAM interface protocol and communicate with the DRAMs 2500a and 2500b to control the DRAMs 2500a and 2500b through commands that comply with the Joint Electron Device Engineering Council (JEDEC) standard and mode register (MRS) settings, or use company-specific functions such as low voltage / high speed / reliability and cyclic redundancy check (CRC) / error correction code (ECC) functions. For example, the AP 2800 may communicate with the DRAM 2500a through an interface that complies with the JEDEC standard, such as LPDDR4 and LPDDR5, and the accelerator block or accelerator chip 2820 may set and use a new DRAM interface protocol to control the DRAM 2500b for an accelerator that has a greater bandwidth than the DRAM 2500a.

[0127] although Fig.18 Only DRAM 2500a and 2500b are shown, but the present disclosure is not limited thereto. As long as the bandwidth, response speed and voltage conditions of AP 2800 or accelerator chip 2820 are met, any memory such as PRAM, SRAM, MRAM, RRAM, FRAM or hybrid RAM can be used. DRAMs 2500a and 2500b have relatively smaller delay and bandwidth than I / O devices 2700a and 2700b or flash memory 2600a and 2600b. When system 2000 is powered on and OS and application data are loaded therein, DRAM 2500a and 2500b are initialized, so DRAM 2500a and 2500b can be used as temporary storage of OS and application data, or can be used as execution space of various software codes.

[0128] In DRAM 2500a and 2500b, four arithmetic operations (i.e., addition, subtraction, multiplication, and division), vector calculations, address calculations, or fast Fourier transform (FFT) calculations can be performed. In addition, in DRAM 2500a and 2500b, functions for operations for reasoning can be performed. Here, an artificial neural network can be used to perform inference in a deep learning algorithm. The deep learning algorithm may include a training operation for learning a model through various data and an inference operation for identifying data using a trained model. According to an embodiment, the image captured by the user through the camera 2100 is signal processed and stored in the DRAM 2500b, and the accelerator block or accelerator chip 2820 can use the data stored in the DRAM 2500b and the function for reasoning to perform AI data calculations for identifying data.

[0129] The system 2000 may include a plurality of storage devices or flash memories 2600a and 2600b having a larger capacity than the DRAM 2500a and 2500b. The accelerator block or accelerator chip 2820 may use the flash memories 2600a and 2600b to perform training operations and AI data calculations. According to an embodiment, the flash memories 2600a and 2600b may include a memory controller 2610 and a flash memory device 2620, and the training operations and inference AI data calculations performed by the AP 2800 and / or the accelerator chip 2820 may be performed more efficiently by using an arithmetic unit included in the memory controller 2610. The flash memories 2600a and 2600b may store images taken by the camera 2100 or data sent over a data network. For example, the flash memories 2600a and 2600b may store augmented reality / virtual reality content, high definition (HD) content, or ultra high definition (UHD) content.

[0130] The system 2000 may perform a first loop operation through a first loop based on a phase difference between the data and the clock to adjust a skew between the data and the clock due to a change in the power supply voltage during clock training between components, and then perform a second loop operation through a second loop. The first loop operation may be performed until there is no phase difference between the data and the clock, and the second loop operation may be performed until a first slope representing a delay change of the DQ data relative to a level of the power supply voltage and a second slope representing a delay change of the DQS clock become identical to each other. Therefore, since no skew occurs between the data and the clock due to power noise, the system 2000 may ensure a valid data window margin in a high-speed data reception operation. The camera 2100, display 2200, audio processor 2300, modem 2400, DRAM 2500a, 2500b, flash memory 2600a, 2600b, I / O devices 2700a and 2700b, and / or AP 2800 in the system 2000 may be partially or completely combined with the above references. Figures 1 to 17 Described embodiments.

[0131] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A device driven by a power supply voltage, the device comprising: A clock circuit comprising: a clock delay scheduler; a first counting logic circuit; and a scheduler controller, wherein the clock circuit is configured to receive a clock signal and adjust a skew between a data signal and the clock signal; and a data input circuit, the data input circuit comprising a sampler circuit configured to receive the data signal and latch the data signal in response to a second clock signal provided by the clock delay scheduler, wherein the first loop includes the clock delay scheduler, the sampler circuit and the first counting logic circuit, and the second loop includes the scheduler controller and the clock delay scheduler, wherein the first counting logic circuit is configured to receive the data signal from the sampler circuit and generate a first counting code based on a phase difference between the clock signal and the data signal, The clock delay scheduler is configured to adjust the delay of the clock signal based on a second counting code and generate the second clock signal. The scheduler controller is configured to generate the second counting code based on the first adjustment code and the second adjustment code, and The clock circuit is further configured as follows: based on identifying a phase difference between the data signal and the clock signal, causing one or more first loop operations to be performed through the first loop until the phase difference is eliminated, obtaining a first value of the first counting code by causing one or more of the one or more first loop operations to be performed when the level of the power supply voltage is a first power supply voltage level, and storing the first value as the first adjustment code, obtaining a second value of the first counting code by causing one or more of the one or more first loop operations to be performed when the level of the power supply voltage is a second power supply voltage level higher than the first power supply voltage level, and storing the second value as the second adjustment code, and Based on identifying a difference between a first slope representing a change in delay of the data signal relative to the first power supply voltage level and the second power supply voltage level and a second slope representing a change in delay of the clock signal, one or more second loop operations are performed through the second loop until the first slope and the second slope are the same.

2. The device according to claim 1, wherein the clock circuit further comprises a variable delay circuit configured to delay the clock signal based on the first counting code, and The first loop further includes the variable delay circuit. 3 . The apparatus according to claim 2 , wherein the variable delay circuit comprises a delay unit configured to be turned on or off according to the first counting code.

4. The device according to claim 1, The clock delay scheduler includes a plurality of first delay circuits and a plurality of second delay circuits connected in series, and the clock signal is input to the plurality of first delay circuits and the plurality of second delay circuits. wherein the plurality of first delay circuits are configured to have positive sensitivity, wherein the delay amount changes in response to the first power supply voltage level and the second power supply voltage level, and the plurality of second delay circuits are configured to have negative sensitivity, wherein the delay amount does not change, and The clock circuit is further configured as follows: The number of the plurality of first delay circuits is increased by changing at least one of the plurality of second delay circuits from negative sensitivity to positive sensitivity.

5. The apparatus of claim 1, wherein the scheduler controller comprises: a register configured to store the first adjustment code and the second adjustment code; a comparator configured to compare the first adjustment code and the second adjustment code; as well as A second counting logic circuit is configured to generate the second counting code based on a difference between the first adjustment code and the second adjustment code.

6. The device according to claim 1, wherein: The data input circuit also includes a circuit element configured to transmit the data signal to the sampler circuit.

7. The device according to claim 6, wherein the data input circuit further comprises a variable delay circuit configured to delay the data signal based on the first counting code, and in, The first loop also includes the variable delay circuit and the circuit element. 8 . The apparatus according to claim 7 , wherein the variable delay circuit comprises a delay unit configured to be turned on or off according to the first counting code. 9 . The apparatus of claim 1 , further comprising a voltage regulator configured to provide the first power voltage level or the second power voltage level to a power voltage line.

10. A device driven by a power supply voltage, the device comprising: a data input circuit comprising a sampler circuit configured to receive a data signal and latch the data signal in response to a clock signal provided by a clock delay scheduler; as well as A clock circuit comprising: the clock delay scheduler; a clock buffer; a duty cycle corrector; a first logic circuit; and a scheduler controller, Wherein, the clock circuit is configured as follows: receiving a first clock signal having a first swing width through the clock buffer, converting the first clock signal into a second clock signal, wherein the second clock signal is amplified to a second swing width greater than the first swing width, and adjusting a skew between the data signal and the second clock signal, wherein a first loop includes the clock delay scheduler, the duty cycle corrector, the sampler circuit and a first counting logic circuit, and a second loop includes the scheduler controller and the clock delay scheduler, wherein the duty cycle corrector is configured to receive the first clock signal from the clock buffer and adjust the duty cycle of the first clock signal based on a first counting code, wherein the first counting logic circuit is configured to receive the data signal from the sampler circuit and generate the first counting code based on a phase difference between the second clock signal and the data signal, wherein the clock delay scheduler is configured to receive the first clock signal from the duty cycle corrector and adjust the first clock signal based on a second counting code, wherein the scheduler controller is configured to generate the second counting code based on the first adjustment code and the second adjustment code, and The clock circuit is further configured as follows: obtaining a first value of the first counting code by causing one or more first loop operations to be performed through the first loop when the level of the power supply voltage is a first power supply voltage level, and storing the first value as the first adjustment code, obtaining a second value of the first counting code by causing one or more of the one or more first loop operations to be performed through the first loop when the level of the power supply voltage is a second power supply voltage level higher than the first power supply voltage level, and storing the second value as the second adjustment code, and Based on identifying a difference between a first slope representing a change in delay of the data signal relative to the first power supply voltage level and the second power supply voltage level and a second slope representing a change in delay of the clock signal, one or more second loop operations are performed through the second loop until the first slope and the second slope are the same.

11. The device according to claim 10, The clock delay scheduler comprises: a level conversion circuit configured to convert the first clock signal into the second clock signal; and multiple delay circuits, wherein the plurality of delay circuits are configured to have negative sensitivity, wherein an amount of delay does not change in response to the first power supply voltage level and the second power supply voltage level, and The clock circuit is further configured as follows: Based on the second count code, the number of the plurality of delay circuits is increased by operating at least one of the plurality of delay circuits with a positive sensitivity in which the delay amount changes with respect to the first power supply voltage level and the second power supply voltage level.

12. The apparatus of claim 10, wherein the scheduler controller comprises: a register configured to store the first adjustment code and the second adjustment code; a comparator configured to compare the first adjustment code and the second adjustment code; as well as The second counting logic circuit is configured to generate the second counting code based on a difference between the first adjustment code and the second adjustment code.

13. The device according to claim 10, wherein the clock buffer comprises a frequency divider circuit configured to receive the first clock signal and generate a multi-phase clock signal, wherein the multi-phase clock signal comprises a first-phase clock signal, a second-phase clock signal, a third-phase clock signal and a fourth-phase clock signal, wherein the first-phase clock signal, the second-phase clock signal, the third-phase clock signal and the fourth-phase clock signal are all generated by dividing the frequency of the first clock signal, and Each of the first phase clock signal, the second phase clock signal, the third phase clock signal and the fourth phase clock signal is provided to the duty cycle corrector. 14 . The apparatus of claim 10 , further comprising a voltage regulator configured to provide the first power supply voltage level or the second power supply voltage level to a power supply voltage line.

15. A method for adjusting a skew between a data signal and a clock signal of a device, the device being driven by a power supply voltage and comprising a sampler circuit that latches the data signal in response to the clock signal, the method comprising: receiving the data signal via a data buffer of the device; receiving the clock signal via a clock buffer of the device; repeatedly performing one or more first loop operations through a first loop of the apparatus until the phase difference is eliminated based on identifying a phase difference between the data signal and the clock signal, wherein the first loop includes the sampler circuit and a first counting logic circuit; when the level of the power supply voltage is a first power supply voltage level, obtaining a first adjustment code by causing one or more of the one or more first loop operations to be performed through the first loop; when the level of the power supply voltage is a second power supply voltage level higher than the first power supply voltage level, obtaining a second adjustment code by causing one or more of the one or more first loop operations to be performed; storing the first adjustment code and the second adjustment code in a scheduler controller of the device; as well as Based on identifying a difference between a first slope representing a change in the delay of the data signal relative to the first power supply voltage level and the second power supply voltage level and a second slope representing a change in the delay of the clock signal, one or more second loop operations are performed by a second loop of the device until the first slope and the second slope are the same, wherein the second loop includes the scheduler controller and the clock delay scheduler of the device.

16. The method according to claim 15, wherein the apparatus further comprises a variable delay circuit connected to the clock buffer, and the first loop further comprises the variable delay circuit, and in, Performing the one or more first loop operations by the first loop includes: generating a first counting code by comparing a phase of the data signal with a phase of the clock signal based on that the level of the power supply voltage is the first power supply voltage level; updating the first counting code based on identifying a difference between a phase of the data signal and a phase of the clock signal; adjusting a delay amount of the variable delay circuit based on the first counting code; and Based on recognizing that a difference between a phase of the data signal and a phase of the clock signal is eliminated, the first count code is stored in the scheduler controller as the first adjustment code.

17. The method according to claim 15, wherein the apparatus further comprises a variable delay circuit connected to the clock buffer, and the first loop further comprises the variable delay circuit, and in, Performing the one or more first loop operations by the first loop includes: generating a first counting code by comparing a phase of the data signal with a phase of the clock signal based on that the level of the power supply voltage is the second power supply voltage level; updating the first counting code based on identifying a difference between a phase of the data signal and a phase of the clock signal, adjusting a delay amount of the variable delay circuit based on the first counting code; and Based on recognizing that a difference between a phase of the data signal and a phase of the clock signal is eliminated, the first count code is stored in the scheduler controller as the second adjustment code.

18. The method according to claim 15, The clock delay scheduler includes a plurality of first delay circuits and a plurality of second delay circuits connected in series, wherein the plurality of first delay circuits are configured to have positive sensitivity, wherein the delay amount changes in response to the first power supply voltage level and the second power supply voltage level, and the plurality of second delay circuits are configured to have negative sensitivity, wherein the delay amount does not change, and Wherein performing the one or more second loop operations through the second loop includes increasing the number of the plurality of first delay circuits by causing at least one second delay circuit of the plurality of second delay circuits to operate with the positive sensitivity.

19. The method according to claim 15, in, The apparatus further includes a circuit element configured to transmit the data signal to the sampler circuit; and a variable delay circuit connected to the clock buffer and configured to delay the data signal based on the first counting code, and wherein the variable delay circuit and the circuit element are included in the first loop, and The method further includes delaying the data signal using the circuit element and the variable delay circuit.

20. The method of claim 15, wherein receiving the clock signal through the clock buffer comprises: receiving a first clock signal including a first swing width; as well as The duty cycle of the first clock signal is adjusted.

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