Memory systems, their operation methods, and readable storage media

Abstract

Embodiments of the present disclosure provide a memory system and an operating method thereof and a readable storage medium, the memory system comprising: a memory device; a memory controller coupled with the memory device and configured to: compress a first mapping table to obtain a second mapping table; the first mapping table comprising a correspondence between an index part of each element of all elements corresponding to an error correction coding equation and an equation coefficient, the index part of all elements being a group of continuous data; the second mapping table comprising a correspondence between an index part of part of all elements and an equation coefficient, the index part of the part being a plurality of node data extracted from the continuous data; and using the node data in the second mapping table, obtaining the equation coefficient corresponding to the index part of any element of all elements through segmented query.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a memory system, its operation method, and a readable storage medium. Background Technology

[0002] Memory devices are storage equipment used to preserve information in modern information technology. As a typical non-volatile semiconductor memory, NAND flash memory has gradually become the mainstream product in the memory market due to its high storage density, controllable production costs, suitable erase and rewrite speeds, and retention characteristics. However, as people's requirements for storage devices continue to increase, there is still much room for improvement in memory devices and their systems. Summary of the Invention

[0003] According to some aspects of embodiments of this disclosure, a memory system is provided, comprising:

[0004] Memory devices;

[0005] A memory controller, coupled to the memory device and configured to:

[0006] The first mapping table is compressed to obtain a second mapping table. The first mapping table includes the correspondence between the exponents of all elements in the error correction coding equation and the equation coefficients, where the exponents of all elements are a set of continuous data. The second mapping table includes the correspondence between the exponents of some elements in the entire set and the equation coefficients, where the exponents of some elements are multiple node data extracted from the continuous data. Using the node data in the second mapping table, the equation coefficients corresponding to the exponents of any element in the entire set are obtained through segmented queries.

[0007] In some embodiments, all elements and their corresponding equation coefficients are finite fields; the memory controller is configured to: generate all elements corresponding to the error correction coding equation; generate the first mapping table based on all elements; group the exponents of each element in the first mapping table and their corresponding equation coefficients, and select the exponent of a fixed element in each group as the node data; and obtain the second mapping table using the node data and the equation coefficients corresponding to the node data.

[0008] In some embodiments, the total number of elements contained in each group is substantially the same, the exponent portion of all elements contained in each group is a set of continuous data, and the exponent portion of a fixed element in each group is the first data in the continuous data in each group.

[0009] In some embodiments, the memory controller is further configured to: when an error occurs while reading stored data in the memory device, obtain an error correction decoding inverse matrix by querying node data in the second mapping table and calculating the corresponding bias; and use the error correction decoding inverse matrix to perform error correction.

[0010] In some embodiments, the memory controller is specifically configured to:

[0011] When an error occurs while reading stored data from the memory device, multiple elements corresponding to the erroneous stored data are retrieved;

[0012] Using the multiple elements corresponding to the erroneous stored data, a first matrix is ​​obtained;

[0013] Obtain the equation coefficients corresponding to the exponential part of each element in the first matrix to obtain the second matrix;

[0014] Calculate the inverse of the second matrix to obtain the error correction decoding inverse matrix.

[0015] In some embodiments, the memory controller is specifically configured to:

[0016] For the exponent portion of each element in the first matrix, determine the group to which the exponent portion of the corresponding element falls and the offset between the exponent portion of the corresponding element and the exponent portion of a fixed element in the corresponding group; and

[0017] By querying the second mapping table, the equation coefficients corresponding to the exponential part of the fixed element falling into the corresponding group are obtained;

[0018] Using the obtained equation coefficients and the offset values, calculate the equation coefficients corresponding to the exponential part of the corresponding element.

[0019] In some embodiments, the memory controller further includes: an encoding circuit configured to:

[0020] Based on all the elements, generate the corresponding equation coefficient matrix;

[0021] Using the coefficient matrix of the equation, generate the encoding matrix;

[0022] Using the encoding matrix, the stored data to be written into the memory device is encoded to obtain the verification data corresponding to the stored data.

[0023] In some embodiments, the memory controller further includes a decoding circuit, the decoding circuit being configured to:

[0024] The recovered stored data is obtained by performing a decoding operation using the error correction decoding inverse matrix, the remaining stored data that has not contained errors, and the verification data corresponding to the stored data.

[0025] In some embodiments, the encoding circuit and / or the decoding circuit both include a linear feedback shift register (LFSR) circuit.

[0026] In some embodiments, the memory controller is further configured to:

[0027] Perform a read operation on the stored data in the memory device:

[0028] When an error occurs in the stored data being read, the erroneous stored data is reread.

[0029] If the stored data still contains errors after being reread, perform software decoding on the stored data that still contains errors.

[0030] When errors still occur in the stored data after software decoding, the errors are corrected using the error correction decoding inverse matrix.

[0031] In some embodiments, the second mapping table is stored in the read-only memory (ROM) of the memory device or the memory controller.

[0032] According to some aspects of embodiments of this disclosure, a method for operating a memory system is provided, including:

[0033] The first mapping table is compressed to obtain the second mapping table. The first mapping table includes the correspondence between the exponent part of each element in the error correction coding equation and the equation coefficients. The exponent part of all elements is a set of continuous data. The second mapping table includes the correspondence between the exponent part of some elements in the entire set and the equation coefficients. The exponent part of some elements is multiple node data extracted from the continuous data.

[0034] Using the node data in the second mapping table, the equation coefficients corresponding to the exponential part of any element among all the elements are obtained through segmented queries.

[0035] In some embodiments, all elements and their corresponding equation coefficients are finite fields; the method further includes:

[0036] Generate all elements corresponding to the error correction coding equation;

[0037] Generate the first mapping table based on all the elements;

[0038] During the compression of the first mapping table, the exponent part of each element and the corresponding equation coefficient in all elements of the first mapping table are grouped, and the exponent of a fixed element in each group is selected as node data.

[0039] The second mapping table is obtained using the node data and the corresponding equation coefficients.

[0040] In some embodiments, the total number of elements contained in each group is substantially the same, the exponent portion of all elements contained in each group is a set of continuous data, and the exponent portion of a fixed element in each group is the first data in the continuous data in each group.

[0041] In some embodiments, the method further includes:

[0042] When an error occurs while reading stored data from the memory device, the error correction decoding inverse matrix is ​​obtained by querying the node data in the second mapping table and calculating the corresponding bias.

[0043] Error correction is performed using the inverse error correction decoding matrix.

[0044] In some embodiments, obtaining the error correction decoding inverse matrix by querying node data in the second mapping table and calculating the corresponding bias includes:

[0045] When an error occurs while reading stored data from the memory device, multiple elements corresponding to the erroneous stored data are retrieved;

[0046] Using the multiple elements corresponding to the erroneous stored data, a first matrix is ​​obtained;

[0047] Obtain the equation coefficients corresponding to the exponential part of each element in the first matrix to obtain the second matrix;

[0048] Calculate the inverse of the second matrix to obtain the error correction decoding inverse matrix.

[0049] In some embodiments, obtaining the equation coefficients corresponding to the exponential portion of each element in the first matrix includes:

[0050] For each element's partial exponent in the first matrix, determine the group to which the exponent portion of the corresponding element falls and the offset between the exponent portion of the corresponding element and the exponent portions of fixed elements within the corresponding group; and

[0051] By querying the second mapping table, the equation coefficients corresponding to the power exponents of the fixed elements falling into the corresponding group are obtained;

[0052] Using the obtained equation coefficients and the offset values, calculate the equation coefficients corresponding to the exponential part of the corresponding element.

[0053] In some embodiments, the method further includes:

[0054] Based on all the elements, generate the corresponding equation coefficient matrix;

[0055] Using the coefficient matrix of the equation, generate the encoding matrix;

[0056] Using the encoding matrix, the stored data to be written into the memory device is encoded to obtain the verification data corresponding to the stored data.

[0057] In some embodiments, the error correction using the error correction decoding inverse matrix includes:

[0058] The recovered stored data is obtained by performing a decoding operation using the error correction decoding inverse matrix, the remaining stored data that has not contained errors, and the verification data corresponding to the stored data.

[0059] In some embodiments, the method further includes:

[0060] Perform a read operation on the stored data in the memory device:

[0061] When an error occurs in the stored data being read, the erroneous stored data is reread.

[0062] If the stored data still contains errors after being reread, perform software decoding on the stored data that still contains errors.

[0063] When errors still occur in the stored data after software decoding, the errors are corrected using the error correction decoding inverse matrix.

[0064] According to some aspects of embodiments of the present disclosure, a memory controller is provided, the memory controller being configured to:

[0065] The first mapping table is compressed to obtain the second mapping table. The first mapping table includes the correspondence between the exponent part of each element in the error correction coding equation and the equation coefficients. The exponent part of all elements is a set of continuous data. The second mapping table includes the correspondence between the exponent part of some elements in the entire set and the equation coefficients. The exponent part of some elements is multiple node data extracted from the continuous data.

[0066] Using the node data in the second mapping table, the equation coefficients corresponding to the exponential part of any element among all the elements are obtained through segmented queries.

[0067] According to some aspects of embodiments of the present disclosure, a readable storage medium is provided that stores a computer program, which, when executed, implements the operation method.

[0068] This embodiment compresses the first mapping table to generate a second mapping table. The second mapping table includes the correspondence between the exponents of some elements in all elements and the coefficients of the equations. The exponents of some elements are multiple node data extracted from the continuous data. Using the node data in the second mapping table, the equation coefficients corresponding to the exponents of any element in all elements are obtained through segmented queries. In this way, the second mapping table can obtain arbitrary equation coefficients. At the same time, the amount of data included in the second mapping table is smaller than that in the first mapping table, and storing the second mapping table can reduce the storage capacity occupied by the mapping table. Attached Figure Description

[0069] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0070] Figure 2a This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0071] Figure 2b This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of the present disclosure;

[0072] Figure 3 This is a schematic diagram of an exemplary memory device including peripheral circuitry according to an embodiment of the present disclosure;

[0073] Figure 4 This is a schematic cross-sectional view of a memory cell array including NAND memory strings according to an embodiment of the present disclosure;

[0074] Figure 5 This is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuitry according to an embodiment of the present disclosure;

[0075] Figure 6 This is a schematic diagram of a read operation process including a reread operation according to an embodiment of the present invention;

[0076] Figure 7 This is a block diagram illustrating the application of a memory controller including an error correction module in a memory system according to an embodiment of the present disclosure.

[0077] Figures 8a to 8d This is a schematic diagram of the equation coefficients in an embodiment of the present disclosure;

[0078] Figure 9 This is a schematic diagram of a mapping table according to an embodiment of the present disclosure;

[0079] Figure 10a This is a schematic diagram of a first mapping table according to an embodiment of the present disclosure;

[0080] Figure 10b This is a schematic diagram of a second mapping table according to an embodiment of the present disclosure;

[0081] Figure 10c This is a schematic diagram of a table lookup calculation method according to an embodiment of the present disclosure;

[0082] Figures 11a to 11e This is a schematic diagram of error correction encoding and error correction decoding according to an embodiment of the present disclosure;

[0083] Figures 12a to 12d This is a schematic diagram illustrating the use of inverse matrix decoding in an embodiment of this disclosure;

[0084] Figures 13a to 13b This is a schematic diagram illustrating another embodiment of the present disclosure using inverse matrix decoding;

[0085] Figure 14 This is a schematic diagram illustrating an operation method of a memory system according to an embodiment of the present disclosure.

[0086] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0087] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0088] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0089] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0090] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments of this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0091] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0092] The memory devices in the embodiments of this disclosure include, but are not limited to, three-dimensional NAND type memory. For ease of understanding, three-dimensional NAND type memory will be used as an example for explanation.

[0093] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory device 104.

[0094] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0095] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0096] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2aIn one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include components for connecting the SSD 206 to a host computer (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0097] Figure 3 A schematic circuit diagram of an exemplary memory device 300, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 104 is provided. Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 is illustrated as a three-dimensional NAND-type memory cell array, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0098] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to write one of three possible nominal storage values ​​into the cell, while a fourth nominal storage value in addition to these three nominal storage values ​​can be used to indicate an erase state.

[0099] like Figure 3 As shown, each NAND memory string 308 may include a lower select gate (BSG) 310 at its source end and an upper select gate (TSG) 312 at its drain end. BSG 310 and TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of NAND memory strings 308 within the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 within the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0100] like Figure 3As shown, NAND memory strings 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304a, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 314 of the selected memory block 304a and the unselected memory block 304b on the same face as the selected memory block 304a. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0101] Figure 4 A schematic cross-sectional view of an exemplary memory cell array 301 including NAND memory strings 308 is shown, according to some aspects of this disclosure. Figure 4 As shown, the NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 stacked alternately in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 determines the number of memory cells included in the memory cell array 301.

[0102] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0103] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0104] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0105] Return to reference Figure 3 The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0106] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory cell array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store programming data (write data) to be programmed into memory cell array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0107] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0108] In some specific embodiments, the programming operation may include multiple stages. For example, the programming operation may include a channel pre-charge stage, a channel boost stage, a programming pulse stage, and a recovery stage. In the channel pre-charge stage, a voltage generator can generate the voltage required for the next stage, such as the voltage applied to each gate, the channel boost voltage, etc.; in the channel boost stage, a channel boost voltage can be applied to the selected word line; in the programming pulse stage, the target voltage for each programming operation can be applied to the selected word line. In the recovery stage, the voltage can be reduced to the corresponding voltage, such as Vcc or Vdd, for both unselected and selected word lines. The recovery stage can achieve this by stepping down the voltage to the corresponding voltage once or multiple times, for example, by first reducing the voltage to an intermediate voltage, maintaining it at that intermediate voltage for a period of time, and then reducing it to the corresponding voltage.

[0109] Control logic 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bitline driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0110] In some embodiments, the storage cells of a NAND type memory can be classified into single-level storage cells (one-bit storage cell), double-level storage cells (two-bit storage cells), triple-level storage cells (three-bit storage cells), quadruple-level storage cells (four-bit storage cells), and five-level storage cells (five-bit storage cells) according to storage density. However, regardless of whether it is a single-level or multi-level storage cell, its read operation can be performed on a page-by-page basis. Specifically, when performing a read operation, a read voltage is applied to the word line (i.e., the selected word line) coupled to the selected page in the memory device 104. When the read voltage reaches the threshold voltage of the plurality of storage cells coupled to the selected word line, or when the number of storage cells that do not reach the threshold voltage is within an allowable range, the read operation of the entire page ends. The storage cell can be an M-bit storage cell, and the storage cell has 2 bits including an erase state. M One storage state, through 2 M-1 read voltage reads M bits of stored data. For example, the first read voltage is between the threshold voltages of the erase state and the first storage state. When the first read voltage is applied to the word line, the memory cell in the erase state is turned on, and the memory cell in the first storage state is not turned on. The erase state and the first storage state are distinguished and read.

[0111] It should be noted that during the read operation, memory cells that do not reach the target threshold voltage are marked as error bits. To prevent read errors, an error correction code (ECC) is introduced. When the number of error bits is less than or equal to the maximum number of failure bits that the error correction code can correct, all error bits in the read operation can be corrected, thus enabling correct data reading.

[0112] In some embodiments, the host 108 sends a read command (or read instruction, read request) to the memory controller 106 according to the current user command requirements. The memory controller 106 transmits the read control command, including information such as a logical address-physical address mapping table, to the memory device 104 through interface 516, controlling the memory device 104 to perform a read operation on the memory cell corresponding to the corresponding physical address. The memory device 104 then sends the read data back to the memory controller 106 through interface 516. The memory controller 106 then feeds the data back to the host 108 via an interface such as PCIe or SATA. Specifically, the memory controller 106 sends the read control command to the control logic of the memory device through interface 516. The control logic applies a relevant operating voltage to the selected word line or bit line according to the relevant physical address, thereby performing a read operation on the corresponding memory cell. The operating voltage can be generated by the control logic according to the relevant read voltage mapping table, controlled by a voltage generator, and then applied to the word line of the corresponding address after decoding by a row decoder, or applied to the bit line of the corresponding address after decoding by a column decoder.

[0113] In other embodiments, when the memory device 104 reads a corresponding memory cell under the control of the memory controller 106 and a read error occurs, the memory controller 106 responds to the read operation failure by controlling the memory (or the error correction module in the memory controller 106). The error correction mode may include ECC error correction. According to some aspects of embodiments of this disclosure, Figure 6 A schematic diagram illustrating an exemplary read operation flow of a memory system 102 is shown. Combined with Figure 6As shown, when the memory controller 106 controls the memory device 104 to perform a read operation, it first performs a default read operation (FW default read) on the memory cell at the corresponding physical address. If the default read fails, a read retry operation is performed. If the read retry operation fails, a soft decode operation is performed. If the soft decode operation fails, a redundant array data recovery (RAID) operation is performed. If the RAID operation fails, the read operation stops and fails because it cannot correct errors. The memory controller 106 sends a read fail signal to the host 108. The read retry operation and the default read operation can be applied to hardware decoding.

[0114] Error correction operations such as rereading, software decoding, and RAID can be performed on the memory device 104 by the error correction module 1064 (e.g., an ECC module) in the memory controller 106. Control commands are sent from the memory controller 106 to the memory device 104 via interface 516, and the memory device 104 feeds back the read information to the memory controller 106 via interface 516. It should be noted that subsequent operations can be stopped after any one of the rereading, software decoding, or RAID operations is successfully completed. Figure 6 The illustration shows only one example of a read operation process. In some other embodiments, the memory controller 106 can control the memory device 104 to perform reread operations, software decoding, and RAID operations in any order. This disclosure does not limit the execution order. According to some aspects of embodiments of this disclosure, Figure 7 A block diagram of a memory system 102 including a memory controller 106 and an error correction module 1064 is provided. (Refer to...) Figure 7 As shown, the memory system 102 includes a memory controller 106 and a memory. The memory controller 106 and the memory device 104 can be coupled in any suitable manner. In this embodiment, the memory controller 106 includes a host I / F 1061, a memory I / F 1062, a control unit 1063, an error correction (ECC) module 1064, a data buffer 1067, and an internal bus 1060. The error correction module 1064 includes an encoding unit 1065 and a decoding unit 1066. The host I / F 1061 outputs commands received from the host 108, user data (write data), etc., to the internal bus 1060, and sends user data read from the memory device 104 (read data), responses from the control unit 1063, etc., back to the host 108.

[0115] The memory I / F controls the processes of writing user data to and reading from the memory device 104 based on instructions from the control unit 1063. The control unit 1063, such as a central processing unit (CPU) or microprocessor (MPU), controls the memory system 102 as a whole. The control unit 1063 performs control according to commands received from the host 108 via the host I / F 1061. For example, the control unit 1063 instructs the memory I / F to write user data and perform parity checks on the memory device 104 based on commands from the host 108. Furthermore, the control unit 1063 instructs the memory I / F to read user data and perform parity checks from the memory device 104 based on commands from the host 108.

[0116] The error correction module 1064 includes an encoding unit 1065 and a decoding unit 1066. The encoding unit 1065 encodes user data of a predetermined size written on the same page to generate parity data. The parity data is written to the page containing the user data that forms the basis of the encoding, and the decoding unit 1066 uses the parity data for decoding. The data buffer 1067 temporarily stores user data received from the host 108 before storing it in the memory device 104, and temporarily stores data read from the memory device 104 before sending it to the host 108. The encoding unit 1065 includes encoding circuitry for encoding, and the decoding unit 1066 includes decoding circuitry for decoding.

[0117] In some specific embodiments, a software decoding operation can be understood as performing data re-decoding through a decoding unit (e.g., a software decoder) in the memory controller 106, and then performing a read operation based on the re-decoded data. A RAID operation can be understood as achieving data mirroring through secondary encoding, reconstructing the stored data and its parity check data. Typically, the re-encoding of the stored data for a redundant array is performed in the data buffer of the memory controller 106.

[0118] Regarding RAID error correction, when writing to a region of the memory device, the written data is encoded according to the relevant RAID encoding method. Simultaneously, parity data generated from the written data is stored. When a data read error occurs and RAID error correction is required, the correct data is deduced from the parity data and other intact data. Data written to the memory device can be grouped, with each group designated as a source data group. Each source data group is processed using the same encoding equation (e.g., XORing each group of written data) to obtain multiple sets of parity data, each corresponding to a specific set of parity data. When data errors or failures occur, each set of parity data can correct and recover one or more erroneous data points from its corresponding group. Essentially, this method solves a linear equation using parity data. To achieve higher error correction capabilities, multiple different error correction encoding equations need to be constructed to generate multiple sets of parity data for each group of written data. Solving these equations corrects and recovers erroneous data from a given group of written data. In some embodiments, RAID error correction can be implemented through the memory controller to correct read errors. Each set of data may include data written to multiple storage units, or data written to multiple pages. The memory controller may include an encoding unit 1065 and a decoding unit 1066. The encoding unit 1065 includes an encoding circuit and performs RAID encoding operations. The decoding unit 1066 includes a decoding circuit and performs RAID decoding operations, and interacts with the memory device through the memory I / F 1062.

[0119] In some embodiments, for example, a source data group may include data stored in one or more word-line coupled storage units, such as P data items written to one or more word lines, where P is a positive integer. The corresponding coefficients applied to RAID encoding are also P. In some embodiments, the memory device has a higher integration level, and a source data group may include 2... ^ Writing data to 16 pages requires 2 ^ Sixteen equation coefficients or more.

[0120] In this embodiment of the RAID, the encoding coefficients can be used in matrix operations with the source data group during encoding to obtain check data. Multiple encoding coefficients constitute an error correction encoding equation. One error correction encoding equation is operated with the source data group to obtain one check data. Multiple error correction encoding equations are operated with the source data multiple times to obtain multiple check data. The number of check data is the maximum data volume of the subsequent RAID decoding and recovery data. The equation coefficients are the encoding coefficients, and the equation coefficients corresponding to multiple error correction encoding equations are all linearly independent, making the RAID decoding and recovery data have a unique solution.

[0121] In some embodiments, Figure 8a A schematic diagram illustrating the encoding of verification data according to an embodiment of this disclosure is shown. (Refer to...) Figure 8a As shown, the source data group includes 2 ^ 16-1 data blocks, D0 to D(2 ^ 16-1), each data block may include data in a storage unit or data written to a page. D0 to D(2 ^ 16-1) Form a column vector (which can also be considered as a matrix with only one column) with 2 rows. ^ 16. The matrix multiplied by a column vector is the coefficient matrix of the equation. The number of columns in the coefficient matrix is ​​n = 2. ^ 16, each row represents an error correction coding equation, and each error correction coding equation includes 2 ^ The coefficients of the 16 equations are equal to the number of data blocks in the source data set. The number of rows in the equation coefficient matrix, i.e., the number of error-correcting coding equations, is equal to the number of generated check data. Figure 8a The equation coefficient matrix shown has k=4 rows, meaning there are 4 error correction coding equations multiplied by the source data set to obtain 4 parity data, Parity1 to Parity4. The equation matrix is ​​a linearly independent matrix; the equation coefficients in the first row can all be 1, and the equation coefficients in the first column can all be 1. When D0 to D(2 ^ If no more than four data blocks in 16-1) are faulty at the same time, the same number of check data blocks as the number of faulty data blocks can be selected for decoding and recovery.

[0122] In some embodiments, combined with Figure 8a As shown, when decoding RAID to reverse-engineer the source data, matrix calculations are needed to perform on the parity data and the inverse matrix of the equation coefficient matrix to reverse-engineer the source data group, thereby recovering the data that was read incorrectly. Alternatively, rows corresponding to the erroneous data can be selected from the equation coefficient matrix to form a matrix, and its inverse matrix can be used to reverse-engineer and read the erroneous data. In this embodiment, the equation coefficient matrix can be configured with coefficients similar to the Vandermonde matrix, making it a full-rank matrix. The entire equation coefficient matrix is ​​invertible, and any m rows taken from the equation coefficient matrix to form an m-order matrix are also invertible. (Refer to...) Figure 8b As shown, in this embodiment of the disclosure, each row of the Vandermonde matrix can be mapped to an exponential term. For example, the first row of data can correspond to 1^0, the second row of data can correspond to an exponent of 1, and the third row of data can correspond to an exponent of 2; the first column of data is all 1. Any m rows taken from this matrix to form an m-order matrix are invertible and can be linearly independent matrices. (Refer to...) Figure 8c As shown, Figure 8b When the Vandermonde matrix is ​​applied to the coefficient matrix of equations, the coefficients of each equation in the coefficient matrix are related to... Figure 8b The Vandermonde matrices in the matrix correspond one-to-one. For example, GF(1) corresponds to x^1, GF(2) corresponds to x^2, and GF((k-1)(n-1)) corresponds to (x^(n-1))^(k-1).

[0123] In some embodiments, it can be based on Figure 8a The equation coefficient matrix is ​​processed to obtain a new matrix, which can be denoted as the encoding matrix. For example, an identity matrix (with all data on the diagonal being 1 and the rest being 0) can be added to the equation coefficient matrix. The number of data in each row of the identity matrix is ​​equal to the number of data in each row of the equation coefficient matrix, so that the data obtained after matrix multiplication includes both check data and data from D0 to D(2). ^ 16-1), the data can be stored in the whole in the future to reduce the loss of source data.

[0124] In this embodiment of the disclosure, reference is made to Figures 8a to 8c As shown, the equation coefficients in the equation coefficient matrix can be taken from a data field containing non-zero numbers, and the number of data points in the data field is greater than or equal to the number of elements D in the source data set. Figure 8a In the source data set, D0 to D(2) ^ For example, 16-1) includes at least 2 ^ 16 data points. Corresponding to computer binary algorithms, this can be... Figure 8b If x is 2, then Figure 8c The coefficients of the equations can be denoted as 1, GF(2^1), GF(2^2), GF(2^3), GF(2^(n-1)). 2^(n-1) can be recorded or mapped as an element in the relevant mapping table, and can be denoted as element 2^i in the mapping table, with the exponent part of the element being i, and the coefficients of the relevant equations are denoted as GF(2^i).

[0125] Reference Figure 8d , Figure 8d A schematic diagram of a portion of the equation coefficient matrix is ​​shown, showing only GF(2^1) to GF(2^10), i.e., the exponents 1 to 10; more exponents are not shown. The equation coefficients can be associated with a mapping table, facilitating firmware calls or calculation of equation coefficients. The more equation coefficients, the larger the data volume of the mapping table. This disclosure provides a memory system that, while satisfying RAID error correction encoding or decoding operations with the same amount of data written, reduces the data volume of the relevant mapping table, thereby reducing the storage space occupied by the relevant mapping table.

[0126] According to some aspects of embodiments of this disclosure, a memory system is provided, comprising:

[0127] Memory devices;

[0128] A memory controller, coupled to the memory device and configured to:

[0129] The first mapping table is compressed to obtain the second mapping table. The first mapping table includes the correspondence between the exponent part of each element in the error correction coding equation and the equation coefficients. The exponent part of all elements is a set of continuous data. The second mapping table includes the correspondence between the exponent part of some elements in the entire set and the equation coefficients. The exponent part of some elements is multiple node data extracted from the continuous data.

[0130] Using the node data in the second mapping table, the equation coefficients corresponding to the exponential part of any element among all the elements are obtained through segmented queries.

[0131] Combination Figure 8d As shown, an error correction coding equation can be Figure 8d In the equation coefficient matrix, each element corresponding to the error correction coding equation in a row includes 2^i, where i is a natural number and i represents the exponent of each element. The equation coefficient is the value in a row of the equation coefficient matrix. i takes the form of a natural number; when i is 0, the corresponding equation coefficient is 1, and when i is a non-zero number, the corresponding equation coefficient is GF(2^i).

[0132] Combination Figure 8b As shown, the equation coefficient matrix formed by the equation coefficients in this embodiment of the present disclosure can be a linearly independent matrix and an invertible full-rank matrix. The values ​​of the equation coefficients can be associated with the exponent to satisfy the above-mentioned matrix properties. Based on Figure 8b The equation coefficient matrix is ​​shown. The value of a coefficient of a high-exponent equation can be obtained by multiplying or adding the coefficients of other low-exponent equations, or the value of a coefficient of a high-exponent equation can be obtained by factoring the coefficients of other low-exponent equations. Based on this, refer to... Figure 9 , Figure 9 A schematic diagram of a mapping table according to an embodiment of the present disclosure is shown, with i taking consecutive values ​​from 0 to 15 as an example. Figure 9 The value of gfilog[i] can be used as the value of the coefficient of an equation, where the value of i represents the exponential part of the coefficient of that equation. When constructing the coefficient matrix of the equation, it can be based on... Figure 9 The values ​​can be taken from the mapping table. For example, Figure 8d The 1 in the equation corresponds to the gfilog[0] value when i = 0, which is 1. GF(2^1) corresponds to the gfilog[1] value when i = 1, which is 2. The highest exponent has no corresponding value. Figure 9In the mapping table, the value of gfilog[i] of the high exponent i can be calculated from the gfilog[i] of the low exponent i. When i is large, such as i = 2^16-1, there are at least 2^16-1 data, each data occupies 2 bytes of storage. One row of data in the mapping table requires 2^18B = 256KB. For a 32-bit LFSR circuit, the required storage space is about 16GB. If other items need to be mapped, the storage capacity will increase further.

[0133] Figure 9 The mapping table also shows the gflog[i] item, and the data size of the mapping table will double to 32GB. gflog maps binary form to element-exponential form, while gfilog maps element-exponential form to binary form, providing a data source for different error correction encoding and decoding methods.

[0134] Figure 9 The mapping table in the table can be set based on a finite field, for example, to limit the value of gfilog[i] to its range. Figure 9 The elements of the mapping table can be mapped to primitive polynomials, and the range of gfilog[i] can be denoted as GF(2^w), where w = i + 1. Commonly used primitive polynomials P(x) for the GF(2^w) field include:

[0135] When w = 4, x^4 + x + 1;

[0136] When w = 8, x^8 + x^4 + x^3 + x^2 + 1;

[0137] When w = 16, x^16 + x^12 + x^3 + x + 1;

[0138] When w = 32, x^32 + x^22 + x^2 + x + 1;

[0139] When w = 64, x^64 + x^4 + x^3 + x + 1.

[0140] Figure 9 The original polynomial P(x) = x^4 + x + 1 corresponding to the mapping table, when i = 0, 1, 2, 3, the exponent part does not exceed 4, and the value of gfilog[i] = x^i (2^i) is given.

[0141] i=4, gfilog[4]=x^4=x^3*x=x^4mod P(x)=x+1=2+1=3;

[0142] i=5, gfilog[5]=x^5=x^4*x=(x+1)*x=x^2+x=4+2=6;

[0143] i=6, gfilog[6]=x^6=x^5*x=(x^2+x)*x=x^3+x^2=8+4=12;

[0144] i = 7, gfilog[7] = x^7 = (x^3 + x^2) * x = (x^4 + x^3 mod P(x)) = x^3 + x + 1 = 8 + 2 + 1 = 11. Subsequent gfilog[i] values ​​are generated sequentially, which will not be elaborated further.

[0145] It is understandable that as the value of i increases, the original polynomial corresponding to the gfilog[i] value of the next i is the original polynomial corresponding to the gfilog[i] value of the previous i multiplied by x. For example, gfilog[4] = x^4 = x^3 * x and gfilog[5] = x^5 = x^4 * x. In other words, after the algorithm for forming the original polynomial is fixed, for the current i and gfilog[i] value, they can be calculated based on the previous i and gfilog[i] value.

[0146] It should be pointed out that, Figure 9 The values ​​of gfilog[i] and gflog[i] shown in the mapping table do not increase or decrease with the value of i. Taking gfilog[i] as an example, its value can be calculated by taking the modulus of a polynomial to fix its value within a finite field. Its value is not positively or negatively correlated with the value of i. The values ​​of i, gfilog[i], and gflog[i] are all limited to a similar range in the entire mapping table, such as... Figure 9 In this embodiment, the value of i ranges from 0 to 15, the value of gflog[i] ranges from 0 to 14, and the value of gfilog[i] ranges from 1 to 15. This embodiment can compress the mapping table, retaining only a portion of the mapping table data, while the other data can be calculated based on known data, thereby reducing the size of the mapping table and the storage capacity required.

[0147] In some embodiments, refer to Figure 10a , Figure 10a A schematic diagram of a first mapping table is shown, which may only include the gfilog[i] values. The first mapping table records or maps the numerical correspondence between the exponential part (i) and the equation coefficients (gfilog[i]). Figure 10a This includes all gfilog[i] values ​​corresponding to the continuous exponent portion from 0 to (2^16-1). The first mapping table is an uncompressed mapping table. As mentioned earlier, the gfilog value of a high exponent can be calculated from one or more low exponent gfilog values, and the calculation method can include multiplication, addition, or the inverse operation of multiplication and addition. Accordingly, refer to... Figure 10bAs shown, the first mapping table is compressed, and several indices (several i values) in the first mapping table are selected as all i value nodes, and several corresponding gfilog[i] values ​​are selected as all gfilog[i] value node data. A numerical interval can be separated between every two i values ​​to divide all gfilog[i] values ​​in the first mapping table into several data segments. When the gfilog[i] value corresponding to a certain i value is needed, the gfilog[i] value corresponding to the required i value can be calculated based on the node interval where the i value is located and the gfilog[i] values ​​before and after it.

[0148] Specifically, in Figure 10b In the example where i = 256 and gfilog

[256] represents one node's data, and i = 521 and gfilog

[521] represents another node's data, when 256 < i < 521, the gfilog[i] value corresponding to any value between 256 < i < 521 can be calculated using the value of gfilog

[256] . For example, if i = 288, it is determined that i falls between 256 and 521. A lookup in the second mapping table reveals that the gfilog

[256] corresponding to the value 256 is 2863. The offset is 288 - 256 = 32. Based on the method for generating gfilog[i] mentioned earlier, gfilog

[288] = 59187 can be calculated using the offset. Similarly, by segmenting the relevant node data in the second mapping table, all or any number of gfilog[i] values ​​from the first mapping table can be recovered, thereby obtaining all the equation coefficients required to construct the equation coefficient matrix. The compressed second mapping table can retrieve coefficients of any equation or reconstruct the first mapping table, while containing less data than the uncompressed first mapping table, thus reducing the data size and storage footprint of the mapping table. It should be noted that... Figure 10a The first mapping table in can be based on Figure 9 The mapping table is obtained by adding elements. Figure 10a In this case, i=15 is no longer the last element, and gfilog

[15] is valid data.

[0149] by Figure 9 Taking the mapping table as an example, where i ranges from 0 to 15, a finite field GF is defined as all values ​​from 0 to 15, with a total of 16 elements. All values ​​of the corresponding gfilog[i] will also fall within this GF field; that is, any gfilog[i] value will be equal to a value between 0 and 15. This GF field can be selected or set based on the Galois field. In the Galois field, each element can be generated according to an exponential polynomial, and the results of addition, subtraction, multiplication, and division operations all fall within this field. Therefore, the Galois field can satisfy the equation coefficient setting characteristics in this embodiment, and when performing related calculations, the results can be obtained by looking up values ​​in the Galois field, simplifying calculations and saving computational power.

[0150] Reference Figure 9 As shown, according to the calculation rules of Galois fields, the value of gfilog[i] is set. The value of gfilog[i] with a high exponent can be calculated by one or more gfilog[i] values ​​with a low exponent. The value of gfilog[i] falls within the range of all values ​​of i. gfilog[i] can be the inverse table of the mapping table associated with the Galois field, indicating that the element-exponential form is mapped to the binary form; gfilog[i] can be the positive table of the mapping table associated with the Galois field, indicating that the binary form is mapped to the element-exponential form. According to the setting rules of Galois fields, there is an association between the positive table and the inverse table. When gfilog[i=n]=m, gflog[i=m]=n. For example, gfilog[4]=3, gflog[3]=4. The inverse table can be obtained based on the positive table, and the positive table can be obtained based on the inverse table. As previously mentioned, the first mapping table in this embodiment may include gfilog[i]. In other embodiments, the first mapping table may also include gflog[i] for table lookup calculation, which simplifies the algorithm and saves computing power.

[0151] Reference Figure 10b As shown, the first mapping table may also include the gflog[i] value. The mapping table composed of gflog[i] values ​​can also be compressed, or the first mapping table may not include the gflog[i] value. The gflog[i] value can be calculated from the gfilog[i] value in the first mapping table, or calculated based on the compressed second mapping table. As mentioned earlier, when gfilog[i=n]=m, gflog[i=m]=n. The calculation of the gflog[i] value using the uncompressed first mapping table will not be elaborated further. Figure 10c The example calculates the value of gflog[i] using the compressed second mapping table. For instance, to find gflog

[2863] , which is the value of i when giflog[i] = 2863, we look up the table and find that giflog

[256] = 2863 is recorded in the second mapping table, thus obtaining gflog

[2863] = 256. Another example is to find gflog

[288] . Since giflog[i] = 288 is not recorded in the second mapping table, we need to inversely solve for the value of i when gfilog[i] = 288. The algorithm here is to set gfilog[i + i_offset] = N, allowing N to be found in the gfilog[i] table and recording the value from i_offset, finally obtaining gflog

[288] = 33422; gfilog[i = 256 * 131 = 33536] = N = 1282, i_offset = -114.

[0152] The mapping table in this embodiment is presented in decimal for ease of explanation, but in actual memory system storage, retrieval, and calculation processes, it is performed in binary.

[0153] In some embodiments, all elements and their corresponding equation coefficients are finite fields; the memory controller is configured to:

[0154] Generate all elements corresponding to the error correction coding equation;

[0155] Generate the first mapping table based on all the elements;

[0156] Group the exponential part of each element in the first mapping table and the corresponding equation coefficients, and select the exponential part of a fixed element in each group as the node data.

[0157] The second mapping table is obtained using the node data and the equation coefficients corresponding to the node data.

[0158] In this embodiment of the disclosure, all elements corresponding to the error correction coding equation are generated. If the corresponding source data group includes D0, D1, D2 to D(2... ^ i) Data block, then the corresponding selectable elements are all 0 to 2. ^ i, where i is the exponent of the element, and the coefficients of the equation can be gfilog[i].

[0159] For example, Figure 9 The example provided shows that the source data sets to be encoded include D0, D1, D2 to D(2). ^ 4-1), the total number of elements is 16, and each element can be represented as 2. ^ i, where i takes any natural number from 0 to 15, generates 2 in sequence. ^ 0, 2 ^ 1 to 2 ^ All elements of 15, the corresponding first mapping table may include at least gfilog[0], gfilog[1] up to gfilog

[15] , and the value of gfilog

[15] is invalid.

[0160] For example, Figure 10a As shown, the source data groups that need to be encoded include D0, D1, D2 to D(2). ^ 16-1), the total number of elements is 2. ^ 16-1, an element can be represented as 2 ^ Let i be any natural number from 0 to (256*256-1), and generate 2 in sequence. ^ 0, 2 ^ 1 to 2 ^All elements of (256*256-1) can be included in the first mapping table, which may include at least gfilog[0], gfilog[1] up to gfilog[256*256-1]. The value of gfilog[256*256-1] is invalid.

[0161] Will Figure 10a The first mapping table in the algorithm groups the values ​​of the exponent i. Each group includes a range of values ​​for i, and one i value in each group serves as a node data. The gfilog[i] value corresponding to the i value is the coefficient of the equation corresponding to that node data. For example, i values ​​from 0 to 255 are grouped together, 256 to 511 are grouped together, and so on, until all elements from 0 to (256*256-1) are divided. One or more node data from each group and their corresponding gfilog[i] values ​​are recorded in the second mapping table. There can be any number of i value ranges in the grouping, and the number of i values ​​included in each group can be the same or different.

[0162] In some embodiments, the total number of elements contained in each group is substantially the same, the exponent portion of all elements contained in each group is a set of continuous data, and the exponent portion of a fixed element in each group is the first data in the continuous data in each group.

[0163] For example, in Figure 10a In this approach, elements from 0 to (256*256-1) are divided into 256 groups based on 256 values ​​of i. Each group may have the same total number of elements. The first element of each group is recorded as a fixed element in a second mapping table. Some groups may record a small number of additional elements, but the total number remains roughly the same. For example, the first group, in addition to recording the first fixed element, also records the second element, with an exponent of 0, used as a coefficient in the equation. Figure 8d The coefficient matrix of the example equation may be used repeatedly, or the negative value 1 may be used directly without accessing the mapping table. Therefore, i=1 as the second element of the first group will also be recorded, that is, i=0 and i=1 are recorded simultaneously. Other groups can record only the first element of each group, such as recording i=256, 512, 256*254, 256*255. In addition to recording the first fixed element, the last group can also record the last element 256*256-1, and its corresponding gfilog[i] value is invalid.

[0164] In some embodiments, the memory controller further includes: an encoding circuit configured to:

[0165] Based on all the elements, generate the corresponding equation coefficient matrix;

[0166] Using the coefficient matrix of the equation, generate the encoding matrix;

[0167] Using the encoding matrix, the stored data to be written into the memory device is encoded to obtain the verification data corresponding to the stored data.

[0168] In some embodiments, the memory controller further includes a decoding circuit, the decoding circuit being configured to:

[0169] The recovered stored data is obtained by performing a decoding operation using the error correction decoding inverse matrix, the remaining stored data that has not contained errors, and the verification data corresponding to the stored data.

[0170] Reference Figure 7 As shown, the memory controller 106 may include an encoding unit 1065 and a decoding unit 1066.

[0171] The encoding unit 1065 includes an encoding circuit that can encode data, generate an encoding matrix, and encode stored data to generate verification data; the decoding unit 1066 may include a decoding circuit that uses the verification data to decode and recover erroneous stored data.

[0172] by Figure 8d Taking the generated equation coefficient matrix as an example, Figure 8d The equation coefficient matrix can be a complete equation coefficient matrix encoding D0, D1, D2 through D5, or a partial example of an equation coefficient matrix encoding more data. Figure 8d To generate the example equation coefficient matrix, add an identity matrix (with all diagonal data being 1 and the rest being 0) to the matrix. Figure 11a The encoding matrix has the same number of data in each row of the identity matrix as the number of data in each row of the equation coefficient matrix. This ensures that the data obtained after matrix multiplication includes not only the check data P1, P2, and P3, but also the source data D0, D1, D2 to D5, which can be used to recover up to any 3 errors from D0 to D5.

[0173] Reference Figure 11b As shown, taking three data blocks with errors as an example, when errors occur in D0, D2, and D5, the coefficient matrix multiplied by the column vector containing the erroneous data is a 6×6 matrix. For ease of understanding, this 6×6 square matrix is ​​referred to as the R matrix. The R matrix is... Figure 11a The R matrix is ​​a part of the encoding matrix. It retains the three rows of equation coefficients corresponding to P1 to P3, that is, it retains the original equation coefficient matrix part and also retains the three rows of equation coefficients corresponding to the data that has not been erroneous.

[0174] Reference Figure 11c As shown, the inverse matrix R' of matrix R is generated. R' can be denoted as the error correction decoding inverse matrix. The equation still holds when both sides of the equation are multiplied by R'. Figure 11c After transforming the equation, we get Figure 11d The equation shown is used to recover the erroneous data blocks D0, D2, and D5. If recovering data from two data blocks D, any two of P1 to P3 can be selected, similar to... Figure 11c The R' error correction inverse matrix is ​​constructed; if more data needs to be recovered, more P is generated during the encoding stage. The encoding circuit involved in the embodiments of this disclosure can perform... Figure 11a In addition to encoding operations, the decoding circuit can also perform other encoding operations. Figure 11d In addition to the aforementioned decoding operation, other decoding operations can also be performed.

[0175] In some embodiments, the memory controller is further configured to:

[0176] When an error occurs while reading stored data from the memory device, the error correction decoding inverse matrix is ​​obtained by querying the node data in the second mapping table and calculating the corresponding bias.

[0177] Error correction is performed using the inverse error correction decoding matrix.

[0178] Reference Figure 11e As shown, Figures 11a to 11c The equation coefficients shown are GF(2) ^ 2 in i) ^ i corresponds to Figure 9 and Figure 10a The elements in the mapping table, where the exponent i corresponds to the value i in the mapping table, are used to find the gfilog[i] value in the mapping table based on the value i to obtain GF(2). ^ i) Values ​​are used to generate the required equation coefficient matrix and encoding matrix. The data rows corresponding to the encoding matrix are selected to restore the position of the data in the source data group as needed, forming a new R matrix. The R matrix is ​​inverted by bias calculation to obtain the error correction decoding inverse matrix. The source data is solved using the error correction decoding matrix.

[0179] In some embodiments, the memory controller is specifically configured to:

[0180] When an error occurs while reading stored data from the memory device, multiple elements corresponding to the erroneous stored data are retrieved;

[0181] Using the multiple elements corresponding to the erroneous stored data, a first matrix is ​​obtained;

[0182] Obtain the equation coefficients corresponding to the exponential part of each element in the first matrix to obtain the second matrix;

[0183] Calculate the inverse of the second matrix to obtain the error correction decoding inverse matrix.

[0184] Reference Figure 12a The first matrix shown has an exponential part, x and Figure 9 In the mapping table, i represents the same thing, x can be 2, and the second matrix is ​​for querying. Figure 9 The matrix after retrieving values ​​from the mapping table has its inverse matrix as the inverse of the second matrix. Taking errors in reading D0, D2, and D5 as an example, the first matrix is ​​a ternary matrix, and D0 corresponds to... Figure 8d The first column of data shown is 1, 1, 1; D2 corresponds to the third column of data, 1, GF(2). ^ 2), and GF(2) ^ 4); D5 corresponds to 1, GF(2) in the sixth column of data. ^ 5) and GF(2) ^ 10).

[0185] Reference Figure 12b As shown, during the encoding process, the result of matrix operations performed between the first matrix and the errors D0, D2, and D5 is the third matrix.

[0186] go through Figure 11a The matrix operations shown can be represented in exponential form, referring to the first matrix:

[0187] P1 = D0 + D1 + D2 + D3 + D4 + D5

[0188] P2 = D0 + x ^ 1*D1+x ^ 2*D2+x ^ 3*D3+x ^ 4*D4+x ^ 5*D5

[0189] P3 = D0 + x ^ 2*D1+x ^ 4*D2+x ^ 6*D3+x ^ 8*D4+x ^ 10*D5

[0190] Represent the values ​​of P1, P2, and P3 using the error-free values ​​D1, D3, and D4, and substitute them into... Figure 12b In the third matrix, the matrix formed by D0, D2, and D5 is equal to the product of the inverse matrix and the third matrix. For example, D0 + D2 + D5 = P1 - D1 - D3 - D4. As mentioned above, the mapping table values ​​in this embodiment are limited to a closed domain. Addition and subtraction operations are both binary XOR calculations. Since addition and subtraction are the same, this embodiment can unify addition and subtraction into addition operations, which can be written as D0 + D2 + D5 = P1 + D1 + D3 + D4. The inverse matrix can be... Figure 11c Part of the data in the error correction decoding inverse matrix R'. Figure 12c This shows how to find based on the index part. Figure 9 , Figure 10aor Figure 10b The process of solving the mapping table in the matrix to obtain D0, D2, and D5 can be achieved by first solving for the specific numerical values ​​shown in the table. Figure 12c In the table, the specific numerical values ​​are then mapped to elements with exponents, as shown in the table. Figure 12d In the table. In some embodiments, when D1 and D4 read errors occur, a first matrix is ​​constructed. The first matrix is ​​a 2nd order matrix, and D1 corresponds to... Figure 8d The second column of data shown is 1, GF(2) ^ 1); D4 corresponds to 1, GF(2) in the fifth column of data. ^ 4). The first matrix and its inverse are as follows: Figure 13a As shown, the process of solving D1 and D4 using the inverse matrix is ​​similar to that of solving D0, D2, and D5, and will not be described again. In some embodiments, Figure 12c Furthermore, the calculation of each specific value of the matrix in 12b can be performed according to the calculation rules of the closed field of the present disclosure, rather than conventional decimal arithmetic, thereby limiting each calculated value to the closed field and restricting the number of bits and size of the data to be calculated.

[0191] Still with Figure 9 Taking the mapping table in the table as an example, the following are examples of addition, subtraction, multiplication, and division operations on the data obtained from the table lookup:

[0192] Addition 6 + 7 = b0110 xor b0111 = b0001 = 1 (decimal); xor is the binary XOR operation, where the corresponding bits with the same value are both 0, and the opposite bits are 1.

[0193] Subtraction, 9 - 3 = b1001 xor b0011 = b1010 = 10 (decimal).

[0194] Multiplication, 7*9=gfilog[gflog[7]+gflog[9]]=gfilog[10+14]=gfilog[24mod15]=gfilog

[0195] [9] = 10; look up the value of gfilog[9]. Figure 9 The mapping table is obtained.

[0196] Division, 13 / 11 = gfilog[gflog

[13] - gflog

[11] ] = gfilog[13 - 7] = gfilog[6] = 12; look up the value of gfilog[6]. Figure 9 The mapping table is obtained. Addition and subtraction operations yield the same result, as in this embodiment of the disclosure. Figure 12c and Figure 13b The subtraction involved can be replaced by addition.

[0197] In some embodiments, the memory controller is specifically configured to:

[0198] For the exponent portion of each element in the first matrix, determine the group to which the exponent portion of the corresponding element falls and the offset between the exponent portion of the corresponding element and the exponent portion of a fixed element in the corresponding group; and

[0199] By querying the second mapping table, the equation coefficients corresponding to the exponential part of the fixed element falling into the corresponding group are obtained;

[0200] Using the obtained equation coefficients and the offset values, calculate the equation coefficients corresponding to the exponential part of the corresponding element.

[0201] When the second mapping table is a compressed mapping table, for each value in the first matrix, refer to... Figure 10b As shown, the index is determined to fall into which group, and the values ​​of the first matrix are calculated based on the fixed element values ​​recorded in the second mapping table for that group.

[0202] In some embodiments, the encoding circuit and / or the decoding circuit both include a linear feedback shift register circuit for buffering the first mapping table or the second mapping table. Figure 7 The encoding circuit in the encoding unit 1065 and / or the decoding circuit in the decoding unit 1066.

[0203] Here, a linear feedback shift register circuit refers to a shift register that, given the output of a previous state, uses a linear function of that output as its input. XOR operations can be performed using a linear feedback shift register circuit; for example, XORing certain bits of the register and using them as input can then shift all the bits in the register as a whole.

[0204] In some embodiments, the memory controller is further configured to:

[0205] Perform a read operation on the stored data in the memory device:

[0206] When an error occurs in the stored data being read, the erroneous stored data is reread.

[0207] If the stored data still contains errors after being reread, perform software decoding on the stored data that still contains errors.

[0208] When errors still occur in the stored data after software decoding, the errors are corrected using the error correction decoding inverse matrix.

[0209] Reference Figure 6As shown, when the memory controller 106 controls the memory device 104 to perform a read operation, it first performs a default read operation on the memory cell at the corresponding physical address. If the default read operation fails, a reread operation is performed. If the reread operation fails, a software decoding operation is performed. If the software decoding operation fails, a redundant array data recovery operation is performed. If the RAID operation fails, the read operation stops and fails because it cannot correct errors. The memory controller 106 sends a read failure signal to the host 108. The reread operation and the default read operation can be applied to hardware decoding.

[0210] In some embodiments, the second mapping table is stored in the read-only memory (ROM) of the memory device or the memory controller. When the memory device is not powered on, the second mapping table may be stored in the memory cell array of the memory device, and written into the read-only memory (ROM) of the memory device or the memory controller when the memory device is powered on.

[0211] According to some aspects of embodiments of this disclosure, a memory controller 106 is provided, the memory controller 106 being configured to: compress a first mapping table to obtain a second mapping table; the first mapping table includes the correspondence between the exponent part of each element in all elements corresponding to the error correction coding equation and the equation coefficients, the exponent part of all elements being a set of continuous data; the second mapping table includes the correspondence between the exponent part of some elements in all elements and the equation coefficients, the exponent part of the some elements being multiple node data extracted from the continuous data;

[0212] Using the node data in the second mapping table, the equation coefficients corresponding to the exponential part of any element among all the elements are obtained through segmented queries.

[0213] According to some aspects of embodiments of this disclosure, Figure 14 A method for operating a memory system is provided, the method comprising:

[0214] The first mapping table is compressed to obtain the second mapping table. The first mapping table includes the correspondence between the exponent part of each element in the error correction coding equation and the equation coefficients. The exponent part of all elements is a set of continuous data. The second mapping table includes the correspondence between the exponent part of some elements in the entire set and the equation coefficients. The exponent part of some elements is multiple node data extracted from the continuous data.

[0215] Using the node data in the second mapping table, the equation coefficients corresponding to the exponential part of any element among all the elements are obtained through segmented queries.

[0216] In some embodiments, all elements and their corresponding equation coefficients are finite fields; the method further includes:

[0217] Generate all elements corresponding to the error correction coding equation;

[0218] Generate the first mapping table based on all the elements;

[0219] During the compression of the first mapping table, the exponent part of each element and the corresponding equation coefficient in all elements of the first mapping table are grouped, and the exponent of a fixed element in each group is selected as node data.

[0220] The second mapping table is obtained using the node data and the corresponding equation coefficients.

[0221] In some embodiments, the total number of elements contained in each group is substantially the same, the exponent portion of all elements contained in each group is a set of continuous data, and the exponent portion of a fixed element in each group is the first data in the continuous data in each group.

[0222] In some embodiments, the method further includes:

[0223] When an error occurs while reading stored data from the memory device, the error correction decoding inverse matrix is ​​obtained by querying the node data in the second mapping table and calculating the corresponding bias.

[0224] Error correction is performed using the inverse error correction decoding matrix.

[0225] In some embodiments, obtaining the error correction decoding inverse matrix by querying node data in the second mapping table and calculating the corresponding bias includes:

[0226] When an error occurs while reading stored data from the memory device, multiple elements corresponding to the erroneous stored data are retrieved;

[0227] Using the multiple elements corresponding to the erroneous stored data, a first matrix is ​​obtained;

[0228] Obtain the equation coefficients corresponding to the exponential part of each element in the first matrix to obtain the second matrix;

[0229] Calculate the inverse of the second matrix to obtain the error correction decoding inverse matrix.

[0230] In some embodiments, obtaining the equation coefficients corresponding to the exponential portion of each element in the first matrix includes:

[0231] For each element's partial exponent in the first matrix, determine the group to which the exponent portion of the corresponding element falls and the offset between the exponent portion of the corresponding element and the exponent portions of fixed elements within the corresponding group; and

[0232] By querying the second mapping table, the equation coefficients corresponding to the power exponents of the fixed elements falling into the corresponding group are obtained;

[0233] Using the obtained equation coefficients and the offset values, calculate the equation coefficients corresponding to the exponential part of the corresponding element.

[0234] In some embodiments, the method further includes:

[0235] Based on all the elements, generate the corresponding equation coefficient matrix;

[0236] Using the coefficient matrix of the equation, generate the encoding matrix;

[0237] Using the encoding matrix, the stored data to be written into the memory device is encoded to obtain the verification data corresponding to the stored data.

[0238] In some embodiments, the error correction using the error correction decoding inverse matrix includes:

[0239] The recovered stored data is obtained by performing a decoding operation using the error correction decoding inverse matrix, the remaining stored data that has not contained errors, and the verification data corresponding to the stored data.

[0240] In some embodiments, the method further includes:

[0241] Perform a read operation on the stored data in the memory device:

[0242] When an error occurs in the stored data being read, the erroneous stored data is reread.

[0243] If the stored data still contains errors after being reread, perform software decoding on the stored data that still contains errors.

[0244] When errors still occur in the stored data after software decoding, the errors are corrected using the error correction decoding inverse matrix.

[0245] According to some aspects of embodiments of the present disclosure, a readable storage medium is provided that stores a computer program, which, when executed, implements the operation method.

[0246] The memory device may include NAND memory, and the memory cells of the NAND memory may include floating-gate type memory cells with floating-gate transistors or charge-trapping type memory cells with charge-trapping transistors.

[0247] The storage medium can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; or it can be any device that includes one or any combination of the above-mentioned memory devices.

[0248] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0249] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborative files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0250] As an example, executable instructions can be deployed to execute on a single electronic device, or on multiple electronic devices located in one location, or on multiple electronic devices distributed across multiple locations and interconnected via a communication network.

[0251] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A memory system, characterized by, The application relates to a memory device and a memory controller. The memory device comprises: a memory controller coupled to the memory device and configured to: compress a first mapping table to obtain a second mapping table; the first mapping table comprises a correspondence between an index part of each element of all elements corresponding to error correction coding equations and an equation coefficient, and the index part of all elements is a group of continuous data; wherein the all elements corresponding to the error correction coding equations form a Vandermonde matrix, and an element of an error correction coding equation corresponds to a row of the Vandermonde matrix; and the equation coefficient is set according to a calculation rule of a Galois field; the second mapping table comprises a correspondence between an index part of part of the all elements and the equation coefficient, and the index part of the part of the all elements is a plurality of node data extracted from the continuous data; by using the node data in the second mapping table, the equation coefficient corresponding to the index part of any element of the all elements is obtained through segmented query.

2. The memory system of claim 1, wherein, The all elements and the corresponding equation coefficients are finite fields; and the memory controller is configured to: generate all elements corresponding to error correction coding equations; generate the first mapping table according to the all elements; group the index part of each element of the all elements in the first mapping table and the corresponding equation coefficient, and select the index part of a fixed element in each group as the node data; obtain the second mapping table by using the node data and the equation coefficient corresponding to the node data.

3. The memory system of claim 2, wherein, The total number of elements contained in each group is substantially the same, the index part of all elements contained in each group is a group of continuous data, and the index part of a fixed element in each group is the first data in the continuous data in each group.

4. The memory system of claim 2, wherein, The memory controller is further configured to: when reading stored data in the memory device is erroneous, obtain an error correction decoding inverse matrix by querying the node data in the second mapping table and corresponding offset calculation; perform error correction by using the error correction decoding inverse matrix.

5. The memory system of claim 4, wherein, The memory controller is specifically configured to: when reading stored data in the memory device is erroneous, obtain a plurality of elements corresponding to the erroneous stored data; obtain a first matrix by using the plurality of elements corresponding to the erroneous stored data; obtain a second matrix by obtaining the equation coefficient corresponding to the index part of each element in the first matrix; obtain the error correction decoding inverse matrix by calculating an inverse matrix of the second matrix.

6. The memory system of claim 5, wherein, The memory controller is specifically configured to: for the index part of each element in the first matrix, determine a group into which the index part of the corresponding element falls and an offset value between the index part of the corresponding element and the index part of a fixed element in the corresponding group; and obtain the equation coefficient corresponding to the index part of the fixed element in the corresponding group by querying the second mapping table; obtain the equation coefficient corresponding to the index part of the corresponding element by using the obtained equation coefficient and the offset value.

7. The memory system of claim 4, wherein, The memory controller further comprises an encoding circuit configured to: generate a corresponding equation coefficient matrix according to the all elements; generate an encoding matrix by using the equation coefficient matrix; and generate the first mapping table by using the encoding matrix. The storage data to be written into the memory device is subjected to an encoding operation by using the encoding matrix, to obtain the check data corresponding to the storage data.

8. The memory system of claim 7, wherein, The memory controller further comprises a decoding circuit configured to: The decoding operation is performed by using the error correction decoding inverse matrix, the storage data without error and the check data corresponding to the storage data, to obtain the recovered storage data.

9. The memory system of claim 8, wherein, The encoding circuit and / or the decoding circuit each comprises a linear feedback shift register circuit (LFSR).

10. The memory system of claim 4, wherein, The memory controller is further configured to: perform a read operation on the storage data in the memory device: perform a read operation on the storage data in the memory device: when the read storage data has error, perform a re-reading process on the storage data with error; when the storage data after the re-reading process still has error, perform a soft decoding process on the storage data still with error; 11. The memory system of claim 1, wherein, when the storage data after the soft decoding process still has error, perform error correction by using the error correction decoding inverse matrix.

12. An operating method of a memory system, characterized by, The second mapping table is stored in the memory device or a read-only memory (ROM) of the memory controller. comprises: compressing the first mapping table to obtain a second mapping table; the first mapping table comprises a corresponding relationship between an index part of each element in all elements corresponding to an error correction encoding equation and an equation coefficient, and the index part of all elements is a group of continuous data; wherein all elements corresponding to the error correction encoding equation form a Vandermonde matrix, and an element of an error correction encoding equation corresponds to a row of the Vandermonde matrix; the equation coefficient is set according to the calculation rule of a Galois field; the second mapping table comprises a corresponding relationship between an index part of part of elements in all elements and an equation coefficient, and the index part of the part of elements is a plurality of node data extracted from the continuous data; 13. The method of operation of claim 12, wherein, by using the node data in the second mapping table, the equation coefficient corresponding to the index part of any element in all elements is obtained through segmented query. The all elements and the corresponding equation coefficients are finite fields; the method further comprises: generating all elements corresponding to an error correction encoding equation; generating the first mapping table according to the all elements; in the process of compressing the first mapping table, the index part of each element in all elements in the first mapping table and the corresponding equation coefficient are grouped, and the index of a fixed element in each group is selected as node data; 14. The method of claim 13, wherein, by using the node data and the corresponding equation coefficient, the second mapping table is obtained.

15. The method of claim 13, wherein, The total number of elements contained in each group is substantially the same, and the index part of all elements contained in each group is a group of continuous data, and the index part of a fixed element in each group is the first data in the continuous data in each group. The method further comprises: when the read storage data in the memory device has error, an error correction decoding inverse matrix is obtained by querying the node data in the second mapping table and corresponding bias calculation; 16. The method of operation of claim 15, wherein, error correction is performed by using the error correction decoding inverse matrix. The error correction decoding inverse matrix is obtained by querying the node data in the second mapping table and corresponding bias calculation, comprising: When an error occurs in reading stored data in the memory device, a plurality of elements corresponding to the error of the stored data are obtained; A first matrix is obtained by using the plurality of elements corresponding to the error of the stored data; An equation coefficient corresponding to an index part of each element in the first matrix is obtained to obtain a second matrix; An inverse matrix of the second matrix is calculated to obtain the error correction decoding inverse matrix.

17. The method of operation of claim 16, wherein, The equation coefficient corresponding to the index part of each element in the first matrix is obtained, including: For the index part of each element in the first matrix, a group into which the index part of the corresponding element falls and an offset value of the index part of the corresponding element and the index part of a fixed element in the corresponding group are determined; and The equation coefficient corresponding to the index of the fixed element in the corresponding group is obtained by querying the second mapping table; The equation coefficient corresponding to the index part of the corresponding element is calculated by using the obtained equation coefficient and the offset value.

18. The operating method according to claim 15, characterized in that, The method further includes: A corresponding equation coefficient matrix is generated according to the all elements; An encoding matrix is generated by using the equation coefficient matrix; An encoding operation is performed on the stored data to be written into the memory device by using the encoding matrix to obtain the check data corresponding to the stored data.

19. The method of claim 15, wherein, The error correction is performed by using the error correction decoding inverse matrix, including: A decoding operation is performed on the remaining stored data without error and the check data corresponding to the stored data by using the error correction decoding inverse matrix to obtain the recovered stored data.

20. The operating method according to claim 15, characterized in that, The method further includes: A read operation is performed on the stored data in the memory device: When the read stored data has an error, the error of the stored data is re-read; When the stored data after the re-reading still has an error, a soft decoding operation is performed on the stored data still having an error; When the stored data after the soft decoding operation still has an error, the error is corrected by using the error correction decoding inverse matrix.

21. A memory controller, comprising: The memory controller is configured to: A first mapping table is compressed to obtain a second mapping table; the first mapping table includes a corresponding relationship between an index part of each element in all elements corresponding to an error correction encoding equation and an equation coefficient, and the index part of the all elements is a group of continuous data; wherein the all elements corresponding to the error correction encoding equation form a Vandermonde matrix, and an element of one error correction encoding equation corresponds to a row of the Vandermonde matrix; the equation coefficient is set according to a calculation rule of a Galois field; The second mapping table includes a corresponding relationship between an index part of a part of the elements and the equation coefficient, and the index part of the part of the elements is a plurality of node data extracted from the continuous data; By using the node data in the second mapping table, the equation coefficient corresponding to the index part of any element in the all elements is obtained by segment query.

22. A readable storage medium, characterized by, The readable storage medium stores a computer program, and the computer program is executed to implement the operation method of any one of claims 12-20.

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