Testing device for etching yield control and preparation method and testing method thereof

Abstract

The invention provides a testing device for etching yield control. The testing device comprises a substrate; the intermediate layer is arranged on the upper surface of the substrate; the bottom conducting layer is arranged on the upper surface of the intermediate layer; the magnetic tunnel junction array comprises a plurality of magnetic tunnel junctions arranged in an array, and the magnetic tunnel junctions are arranged on the upper surface of the bottom conducting layer; and the top metal is arranged on the top of each magnetic tunnel junction. According to the test device for etching yield control, the preparation method thereof and the test method provided by the invention, the conditions of short circuit and bit damage caused by etching can be quickly obtained.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a test device for etching yield control and a preparation method and a test method thereof. Background Art

[0002] The bit of MRAM is composed of a free layer, a barrier layer, a reference layer, etc. The total number of bit material layers can be as high as 25 to 35 layers or more. Except for the barrier layer, all other layers are metal films. The barrier layer is a layer of high-resistance material with a thickness of several atoms. One of the key issues to ensure the yield in the MRAM production process is how to avoid the short circuit caused by the etched metal atoms splashing onto the barrier layer during etching and reduce the damage caused by etching, especially the statistical etching short circuit and etching damage.

[0003] Statistical etching short circuits and etching damage require testing a large number of bits. The current practice is to complete the entire process flow, and then measure the resistance of each bit to determine whether the bit is short-circuited / partially short-circuited, and whether there is damage. In the existing technology, completing the entire process takes a long time and is costly. Summary of the invention

[0004] The etching yield control test device and its preparation method and test method provided by the present invention can quickly obtain the short circuit and bit damage caused by etching.

[0005] In a first aspect, the present invention provides a test device for etching yield control, comprising:

[0006] substrate;

[0007] An interposer layer is disposed on the upper surface of the substrate;

[0008] A bottom conductive layer, disposed on the upper surface of the interposer layer;

[0009] A magnetic tunnel junction array, comprising a plurality of magnetic tunnel junctions arranged in an array, wherein the magnetic tunnel junctions are arranged on an upper surface of the bottom conductive layer;

[0010] A top metal is disposed on the top of each magnetic tunnel junction.

[0011] Optionally, the bottom conductive layer includes an array region and an electrode region; and the magnetic tunnel junction array is arranged on an upper surface of the array region.

[0012] Optionally, the electrode region is provided with a conductive electrode.

[0013] Optionally, an insulating medium is provided in the intervals between adjacent magnetic tunnel junctions in the magnetic tunnel junction array, and the insulating medium is provided with an opening at least at a position corresponding to the top metal to expose the top metal.

[0014] Optionally, a height difference between an upper surface of the insulating medium and an upper surface of the top metal is within ±30 nm.

[0015] Optionally, the device further comprises:

[0016] The conductive electrode covers a portion of the insulating medium and a portion of the top metal, and the conductive electrode forms a conductive contact with the covered top metal.

[0017] In a second aspect, the present invention provides a method for preparing a test device for etching yield control, the method comprising:

[0018] Providing a stacked structure, the stacked structure comprising a substrate, an intermediate layer, a bottom conductive layer, a magnetic tunnel junction layer and a top metal layer arranged from bottom to top;

[0019] The top metal layer and the magnetic tunnel junction layer in the stacked structure are etched to form a magnetic tunnel junction array and a top metal corresponding to each magnetic tunnel junction in the magnetic tunnel junction array.

[0020] Optionally, etching the top metal layer and the magnetic tunnel junction layer in the stacked structure includes:

[0021] Etching the top metal layer and the magnetic tunnel junction layer corresponding to the array region of the bottom conductive layer according to a predetermined pattern to form a magnetic tunnel junction array and a top metal corresponding to each magnetic tunnel junction in the magnetic tunnel junction array;

[0022] The top metal layer and the magnetic tunnel junction layer corresponding to the electrode region of the bottom conductive layer are etched to expose the electrode region of the bottom conductive layer.

[0023] Optionally, the method further comprises:

[0024] A conductive material is used to form a conductive electrode in the electrode region.

[0025] Optionally, it also includes:

[0026] An insulating medium is formed on the magnetic tunnel junction array, and an opening is formed at a position of the insulating medium corresponding to the top metal layer to expose the top metal layer.

[0027] Optionally, a height difference between an upper surface of the insulating medium and an upper surface of the top metal is within ±30 nm.

[0028] In a third aspect, the present invention provides a test method for etching yield control, the method comprising:

[0029] Arrange any one of the above-mentioned etching yield control test devices on a conductive base, and electrically connect the bottom conductive layer to the conductive base;

[0030] A probe is used to test each magnetic tunnel junction in the magnetic tunnel junction array.

[0031] In the technical solution provided by the present invention, the test device has a simple structure and a simple manufacturing process, and can quickly test the short circuit and bit damage caused during the etching process. The technical solution provided by the present invention can effectively speed up the test feedback process, which is conducive to shortening the research and development cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of the structure of a testing device for etching yield control according to an embodiment of the present invention;

[0033] Figure 2 A schematic diagram of the distribution of conductive electrodes of a test device for etching yield control according to an embodiment of the present invention;

[0034] Figure 3 A schematic diagram of the distribution of conductive electrodes of a test device for etching yield control according to an embodiment of the present invention;

[0035] Figure 4 A schematic diagram of the distribution of conductive electrodes of a test device for etching yield control according to an embodiment of the present invention;

[0036] Figure 5 A schematic diagram of an insulating medium filled between magnetic tunnel junctions of an etching yield control test device according to an embodiment of the present invention;

[0037] Figure 6 A schematic diagram of a conductive electrode covering a portion of the top metal of an etching yield control test device according to an embodiment of the present invention;

[0038] Figure 7 A schematic diagram of a stacked structure of a method for preparing a test device for etching yield control according to an embodiment of the present invention;

[0039] Figure 8 A schematic diagram of a stacked structure after etching according to a method for preparing a test device for etching yield control according to an embodiment of the present invention;

[0040] Fig. 9 This is a system schematic diagram of a testing method for etching yield control according to an embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] The embodiment of the present invention provides a test device for etching yield control, such as Figure 1 As shown, including:

[0043] In some embodiments, the substrate may be, for example, SiO deposited on a Si wafer. 2 a formed substrate;

[0044] An intermediary layer is arranged on the upper surface of the substrate; in some embodiments, the intermediary layer can serve as a base layer for growth or has an adhesion effect, the thickness of the intermediary layer can be 0, and the material of the intermediary layer includes but is not limited to Ta, Au, Al, Ag, W, and Pt;

[0045] A bottom conductive layer is disposed on the upper surface of the interposer; in some embodiments, the material of the bottom conductive layer includes but is not limited to W, Ta, Pt, Pd, Au, Cu, Ru, Hf, Mo, Ti, Ir, Mn, Bi x Se (1-x) , Sb x Te (1-x) and Bi x Te (1-x) and their alloys or multilayer films;

[0046] A magnetic tunnel junction array comprises a plurality of magnetic tunnel junctions arranged in an array, wherein the magnetic tunnel junction is arranged on the upper surface of the bottom conductive layer; in some embodiments, the magnetic tunnel junction comprises a free layer, a reference layer, and a barrier layer, wherein the materials of the free layer and the reference layer include but are not limited to Co, Fe, Ni, B, Pt, Pd, Mo, W, Ir, Ta, Ru, Nb, Hf and the like to form an alloy or a multilayer film, and the materials of the barrier layer include but are not limited to MgO, MgAl 2 O 4 、Al 2 O 3 , Gd 2 O 3 , HfO 2 ;

[0047] A top metal is disposed on the top of each magnetic tunnel junction; in some embodiments, the top metal layer is a metal material or a metal doped with a non-metallic element, including but not limited to Ta, TaN, TiN, Ti, WN, W, TiS 2 , WS 2 、MoS 2 、TiSe 2 ,WSe 2 、MoSe 2 , B 2 S 3 , Sb 2 S 3 、 2 S.Re 2 S 7 .

[0048] In the technical solution provided by the embodiment of the present invention, the test device has a simple structure and a simple manufacturing process, and can quickly test the short circuit and bit damage caused by the etching process. The technical solution provided by the embodiment of the present invention can effectively speed up the test feedback process, which is conducive to shortening the research and development cycle.

[0049] As an optional implementation, the bottom conductive layer includes an array region and an electrode region; and the magnetic tunnel junction array is arranged on an upper surface of the array region.

[0050] As an optional implementation, the electrode region is provided with a conductive electrode.

[0051] In some embodiments, the conductive electrode can be of any shape and can be multiple in number. The conductive electrode can be located on one side of the MTJ array, such as Figure 2 As shown, the conducting electrodes can be located on both sides of the MTJ array, such as Figure 3 As shown. The conductive electrode may partially surround or fully surround the MTJ array. The conductive electrode may also cover part of the MTJ array, such as Figure 4 As shown. The conductive electrode can be a conductive glue, solder or other materials. In some preferred embodiments, for the SOT-MRAM structure, two electrodes can be set on both sides of the MTJ array, and the connected conductive electrodes are selected according to the reversal of the free layer magnetic moment. In certain cases, an external magnetic field is also required to assist the reversal. Because under the same current, the free layer magnetic moment may be reversed when the electrode on one side is connected, and the free layer magnetic moment may not be reversed when the electrode on the other side is connected.

[0052] As an optional implementation, Figure 5 As shown, an insulating medium is disposed in the intervals between adjacent magnetic tunnel junctions in the magnetic tunnel junction array, and the insulating medium is provided with an opening at least at a position corresponding to the top metal to expose the top metal.

[0053] As an optional implementation, the height difference between the upper surface of the insulating medium and the upper surface of the top metal is within ±30 nm. As a preferred implementation, the upper surface of the insulating medium is aligned with the upper surface of the top metal.

[0054] In some embodiments, this structure can prevent the probe from damaging the magnetic tunnel junction during the test process, such as the probe scraping the magnetic tunnel junction.

[0055] As an optional implementation, Figure 6 As shown, the device also includes:

[0056] The conductive electrode covers a portion of the insulating medium and a portion of the top metal, and the conductive electrode forms a conductive contact with the covered top metal.

[0057] In some embodiments, when the conductive electrode forms a conductive contact with the top metal, the covered top metal and the corresponding magnetic tunnel junction will be used as a wire to form a conductive path of the conductive electrode, the covered top metal, the covered magnetic tunnel junction, the bottom conductive layer, the tested magnetic tunnel junction, and the tested top metal. Therefore, in this case, the conductive electrode does not need to be in direct contact with the bottom conductive layer.

[0058] An embodiment of the present invention further provides a method for preparing a test device for etching yield control, the method comprising:

[0059] A stacked structure is provided, wherein the stacked structure includes a substrate, an intermediate layer, a bottom conductive layer, a magnetic tunnel junction layer and a top metal layer arranged from bottom to top; the stacked structure is as follows Figure 7 As shown;

[0060] The top metal layer and the magnetic tunnel junction layer in the stacked structure are etched to form a magnetic tunnel junction array and a top metal corresponding to each magnetic tunnel junction in the magnetic tunnel junction array; the structure after etching is as follows Figure 8 shown.

[0061] As an optional implementation manner, etching the top metal layer and the magnetic tunnel junction layer in the stacked structure includes:

[0062] Etching the top metal layer and the magnetic tunnel junction layer corresponding to the array region of the bottom conductive layer according to a predetermined pattern to form a magnetic tunnel junction array and a top metal corresponding to each magnetic tunnel junction in the magnetic tunnel junction array;

[0063] The top metal layer and the magnetic tunnel junction layer corresponding to the electrode region of the bottom conductive layer are etched to expose the electrode region of the bottom conductive layer.

[0064] As an optional implementation, the method further includes:

[0065] A conductive material is used to form a conductive electrode in the electrode region.

[0066] As an optional implementation, it also includes:

[0067] An insulating medium is formed on the magnetic tunnel junction array, and an opening is formed at a position of the insulating medium corresponding to the top metal layer to expose the top metal layer.

[0068] As an optional implementation, the height difference between the upper surface of the insulating medium and the upper surface of the top metal is within ±30 nm. As an optional implementation, the upper surface of the insulating medium is aligned with the upper surface of the top metal.

[0069] The embodiment of the present invention also provides a test method for etching yield control. The system principle during the test is as follows: Fig. 9 As shown, the method includes:

[0070] Arrange any one of the above-mentioned etching yield control test devices on a conductive base, and electrically connect the bottom conductive layer to the conductive base;

[0071] A probe is used to test each magnetic tunnel junction in the magnetic tunnel junction array.

[0072] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A test device for etching yield control, characterized in that: include: substrate; An interposer layer is disposed on the upper surface of the substrate; A bottom conductive layer, disposed on the upper surface of the interposer layer; A magnetic tunnel junction array, comprising a plurality of magnetic tunnel junctions arranged in an array, wherein the magnetic tunnel junctions are arranged on an upper surface of the bottom conductive layer; A top metal is disposed on the top of each magnetic tunnel junction.

2. The etching yield control test device according to claim 1, characterized in that: The bottom conductive layer includes an array region and an electrode region; the magnetic tunnel junction array is arranged on the upper surface of the array region.

3. The etching yield control test device according to claim 2, characterized in that: The electrode region is provided with a conductive electrode.

4. The etching yield control test device according to claim 1, characterized in that: An insulating medium is disposed in the intervals between adjacent magnetic tunnel junctions in the magnetic tunnel junction array, and the insulating medium is provided with an opening at least at a position corresponding to the top metal to expose the top metal.

5. The etching yield control test device according to claim 4, characterized in that: The device also includes: The conductive electrode covers a portion of the insulating medium and a portion of the top metal, and the conductive electrode forms a conductive contact with the covered top metal.

6. A method for preparing a test device for etching yield control, characterized in that: The method comprises: Providing a stacked structure, the stacked structure comprising a substrate, an intermediate layer, a bottom conductive layer, a magnetic tunnel junction layer and a top metal layer arranged from bottom to top; The top metal layer and the magnetic tunnel junction layer in the stacked structure are etched to form a magnetic tunnel junction array and a top metal corresponding to each magnetic tunnel junction in the magnetic tunnel junction array.

7. The method according to claim 6, characterized in that Etching the top metal layer and the magnetic tunnel junction layer in the stacked structure includes: Etching the top metal layer and the magnetic tunnel junction layer corresponding to the array region of the bottom conductive layer according to a predetermined pattern to form a magnetic tunnel junction array and a top metal corresponding to each magnetic tunnel junction in the magnetic tunnel junction array; The top metal layer and the magnetic tunnel junction layer corresponding to the electrode region of the bottom conductive layer are etched to expose the electrode region of the bottom conductive layer.

8. The method according to claim 7, characterized in that The method further comprises: A conductive material is used to form a conductive electrode in the electrode region.

9. The method according to claim 6, characterized in that Also includes: An insulating medium is formed on the magnetic tunnel junction array, and an opening is formed at a position of the insulating medium corresponding to the top metal layer to expose the top metal layer.

10. A test method for etching yield control, characterized in that: The method comprises: The etching yield control test device according to any one of claims 1 to 5 is arranged on a conductive base, and the bottom conductive layer is electrically connected to the conductive base; A probe is used to test each magnetic tunnel junction in the magnetic tunnel junction array.

Images