A test chip and circuit modification method thereof

Abstract

The present invention discloses a test chip and a circuit modification method thereof, and relates to the field of semiconductor technology. The circuit modification method includes: providing a chip to be tested, the chip to be tested including a substrate, a multi-layer conductive layer located on one side of the substrate, and a top dielectric layer located on the side of each conductive layer facing away from the substrate; the conductive layer to be tested in each conductive layer includes a circuit to be tested; forming circuit lead-out holes penetrating each film layer on the side of the layer to be tested facing away from the substrate to expose the circuit to be tested, and in the first circuit lead-out hole of the circuit lead-out hole, the size of the first circuit lead-out hole close to the circuit to be tested is smaller than the size of the first circuit lead-out hole away from the circuit to be tested; depositing conductive material around and in the circuit lead-out hole to form a test pad and a lead-out line connecting the test pad and the circuit to be tested. The technical solution of the present invention improves the accuracy of circuit modification by forming a first circuit lead-out hole that is wide at the top and narrow at the bottom, so that the conductive material can be deposited on the side wall of the first circuit lead-out hole.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to a test chip and a circuit modification method thereof. Background Art

[0002] Semiconductor chip design often contains defects that are difficult to detect during the design phase. These defects are usually only revealed after the chip is manufactured and tested. After discovering a defect, designers typically use circuit repair methods to improve it. Among these, the main circuit modification method is to bring the underlying metal wiring to the chip surface to create micro-probe test contacts.

[0003] The circuit modification method in the prior art usually adopts the Focused Ion Beam (FIB) technology to dig a groove from just above the designated lower wiring position to expose the specific metal wiring, and then connect the lower wiring to the chip surface by depositing platinum (Pt), and finally make a micro-probe test contact. However, this method has difficulties when processing chips with a lower level of designated metal wiring or a thicker upper dielectric layer (such as isolation chips). Due to the presence of a thicker dielectric layer just above the designated metal wiring, the groove formed by FIB digging has a larger aspect ratio. During the platinum deposition process, the sidewall deposition rate will affect the deposition result. The platinum deposited on the sidewall of the groove with a larger aspect ratio will close quickly, hindering the platinum from continuing to deposit downward, and eventually leading to the formation of a void at the lower end of the deep groove, which cannot effectively lead out the designated metal wiring of the lower layer. Summary of the Invention

[0004] The present invention provides a circuit modification method and a test chip, which can form an effective lead-out line to lead out the circuit to be tested, thereby improving the accuracy and effectiveness of chip testing.

[0005] A first aspect of the present invention provides a line modification method, the line modification method comprising:

[0006] A chip to be tested is provided; the chip to be tested comprises a substrate, a multilayer film layer located on one side of the substrate; the multilayer film layer comprises a plurality of conductive layers with insulating intervals, and a top dielectric layer located on a side of each conductive layer facing away from the substrate; each conductive layer comprises at least one conductive layer to be tested, and the conductive layer to be tested comprises a circuit to be tested;

[0007] forming circuit lead-out holes penetrating each of the film layers on a side of the conductive layer to be tested facing away from the substrate to expose the circuit to be tested; at least some of the circuit lead-out holes are first circuit lead-out holes; and within the same first circuit lead-out holes, the size of the first circuit lead-out holes closer to the circuit to be tested is smaller than the size of the first circuit lead-out holes farther away from the circuit to be tested;

[0008] Conductive material is deposited in at least a portion of the area around the circuit lead-out hole and in the circuit lead-out hole to form a test pad and a lead connecting the test pad and the circuit to be tested.

[0009] Optionally, before forming a circuit lead-out hole penetrating each film layer on a side of the conductive layer to be tested facing away from the substrate to expose the circuit to be tested, the method further includes:

[0010] Obtaining design parameters of the chip to be tested;

[0011] Determining the size of a circuit-free region in each of the film layers on a side of the circuit to be tested facing away from the substrate based on design parameters of the chip to be tested; wherein no conductive structure is provided in the circuit-free region, and the circuit-free region overlaps the circuit to be tested in a direction perpendicular to the plane of the substrate;

[0012] The maximum size of the circuit lead-out hole formed in each film layer is determined according to the size of the circuit-free area in each film layer; wherein the circuit lead-out hole passing through each film layer is located in the circuit-free area of each film layer.

[0013] Optionally, before forming a circuit lead-out hole penetrating each film layer on a side of the conductive layer to be tested facing away from the substrate to expose the circuit to be tested, the method further includes:

[0014] Determine the depth d and width w of the circuit under test based on the design parameters of the chip under test; the depth d of the circuit under test is the distance between the circuit under test and the surface of the top dielectric layer facing away from the substrate, and the width w of the circuit under test is the dimension of the circuit under test in a direction perpendicular to the extension of the circuit under test;

[0015] The number of punching times m when forming the circuit lead-out hole is determined according to the depth d of the circuit to be tested, the width w of the circuit to be tested, and the size of the circuit-free area in each film layer.

[0016] Optionally, determining the number of punching times m when forming the circuit lead-out hole according to the depth d of the circuit to be tested, the width w of the circuit to be tested, and the size of the circuit-free area in each film layer includes:

[0017] Determining the aspect ratio n of the circuit to be tested according to the depth d of the circuit to be tested and the width w of the circuit to be tested;

[0018] The number of punching times m when forming the circuit lead-out holes is determined according to the aspect ratio n of the circuit to be tested and the size of the circuit-free area in each of the film layers; m is a positive integer.

[0019] Optionally, determining the number of punching times m when forming the circuit lead-out hole according to the aspect ratio n of the circuit to be tested and the size of the circuit-free area in each of the film layers includes:

[0020] Determining whether the aspect ratio n of the circuit to be tested and the size of the circuit-free area in the top dielectric layer meet a first preset condition; the first preset condition is that the aspect ratio n of the circuit to be tested is greater than or equal to a preset value k, and the size of the circuit-free area in the top dielectric layer is greater than or equal to k*w;

[0021] If so, determining the circuit to be tested as the first circuit to be tested, and determining the circuit lead-out hole exposing the first circuit to be tested as the first circuit lead-out hole;

[0022] The number m of punching times when forming the first circuit lead-out hole exposing the first circuit to be tested is determined to be a positive integer greater than or equal to n.

[0023] Optionally, the method further includes determining the number of punching times m when forming the circuit lead-out holes according to the aspect ratio n of the circuit to be tested and the size of the circuit-free area in each of the film layers:

[0024] If the aspect ratio n of the circuit to be tested is less than the preset ratio k, the circuit to be tested is determined as a second circuit to be tested, and the circuit lead-out hole exposing the second circuit to be tested is determined as a second circuit lead-out hole;

[0025] The number m of punching times when forming the second line lead-out hole exposing the second line to be tested is determined to be 1.

[0026] Optionally, forming a circuit lead-out hole penetrating each film layer on a side of the conductive layer to be tested facing away from the substrate to expose the circuit to be tested includes:

[0027] A focused ion beam is used to perform m etching on each film layer on a side of the conductive layer to be tested away from the substrate to form the circuit lead-out hole exposing the circuit to be tested; wherein each etching penetrates at least one film layer.

[0028] Optionally, the size of the circuit lead-out hole in the film layer penetrated during the (i-1)th etching is larger than the size of the circuit lead-out hole in the film layer penetrated during the i-th etching, where i is a positive integer greater than 1 and less than or equal to m.

[0029] Optionally, the size of the circuit lead-out hole in the film layer penetrated during the first etching is K*w, where K is a positive integer greater than or equal to a preset value k;

[0030] The size of the circuit lead-out hole in the film layer penetrated during the i-th etching is [K-(i-1)*(K-1) / (m-1)]*w.

[0031] A second aspect of the present invention provides a test chip, which uses the above-mentioned circuit modification method to perform circuit modification, and the test chip includes:

[0032] substrate;

[0033] A multilayer film layer located on one side of the substrate; the multilayer film layer includes a plurality of conductive layers with insulating intervals, and a top dielectric layer located on a side of each conductive layer facing away from the substrate; each conductive layer includes at least one conductive layer to be tested, and the conductive layer to be tested includes a circuit to be tested;

[0034] A circuit lead-out hole is provided in each of the film layers on the side of the conductive layer to be tested facing away from the substrate; at least some of the circuit lead-out holes are first circuit lead-out holes; and among the same first circuit lead-out holes, the size of the first circuit lead-out hole close to the circuit to be tested is smaller than the size of the first circuit lead-out hole far from the circuit to be tested;

[0035] A test pad and a lead wire; the test pad is located in at least a portion of the area around the circuit lead hole, the lead wire is located in the circuit lead hole, and the lead wire connects the test pad and the circuit to be tested.

[0036] The technical solution of the present invention is to form a circuit lead-out hole in the chip to be tested, penetrating each film layer of the conductive layer to be tested of the chip to be tested on a side facing away from the substrate, so as to expose the circuit to be tested. In addition, the size of the first circuit lead-out hole close to the circuit to be tested is smaller than the size of the first circuit lead-out hole away from the circuit to be tested, that is, the first circuit lead-out hole has a structure that is wide at the top and narrow at the bottom. When depositing conductive material in at least a portion of the area around the circuit lead-out hole and in the circuit lead-out hole, the conductive material can be deposited along the sidewall of the first circuit lead-out hole with the wide at the top and narrow at the bottom until it contacts the circuit to be tested, thereby preventing the conductive material from closing on the upper side of the first circuit lead-out hole and being unable to electrically connect to the cable to be tested. As a result, test pads and lead wires connecting the test pads and the circuit to be tested are formed around the circuit lead-out hole. The circuit to be tested can then be accurately led to the surface layer of the chip to be tested via the lead wires, thereby ensuring accuracy and effectiveness in testing the circuit to be tested of the chip to be tested.

[0037] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 This is a flow chart of a line modification method provided by an embodiment of the present invention;

[0040] Figure 2 This is a process flow chart of a circuit modification method provided by an embodiment of the present invention;

[0041] Figure 3 1 is a flow chart of a method for determining the maximum size of a circuit lead-out hole provided by an embodiment of the present invention;

[0042] Figure 4 This is a flow chart of a method for determining the number of times a line lead hole is punched, provided by an embodiment of the present invention;

[0043] Figure 5 1 is a schematic structural diagram of a chip to be tested provided by an embodiment of the present invention;

[0044] Figure 6 is a schematic structural diagram of another chip to be tested provided by an embodiment of the present invention;

[0045] Figure 7 is a schematic structural diagram of another chip to be tested provided by an embodiment of the present invention;

[0046] Figure 8 1 is a schematic diagram of a top view of a chip to be tested provided by an embodiment of the present invention;

[0047] Figure 9 It is a structural diagram of another test chip provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0049] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0050] Figure 1 This is a flow chart of a circuit modification method provided by an embodiment of the present invention. This embodiment is applicable to the case where a circuit to be tested of a chip is tested by using the circuit modification method. Figure 2 This is a process flow chart of a circuit modification method provided by an embodiment of the present invention, with reference to Figure 1 and Figure 2 , the line modification method may include:

[0051] S101. Provide a chip to be tested.

[0052] Among them, the chip to be tested includes a substrate and a multilayer film layer located on one side of the substrate; the multilayer film layer includes a multilayer conductive layer with insulating intervals, and a top dielectric layer located on the side of each conductive layer facing away from the substrate; each conductive layer includes at least one conductive layer to be tested, and the conductive layer to be tested includes a circuit to be tested.

[0053] The chip to be tested can be specifically understood as a chip with a specific structure and function prepared according to a design drawing, so as to be able to test and verify the function and performance of the circuits in the designed chip.

[0054] Specifically, such as Figure 2As shown, substrate 01 can be a silicon substrate. A multilayer conductive layer 020 is formed on one side of the substrate by deposition, etching, or other methods. A dielectric layer is provided between adjacent conductive layers, for example, between conductive layer 021 and conductive layer 022, and between conductive layer 022 and conductive layer 023, to insulate the conductive layers from each other and prevent short circuits in the circuits within each conductive layer. In addition, a top dielectric layer 02 is provided on the side of the topmost conductive layer 023 facing away from substrate 01 to protect the topmost conductive layer. The top dielectric layer 02 can be designed to have specific functions, such as optical properties, protective performance, or other customized functions, thereby expanding the use and application of the chip. The multilayer conductive layer 020 can include one or more conductive layers to be tested, and the conductive layer to be tested can include one or more circuits to be tested. For example, in the case where the multilayer conductive layer 020 includes a conductive layer to be tested 021, and the conductive layer to be tested 021 includes a circuit to be tested A, the circuit to be tested A can be a device structure made of a conductive material such as metal, or a connecting line between devices. If there is a defect in the circuit A to be tested, such as an open circuit or a short circuit, the device including the circuit A to be tested or the device electrically connected using the circuit A to be tested will not be able to work accurately. Therefore, after the chip to be tested is prepared, the circuit A to be tested needs to be tested in order to verify the rationality of the chip design drawings.

[0055] S102 , forming circuit lead-out holes penetrating through each film layer on a side of the conductive layer to be tested facing away from the substrate, so as to expose the circuit to be tested.

[0056] At least some of the line lead-out holes are first line lead-out holes; among the same first line lead-out holes, the size of the first line lead-out hole close to the line to be tested is smaller than the size of the first line lead-out hole far from the line to be tested.

[0057] Specifically, the film layers on the side of the circuit A to be tested in the conductive layer to be tested 023 facing away from the substrate 01 can be removed by etching to form circuit lead-out holes that penetrate the top dielectric layer 02 and the film layers between the top dielectric layer 02 and the conductive layer to be tested 021, thereby exposing the circuit A to be tested. At least some of the circuit lead-out holes are first circuit lead-out holes 03, and the dimension W01 of the first circuit lead-out holes 03 near the circuit A to be tested is smaller than the dimension W02 of the first circuit lead-out holes 03 away from the circuit A to be tested. In other words, the first circuit lead-out holes 03 have a structure that is wider at the top and narrower at the bottom, resulting in the side edges of the first circuit lead-out holes 03 having a slope-like structure.

[0058] S103 , depositing a conductive material on at least a portion of the area around the circuit lead-out hole and inside the circuit lead-out hole to form a test pad and a lead connecting the test pad and the circuit to be tested.

[0059] The conductive material may be specifically understood as a metal or non-metal material that can conduct electrical signals. In an exemplary embodiment, the conductive material may include platinum metal, which has good electrical conductivity.

[0060] For details, please refer to Figure 2 By depositing a conductive material on at least a portion of the area around the circuit lead-out hole 03, a test pad 04 can be formed around the circuit lead-out hole. The specific shape and size of the test pad 04 can be designed according to the size and shape of the test probe. The embodiment of the present invention does not specifically limit this. In an exemplary embodiment, the shape of the test pad 04 can be a "cross" shape centered on the circuit lead-out hole 03. At the same time, by depositing a conductive material inside the circuit lead-out hole 03, a corresponding lead wire 05 can be formed inside the circuit lead-out hole 03. The lead wire 05 can electrically connect the test pad 04 and the circuit A to be tested. In this way, when testing the circuit A to be tested, the test probe can be brought into contact with the test pad 04 and electrically connected to the circuit A to be tested through the test pad 04 and the lead wire 05, thereby testing the performance and connection status of the circuit A to be tested.

[0061] Accordingly, since at least part of the circuit lead-out holes 03 are first circuit lead-out holes, and the first circuit lead-out holes 03 have a structure that is wide at the top and narrow at the bottom, the sidewalls of the first circuit lead-out holes 03 are sloped. Therefore, when depositing the conductive material in the first circuit lead-out holes 03, the conductive material can be deposited along the sidewalls of the first circuit lead-out holes 03 from the surface of the circuit A to be tested toward the side away from the circuit A to be tested, thereby preventing the conductive material from clogging the first circuit lead-out holes 03 due to the large depth-to-width ratio of the first circuit lead-out holes 03. As a result, lead wires 05 connecting the test pads 04 and the circuit A to be tested can be formed, and the circuit A to be tested can be effectively connected to the surface of the chip to be tested via the lead wires 05 and the test pads 04.

[0062] In this embodiment, after providing a chip to be tested, a circuit lead-out hole is formed in the chip to be tested, penetrating each film layer of the conductive layer to be tested on a side of the chip to be tested facing away from the substrate, to expose the circuit to be tested. Furthermore, the size of a first circuit lead-out hole near the circuit to be tested is smaller than the size of a first circuit lead-out hole farther away from the circuit to be tested, i.e., the first circuit lead-out hole has a structure that is wider at the top and narrower at the bottom. This allows conductive material to be deposited along the sidewalls of the first circuit lead-out hole with the wider at the top and narrower at the bottom until it contacts the circuit to be tested, preventing the conductive material from closing on the upper side of the first circuit lead-out hole and becoming unable to electrically connect to the cable to be tested. Consequently, test pads and lead wires connecting the test pads and the circuit to be tested are formed around the new lead-out hole. Furthermore, the circuit to be tested can be accurately led to the surface layer of the chip to be tested via the lead wires, thereby ensuring accuracy and effectiveness in testing the circuit to be tested of the chip to be tested.

[0063] Optionally, before forming the line lead-out hole, it is necessary to determine the maximum size of the formed line lead-out hole, such as Figure 3 As shown, the method for determining the maximum size of the line lead-out hole may include:

[0064] S201: Obtain design parameters of the chip to be tested.

[0065] The design parameters may include the overall dimensions of the chip under test, the number of film layers, and the dimensions and positions of the device and connection structures within each film layer. The design parameters of the chip under test may be stored in a corresponding memory. In this case, the design parameters of the chip under test can be directly retrieved from the memory to obtain information such as the overall dimensions of the chip under test, the number of film layers, and the dimensions and positions of the device and connection structures within each film layer, thereby providing the necessary foundation for subsequent testing and analysis of the chip under test.

[0066] S202 : Determine the size of the circuit-free area in each film layer on the side of the circuit to be tested facing away from the substrate according to the design parameters of the chip to be tested.

[0067] The circuit-free region has no conductive structure, meaning it can be understood as a region that does not contain any conductive elements or connection structures. The circuit-free region overlaps the circuit under test in a direction perpendicular to the substrate plane, meaning it can be located above the circuit under test.

[0068] Specifically, since the circuit extraction hole needs to penetrate each film layer on the side of the circuit under test facing away from the substrate, to prevent the circuit extraction hole from damaging the conductive structures in each film layer, the circuit extraction hole should be located in the circuit-free area of each film layer. In this case, based on the design parameters of the chip under test, the size of the circuit-free area in each film layer on the side of the circuit under test facing away from the substrate (i.e., the size of the area above the circuit under test and without conductive structures) can be determined, as well as the overlap between the circuit-free area and the circuit under test, for example, whether the circuit-free area covers the circuit under test.

[0069] S203 , determining the maximum size of the circuit lead-out holes formed in each film layer according to the size of the circuit-free area in each film layer.

[0070] The circuit lead-out holes penetrating each film layer are respectively located in the circuit-free area of each film layer.

[0071] It's understandable that when the circuit lead-out holes in each film layer overlap with the conductive structures within each film layer, the conductive structures within each film layer will be damaged. When lead-out wires are subsequently formed, they will connect to the conductive structures within each film layer, short-circuiting the circuit under test and the conductive structures within each film layer, making it impossible to test the cable under test. Therefore, the circuit lead-out holes that penetrate each film layer should be located within the circuit-free area of each film layer. In this case, the size of the circuit-free area in each film layer that overlaps the circuit under test is the maximum size for the circuit lead-out holes in each film layer.

[0072] Specifically, based on the size of the circuit-free area in each film layer, the maximum size of the circuit lead-out hole formed in each film layer can be determined accordingly to ensure that the circuit lead-out hole in each film layer is located in the circuit-free area in each film layer, avoiding contact with the conductive structure in each film layer, thereby ensuring that the circuit to be tested can be accurately and effectively led to the surface of the chip to be tested.

[0073] Optionally, after determining the maximum size of the circuit lead-out hole formed according to the design parameters of the chip to be tested, the number of punching times m when forming the circuit lead-out hole needs to be adjusted according to the design parameters of the chip to be tested, such as Figure 4 As shown, the method for determining the number of punching times m when forming a line lead-out hole may include:

[0074] S204 : Determine the depth d and the width w of the circuit to be tested according to the design parameters of the chip to be tested.

[0075] The depth d of the circuit under test is the distance between the circuit under test and the surface of the top dielectric layer facing away from the substrate, and the width w of the circuit under test is the dimension of the circuit under test in the direction perpendicular to the extension direction of the circuit under test.

[0076] Specifically, based on the design parameters of the chip under test, the distance d between the circuit under test A and the surface of the top dielectric layer facing away from the substrate, i.e., the depth d of the circuit under test A, can be determined, and the dimension w of the circuit under test A in the direction perpendicular to the extension of the circuit under test A, i.e., the width w of the circuit under test A, can be determined. For example, Figure 5 As shown, the depth d of the circuit A to be tested is the vertical distance between the circuit A to be tested and the surface of the top dielectric layer 02 facing away from the substrate 01 along the Z direction, and the width w of the circuit A to be tested is the size of the circuit to be tested in the X direction.

[0077] S205 , determining the number of punching times m when forming the circuit lead-out holes according to the depth d of the circuit to be tested, the width w of the circuit to be tested, and the size of the circuit-free area in each film layer.

[0078] Among them, continue to refer to Figure 5 The greater the depth d of the circuit under test, the greater the distance between the circuit under test and the surface of the top dielectric layer 02 facing away from the substrate 01, resulting in a deeper depth of the circuit lead-out hole. When the ratio between the depth d and the width w of the circuit under test A is large, if the depth and width of the formed circuit lead-out hole are designed based on the depth d and width w of the circuit under test A, a circuit lead-out hole with a large aspect ratio will be formed. The circuit lead-out hole cannot be accurately exposed in a single drilling operation, and a circuit lead-out hole with a large aspect ratio is not conducive to the subsequent deposition of conductive material.

[0079] After determining the depth d of the circuit to be tested, the width w of the circuit to be tested, and the size of the circuit-free area in each film layer, this embodiment can determine the number of times the circuit lead-out hole is punched based on the depth d of the circuit to be tested, the width w of the circuit to be tested, and the size of the circuit-free area in each film layer, so that the depth of each punching is within a certain depth range, thereby preventing the situation where the position of the circuit to be tested cannot be accurately determined due to excessive drilling depth each time; at the same time, the hole width of each punching can be the same or different, thereby being able to adapt to the size of the circuit-free area in each film layer, so that the circuit lead-out hole can be located in the circuit-free area; in addition, when the hole width of each punching is different, the hole width of the previous punching can be larger than the hole width of the next punching, so that the circuit lead-out hole can form a structure that is wide at the top and narrow at the bottom, and the sidewall of the circuit lead-out hole can be similar to a slope, which is conducive to the subsequent deposition of conductive material.

[0080] Optionally, the number of punching times m when forming the circuit lead-out hole is determined based on the depth d of the circuit to be tested, the width w of the circuit to be tested, and the size of the circuit-free area in each film layer. Specifically, the number of punching times m when forming the circuit lead-out hole may include: determining the aspect ratio n of the circuit to be tested based on the depth d of the circuit to be tested and the width w of the circuit to be tested; determining the number of punching times m when forming the circuit lead-out hole based on the aspect ratio n of the circuit to be tested and the size of the circuit-free area in each film layer; m is a positive integer.

[0081] The aspect ratio n of the circuit to be tested is the ratio between the depth d of the circuit to be tested and the width w of the circuit to be tested.

[0082] Specifically, when the aspect ratio n of the circuit to be tested is large, the circuit lead-out holes exposing the circuit to be tested can be formed in multiple passes. If the hole width varies with each pass, and the hole width of the previous pass can be larger than the hole width of the next pass, the maximum size of the circuit lead-out holes formed in each film layer can be determined based on the size of the circuit-free area in each film layer. In this way, the number of passes m required to form the circuit lead-out holes exposing the circuit to be tested, as well as the film layer penetrated by each pass and the size of the circuit lead-out holes in the film layer penetrated, can be determined based on the aspect ratio of the circuit to be tested and the size of the circuit-free area in each film layer.

[0083] It is understandable that when the aspect ratio n is large, it means that the depth of the circuit A to be tested is deep. In order to ensure the success rate of circuit modification, it is necessary to use multiple punching methods to form a circuit lead-out hole with a structure that is wide at the top and narrow at the bottom, so that the conductive material deposited in the circuit lead-out hole can be deposited along the sloped sidewalls of the circuit lead-out hole to connect with the circuit A to be tested, thereby effectively leading the circuit A to be tested to the surface of the chip to be tested. When the aspect ratio n is small, it means that the circuit A to be tested is shallow. Since the circuit A to be tested is shallow, the depth of the circuit lead-out hole is also shallow. Therefore, when the conductive material is deposited in the circuit lead-out hole, it will not close. At this time, a straight-cylinder circuit lead-out hole can be formed by punching once, and the conductive material can be deposited in the circuit lead-out hole to lead the circuit A to be tested to the surface of the chip to be tested.

[0084] It can also be understood that the number of times the circuit lead-out holes are punched is also related to the size of the circuit-free area in each film layer. When the size D of the circuit-free area is small, for example, D < 3w, continue to refer to Figure 5The size of the line lead-out hole located in the line-free area can only vary within a small range. The width of the line lead-out hole formed by m times of drilling is also narrow, resulting in a large angle of the line lead-out hole sidewall slope. In this case, the sidewall slope of the line lead-out hole cannot play a positive role in the deposition of conductive material. In addition, when drilling multiple times, the parameters of each drilling need to be designed separately, making the multiple drilling method more complicated. Therefore, when the size D of the line-free area is small, it is not easy to use the multiple drilling method to set the line lead-out hole. The line lead-out hole can be formed by a simple single drilling method. When the size D of the circuit-free area is large, for example, when D ≥ 3w, the size of the circuit lead-out hole can vary within a large range. In the circuit lead-out hole formed by m times of drilling, the portion away from the circuit to be tested can have a wider width, while the portion close to the circuit to be tested can have a relatively smaller size, so that the circuit lead-out hole can have a structure that is significantly wider at the top and narrower at the bottom. The sidewalls of the circuit lead-out hole can have a smaller slope angle. In this case, the conductive material can be deposited along the sidewalls of the circuit lead-out hole to connect with the circuit to be tested A, thereby effectively leading the circuit to be tested to the surface of the chip to be tested.

[0085] In summary, the number of punching times m when forming the circuit lead-out hole is determined by comprehensively considering the aspect ratio n of the circuit to be tested and the size of the circuit-free area in each film layer. Under the premise of simplifying the process, it is ensured that the formed circuit lead-out hole can accurately expose the circuit to be tested. At the same time, when the conductive material is deposited in the circuit lead-out hole, the circuit to be tested can be accurately led to the surface layer of the chip to be tested, which is convenient for subsequent performance testing of the chip to be tested.

[0086] Optionally, determining the number of punching times m when forming a circuit lead-out hole based on the aspect ratio n of the circuit to be tested and the size of the circuit-free area in each film layer may specifically include: judging whether the aspect ratio n of the circuit to be tested and the size of the circuit-free area in the top dielectric layer meet a first preset condition; the first preset condition is that the aspect ratio n of the circuit to be tested is greater than or equal to a preset value k, and the size of the circuit-free area in the top dielectric layer is greater than or equal to k*w; if so, determining the circuit to be tested as a first circuit to be tested, and determining the circuit lead-out hole exposing the first circuit to be tested as a first circuit lead-out hole; and determining the number of punching times m when forming the first circuit lead-out hole exposing the first circuit to be tested to be a positive integer greater than or equal to n.

[0087] The preset value k can be designed according to actual needs and is not specifically limited in the embodiment of the present invention. In an exemplary embodiment, k can be 3. Thus, when the aspect ratio n of the circuit to be tested is greater than or equal to k, it can be considered that the circuit to be tested has a large aspect ratio n, and a circuit lead-out hole with a wide-upper-narrow-lower structure needs to be provided to ensure that the conductive material can be deposited along the side of the circuit lead-out hole, so that the conductive material can cover the circuit lead-out hole, thereby accurately leading the circuit lead-out hole to the surface layer of the chip to be tested. At the same time, when the size of the circuit-free area in the top dielectric layer that overlaps with the circuit to be tested is greater than or equal to k*w, it can be determined that the size of the circuit-free area in the top dielectric layer is large, which can meet the size requirement for providing the circuit lead-out hole with a wide-upper-narrow-lower structure.

[0088] Specifically, refer to Figure 6 When it is determined that the aspect ratio n of the circuit to be tested and the size of the circuit-free area in the top dielectric layer O2 meet the first preset condition, the circuit to be tested A can be determined as the first circuit to be tested, and the circuit lead-out hole exposing the first circuit to be tested can be determined as the first circuit lead-out hole. In this case, multiple punching operations can be performed to form a first circuit lead-out hole with a structure that is wide at the top and narrow at the bottom. During the m punching operations, the partial size of the first circuit lead-out hole formed after the previous punching operation is larger than the width of the first circuit lead-out hole formed after the next punching operation, so that the sidewalls of the first circuit lead-out hole can be sloped, and the slope angle is relatively small. In this way, when depositing the conductive material, the conductive material can be deposited along the sidewalls of the first circuit lead-out hole until it connects with the circuit to be tested A, thereby accurately leading the circuit to be tested A to the surface layer of the chip to be tested.

[0089] It is understood that the number of perforations m when forming the first circuit lead-out hole exposing the first circuit to be tested is a positive integer greater than or equal to n, that is, m can be any positive integer greater than or equal to n. For example, when the aspect ratio n of the first circuit to be tested is 3.5, the number of perforations m when forming the first circuit lead-out hole exposing the first circuit to be tested can be 4, 5, or 6, etc., to ensure that the first circuit lead-out hole formed by the m number of perforations has a wide top and narrow bottom structure while being able to expose the first circuit to be tested. Generally, the value of m is not infinite, and its specific number is closely related to the depth d of the first circuit to be tested. Based on empirical considerations, the number of perforations m is usually less than or equal to 10. The specific value of the number of perforations m can be designed according to actual needs and is not specifically limited in the embodiments of the present invention.

[0090] Optionally, determining the number of punching times m when forming the circuit lead-out hole based on the aspect ratio n of the circuit to be tested and the size of the circuit-free area in each film layer may also include: if the aspect ratio n of the circuit to be tested is less than a preset ratio k, determining the circuit to be tested as a second circuit to be tested, and determining the circuit lead-out hole exposing the second circuit to be tested as a second circuit lead-out hole; and determining the number of punching times m when forming the second circuit lead-out hole exposing the second circuit to be tested to be 1.

[0091] Specifically, such as Figure 7 As shown, when the aspect ratio n of the circuit under test A is less than the preset ratio k, the circuit under test can be determined to have a smaller aspect ratio n. Circuit under test A can be designated as the second circuit under test, and the circuit lead-out hole exposing the second circuit under test can be designated as the second circuit lead-out hole. In this case, a straight-tube circuit lead-out hole can be formed through a single punching operation, thereby simplifying the punching process, improving the efficiency of circuit modification, and ensuring that circuit under test A can effectively connect to the chip surface.

[0092] It can be understood that when the depth of the line A to be tested is d, and the average drilling rate when forming the line lead-out hole capable of exposing the line A to be tested by drilling m times is v, and the average time is t, the relationship between t and d, m, and v can be:

[0093] Optionally, based on the above embodiment, forming a circuit lead-out hole penetrating each film layer on the side of the conductive layer to be tested facing away from the substrate to expose the circuit to be tested may include: using a focused ion beam to etch each film layer on the side of the conductive layer to be tested facing away from the substrate m times to form the circuit lead-out hole exposing the circuit to be tested, wherein each etching step penetrates at least one film layer.

[0094] Among them, the focused ion beam can be specifically understood as a high-energy ion beam, which is used to accurately control the process of etching each film layer on the side of the conductive layer to be tested away from the substrate. Specifically, the focused ion beam is used to etch each film layer on the side of the conductive layer to be tested away from the substrate 01 m times to form a circuit lead-out hole 03 exposing the circuit A to be tested. The beam spot size and capacity of the focused ion beam during each etching can be the same or different, and can be designed according to actual needs. By controlling the beam spot size and / or energy of the focused ion beam, the size of the circuit lead-out hole in the film layer penetrated during each etching can be controlled to ensure that the formed circuit lead-out hole can accurately expose the circuit A to be tested. At the same time, when the conductive material is subsequently deposited, the conductive material can be accurately deposited on the surface of the circuit A to be tested, so that the circuit to be tested can be accurately guided to the surface layer of the chip to be tested.

[0095] Optionally, the size of the circuit lead-out hole in the film layer penetrated during the (i-1)th etching is larger than the size of the circuit lead-out hole in the film layer penetrated during the i-th etching, where i is a positive integer greater than 1 and less than or equal to m.

[0096] Specifically, when the circuit A to be tested is deep and multiple punching operations are required to form a circuit lead-out hole with a structure that is wide at the top and narrow at the bottom, the size of the circuit lead-out hole in the film layer penetrated during the i-1th etching is larger than the size of the circuit lead-out hole in the film layer penetrated during the i-th etching. For example, when the aspect ratio n of the circuit A to be tested is 3.5, m can be 4, that is, 4 punching operations are required to form the circuit lead-out hole. At this time, when i is 2, the size of the circuit lead-out hole in the film layer penetrated during the first etching is larger than the size of the circuit lead-out hole in the film layer penetrated during the second etching; when i is 3, the size of the circuit lead-out hole in the film layer penetrated during the second etching is larger than the size of the circuit lead-out hole in the film layer penetrated during the third etching; when i is 4, the size of the circuit lead-out hole in the film layer penetrated during the third etching is larger than the size of the circuit lead-out hole in the film layer penetrated during the fourth etching. In this way, the size of the line lead-out hole close to the line A to be tested can be smaller than the size of the line lead-out hole far from the line A to be tested, so that a line lead-out hole with a structure of being wide at the top and narrow at the bottom can be formed by drilling m times.

[0097] Optionally, the size of the circuit lead-out hole in the film layer penetrated during the first etching is K*w, where K is a positive integer greater than or equal to a preset value k; the size of the circuit lead-out hole in the film layer penetrated during the i-th etching is [K-(i-1)*(K-1) / (m-1)]*w.

[0098] Among them, K can be determined according to the size of the line-free area in each film layer to be penetrated at the first moment to ensure that the line lead-out hole can be located in the line-free area of each film layer. In an exemplary embodiment, K can be greater than or equal to 3 and less than or equal to 10.

[0099] For example, Figure 8As shown, taking m equal to 4 as an example, the size of the circuit lead-out hole in the film layer penetrated during the first etching is K*w, the size of the circuit lead-out hole in the film layer penetrated during the second etching is [K-(K-1) / 3]*w, the size of the circuit lead-out hole in the film layer penetrated during the third etching is [K-2*(K-1) / 3]*w, and the size of the circuit lead-out hole in the film layer penetrated during the fourth etching is [K-3*(K-1) / 3]w. For example, taking the size of the circuit lead-out hole in the film layer penetrated during the first etching as 3*w, the size of the circuit lead-out hole in the film layer penetrated during the second etching is 7 / 3*w, the size of the circuit lead-out hole in the film layer penetrated during the third etching is 5 / 3*w, and the size of the circuit lead-out hole in the film layer penetrated during the fourth etching is w. Thus, a circuit lead-out hole with a structure of wide top and narrow bottom is formed by punching four times, so that the conductive material deposited in the circuit lead-out hole can be connected to the circuit A to be tested along the side wall of the circuit lead-out hole, thereby effectively leading the circuit A to be tested to the surface layer of the chip to be tested.

[0100] Based on the same inventive concept, an embodiment of the present invention further provides a test chip, which uses the circuit modification method in the above embodiment to perform circuit modification, such as Figure 9 As shown, the test chip includes: a substrate 01, a multi-layer film layer located on one side of the substrate, a test pad 04 and a lead 05.

[0101] Substrate 01 may be a silicon substrate. The multilayer film layer includes multiple conductive layers 020 with insulating spacing, and a top dielectric layer 02 located on the side of each conductive layer facing away from the substrate. Each conductive layer includes at least one conductive layer to be tested 021, which includes a circuit A to be tested. Circuit lead-out holes are provided in each film layer on the side of the conductive layer to be tested 021 facing away from substrate 01. At least some of the circuit lead-out holes are first circuit lead-out holes 03. Within the same first circuit lead-out hole, the size of the first circuit lead-out hole 03 closer to the circuit A to be tested is smaller than the size of the first circuit lead-out hole 03 farther away from the circuit A to be tested. A test pad 04 is located in at least a portion of the area surrounding the circuit lead-out hole. A lead-out line 05 is located within the circuit lead-out hole, and the lead-out line 05 connects the test pad 04 and the circuit A to be tested.

[0102] The test chip can be modified using the circuit modification method provided in any embodiment of the present invention, and has the corresponding beneficial effects of the circuit modification method. For technical details not fully described in this embodiment, please refer to the circuit modification method provided in any embodiment of the present invention.

[0103] Since the test chip described above can be modified using the circuit modification method provided in any embodiment of the present invention, those skilled in the art will be able to understand the specific implementation and various variations of the test chip of this embodiment based on the circuit modification method described in the embodiments of the present invention. Therefore, how to modify the circuit of the test chip using the circuit modification method provided in any embodiment of the present invention will not be described in detail here. As long as those skilled in the art implement the circuit modification method provided in any embodiment of the present invention to modify the circuit of the test chip, it falls within the scope of protection of this application.

[0104] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A line modification method, characterized in that: include: Providing a chip to be tested; the chip to be tested includes a substrate and a multilayer film layer located on one side of the substrate; The multilayer film layer includes a plurality of conductive layers with insulating intervals, and a top dielectric layer located on a side of each conductive layer facing away from the substrate; each conductive layer includes at least one conductive layer to be tested, and the conductive layer to be tested includes a circuit to be tested; forming a circuit lead-out hole penetrating through each of the film layers on a side of the conductive layer to be tested away from the substrate to expose the circuit to be tested; At least some of the circuit lead-out holes are first circuit lead-out holes; In the same first circuit lead-out hole, the size of the first circuit lead-out hole close to the circuit to be tested is smaller than the size of the first circuit lead-out hole far from the circuit to be tested; Depositing a conductive material in at least a portion of the area around the circuit lead-out hole and in the circuit lead-out hole to form a test pad and a lead connecting the test pad and the circuit to be tested; Before forming a circuit lead-out hole penetrating each film layer on a side of the conductive layer to be tested away from the substrate to expose the circuit to be tested, the method further includes: Obtaining design parameters of the chip to be tested; Determining the size of a circuit-free region in each of the film layers on a side of the circuit to be tested facing away from the substrate based on design parameters of the chip to be tested; wherein no conductive structure is provided in the circuit-free region, and the circuit-free region overlaps the circuit to be tested in a direction perpendicular to the plane of the substrate; Determine the depth d and width w of the circuit under test based on the design parameters of the chip under test; the depth d of the circuit under test is the distance between the circuit under test and the surface of the top dielectric layer facing away from the substrate, and the width w of the circuit under test is the dimension of the circuit under test in a direction perpendicular to the extension of the circuit under test; Determining the number of punching times m when forming the circuit lead-out hole according to the depth d of the circuit to be tested, the width w of the circuit to be tested, and the size of the circuit-free area in each film layer; The size of the circuit lead-out hole in the film layer penetrated during the first drilling is K×w, where K is a positive integer greater than or equal to a preset value k; The size of the circuit lead-out hole in the film layer penetrated during the i-th punching is [K-(i-1)×(K-1) / (m-1)]×w, where i is a positive integer greater than 1 and less than or equal to m.

2. The line modification method according to claim 1, characterized in that: Before forming a circuit lead-out hole penetrating each film layer on a side of the conductive layer to be tested away from the substrate to expose the circuit to be tested, the method further includes: The maximum size of the circuit lead-out hole formed in each film layer is determined according to the size of the circuit-free area in each film layer; wherein the circuit lead-out hole passing through each film layer is located in the circuit-free area of each film layer.

3. The line modification method according to claim 1, characterized in that: Determining the number of punching times m when forming the circuit lead-out hole according to the depth d of the circuit to be tested, the width w of the circuit to be tested, and the size of the circuit-free area in each film layer includes: Determining the aspect ratio n of the circuit to be tested according to the depth d of the circuit to be tested and the width w of the circuit to be tested; The number of punching times m when forming the circuit lead-out holes is determined according to the aspect ratio n of the circuit to be tested and the size of the circuit-free area in each of the film layers; m is a positive integer.

4. The line modification method according to claim 3, characterized in that: Determining the number of punching times m when forming the circuit lead-out hole according to the aspect ratio n of the circuit to be tested and the size of the circuit-free area in each of the film layers includes: Determining whether the aspect ratio n of the circuit to be tested and the size of the circuit-free area in the top dielectric layer meet a first preset condition; the first preset condition is that the aspect ratio n of the circuit to be tested is greater than or equal to a preset value k, and the size of the circuit-free area in the top dielectric layer is greater than or equal to k×w; If yes, the circuit to be tested is determined as the first circuit to be tested, and the circuit lead-out hole exposing the first circuit to be tested is determined as the first circuit lead-out hole; The number m of punching times when forming the first circuit lead-out hole exposing the first circuit to be tested is determined to be a positive integer greater than or equal to n.

5. The line modification method according to claim 4, characterized in that: Determining the number of punching times m when forming the circuit lead-out holes according to the aspect ratio n of the circuit to be tested and the size of the circuit-free area in each of the film layers, further comprising: If the aspect ratio n of the circuit to be tested is less than the preset value k, the circuit to be tested is determined as a second circuit to be tested, and the circuit lead-out hole exposing the second circuit to be tested is determined as a second circuit lead-out hole; The number m of punching times when forming the second line lead-out hole exposing the second line to be tested is determined to be 1.

6. The line modification method according to claim 3, characterized in that: Forming a circuit lead-out hole penetrating each film layer on a side of the conductive layer to be tested away from the substrate to expose the circuit to be tested, comprising: A focused ion beam is used to perform m etching on each film layer on a side of the conductive layer to be tested away from the substrate to form the circuit lead-out hole exposing the circuit to be tested; wherein each etching penetrates at least one film layer.

7. The line modification method according to claim 6, characterized in that: The size of the circuit lead-out hole in the film layer penetrated during the i-1th etching is larger than the size of the circuit lead-out hole in the film layer penetrated during the i-th etching, where i is a positive integer greater than 1 and less than or equal to m.

8. A test chip, wherein the circuit modification method according to any one of claims 1 to 7 is used for circuit modification, wherein: include: substrate; A multilayer film layer is located on one side of the substrate; The multilayer film layer includes a plurality of conductive layers with insulating intervals, and a top dielectric layer located on a side of each conductive layer facing away from the substrate; each conductive layer includes at least one conductive layer to be tested, and the conductive layer to be tested includes a circuit to be tested; A circuit lead-out hole is provided in each of the film layers on the side of the conductive layer to be tested facing away from the substrate; at least some of the circuit lead-out holes are first circuit lead-out holes; and among the same first circuit lead-out holes, the size of the first circuit lead-out hole close to the circuit to be tested is smaller than the size of the first circuit lead-out hole far from the circuit to be tested; A test pad and a lead wire; the test pad is located in at least a portion of the area around the circuit lead hole, the lead wire is located in the circuit lead hole, and the lead wire connects the test pad and the circuit to be tested; Among them, the circuit lead-out hole is formed by punching m times, and the size of the circuit lead-out hole in the film layer penetrated during the first punching is K×w, where K is a positive integer greater than or equal to a preset value k; the size of the circuit lead-out hole in the film layer penetrated during the i-th punching is [K-(i-1)×(K-1) / (m-1)]×w, where i is a positive integer greater than 1 and less than or equal to m.

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