Method for forming interconnection structure

Abstract

A method of forming an interconnect structure includes forming a multi-layer stack on a substrate having a conductive layer, where the multi-layer stack includes a very low dielectric layer over the conductive layer and a mask layer over the very low dielectric layer. The method further includes etching the multi-layer stack to form a trench exposing the very low dielectric layer, forming a spacer layer on sidewalls of the trench that applies a tensile stress to the mask layer, etching the very low dielectric layer to form a via opening exposing the conductive line layer, filling the trench and the via opening with a conductive material, and removing the conductive material from the trench. And performing a planarization process on the multilayer stack to remove the spacer layer. The spacer layer anchors the mask layer to maintain the structure and position of the mask layer, so that the possibility of deformation of the trench caused by the mask layer can be reduced, thereby improving the reliability of the interconnect structure.

Description

Technical Field

[0001] The present disclosure relates to a method for forming an interconnect structure, and more particularly to a method for forming an interconnect structure using a damascene process. Background Art

[0002] The damascene process can be used to form an interconnect structure in a device, wherein the damascene process generally includes forming a gap in a dielectric layer and filling the gap with a metal material to form a conductive path for the interconnect structure. Since the damascene process has simplified steps compared to other methods, forming an interconnect structure by the damascene process can provide a high yield. However, as the feature size of the device decreases, the interconnect structure may have defects such as distortion during the damascene process, causing electrical abnormalities in the interconnect structure. Summary of the invention

[0003] According to some embodiments of the present disclosure, a method for forming an internal wiring structure includes the following steps. A multilayer stack is formed on a substrate including a conductor layer, wherein the multilayer stack includes an extremely low dielectric layer located above the conductor layer and a mask layer located above the extremely low dielectric layer. The multilayer stack is etched to form a groove, wherein the groove exposes the extremely low dielectric layer. A spacer layer is formed on the sidewall of the groove, wherein the spacer layer physically contacts the mask layer. The extremely low dielectric layer is etched to form a dielectric window opening, wherein the dielectric window opening exposes the conductor layer. The groove and the dielectric window opening are filled with a conductive material. A planarization process is performed on the multilayer stack to remove the spacer layer.

[0004] According to some embodiments of the present disclosure, a method for forming an internal wiring structure includes the following steps. An extremely low dielectric layer is formed above a substrate, wherein the substrate includes a wire layer. A first deposition process is performed to form a first titanium nitride layer above the extremely low dielectric layer. A first etching process is performed to form a first trench in the first titanium nitride layer and the extremely low dielectric layer. A second deposition process is performed to form a second titanium nitride layer on the sidewall of the first trench. A second etching process is performed to form a dielectric window opening in the extremely low dielectric layer, wherein the dielectric window opening exposes the wire layer. The first trench and the dielectric window opening are filled with a conductive material. The first titanium nitride layer and the second titanium nitride layer are removed.

[0005] According to the above-mentioned embodiment of the present disclosure, the method for forming an internal connection structure includes forming a spacer layer in a multi-layer stacked groove, wherein the spacer layer physically contacts the multi-layer stacked mask layer. Since the spacer layer can anchor the mask layer to maintain the structure and position of the mask layer, the influence on the groove shape can be reduced, thereby improving the reliability of the internal connection structure formed by the groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1 to 7 Some embodiments of the present disclosure illustrate cross-sectional views of an interconnect structure at multiple manufacturing stages. DETAILED DESCRIPTION

[0007] In order to realize the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. The following describes specific examples of components, configurations, etc. to simplify the present disclosure. Of course, these are only examples and are not restrictive.

[0008] In addition, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," etc., may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures.

[0009] The present disclosure provides a method for forming an interconnect structure, which includes forming a groove in a multi-layer stack of the interconnect structure, and forming a spacer layer in the groove to contact a mask layer of the multi-layer stack. During the process of the interconnect structure, the spacer layer can maintain the structure and position of the mask layer, thereby reducing the possibility of deformation of the groove by the mask layer, thereby improving the reliability of the interconnect structure.

[0010] refer to Figure 1 , a multilayer stack 200 is formed on the substrate 100. Specifically, the multilayer stack 200 includes a plurality of horizontally stacked material layers formed on the top surface of the substrate 100, wherein these material layers will be used to form an internal wiring structure on the substrate 100. In some embodiments, the substrate 100 may include a wire layer 110, and the multilayer stack 200 is formed on the substrate 100 and covers the wire layer 110. The wire layer 110 may include a barrier layer 112 and a conductive material 114, wherein the barrier layer 112 surrounds the conductive material 114 to separate the conductive material 114 from the substrate 100. In such an embodiment, the substrate 100 and the wire layer 110 may be a lower-layer internal wiring structure formed first, and the multilayer stack 200 will be used to form an upper-layer internal wiring structure relative to the substrate 100.

[0011] The multilayer stack 200 may include an etch stop layer 210, an adhesion layer 220, an extreme low-k (ELK) layer 230, an adhesion layer 240, a dielectric layer 250, and a mask layer 260 stacked in sequence from the top surface of the substrate 100. In the multilayer stack 200, the extreme low-k layer 230 may serve as an interlayer dielectric (ILD) of a subsequently formed interconnect structure. The extremely low-k layer 230 having a low dielectric constant may reduce parasitic capacitance in the structure, thereby improving the electrical performance of the subsequently formed interconnect structure, for example, reducing the resistance capacitance delay (RC delay) of the interconnect structure. In some embodiments, the extremely low-k layer 230 may include an extremely low-k material having a dielectric constant less than about 2.5. For example, the extremely low-k layer 230 may be made of an organic silicon oxide material (SiOCH), a porous silicon material, the like, or a combination thereof. In the embodiment where the substrate 100 is a lower interconnect structure, the material of the substrate 100 may be the same as the material of the very low dielectric layer 230 .

[0012] The mask layer 260 is formed on the very low dielectric layer 230 by a suitable deposition process, such as chemical vapor deposition (CVD), spin-coating, or the like. The surface area of ​​the mask layer 260 may be not less than the surface area of ​​the very low dielectric layer 230, so that the vertical projection of the mask layer 260 in the Z direction can cover the very low dielectric layer 230. In subsequent processes, the pattern of the mask layer 260 can be transferred to the very low dielectric layer 230 below to define the pattern of the interconnect structure in the very low dielectric layer 230. In some embodiments, the mask layer 260 may include a material different from the very low dielectric layer 230, such as a nitride such as titanium nitride (TiN). In some embodiments, the mask layer 260 may be the topmost layer of the multilayer stack 200, so that the mask layer 260 is exposed to the outside.

[0013] In some embodiments, the etch stop layer 210 may be located between the very low dielectric layer 230 and the substrate 100, so that when forming the pattern of the interconnect structure in the very low dielectric layer 230, the etch stop layer 210 can be used to protect the substrate 100 below. For example, the etch stop layer 210 can be made of silicon carbide (SiC) or the like. In some embodiments, the etch stop layer 210 can also serve as a barrier layer to prevent the conductive material (e.g., Figure 6 The conductive material 404 shown does not easily diffuse in the X direction to cause an undesired conductive path.

[0014] In some embodiments, the dielectric layer 250 may be located between the ultra-low dielectric layer 230 and the mask layer 260, so that when forming the pattern of the interconnect structure in the ultra-low dielectric layer 230, the dielectric layer 250 may be used to improve the accuracy of the pattern. Specifically, the dielectric layer 250 may have a hardness greater than that of the ultra-low dielectric layer 230, thereby reducing the possibility of over-etching the ultra-low dielectric layer 230 in the process of transferring the pattern of the mask layer 260 to the ultra-low dielectric layer 230 to maintain the pattern of the interconnect structure. For example, the dielectric layer 250 may be made of plasma enhanced oxide (PEOX) or the like.

[0015] In some embodiments, a plurality of adhesion layers 220 and adhesion layers 240 may be provided and sandwiched between different material layers of the multilayer stack 200 to enhance the structural stability of the multilayer stack 200. For example, the adhesion layers 220 and adhesion layers 240 may be made of tetraethoxysilane (TEOS) or the like. In this embodiment, the adhesion layer 220 may be located between the very low dielectric layer 230 and the etch stop layer 210, and the adhesion layer 240 may be located between the very low dielectric layer 230 and the dielectric layer 250.

[0016] refer to Figure 2 , etching the multilayer stack 200 to form the first trench 300. Specifically, a photoresist layer (not shown) may be first formed on the top surface of the multilayer stack 200, and the photoresist layer may be patterned to form an opening exposing the multilayer stack 200. Next, an etching process is performed on the top surface of the multilayer stack 200 through the opening of the photoresist layer to etch the mask layer 260, the dielectric layer 250, the adhesion layer 240 and the very low dielectric layer 230, thereby forming the first trench 300 exposing the very low dielectric layer 230. In other words, the first trench 300 extends from the top surface of the mask layer 260 toward the substrate 100, and the bottom surface of the first trench 300 is between the top surface and the bottom surface of the very low dielectric layer 230. In subsequent processes, the first trench 300 may be used to form a pattern of an internal connection structure in the very low dielectric layer 230.

[0017] In some embodiments, there may be a first distance D1 between the bottom surface of the first trench 300 and the top surface of the ultra-low dielectric layer 230, and a second distance D2 between the bottom surface of the first trench 300 and the bottom surface of the ultra-low dielectric layer 230, wherein the first distance D1 may be smaller than the second distance D2, so that the ultra-low dielectric layer 230 may retain sufficient thickness below the first trench 300 to form an internal connection structure in the ultra-low dielectric layer 230 in a subsequent process.

[0018] In some embodiments, the etching process may be an anisotropic etching process, such as a dry etching process using plasma, so that the first trench 300 may have flush sidewalls in the mask layer 260, the dielectric layer 250, the adhesion layer 240, and the very low dielectric layer 230, and the first trench 300 may have a uniform width W1 in the X direction. In some embodiments, after forming the first trench 300, the photoresist layer on the multilayer stack 200 may be stripped off so that the mask layer 260 is exposed again.

[0019] refer to Figure 3 , a spacer layer 310 is formed on the sidewall of the first trench 300. Specifically, a deposition process is performed in the first trench 300, so that the material of the spacer layer 310 is deposited along the sidewall of the first trench 300, thereby forming the spacer layer 310 extending from the top surface of the mask layer 260 to the substrate 100. The spacer layer 310 may physically contact the sidewall of the mask layer 260 alone, physically contact the mask layer 260 and the dielectric layer 250, or physically contact the mask layer 260, the dielectric layer 250 and the adhesion layer 240. The spacer layer 310 may also extend from the mask layer 260 to a top surface lower than the very low dielectric layer 230, so that the spacer layer 310 physically contacts the very low dielectric layer 230, but is spaced from the bottom surface of the first trench 300. The spacer layer 310 may have a sidewall perpendicular to the bottom surface of the first trench 300 or may have a sidewall perpendicular to the bottom surface of the first trench 300. Figure 3 Tapered side walls shown.

[0020] In some embodiments, after the spacer layer 310 is formed on the sidewall of the first trench 300, the spacer layer 310 may have tensile stress, so that the mask layer 260 is affected by the tensile stress of the spacer layer 310 and the pattern stability of the mask layer 260 is improved. For example, when the first trench 300 is further etched into the very low dielectric layer 230 in a subsequent process, the spacer layer 310 with tensile stress can maintain the structure and position of the mask layer 260, thereby achieving the effect of anchoring the mask layer 260. Therefore, the spacer layer 310 can reduce the influence of the mask layer 260 on the shape of the first trench 300, so that the subsequently formed internal connection structure has good structural stability. If the spacer layer 310 is missing in the first trench 300, the mask layer 260 may be deformed during the etching process, thereby causing the pattern of the first trench 300 to be wiggled and the electrical abnormality of the subsequent internal connection structure. In some embodiments, the tensile stress of the spacer layer 310 may be greater than or equal to 1 gigapascal (GPa), so that the tensile stress of the spacer layer 310 is sufficient to reduce the deformation of the mask layer 260 during subsequent etching processes. For example, the tensile stress of the spacer layer 310 may be between 1 GPa and 1.7 GPa.

[0021] In some embodiments, the mask layer 260 and the spacer layer 310 may have an appropriate thickness ratio, so that the tensile stress of the spacer layer 310 is sufficient to significantly reduce the deformation of the mask layer 260. The mask layer 260 may have a thickness T1 in the Z direction perpendicular to the top surface of the very low dielectric layer 230, and the spacer layer 310 may have a thickness T2 in the X direction parallel to the top surface of the very low dielectric layer 230, wherein the thickness T1 is greater than the thickness T2. When the thickness T1 and the thickness T2 have an appropriate ratio, the spacer layer 310 will not significantly affect the shape of the first trench 300, and the tensile stress of the spacer layer 310 can reduce the deformation of the mask layer 260 and reduce the impact on the subsequent interconnect structure. For example, the ratio of the thickness T1 to the thickness T2 may be between 1.5 and 2.5. If the ratio of the thickness T1 to the thickness T2 is greater than 2.5, the tensile stress of the spacer layer 310 may not be sufficient to significantly reduce the deformation of the first trench 300 caused by the mask layer 260.

[0022] In some embodiments, the spacer layer 310 may include a material that is the same as or similar to the mask layer 260 and has high adhesion, for example, when the mask layer 260 includes titanium nitride, the spacer layer 310 may be made of titanium nitride, silicon nitride (SiN), silicon carbonitride (SiCN), nitride, carbonitride, the like, or a combination thereof. In some embodiments, the spacer layer 310 and the mask layer 260 may include different materials, so that the spacer layer 310 and the mask layer 260 have different stress characteristics, for example, when the mask layer 260 includes a nitride material, the spacer layer 310 may include a nitride material or a carbonitride material different from the mask layer 260, so that the spacer layer 310 has tensile stress and the mask layer 260 has compression stress.

[0023] In some other embodiments, the spacer layer 310 and the mask layer 260 may include the same material, but the deposition processes for forming the spacer layer 310 and the mask layer 260 have different steps or process parameters, so that the spacer layer 310 and the mask layer 260 have different stress characteristics. For example, the mask layer 260 may be a titanium nitride layer formed by a first deposition process, and the spacer layer 310 may be a titanium nitride layer formed by a second deposition process. Since the bias applied during the first deposition process is different from the bias applied during the second deposition process, or the gas pressure used in the second deposition process is greater than the gas pressure used in the first deposition process, even if the deposition process is performed with the same material (i.e., titanium nitride), the spacer layer 310 may have a tensile stress and the mask layer 260 may have a compressive stress. For another example, the mask layer 260 and the spacer layer 310 may be the same nitride material, but the spacer layer 310 has a horizontal layer growing upward as the main growth direction, while the mask layer 260 has a vertical column growing laterally as the main growth direction. Since the growth direction of the deposited spacer layer 310 is different from the growth direction of the deposited mask layer 260 , even if the deposition process is performed with the same nitride material, the spacer layer 310 may have a tensile stress and the mask layer 260 may have a compressive stress.

[0024] In addition to the tensile stress of the spacer layer 310 reducing the effect of the mask layer 260 on the subsequent interconnect structure, the adhesion of the spacer layer 310 to other material layers in the multilayer stack 200 can also reduce the possibility of pattern distortion. For example, in an embodiment where the dielectric layer 250 includes a plasma enhanced oxide and the adhesion layer 240 includes tetraethoxysilane, the spacer layer 310 may include a nitride material so that the spacer layer 310 has high adhesion to the dielectric layer 250 and the adhesion layer 240. When the spacer layer 310 extends from the mask layer 260 to the substrate 100, the spacer layer 310 may physically contact the dielectric layer 250 and the adhesion layer 240, so that the spacer layer 310 can maintain the sidewalls of the mask layer 260 at a position flush with the sidewalls of the dielectric layer 250 and the sidewalls of the adhesion layer 240, thereby achieving the effect of anchoring the mask layer 260.

[0025] refer to Figure 4, an anti-reflection coating 320 is formed in the first trench 300, and a photoresist layer 330 is formed on the anti-reflection coating 320 to expose the anti-reflection coating 320. Specifically, the anti-reflection coating 320 fills the first trench 300 so that the anti-reflection coating 320 covers the spacer layer 310. The top surface of the anti-reflection coating 320 may be higher than the top surface of the mask layer 260 so that the anti-reflection coating 320 covers the top surface of the mask layer 260. Next, a photoresist layer 330 is formed on the top surface of the anti-reflection coating 320, and a patterning process is performed on the photoresist layer 330 to form an opening 330o in the photoresist layer 330 to expose a portion of the top surface of the anti-reflection coating 320. The opening 330o of the photoresist layer 330 can be used to define a via window (e.g., Figure 7 The pattern of the via window 410 shown in FIG. 4 is shown in FIG. 4 , so the opening 330o may have a width W2 in the X direction, wherein the width W2 is smaller than the spacing of the spacer layer 310 on the sidewall of the first trench 300 in the X direction (ie, Figure 5 Width W3 shown).

[0026] refer to Figure 5 , the very low dielectric layer 230 is etched to form a second trench 340 and a via window opening 350, wherein the via window opening 350 exposes the wire layer 110 in the substrate 100. Specifically, an etching process is performed on the anti-reflective coating 320 and the multilayer stack 200 through the opening 330o, so that the pattern of the opening 330o is transferred to the very low dielectric layer 230 to form the via window opening 350. The via window opening 350 may further extend through the adhesion layer 220 and the etch stop layer 210 below the very low dielectric layer 230, thereby exposing the wire layer 110 in the substrate 100. Since the pattern of the via window opening 350 comes from the opening 330o, the via window opening 350 may have a width W2 in the X direction.

[0027] During the etching process for forming the via window opening 350, the anti-reflective coating 320 and the very low dielectric layer 230 may also be etched along the sidewalls of the spacer layer 310 to form the first trench 300 again to expose the spacer layer 310, and to form the second trench 340 between the first trench 300 and the via window opening 350. In other words, the spacer layer 310 in the first trench 300 may define the pattern of the second trench 340. Since the pattern of the second trench 340 comes from the spacer layer 310, the second trench 340 may have a width W3 in the X direction that is the same as the spacing between the spacers 310, wherein the width W3 is less than the width W1 of the first trench 300 and greater than the width W2 of the via window opening 350.

[0028] During the process of etching the second trench 340 and the via opening 350, the spacer layer 310 can anchor the mask layer 260 to maintain the shape of the first trench 300, thereby significantly reducing the possibility of pattern distortion of the first trench 300, the second trench 340, or the via opening 350. In addition, the high adhesion of the spacer layer 310 to the mask layer 260, the dielectric layer 250, the adhesion layer 240, and the ultra-low dielectric layer 230 also helps to anchor the mask layer 260, thereby improving the structural stability of the first trench 300, the second trench 340, or the via opening 350. In the subsequent process, the second trench 340 and the via opening 350 can be used to form an interconnect structure, so the second trench 340 and the via opening 350 with high stability can improve the reliability of the subsequently formed interconnect structure.

[0029] In some embodiments, the etching process may be an anisotropic etching process, such as a dry etching process using plasma, and may include varying process parameters to form the second trench 340 and the dielectric window opening 350 during the etching process, such as using different etching gases to control the etching rate of the anti-reflective coating 320 and the very low dielectric layer 230, thereby forming the second trench 340 above the dielectric window opening 350 while extending the dielectric window opening 350.

[0030] In some embodiments, the etching process may slightly etch the substrate 100 and the conductive line layer 110 so that the bottom surface of the via window opening 350 is lower than the top surface of the substrate 100 to ensure that the via window opening 350 exposes the conductive line layer 110. In some embodiments, the etching process may also remove Figure 4 The anti-reflective coating 320 and the photoresist layer 330 are provided in the embodiment of the present invention.

[0031] refer to Figure 6 , the first trench 300, the second trench 340 and the via window opening 350 are filled with a conductive material 404, and the conductive material 404 can form a conductive path in the Z direction with the wire layer 110 and can cover the spacer layer 310. After filling the conductive material 404, the top surface of the conductive material 404 can be flush with the top surface of the mask layer 260. In some other embodiments, the conductive material 404 can further extend above the mask layer 260 to cover the top surface of the mask layer 260.

[0032] In some embodiments, the conductive material 404 may be formed by sputtering, electroplating, other suitable deposition processes, or combinations thereof, and the conductive material 404 may include copper metal, copper alloy, the like, or combinations thereof. The conductive material 404 may include a material that is the same or similar to the conductive material 114 to facilitate impedance matching between the conductive material 114 and the conductive material 404. In some embodiments, the conductive material 404 may be a single material or a combination of multiple layers of materials.

[0033] In some embodiments, before filling the conductive material 404, a barrier layer 402 may be deposited in the first trench 300, the second trench 340, and the via window opening 350, so that the barrier layer 402 covers the spacer layer 310, the sidewall and bottom surface of the second trench 340, and the sidewall and bottom surface of the via window opening 350, so as to physically separate the conductive material 404 from the multilayer stack 200 and prevent the conductive material 404 from diffusing into the multilayer stack 200. In some other embodiments, the barrier layer 402 may not be formed between the conductive material 404 and the wire layer 110, so that the conductive material 404 physically contacts the conductive material 114 of the wire layer 110.

[0034] refer to Figure 7 , remove the spacer layer 310 to form the interconnect structure 10. Figure 6 A planarization process is performed on the multilayer stack 200 to remove material layers above the bottom surface of the spacer layer 310, which material layers include the mask layer 260, the dielectric layer 250, the adhesion layer 240, the spacer layer 310, a portion of the ultra-low dielectric layer 230, the barrier layer 402 between the spacer layers 310, and the conductive material 404 between the spacer layers 310.

[0035] After the planarization process, the conductive material 404 filled in the via window opening 350 forms the via window 410 of the interconnect structure 10, and the conductive material 404 filled in the second trench 340 forms the wire layer 420 of the interconnect structure 10. The wire layer 420 is electrically connected to the wire layer 110 in the substrate 100 through the via window 410, thereby forming a conductive path in the Z direction. Since the spacer layer 310 is removed by the planarization process, there is no spacer layer 310 between the wire layer 420 and the ultra-low dielectric layer 230, thereby preventing the spacer layer 310 from affecting the electrical performance of the interconnect structure 10.

[0036] In some embodiments, the planarization process may remove the ultra-low dielectric layer 230, the barrier layer 402, and the conductive material 404 below the spacer layer 310, so that the thickness of the conductive line layer 420 in the Z direction is less than Figure 5 The depth of the second trench 340 is shown.

[0037] According to the above-mentioned embodiments of the present disclosure, the method for forming an interconnect structure of the present disclosure includes forming a groove in a multilayer stack for forming an interconnect structure, and forming a spacer layer on the sidewall of the groove to contact a mask layer of the multilayer stack. Since the spacer layer has tensile stress or has high adhesion with the multilayer stack, the spacer layer can anchor the mask layer and reduce the possibility of deformation of the groove. Therefore, the shape of the groove can be maintained during the process of the interconnect structure, so that the interconnect structure formed by the groove has high structural stability, thereby improving the reliability of the interconnect structure. In addition, the method for forming the interconnect structure includes removing the spacer layer from the interconnect structure, thereby avoiding affecting the electrical performance of the interconnect structure.

[0038]

Explanation of symbols

[0039] 10: Internal connection structure

[0040] 100:Substrate

[0041] 110: Wire layer

[0042] 112: Barrier layer

[0043] 114: Conductive material

[0044] 200:Multi-layer stacking

[0045] 210: Etching stop layer

[0046] 220: Adhesion layer

[0047] 230: Very low dielectric layer

[0048] 240: Adhesion layer

[0049] 250: Dielectric layer

[0050] 260: Mask layer

[0051] 300: First groove

[0052] 310: Spacer layer

[0053] 320: Anti-reflective coating

[0054] 330: Photoresist layer

[0055] 330°: Opening

[0056] 340: Second groove

[0057] 350:Interface window opening

[0058] 402: Barrier layer

[0059] 404: Conductive material

[0060] 410:Interlayer window

[0061] 420: Wire layer

[0062] D1,D2: distance

[0063] T1, T2: thickness

[0064] W1, W2, W3: Width

[0065] X,Z: direction.

Claims

1. A method for forming an inner connection structure, characterized in that: include: A multilayer stack is formed on a substrate including a conductive line layer, wherein the multilayer stack includes: A very low dielectric layer located above the conductive line layer; and a mask layer located above the very low dielectric layer; etching the multi-layer stack to form a trench, wherein the trench exposes the very low dielectric layer; forming a spacer layer on a sidewall of the trench, wherein the spacer layer physically contacts the mask layer; Etching the very low dielectric layer to form a via window opening, wherein the via window opening exposes the conductive line layer; filling the trench and the via opening with a conductive material; and A planarization process is performed on the multi-layer stack to remove the spacer layer. 2 . The method for forming an interconnect structure according to claim 1 , wherein after the spacer layer is formed on the sidewall of the trench, the spacer layer has a tensile stress ranging from 1 GPa to 1.7 GPa. 3 . The method for forming an interconnect structure according to claim 1 , wherein after the spacer layer is formed on the sidewall of the trench, the spacer layer completely covers the sidewall of the mask layer in the trench. 4 . The method for forming an interconnect structure according to claim 1 , wherein after the spacer layer is formed on the sidewall of the trench, the spacer layer extends from the mask layer to the bottom surface of the trench.

5. The method for forming an interconnect structure according to claim 1 , wherein the multi-layer stack further comprises: The dielectric layer is located between the very low dielectric layer and the mask layer, wherein the hardness of the dielectric layer is greater than the hardness of the very low dielectric layer.

6. A method for forming an inner connection structure, characterized in that: include: forming a very low dielectric layer over a substrate, wherein the substrate includes a conductive line layer; performing a first deposition process to form a first titanium nitride layer over the very low dielectric layer; performing a first etching process to form a first trench in the first titanium nitride layer and the ultra-low dielectric layer; performing a second deposition process to form a second titanium nitride layer on the sidewalls of the first trench; Performing a second etching process to form a via window opening in the very low dielectric layer, wherein the via window opening exposes the conductive line layer; Filling the first trench and the via opening with a conductive material; and The first titanium nitride layer and the second titanium nitride layer are removed. 7 . The method for forming an interconnect structure according to claim 6 , wherein a first growth direction of the first deposition process is different from a second growth direction of the second deposition process.

8. The method for forming an interconnect structure according to claim 6, wherein after performing the second deposition process, the first titanium nitride layer has a first thickness in a first direction perpendicular to the top surface of the very low dielectric layer, the second titanium nitride layer has a second thickness in a second direction parallel to the top surface of the very low dielectric layer, and the ratio of the first thickness to the second thickness is between 1.5 and 2.

5. 9 . The method for forming an interconnect structure as claimed in claim 6 , wherein after performing the second deposition process, a bottom surface of the second titanium nitride layer is lower than a bottom surface of the first titanium nitride layer.

10. The method for forming an interconnect structure according to claim 6, wherein performing the second etching process further comprises etching the very low dielectric layer along the sidewall of the second titanium nitride layer to form a second trench, and wherein filling the first trench and the via window opening with the conductive material comprises filling the second trench with the conductive material.

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