Photoelectric co-packaging structure based on reconstructed adapter plate

Abstract

The invention provides a photoelectric co-packaging structure based on a reconfiguration pinboard, the photoelectric co-packaging structure based on the reconfiguration pinboard comprises a plurality of photoelectric mixed core particles and the reconfiguration pinboard, the plurality of photoelectric mixed core particles are arranged on the reconfiguration pinboard, and the reconfiguration pinboard is used for realizing communication connection of the plurality of photoelectric mixed core particles; the photoelectric mixed core particle is integrated with a host chip, a photonic integrated chip and an electronic integrated chip; the reconstruction adapter plate comprises a silicon bridge and a first substrate, and the silicon bridge is embedded into the first substrate. According to the photoelectric co-packaging structure based on the reconstruction adapter plate, integration of a plurality of photoelectric mixed core particles is achieved, decoupling of calculation and transmission resources is achieved, and the computing power of high-performance calculation is expanded.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an optoelectronic co-packaging structure based on a reconstructed adapter plate. Background Art

[0002] Chip technology is a technology that uses advanced packaging methods to heterogeneously integrate chips with different processes / functions. The key to silicon photonics system integration is to form efficient and fast signal interconnection between silicon photonics chips and electrical chips.

[0003] Co-Packaged Optics (CPO) packages the optical engine (OE) and the host application-specific integrated circuit (ASIC) or the electronic integrated chip (EIC) with computing and other functions together. Usually, the OE module is distributed on the edge of the ASIC or EIC. However, with the continuous miniaturization of advanced processes, only a limited number of OE modules can be placed around the ASIC or EIC core particles with computing and other functions. The CPO structure lacks design flexibility, making it difficult to achieve the decoupling of computing and transmission resources and to expand the computing power of high-performance computing. Therefore, how to propose an optoelectronic co-packaging structure with good design flexibility, achieve the decoupling of computing and transmission resources, and expand the computing power of high-performance computing has become an important issue that needs to be urgently addressed in this field. Summary of the invention

[0004] In view of the problems in the prior art, an embodiment of the present invention provides an optoelectronic co-packaging structure based on a reconstructed adapter plate, which can at least partially solve the problems in the prior art.

[0005] The present invention proposes an optoelectronic co-packaging structure based on a reconstructed adapter plate, comprising a plurality of optoelectronic hybrid core particles and a reconstructed adapter plate, wherein:

[0006] A plurality of optoelectronic hybrid core particles are arranged on the reconfiguration adapter board, and the reconfiguration adapter board is used to realize the communication connection of the plurality of optoelectronic hybrid core particles; the optoelectronic hybrid core particles integrate a host chip, a photon integrated chip and an electronic integrated chip;

[0007] The reconstructed adapter plate includes a silicon bridge and a first substrate, wherein the silicon bridge is embedded in the first substrate.

[0008] Further, the multiple optoelectronic hybrid core particles include at least one of a first optoelectronic hybrid core particle, a second optoelectronic hybrid core particle, a third optoelectronic hybrid core particle, a fourth optoelectronic hybrid core particle, a fifth optoelectronic hybrid core particle and a sixth optoelectronic hybrid core particle; the first optoelectronic hybrid core particle, the second optoelectronic hybrid core particle, the third optoelectronic hybrid core particle, the fourth optoelectronic hybrid core particle, the fifth optoelectronic hybrid core particle and the sixth optoelectronic hybrid core particle have different structures and included integrated components.

[0009] Furthermore, the first optoelectronic hybrid core comprises a plurality of electronic integrated chips and an embedded PIC silicon bridge, the embedded PIC silicon bridge integrates a photonic integrated chip, and the plurality of electronic integrated chips are arranged on the embedded PIC silicon bridge.

[0010] Furthermore, the first optoelectronic hybrid core comprises a host chip, an electronic integrated chip and an embedded PIC silicon bridge, the embedded PIC silicon bridge integrates a photonic integrated chip, and the host chip and the electronic integrated chip are arranged on the embedded PIC silicon bridge.

[0011] Furthermore, the second optoelectronic hybrid core comprises a host chip, a photonic integrated chip and an embedded EIC silicon bridge, the embedded EIC silicon bridge integrates an electronic integrated chip, and the host chip and the photonic integrated chip are arranged on the embedded EIC silicon bridge.

[0012] Further, the third optoelectronic hybrid core comprises a host chip and an embedded monolithic optoelectronic integrated silicon bridge, the embedded monolithic optoelectronic integrated silicon bridge integrates a monolithic optoelectronic integrated chip, and the host chip is arranged on the embedded monolithic optoelectronic integrated silicon bridge.

[0013] Furthermore, the first optoelectronic hybrid core comprises a plurality of electronic integrated chips and a PIC adapter board, and the plurality of electronic integrated chips are arranged on the PIC adapter board.

[0014] Furthermore, the fourth optoelectronic hybrid core comprises a host chip, an electronic integrated chip and a PIC adapter board, and the host chip and the electronic integrated chip are arranged on the PIC adapter board.

[0015] Furthermore, the fifth optoelectronic hybrid core comprises a host chip, a photonic integrated chip and an EIC adapter board, and the host chip and the electronic integrated chip are arranged on the EIC adapter board.

[0016] Furthermore, the sixth optoelectronic hybrid core comprises a host chip and a monolithic optoelectronic integrated adapter board, and the host chip is arranged on the monolithic optoelectronic integrated adapter board.

[0017] Furthermore, the host chip includes a computing unit core and / or a storage unit core.

[0018] Furthermore, the optoelectronic hybrid core comprises a passive adapter board, and the passive adapter board is used to carry the computing unit core and / or the storage unit core.

[0019] Furthermore, passive components are integrated on the reconstruction adapter board.

[0020] Furthermore, the first substrate is a molded or glass transfer plate.

[0021] Furthermore, the optoelectronic co-packaging structure based on the reconstructed adapter plate provided in the embodiment of the present invention further includes a second substrate, and the reconstructed adapter plate is disposed on the second substrate.

[0022] The optoelectronic co-packaging structure based on a reconstructed adapter board provided in an embodiment of the present invention includes multiple optoelectronic hybrid core particles and a reconstructed adapter board, wherein the multiple optoelectronic hybrid core particles are arranged on the reconstructed adapter board, and the reconstructed adapter board is used to realize the communication connection of the multiple optoelectronic hybrid core particles; the reconstructed adapter board includes a silicon bridge and a first substrate, and the silicon bridge is embedded in the first substrate, thereby realizing the integration of multiple optoelectronic hybrid core particles, realizing the decoupling of computing and transmission resources, and expanding the computing power of high-performance computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0024] Figure 1 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the first embodiment of the present invention.

[0025] Figure 2 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in a second embodiment of the present invention.

[0026] Figure 3 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the third embodiment of the present invention.

[0027] Figure 4 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in a fourth embodiment of the present invention.

[0028] Figure 5 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the fifth embodiment of the present invention.

[0029] Figure 6It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in a sixth embodiment of the present invention.

[0030] Figure 7 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the seventh embodiment of the present invention.

[0031] Figure 8 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the eighth embodiment of the present invention.

[0032] Fig. 9 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the seventh embodiment of the present invention.

[0033] Fig.10 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the eighth embodiment of the present invention.

[0034] Fig.11 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the eleventh embodiment of the present invention.

[0035] Fig.12 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the twelfth embodiment of the present invention.

[0036] Fig.13 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the thirteenth embodiment of the present invention.

[0037] Fig.14 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the fourteenth embodiment of the present invention.

[0038] Fig.15 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the fifteenth embodiment of the present invention.

[0039] Fig.16 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the sixteenth embodiment of the present invention.

[0040] Fig.17 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the seventeenth embodiment of the present invention.

[0041] Fig.18 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the eighteenth embodiment of the present invention.

[0042] Fig.19 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the nineteenth embodiment of the present invention.

[0043] Fig. 20 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the twentieth embodiment of the present invention.

[0044] Fig.21 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the twenty-first embodiment of the present invention.

[0045] Fig. 22 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the twenty-second embodiment of the present invention.

[0046] Fig.23 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the twenty-third embodiment of the present invention.

[0047] Fig.24 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the twenty-fourth embodiment of the present invention.

[0048] Fig.25 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the twenty-fifth embodiment of the present invention.

[0049] Fig.26 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the twenty-sixth embodiment of the present invention.

[0050] Fig. 27 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the twenty-seventh embodiment of the present invention.

[0051] Fig.28 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the twenty-eighth embodiment of the present invention.

[0052] Fig.29 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the twenty-ninth embodiment of the present invention.

[0053] Fig.30 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the thirtieth embodiment of the present invention.

[0054] Fig.31 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the thirty-first embodiment of the present invention.

[0055] Fig.32 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the thirty-second embodiment of the present invention.

[0056] Fig.33 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the thirty-third embodiment of the present invention.

[0057] Fig.34 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the thirty-fourth embodiment of the present invention.

[0058] Fig.35 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the thirty-fifth embodiment of the present invention.

[0059] Fig.36 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the thirty-sixth embodiment of the present invention.

[0060] Fig.37 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the thirty-seventh embodiment of the present invention.

[0061] Fig.38 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the thirty-eighth embodiment of the present invention.

[0062] Fig.39 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the thirty-ninth embodiment of the present invention.

[0063] Fig.40 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the fortieth embodiment of the present invention.

[0064] Fig.41 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the forty-first embodiment of the present invention.

[0065] Fig.42 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the forty-second embodiment of the present invention.

[0066] Fig.43 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the forty-third embodiment of the present invention.

[0067] Fig.44 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the forty-fourth embodiment of the present invention.

[0068] Fig.45 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the forty-fifth embodiment of the present invention.

[0069] Fig.46It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the forty-sixth embodiment of the present invention.

[0070] Fig.47 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the forty-seventh embodiment of the present invention.

[0071] Fig.48 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the forty-eighth embodiment of the present invention.

[0072] Fig.49 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the forty-ninth embodiment of the present invention.

[0073] Fig.50 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the fiftieth embodiment of the present invention.

[0074] Fig.51 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the fifty-first embodiment of the present invention.

[0075] Fig.52 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the fifty-second embodiment of the present invention.

[0076] Fig.53 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the fifty-third embodiment of the present invention.

[0077] Fig.54 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the fifty-fourth embodiment of the present invention.

[0078] Fig.55 It is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the fifty-fifth embodiment of the present invention. DETAILED DESCRIPTION

[0079] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, in the absence of conflict, the embodiments in this application and the features in the embodiments can be combined arbitrarily with each other. The acquisition, storage, use, and processing of data in the technical scheme in this application all comply with the relevant provisions of laws and regulations.

[0080] In order to facilitate understanding of the technical solution provided by this application, the relevant contents of the technical solution of this application are first explained below.

[0081] The present application proposes an optoelectronic co-packaging structure based on a reconstructed adapter board, in which an active or passive silicon bridge is embedded in a substrate, or a reconstructed adapter board is prepared in a wiring layer and a glass adapter board to realize the integration of multiple optoelectronic hybrid core particles. The structure has good design flexibility, realizes the decoupling of computing and transmission resources, and expands the computing power of high-performance computing. Furthermore, an active adapter board or an active silicon bridge is used to realize the interconnection between the EIC core particles with functions such as ASIC or computing and the EIC, photonic integrated chip (Photonic Integrated Chip, PIC for short) or OE of the OE module, and the module is core-grained and integrated as an optoelectronic hybrid core particle unit. A dedicated Compute-Memory module is used to replace the ASIC, and integrated with an active adapter board or an active silicon bridge as a flexible and efficient way to miniaturize the system.

[0082] Figure 1 is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided by a first embodiment of the present invention, Figure 2 is a schematic structural diagram of an optoelectronic co-packaging structure based on a reconstructed adapter plate provided by a second embodiment of the present invention, such as Figure 1 and Figure 2 As shown, the optoelectronic co-packaging structure based on the reconstructed adapter provided by the embodiment of the present invention includes a plurality of optoelectronic hybrid core particles 1 and a reconstructed adapter plate 2, wherein:

[0083] A plurality of optoelectronic hybrid core particles 1 are arranged on the reconstruction adapter board 2, and the reconstruction adapter board 2 is used to realize the communication connection of the plurality of optoelectronic hybrid core particles 1; the optoelectronic hybrid core particles 1 integrate the host chip, the photonic integrated chip and the electronic integrated chip; the reconstruction adapter board 2 includes a silicon bridge 2-1 and a first substrate 2-2, and the silicon bridge 2-1 is embedded in the first substrate 2-2.

[0084] Specifically, the reconstruction adapter board 2 can be prepared by embedding an active silicon bridge or a passive silicon bridge into the first substrate. A plurality of optoelectronic hybrid core particles 1 are arranged on the reconstruction adapter board 2, and each optoelectronic hybrid core particle 1 can be integrated on the reconstruction adapter board 2 by hybrid bonding technology, or can be bonded on the reconstruction adapter board 2 by bump bonding. Each optoelectronic hybrid core particle 1 can communicate through the reconstruction adapter board 2, and the reconstruction adapter board 2 can realize the integration of multiple optoelectronic hybrid core particles 1. The optoelectronic hybrid core particle 1 integrates a host chip, a photonic integrated chip, and an electronic integrated chip. Among them, the bump bonding in this application includes solder bump bonding, micro bump bonding, etc., which are selected according to actual needs and are not limited in the embodiments of the present invention.

[0085] The reconstruction adapter board 2 includes a silicon bridge 2-1 and a first substrate 2-2, and the silicon bridge 2-1 is embedded in the first substrate 2-2. The silicon bridge 2-1 is used to realize the communication between each optoelectronic hybrid core particle 1, and the first substrate 2-2 is used to carry multiple optoelectronic hybrid core particles 1. The silicon bridge 2-1 can be an active silicon bridge or a passive silicon bridge, which is selected according to actual needs and is not limited in the embodiment of the present invention. Passive components (Integrated Passive Device, referred to as IPD) for improving the electrical performance of the system can be integrated in the reconstruction adapter board 2.

[0086] For example, Figure 1 As shown, a plurality of optoelectronic hybrid core particles 1 are arranged on the reconstruction adapter board 2, and each optoelectronic hybrid core particle 1 is bonded to the reconstruction adapter board 2 through a corresponding first bump 1-1. The reconstruction adapter board 2 includes a silicon bridge 2-1 and a first substrate 2-2, and the silicon bridge 2-1 is embedded in the first substrate 2-2. Each optoelectronic hybrid core particle 1 is connected to the communication through the corresponding first bump 1-1 and the silicon bridge 2-1.

[0087] For example, Figure 2 As shown, a plurality of optoelectronic hybrid core particles 1 are arranged on the reconstruction adapter board 2, and each optoelectronic hybrid core particle 1 is integrated on the reconstruction adapter board 2 by hybrid bonding technology. The reconstruction adapter board 2 includes a silicon bridge 2-1 and a first substrate 2-2, and the silicon bridge 2-1 is embedded in the first substrate 2-2. The optoelectronic hybrid core particles 1 are connected to each other by communication through the silicon bridge 2-1.

[0088] The optoelectronic co-packaging structure based on the reconstructed adapter provided by the embodiment of the present invention includes a plurality of optoelectronic hybrid core particles and a reconstructed adapter plate, wherein the plurality of optoelectronic hybrid core particles are arranged on the reconstructed adapter plate, and the reconstructed adapter plate is used to realize the communication connection of the plurality of optoelectronic hybrid core particles; the reconstructed adapter plate includes a silicon bridge and a first substrate, wherein the silicon bridge is embedded in the first substrate, realizing the integration of the plurality of optoelectronic hybrid core particles, realizing the decoupling of computing and transmission resources, and expanding the computing power of high-performance computing. The reconstructed adapter plate is conducive to realizing the large-area integration of optoelectronic hybrid core particles, ensuring the yield rate, and reducing the process cost.

[0089] like Figure 1 and Figure 2 As shown, based on the above embodiments, the reconfiguration adapter 2 further includes a rewiring layer 2-3, and the rewiring layer 2-3 is arranged on the surface of the reconfiguration adapter 2. Each optoelectronic hybrid core 1 can be electrically connected through the rewiring layer 2-3.

[0090] On the basis of the above embodiments, further, the plurality of optoelectronic hybrid core particles include at least one of a first optoelectronic hybrid core particle, a second optoelectronic hybrid core particle, a third optoelectronic hybrid core particle, a fourth optoelectronic hybrid core particle, a fifth optoelectronic hybrid core particle and a sixth optoelectronic hybrid core particle.

[0091] Specifically, the plurality of optoelectronic hybrid core particles may all be first optoelectronic hybrid core particles, second optoelectronic hybrid core particles, third optoelectronic hybrid core particles, fourth optoelectronic hybrid core particles, fifth optoelectronic hybrid core particles or sixth optoelectronic hybrid core particles.

[0092] The plurality of optoelectronic hybrid core particles may include any two, three, four or five of the first optoelectronic hybrid core particle, the second optoelectronic hybrid core particle, the third optoelectronic hybrid core particle, the fourth optoelectronic hybrid core particle, the fifth optoelectronic hybrid core particle and the sixth optoelectronic hybrid core particle.

[0093] The plurality of optoelectronic hybrid core particles may include a first optoelectronic hybrid core particle, a second optoelectronic hybrid core particle, a third optoelectronic hybrid core particle, a fourth optoelectronic hybrid core particle, a fifth optoelectronic hybrid core particle, and a sixth optoelectronic hybrid core particle.

[0094] The first optoelectronic hybrid core particle includes an embedded PIC silicon bridge, and a photonic integrated chip (PIC) can be embedded into a molded rewiring layer, a glass transfer board or a packaging substrate to obtain an embedded PIC silicon bridge. The embedded PIC silicon bridge integrates a host chip and an EIC chip, or the embedded PIC silicon bridge integrates multiple EIC chips.

[0095] The second optoelectronic hybrid core particle includes an embedded EIC silicon bridge, and the electronic integrated chip can be embedded in a molded rewiring layer, a glass transfer board or a packaging substrate to obtain an embedded EIC silicon bridge. The embedded EIC silicon bridge integrates a host chip and a PIC chip.

[0096] The third optoelectronic hybrid core particle embedded monolithic optoelectronic integrated silicon bridge can embed a monolithic optoelectronic integrated chip into a molded rewiring layer, a glass adapter plate or a packaging substrate to obtain an embedded monolithic optoelectronic integrated silicon bridge. As a type of optical engine (Optical Engine, referred to as OE), the monolithic optoelectronic integrated chip integrates components that realize the functions of electronic integrated chips and photonic integrated chips on a single chip. The embedded monolithic optoelectronic integrated silicon bridge integrates a host chip.

[0097] The fourth optoelectronic hybrid core comprises a PIC adapter board, which uses the PIC as an active adapter board to carry the host chip and the EIC.

[0098] The fifth optoelectronic hybrid core comprises an EIC adapter board, and the EIC is used as an active adapter board to carry the host chip and the PIC.

[0099] The sixth optoelectronic hybrid core comprises a monolithic optoelectronic integrated adapter board, which uses the monolithic optoelectronic integrated chip as an active adapter board to carry the host chip.

[0100] Embedded PIC silicon bridge, embedded EIC silicon bridge and embedded monolithic optoelectronic integrated silicon bridge are all active silicon bridges. PIC adapter board, EIC adapter board and monolithic optoelectronic integrated adapter board are all active adapter boards.

[0101] The optoelectronic hybrid core uses an active adapter board that integrates a photonic integrated chip, an electronic integrated chip or a monolithic optoelectronic integrated chip, shortening the communication distance between the host chip and the optical engine and improving the communication efficiency between the host chip and the OE. At the same time, the active adapter board included in the optoelectronic hybrid core is small in size, high in yield and good in performance.

[0102] Figure 3 is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided by a third embodiment of the present invention, Figure 4 is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter plate provided in a fourth embodiment of the present invention, such as Figure 3 and Figure 4 As shown, on the basis of the above embodiments, further, the first optoelectronic hybrid core particle 101 includes a host chip 101-1, an electronic integrated chip 101-2 and an embedded PIC silicon bridge 101-3, the embedded PIC silicon bridge 101-3 integrates a photonic integrated chip 101-4, and the host chip 101-1 and the electronic integrated chip 101-2 are arranged on the embedded PIC silicon bridge 101-3.

[0103] Specifically, the host chip 101-1 can be integrated on the embedded PIC silicon bridge 101-3 by hybrid bonding technology, or by bump bonding on the embedded PIC silicon bridge 101-3. The electronic integrated chip 101-2 can be integrated on the embedded PIC silicon bridge 101-3 by hybrid bonding technology, or by bump bonding on the embedded PIC silicon bridge 101-3. The embedded PIC silicon bridge 101-3 can be integrated on the reconstruction adapter board 2 by hybrid bonding technology, or by bump bonding on the reconstruction adapter board 2. The host chip 101-1 is electrically connected to the photon integrated chip 101-4, and the electronic integrated chip 101-2 is electrically connected to the photon integrated chip 101-4.

[0104] For example, Figure 3As shown, the host chip 101-1 is bonded to the embedded PIC silicon bridge 101-3 through the second bump 101-1-0, the electronic integrated chip 101-2 is bonded to the embedded PIC silicon bridge 101-3 through the third bump 101-2-1, the embedded PIC silicon bridge 101-3 is bonded to the reconstruction adapter 2 through the first bump 1-1, and the photon integrated chip 101-4 is embedded in the embedded PIC silicon bridge 101-3. The host chip 101-1 is electrically connected to the photon integrated chip 101-4 through the second bump 101-1-0, the electronic integrated chip 101-2 is electrically connected to the photon integrated chip 101-4 through the third bump 101-2-1, and the host chip 101-1 is electrically connected to the electronic integrated chip 101-2 through the second bump 101-1-0, the photon integrated chip 101-4 and the third bump 101-2-1.

[0105] For example, Figure 4 As shown, the host chip 101-1 is hybrid bonded on the embedded PIC silicon bridge 101-3, the electronic integrated chip 101-2 is hybrid bonded on the embedded PIC silicon bridge 101-3, the embedded PIC silicon bridge 101-3 is hybrid bonded on the reconstruction adapter 2, and the photon integrated chip 101-4 is embedded in the embedded PIC silicon bridge 101-3. The host chip 101-1 is electrically connected to the photon integrated chip 101-4, the electronic integrated chip 101-2 is electrically connected to the photon integrated chip 101-4, and the host chip 101-1 is electrically connected to the electronic integrated chip 101-2 through the photon integrated chip 101-4.

[0106] like Figure 3 and Figure 4 As shown, based on the above embodiments, the embedded PIC silicon bridge 101-3 further comprises a horizontal interconnection layer 101-3-1, which is arranged on the surface of the embedded PIC silicon bridge 101-3. The horizontal interconnection layer 101-3-1 comprises a redistribution layer and / or an optical waveguide.

[0107] For example, Figure 3 As shown, the host chip 101-1 is electrically connected to the photonic integrated chip 101-4 through the second bump 101-1-0 and the horizontal interconnection layer 101-3-1, the electronic integrated chip 101-2 is electrically connected to the photonic integrated chip 101-4 through the third bump 101-2-1 and the horizontal interconnection layer 101-3-1, and the host chip 101-1 is electrically connected to the electronic integrated chip 101-2 through the second bump 101-1-0, the horizontal interconnection layer 101-3-1 and the third bump 101-2-1.

[0108] For example, Figure 4As shown, the host chip 101-1 is electrically connected to the photonic integrated chip 101-4 through the horizontal interconnection layer 101-3-1, the electronic integrated chip 101-2 is electrically connected to the photonic integrated chip 101-4 through the horizontal interconnection layer 101-3-1, and the host chip 101-1 is electrically connected to the electronic integrated chip 101-2 through the horizontal interconnection layer 101-3-1.

[0109] like Figure 3 and Figure 4 As shown, based on the above embodiments, the embedded PIC silicon bridge 101-3 further includes a through silicon via 101-3-2. The through silicon via 101-3-2 is used to realize the electrical connection between the host chip 101-1 and other optoelectronic hybrid core particles, and the electrical connection between the electronic integrated chip 101-2 and other optoelectronic hybrid core particles.

[0110] Figure 5 is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided by a fifth embodiment of the present invention, Figure 6 is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter plate provided by a sixth embodiment of the present invention, such as Figure 5 and Figure 6 As shown, based on the above embodiments, the first optoelectronic hybrid core further includes multiple electronic integrated chips 101-2 and an embedded PIC silicon bridge 101-3, the embedded PIC silicon bridge 101-3 integrates a photonic integrated chip 101-4, and the multiple electronic integrated chips 101-2 are arranged on the embedded PIC silicon bridge 101-3.

[0111] Specifically, the electronic integrated chip 101-2 can be integrated on the embedded PIC silicon bridge 101-3 by hybrid bonding technology, or by bump bonding on the embedded PIC silicon bridge 101-3. The embedded PIC silicon bridge 101-3 can be integrated on the embedded PIC silicon bridge 101-3 by hybrid bonding technology, or by bump bonding on the reconfiguration adapter 2. Each electronic integrated chip 101-2 is electrically connected.

[0112] For example, Figure 5 As shown, each electronic integrated chip 101-2 is bonded to the embedded PIC silicon bridge 101-3 through the corresponding third bump 101-2-1, the embedded PIC silicon bridge 101-3 is bonded to the reconstruction adapter 2 through the first bump 1-1, and the photon integrated chip 101-4 is embedded in the embedded PIC silicon bridge 101-3. Each electronic integrated chip 101-2 is electrically connected to the photon integrated chip 101-4 through the corresponding third bump 101-2-1, and each electronic integrated chip 101-2 included in the first optoelectronic hybrid core is electrically connected to the photon integrated chip 101-4 through the corresponding third bump 101-2-1.

[0113] For example, Figure 6 As shown, each electronic integrated chip 101-2 is hybrid bonded on the embedded PIC silicon bridge 101-3, the embedded PIC silicon bridge 101-3 is hybrid bonded on the reconfigurable adapter 2, and the photon integrated chip 101-4 is embedded in the embedded PIC silicon bridge 101-3. Each electronic integrated chip 101-2 is electrically connected to the photon integrated chip 101-4, and each host chip 101-1 included in the first optoelectronic hybrid core is electrically connected through the photon integrated chip 101-4.

[0114] Figure 7 is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter plate provided by a seventh embodiment of the present invention, Figure 8 is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter plate provided in an eighth embodiment of the present invention, such as Figure 7 and Figure 8 As shown, on the basis of the above embodiments, further, the second optoelectronic hybrid core particle includes a host chip 102-1, a photonic integrated chip 102-2 and an embedded EIC silicon bridge 102-3, the embedded EIC silicon bridge 102-3 integrates an electronic integrated chip 102-4, and the host chip 102-1 and the photonic integrated chip 102-2 are arranged on the embedded EIC silicon bridge 102-3.

[0115] Specifically, the host chip 102-1 can be integrated on the embedded EIC silicon bridge 102-3 by hybrid bonding technology, or by bump bonding on the embedded EIC silicon bridge 102-3. The photonic integrated chip 102-2 can be integrated on the embedded EIC silicon bridge 102-3 by hybrid bonding technology, or by bump bonding on the embedded EIC silicon bridge 102-3. The embedded EIC silicon bridge 102-3 can be integrated on the reconfiguration adapter board 2 by hybrid bonding technology, or by bump bonding on the reconfiguration adapter board 2. The host chip 102-1 is electrically connected to the electronic integrated chip 102-4, and the photonic integrated chip 102-2 is electrically connected to the electronic integrated chip 102-4.

[0116] For example, Figure 7As shown, the host chip 102-1 is bonded to the embedded EIC silicon bridge 102-3 through the fourth bump 102-1-0, the photon integrated chip 102-2 is bonded to the embedded EIC silicon bridge 102-3 through the fifth bump 102-2-1, the embedded EIC silicon bridge 102-3 is bonded to the reconstruction adapter 2 through the first bump 1-1, and the electronic integrated chip 102-4 is embedded in the embedded EIC silicon bridge 102-3. The host chip 102-1 is electrically connected to the electronic integrated chip 102-4 through the fourth bump 102-1-0, the photon integrated chip 102-2 is electrically connected to the electronic integrated chip 102-4 through the fifth bump 102-2-1, and the host chip 101-1 is electrically connected to the photon integrated chip 102-2 through the fourth bump 102-1-0, the electronic integrated chip 102-4 and the fifth bump 102-2-1.

[0117] For example, Figure 8 As shown, the host chip 102-1 is hybrid bonded on the embedded EIC silicon bridge 102-3, the photonic integrated chip 102-2 is hybrid bonded on the embedded EIC silicon bridge 102-3, the embedded EIC silicon bridge 102-3 is hybrid bonded on the reconstruction adapter 2, and the electronic integrated chip 102-4 is embedded in the embedded EIC silicon bridge 102-3. The host chip 102-1 is electrically connected to the electronic integrated chip 102-4, the photonic integrated chip 102-2 is electrically connected to the electronic integrated chip 102-4, and the host chip 101-1 is electrically connected to the photonic integrated chip 102-2 through the electronic integrated chip 102-4.

[0118] like Figure 7 and Figure 8 As shown, based on the above embodiments, the embedded EIC silicon bridge 102-3 further includes a horizontal interconnection layer 102-3-1, which is arranged on the surface of the embedded EIC silicon bridge 102-3. The horizontal interconnection layer 102-3-1 includes a rewiring layer.

[0119] For example, Figure 7 As shown, the host chip 102-1 is electrically connected to the electronic integrated chip 102-4 through the fourth bump 102-1-0 and the horizontal interconnection layer 102-3-1, the photonic integrated chip 102-2 is electrically connected to the electronic integrated chip 102-4 through the fifth bump 102-2-1 and the horizontal interconnection layer 102-3-1, and the host chip 102-1 is electrically connected to the photonic integrated chip 102-2 through the fourth bump 102-1-0, the horizontal interconnection layer 102-3-1 and the fifth bump 102-2-1.

[0120] For example, Figure 8As shown, the host chip 102-1 is electrically connected to the electronic integrated chip 102-4 through the horizontal interconnection layer 102-3-1, the photonic integrated chip 102-2 is electrically connected to the electronic integrated chip 102-4 through the horizontal interconnection layer 102-3-1, and the host chip 102-1 is electrically connected to the photonic integrated chip 102-2 through the horizontal interconnection layer 102-3-1.

[0121] like Figure 7 and Figure 8 As shown, based on the above embodiments, the embedded EIC silicon bridge 102-3 further includes a through silicon via 102-3-2. The through silicon via 102-3-2 is used to realize the electrical connection between the host chip 102-1 and other optoelectronic hybrid core particles, and the electrical connection between the photonic integrated chip 102-2 and other optoelectronic hybrid core particles.

[0122] Fig. 9 is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter plate provided by a seventh embodiment of the present invention, Fig.10 is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter plate provided in an eighth embodiment of the present invention, such as Fig. 9 and Fig.10 As shown, based on the above embodiments, further, the third optoelectronic hybrid core comprises a host chip 103-1 and an embedded monolithic optoelectronic integrated silicon bridge 103-2, the embedded monolithic optoelectronic integrated silicon bridge 103-2 integrates a monolithic optoelectronic integrated chip 103-3, and the host chip 103-1 is arranged on the embedded monolithic optoelectronic integrated silicon bridge 103-2. The embedded monolithic optoelectronic integrated silicon bridge 103-2 may include a horizontal interconnect layer having a rewiring layer and an optical waveguide.

[0123] Specifically, the host chip 103-1 can be integrated on the embedded monolithic optoelectronic integrated silicon bridge 103-2 by hybrid bonding technology, or by bump bonding on the embedded monolithic optoelectronic integrated silicon bridge 103-2. The embedded monolithic optoelectronic integrated silicon bridge 103-2 can be integrated on the reconfiguration adapter 2 by hybrid bonding technology, or by bump bonding on the reconfiguration adapter 2. The host chip 103-1 is electrically connected to the monolithic optoelectronic integrated chip 103-3.

[0124] For example, Fig. 9 As shown, the host chip 103-1 is bonded to the embedded monolithic optoelectronic integrated silicon bridge 103-2 through the sixth bump 103-1-0, the embedded monolithic optoelectronic integrated silicon bridge 103-2 is bonded to the reconstructed adapter 2 through the first bump 1-1, and the monolithic optoelectronic integrated chip 103-3 is embedded in the embedded monolithic optoelectronic integrated silicon bridge 103-2. The host chip 103-1 is electrically connected to the monolithic optoelectronic integrated chip 103-3 through the sixth bump 103-1-0.

[0125] For example, Fig.10 As shown, the host chip 103-1 is hybrid bonded on the embedded monolithic optoelectronic integrated silicon bridge 103-2, the embedded monolithic optoelectronic integrated silicon bridge 103-2 is hybrid bonded on the reconfigurable adapter 2, and the monolithic optoelectronic integrated chip 103-3 is embedded in the embedded monolithic optoelectronic integrated silicon bridge 103-2. The host chip 103-1 is electrically connected to the monolithic optoelectronic integrated chip 103-3.

[0126] On the basis of the above embodiments, the embedded monolithic optoelectronic integrated silicon bridge 103-2 further comprises a through silicon via 103-2-1. The through silicon via 103-2-1 is used to realize the electrical connection between the host chip 103-1 and other optoelectronic hybrid core particles.

[0127] Fig.11 is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the eleventh embodiment of the present invention, Fig.12 is a schematic structural diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the twelfth embodiment of the present invention, such as Fig.11 and Fig.12 As shown, based on the above embodiments, the fourth optoelectronic hybrid chip 104 further includes a host chip 104-1, an electronic integrated chip 104-2 and a PIC adapter board 104-3, and the host chip 104-1 and the electronic integrated chip 104-2 are arranged on the PIC adapter board 104-3.

[0128] Specifically, the host chip 104-1 can be integrated on the PIC adapter board 104-3 by hybrid bonding technology, or by bump bonding on the PIC adapter board 104-3. The electronic integrated chip 104-2 can be integrated on the PIC adapter board 104-3 by hybrid bonding technology, or by bump bonding on the PIC adapter board 104-3. The PIC adapter board 104-3 can be integrated on the reconstruction adapter board 2 by hybrid bonding technology, or by bump bonding on the reconstruction adapter board 2. The PIC acts as an active adapter board and becomes the PIC adapter board 104-3. The host chip 104-1 is electrically connected to the PIC adapter board 104-3, and the electronic integrated chip 101-2 is electrically connected to the PIC adapter board 104-3.

[0129] For example, Fig.11As shown, the host chip 104-1 is bonded to the PIC adapter board 104-3 through the seventeenth bump 104-1-0, the electronic integrated chip 104-2 is bonded to the PIC adapter board 104-3 through the eighteenth bump 104-2-1, the PIC adapter board 104-3 is bonded to the reconstruction adapter board 2 through the first bump 1-1, and the PIC acts as an active adapter board, becoming the PIC adapter board 104-3. The host chip 104-1 is electrically connected to the PIC through the seventeenth bump 104-1-0, the electronic integrated chip 104-2 is electrically connected to the PIC through the eighteenth bump 104-2-1, and the host chip 104-1 is electrically connected to the electronic integrated chip 104-2 through the seventeenth bump 104-1-0, the PIC adapter board 104-3 and the eighteenth bump 104-2-1.

[0130] For example, Fig.12 As shown, the host chip 104-1 is hybrid bonded to the PIC adapter board 104-3, the electronic integrated chip 104-2 is hybrid bonded to the PIC adapter board 104-3, the PIC adapter board 104-3 is hybrid bonded to the reconfiguration adapter board 2, and the PIC acts as an active adapter board, becoming the PIC adapter board 104-3. The host chip 104-1 is electrically connected to the PIC, the electronic integrated chip 104-2 is electrically connected to the PIC, and the host chip 104-1 is electrically connected to the electronic integrated chip 104-2 through the PIC adapter board 104-3.

[0131] like Fig.11 and Fig.12 As shown, based on the above embodiments, the PIC adapter board 104-3 further includes a horizontal interconnection layer 104-3-1, and the horizontal interconnection layer 104-3-1 is arranged on the surface of the PIC adapter board 104-3.

[0132] Specifically, the PIC adapter board 104-3 includes a horizontal interconnection layer 104-3-1, which may be disposed on a surface of the PIC adapter board 104-3 close to the host chip 104-1. The horizontal interconnection layer 104-3-1 may include a rewiring layer and / or an optical waveguide.

[0133] For example, Fig.11As shown, the host chip 104-1 is bonded to the PIC adapter board 104-3 through the seventeenth bump 104-1-0, and the electronic integrated chip 104-2 is bonded to the PIC adapter board 104-3 through the eighteenth bump 104-2-1. The host chip 104-1 is electrically connected to the PIC through the seventeenth bump 104-1-0 and the horizontal interconnection layer 104-3-1. The electronic integrated chip 104-2 is electrically connected to the PIC through the eighteenth bump 104-2-1 and the horizontal interconnection layer 104-3-1. The host chip 104-1 can be electrically connected to the electronic integrated chip 104-2 through the horizontal interconnection layer 104-3-1.

[0134] For example, Fig.12 As shown, the host chip 104-1 is integrated on the PIC adapter board 104-3 through hybrid bonding technology, and the electronic integrated chip 104-2 is integrated on the PIC adapter board 104-3 through hybrid bonding technology. The host chip 104-1 is electrically connected to the PIC through a horizontal interconnection layer 104-3-1. The electronic integrated chip 104-2 is electrically connected to the PIC through a horizontal interconnection layer 104-3-1. The host chip 104-1 can be electrically connected to the electronic integrated chip 104-2 through a horizontal interconnection layer 104-3-1.

[0135] like Fig.11 and Fig.12 As shown, based on the above embodiments, a through silicon via 104-3-2 is further provided in the PIC adapter board 104-3. The through silicon via 104-3-2 is used to realize the electrical connection between the host chip 104-1 and other optoelectronic hybrid core particles, and the electrical connection between the electronic integrated chip 104-2 and other optoelectronic hybrid core particles.

[0136] Fig.13 is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided by a fifth embodiment of the present invention, Fig.14 is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter plate provided by a sixth embodiment of the present invention, such as Fig.13 and Fig.14 As shown, based on the above embodiments, the first optoelectronic hybrid core further comprises a plurality of electronic integrated chips 104 - 2 and a PIC adapter board 104 - 3 , and the plurality of electronic integrated chips 101 - 2 are arranged on the PIC adapter board 104 - 3 .

[0137] Specifically, the electronic integrated chip 104-2 can be integrated on the PIC adapter board 104-3 by hybrid bonding technology, or by bump bonding on the PIC adapter board 104-3. The PIC adapter board 104-3 can be integrated on the reconstruction adapter board 2 by hybrid bonding technology, or by bump bonding on the reconstruction adapter board 2. Each electronic integrated chip 104-2 is electrically connected.

[0138] For example, Fig.13 As shown, each electronic integrated chip 104-2 is bonded to the PIC adapter board 104-3 through the corresponding eighteenth bump 104-2-1, the PIC adapter board 104-3 is bonded to the reconstruction adapter board 2 through the first bump 1-1, and the PIC serves as the PIC adapter board 104-3. Each electronic integrated chip 104-2 is electrically connected to the PIC through the corresponding eighteenth bump 104-2-1, and each electronic integrated chip 104-2 included in the fourth optoelectronic hybrid core is electrically connected to the PIC adapter board 104-3 through the corresponding eighteenth bump 104-2-1.

[0139] For example, Fig.14 As shown, each electronic integrated chip 104-2 is hybrid bonded to the PIC adapter board 104-3, the PIC adapter board 104-3 is hybrid bonded to the reconfiguration adapter board 2, and the PIC serves as the PIC adapter board 104-3. Each electronic integrated chip 104-2 is electrically connected to the PIC, and the electronic integrated chips 104-2 included in the fourth optoelectronic hybrid core are electrically connected through the PIC adapter board 104-3. Fig.15 is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided by the thirteenth embodiment of the present invention, Fig.16 is a schematic structural diagram of an optoelectronic co-packaging structure based on a reconstructed adapter plate provided in a fourteenth embodiment of the present invention, such as Fig.15 and Fig.16 As shown, based on the above embodiments, further, the fifth optoelectronic hybrid core 105 includes a host chip 105-1, a photonic integrated chip 105-2 and an EIC adapter board 105-3, and the host chip 105-1 and the photonic integrated chip 105-2 are arranged on the EIC adapter board 105-3.

[0140] Specifically, the host chip 105-1 can be integrated on the EIC adapter board 105-3 by hybrid bonding technology, or by bump bonding on the EIC adapter board 105-3. The photon integrated chip 105-2 can be integrated on the EIC adapter board 105-3 by hybrid bonding technology, or by bump bonding on the EIC adapter board 105-3. The EIC adapter board 105-3 can be integrated on the reconstruction adapter board 2 by hybrid bonding technology, or by bump bonding on the reconstruction adapter board 2. The EIC acts as an active adapter board and becomes the EIC adapter board 105-3. The host chip 105-1 is electrically connected to the EIC adapter board 105-3, and the photon integrated chip 105-2 is electrically connected to the EIC adapter board 105-3.

[0141] For example, Fig.15As shown, the host chip 105-1 is bonded to the EIC adapter board 105-3 through the nineteenth bump 105-1-0, the photon integrated chip 105-2 is bonded to the EIC adapter board 105-3 through the twentieth bump 105-2-1, and the EIC adapter board 105-3 is bonded to the reconstruction adapter board 2 through the first bump 1-1. The EIC serves as the EIC adapter board 105-3. The host chip 105-1 is electrically connected to the EIC through the nineteenth bump 105-1-0, the photon integrated chip 105-2 is electrically connected to the EIC through the twentieth bump 105-2-1, and the host chip 105-1 is electrically connected to the photon integrated chip 105-2 through the nineteenth bump 105-1-0, the EIC adapter board 105-3 and the twentieth bump 105-2-1.

[0142] For example, Fig.16 As shown, the host chip 105-1 is hybrid bonded on the EIC adapter board 105-3, the photon integrated chip 105-2 is hybrid bonded on the EIC adapter board 105-3, and the EIC adapter board 105-3 is hybrid bonded on the reconstruction adapter board 2. The EIC serves as the EIC adapter board 105-3. The host chip 105-1 is electrically connected to the EIC, the photon integrated chip 105-2 is electrically connected to the EIC, and the host chip 105-1 is electrically connected to the photon integrated chip 105-2 through the EIC adapter board 105-3.

[0143] like Fig.15 and Fig.16 As shown, based on the above embodiments, the EIC adapter board 105-3 further includes a horizontal interconnection layer 105-3-1, which is arranged on the surface of the EIC adapter board 105-3. The horizontal interconnection layer 105-3-1 includes a rewiring layer.

[0144] Specifically, the EIC adapter board 105 - 3 includes a horizontal interconnection layer 105 - 3 - 1 , and the horizontal interconnection layer 105 - 3 - 1 may be disposed on a surface of the EIC adapter board 105 - 3 on a side close to the host chip 105 - 1 .

[0145] For example, Fig.15 As shown, the host chip 105-1 is bonded to the EIC adapter board 105-3 through the nineteenth bump 105-1-0, and the photon integrated chip 105-2 is bonded to the EIC adapter board 105-3 through the twentieth bump 105-2-1. The host chip 105-1 is electrically connected to the EIC through the nineteenth bump 105-1-0 and the horizontal interconnection layer 105-3-1. The photon integrated chip 105-2 is electrically connected to the EIC through the twentieth bump 105-2-1 and the horizontal interconnection layer 105-3-1. The host chip 105-1 can be electrically connected to the photon integrated chip 105-2 through the horizontal interconnection layer 105-3-1.

[0146] For example, Fig.16 As shown, the host chip 105-1 is hybrid bonded on the EIC adapter board 105-3, and the photon integrated chip 105-2 is hybrid bonded on the EIC adapter board 105-3. The host chip 105-1 is electrically connected to the EIC through the horizontal interconnection layer 105-3-1. The photon integrated chip 105-2 is electrically connected to the EIC through the horizontal interconnection layer 105-3-1. The host chip 105-1 can be electrically connected to the photon integrated chip 105-2 through the horizontal interconnection layer 105-3-1.

[0147] like Fig.15 and Fig.16 As shown, based on the above embodiments, a through silicon via 105-3-2 is further provided in the EIC adapter board 105-3. The through silicon via 105-3-2 is used to realize the electrical connection between the host chip 105-1 and other optoelectronic hybrid core particles, and the electrical connection between the photonic integrated chip 105-2 and other optoelectronic hybrid core particles.

[0148] Fig.17 is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the seventeenth embodiment of the present invention, Fig.18 is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the eighteenth embodiment of the present invention, such as Fig.17 and Fig.18 As shown, based on the above embodiments, the sixth optoelectronic hybrid core 106 further includes a host chip 106-1 and a monolithic optoelectronic integrated adapter 106-2, wherein the host chip 106-1 is disposed on the monolithic optoelectronic integrated adapter 106-2. The monolithic optoelectronic integrated adapter 106-2 may include a horizontal interconnect layer having a rewiring layer and an optical waveguide.

[0149] Specifically, the host chip 106-1 can be integrated on the monolithic optoelectronic integrated adapter board 106-2 by hybrid bonding technology, or by bump bonding on the monolithic optoelectronic integrated adapter board 106-2. The monolithic optoelectronic integrated adapter board 106-2 can be integrated on the reconstructed adapter board 2 by hybrid bonding technology, or by bump bonding on the reconstructed adapter board 2. The host chip 106-1 is electrically connected to the monolithic optoelectronic integrated chip 103-3.

[0150] For example, Fig.17 As shown, the host chip 106-1 is bonded to the monolithic optoelectronic integrated adapter board 106-2 through the twenty-first bump 106-1-0, the monolithic optoelectronic integrated adapter board 106-2 is bonded to the reconstructed adapter board 2 through the first bump 1-1, and the monolithic optoelectronic integrated chip serves as the monolithic optoelectronic integrated adapter board 106-2. The host chip 106-1 is electrically connected to the monolithic optoelectronic integrated chip through the twenty-first bump 106-1-0.

[0151] For example, Fig.18 As shown, the host chip 106-1 is hybrid bonded on the monolithic optoelectronic integrated adapter 106-2, the monolithic optoelectronic integrated adapter 106-2 is hybrid bonded on the reconstructed adapter 2, and the monolithic optoelectronic integrated chip serves as the monolithic optoelectronic integrated adapter 106-2. The host chip 106-1 is electrically connected to the monolithic optoelectronic integrated chip.

[0152] On the basis of the above embodiments, further, the monolithic optoelectronic integrated adapter board 106-2 includes a through silicon via 106-2-1. The through silicon via 106-2-1 is used to realize the electrical connection between the host chip 106-1 and other optoelectronic hybrid core particles. On the basis of the above embodiments, further, the host chip includes a computing unit core particle and / or a storage unit core particle. The host chip may include a computing unit core particle and a storage unit core particle. The host chip may only include a computing unit core particle. Alternatively, the host chip may only include a storage unit core particle.

[0153] For the first optoelectronic hybrid chip, the computing unit chip and / or the storage unit chip included in the host chip can be bonded to the embedded PIC silicon bridge respectively, or integrated on the embedded PIC silicon bridge after three-dimensional stacking.

[0154] For the second optoelectronic hybrid core, the computing unit core and / or storage unit core included in the host chip can be bonded to the embedded EIC silicon bridge respectively, or integrated on the embedded EIC silicon bridge after three-dimensional stacking.

[0155] For the third optoelectronic hybrid chip, the computing unit chip and / or the storage unit chip included in the host chip can be bonded to the embedded monolithic optoelectronic integrated silicon bridge respectively, or integrated on the embedded monolithic optoelectronic integrated silicon bridge after three-dimensional stacking.

[0156] For the fourth optoelectronic hybrid core particle, the computing unit core particle and / or the storage unit core particle included in the host chip can be bonded to the PIC adapter board respectively, or integrated on the PIC adapter board after three-dimensional stacking.

[0157] For the fifth optoelectronic hybrid chip, the computing unit chip and / or the storage unit chip included in the host chip can be bonded to the EIC adapter board respectively, or integrated on the EIC adapter board after three-dimensional stacking.

[0158] For the sixth optoelectronic hybrid core particle, the computing unit core particle and / or the storage unit core particle included in the host chip can be bonded to a monolithic optoelectronic integrated adapter board respectively, or integrated on a monolithic optoelectronic integrated adapter board after three-dimensional stacking.

[0159] For example, Fig.19As shown, the host chip 101-1 includes a computing unit core particle 101-1-1 and a storage unit core particle 101-1-2. The computing unit core particle 101-1-1 is bonded to the embedded PIC silicon bridge 101-3 through the seventh bump 101-1-1-1, the storage unit core particle 101-1-2 is bonded to the embedded PIC silicon bridge 101-3 through the eighth bump 101-1-2-1, the electronic integrated chip 101-2 is bonded to the embedded PIC silicon bridge 101-3 through the third bump 101-2-1, the embedded PIC silicon bridge 101-3 is bonded to the reconstruction adapter 2 through the first bump 1-1, and the photonic integrated chip 101-4 is embedded in the embedded PIC silicon bridge 101-3. The computing unit core particle 101-1-1 is electrically connected to the photon integrated chip 101-4 through the seventh bump 101-1-1-1, the storage unit core particle 101-1-2 is electrically connected to the photon integrated chip 101-4 through the eighth bump 101-1-2-1, and the electronic integrated chip 101-2 is electrically connected to the photon integrated chip 101-4 through the third bump 101-2-1. The computing unit core particle 101-1-1 is electrically connected to the storage unit core particle 101-1-2 through the seventh bump 101-1-1-1, the photon integrated chip 101-4 and the eighth bump 101-1-2-1.

[0160] For example, Fig. 20 As shown, the host chip 102-1 includes a computing unit core particle 102-1-1 and a storage unit core particle 102-1-2. The computing unit core particle 102-1-1 is bonded to the embedded EIC silicon bridge 102-3 through the ninth bump 102-1-1-1, the storage unit core particle 102-1-2 is bonded to the embedded EIC silicon bridge 102-3 through the tenth bump 102-1-2-1, the photonic integrated chip 102-2 is bonded to the embedded EIC silicon bridge 102-3 through the fifth bump 102-2-1, the embedded EIC silicon bridge 102-3 is bonded to the reconstruction adapter 2 through the first bump 1-1, and the electronic integrated chip 102-4 is embedded in the embedded EIC silicon bridge 102-3. The computing unit core particle 102-1-1 is electrically connected to the electronic integrated chip 102-4 through the ninth bump 102-1-1-1, the storage unit core particle 102-1-2 is electrically connected to the electronic integrated chip 102-4 through the tenth bump 102-1-2-1, and the photon integrated chip 102-2 is electrically connected to the electronic integrated chip 102-4 through the fifth bump 102-2-1. The computing unit core particle 102-1-1 is electrically connected to the storage unit core particle 102-1-2 through the ninth bump 102-1-1-1, the electronic integrated chip 102-4 and the tenth bump 102-1-2-1.

[0161] For example, Fig.21As shown, the host chip 103-1 includes a computing unit core particle 103-1-1 and a storage unit core particle 103-1-2. The computing unit core particle 103-1-1 is bonded to the embedded monolithic optoelectronic integrated silicon bridge 103-2 through the eleventh bump 103-1-1-1, the storage unit core particle 103-1-2 is bonded to the embedded monolithic optoelectronic integrated silicon bridge 103-2 through the twelfth bump 103-1-2-1, the embedded monolithic optoelectronic integrated silicon bridge 103-2 is bonded to the reconstruction adapter 2 through the first bump 1-1, and the monolithic optoelectronic integrated chip 103-3 is embedded in the embedded monolithic optoelectronic integrated silicon bridge 103-2. The computing unit core particle 103-1-1 is electrically connected to the monolithic optoelectronic integrated chip 103-3 through the eleventh bump 103-1-1-1. The storage unit chip 103-1-2 is electrically connected to the monolithic optoelectronic integrated chip 103-3 through the twelfth bump 103-1-2-1. The computing unit chip 103-1-1 can be electrically connected to the storage unit chip 103-1-2 through the eleventh bump 103-1-1-1, the monolithic optoelectronic integrated chip 103-3, and the twelfth bump 103-1-2-1.

[0162] For example, Fig. 22 As shown, the host chip 101-1 includes a computing unit core particle 101-1-1 and a storage unit core particle 101-1-2. The computing unit core particle 101-1-1 is hybrid bonded on the embedded PIC silicon bridge 101-3, the storage unit core particle 101-1-2 is hybrid bonded on the embedded PIC silicon bridge 101-3, the electronic integrated chip 101-2 is hybrid bonded on the embedded PIC silicon bridge 101-3, the embedded PIC silicon bridge 101-3 is hybrid bonded on the reconstruction adapter 2, and the photon integrated chip 101-4 is embedded in the embedded PIC silicon bridge 101-3. The computing unit core particle 101-1-1 is electrically connected to the photon integrated chip 101-4, the storage unit core particle 101-1-2 is electrically connected to the photon integrated chip 101-4, and the electronic integrated chip 101-2 is electrically connected to the photon integrated chip 101-4. The computing unit core 101 - 1 - 1 is electrically connected to the storage unit core 101 - 1 - 2 via the photonic integrated chip 101 - 4 .

[0163] For example, Fig.23As shown, the host chip 102-1 includes a computing unit core particle 102-1-1 and a storage unit core particle 102-1-2. The computing unit core particle 102-1-1 is hybrid bonded on the embedded EIC silicon bridge 102-3, the storage unit core particle 102-1-2 is hybrid bonded on the embedded EIC silicon bridge 102-3, the photon integrated chip 102-2 is hybrid bonded on the embedded EIC silicon bridge 102-3, the embedded EIC silicon bridge 102-3 is hybrid bonded on the reconstruction adapter 2, and the electronic integrated chip 102-4 is embedded in the embedded EIC silicon bridge 102-3. The computing unit core particle 102-1-1 is electrically connected to the electronic integrated chip 102-4, the storage unit core particle 102-1-2 is electrically connected to the electronic integrated chip 102-4, and the photon integrated chip 102-2 is electrically connected to the electronic integrated chip 102-4. The computing unit core 102-1-1 is electrically connected to the storage unit core 102-1-2 via the electronic integrated chip 102-4.

[0164] For example, Fig.24 As shown, the host chip 103-1 includes a computing unit core particle 103-1-1 and a storage unit core particle 103-1-2. The computing unit core particle 103-1-1 is hybrid bonded on the embedded monolithic optoelectronic integrated silicon bridge 103-2, the storage unit core particle 103-1-2 is hybrid bonded on the embedded monolithic optoelectronic integrated silicon bridge 103-2, the embedded monolithic optoelectronic integrated silicon bridge 103-2 is hybrid bonded on the reconstruction adapter 2, and the monolithic optoelectronic integrated chip 103-3 is embedded in the embedded monolithic optoelectronic integrated silicon bridge 103-2. The computing unit core particle 103-1-1 is electrically connected to the monolithic optoelectronic integrated chip 103-3. The storage unit core particle 103-1-2 is electrically connected to the monolithic optoelectronic integrated chip 103-3. The computing unit core particle 103-1-1 can be connected to the storage unit core particle 103-1-2 through the monolithic optoelectronic integrated chip 103-3 and the twelfth bump 103-1-2-1.

[0165] For example, Fig.25 As shown, the host chip 101-1 includes a computing unit core particle 101-1-1 and a storage unit core particle 101-1-2. The storage unit core particle 101-1-2 is bonded to the computing unit core particle 101-1-1 through the eighth bump 101-1-2-1, the computing unit core particle 101-1-1 is bonded to the embedded PIC silicon bridge 101-3 through the seventh bump 101-1-1-1, the embedded PIC silicon bridge 101-3 is bonded to the reconstruction adapter board 2 through the first bump 1-1, and the photon integrated chip 101-4 is embedded in the embedded PIC silicon bridge 101-3. The computing unit core particle 101-1-1 is electrically connected to the storage unit core particle 101-1-2 through the eighth bump 101-1-2-1, and the computing unit core particle 101-1-1 is electrically connected to the photon integrated chip 101-4 through the seventh bump 101-1-1-1.

[0166] For example, Fig.26 As shown, the host chip 102-1 includes a computing unit core particle 102-1-1 and a storage unit core particle 102-1-2. The storage unit core particle 102-1-2 is bonded to the computing unit core particle 102-1-1 through the tenth bump 102-1-2-1, the computing unit core particle 102-1-1 is bonded to the embedded EIC silicon bridge 102-3 through the ninth bump 102-1-1-1, the embedded EIC silicon bridge 102-3 is bonded to the reconstruction adapter 2 through the first bump 1-1, and the electronic integrated chip 102-4 is embedded in the embedded EIC silicon bridge 102-3. The computing unit core particle 102-1-1 is electrically connected to the storage unit core particle 102-1-2 through the tenth bump 102-1-2-1, and the computing unit core particle 102-1-1 is electrically connected to the electronic integrated chip 102-4 through the ninth bump 102-1-1-1.

[0167] For example, Fig. 27 As shown, the host chip 103-1 includes a computing unit core particle 103-1-1 and a storage unit core particle 103-1-2. The storage unit core particle 103-1-2 is bonded to the computing unit core particle 103-1-1 through the twelfth bump 103-1-2-1, the computing unit core particle 103-1-1 is bonded to the embedded monolithic optoelectronic integrated silicon bridge 103-2 through the eleventh bump 103-1-1-1, the embedded monolithic optoelectronic integrated silicon bridge 103-2 is bonded to the reconstruction adapter 2 through the first bump 1-1, and the monolithic optoelectronic integrated chip 103-3 is embedded in the embedded monolithic optoelectronic integrated silicon bridge 103-2. The computing unit chip 103-1-1 is electrically connected to the storage unit chip 103-1-2 through the twelfth bump 103-1-2-1, and the computing unit chip 103-1-1 is electrically connected to the monolithic optoelectronic integrated chip 103-3 through the eleventh bump 103-1-1-1.

[0168] For example, Fig.28As shown, the host chip 104-1 includes a computing unit core 104-1-1 and a storage unit core 104-1-2. The computing unit core 104-1-1 is bonded to the PIC adapter board 104-3 through the twenty-second bump 104-1-1-1, the storage unit core 104-1-2 is bonded to the PIC adapter board 104-3 through the twenty-third bump 104-1-2-1, the electronic integrated chip 104-2 is bonded to the PIC adapter board 104-3 through the eighteenth bump 104-2-1, and the PIC adapter board 104-3 is bonded to the reconstruction adapter board 2 through the first bump 1-1. The computing unit core 104-1-1 is electrically connected to the PIC adapter board 104-3 via the twenty-second bump 104-1-1-1, the storage unit core 104-1-2 is electrically connected to the PIC adapter board 104-3 via the twenty-third bump 104-1-2-1, and the electronic integrated chip 104-2 is electrically connected to the PIC adapter board 104-3 via the eighteenth bump 104-2-1. The computing unit core 104-1-1 is electrically connected to the storage unit core 104-1-2 via the twenty-second bump 104-1-1-1, the PIC adapter board 104-3, and the twenty-third bump 104-1-2-1.

[0169] For example, Fig.29 As shown, the host chip 105-1 includes a computing unit core 105-1-1 and a storage unit core 105-1-2. The computing unit core 105-1-1 is bonded to the EIC adapter board 105-3 through the twenty-fourth bump 105-1-1-1, the storage unit core 105-1-2 is bonded to the EIC adapter board 105-3 through the twenty-fifth bump 105-1-2-1, the photon integrated chip 105-2 is bonded to the EIC adapter board 105-3 through the twentieth bump 105-2-1, and the EIC adapter board 105-3 is bonded to the reconstruction adapter board 2 through the first bump 1-1. The computing unit core grain 102-1-1 is electrically connected to the EIC adapter board 105-3 through the ninth bump 102-1-1-1, the storage unit core grain 102-1-2 is electrically connected to the EIC adapter board 105-3 through the twenty-fourth bump 105-1-1-1, and the photon integrated chip 105-2 is electrically connected to the EIC adapter board 105-3 through the twentieth bump 105-2-1. The computing unit core grain 105-1-1 is electrically connected to the storage unit core grain 105-1-2 through the twenty-fourth bump 105-1-1-1, the EIC adapter board 105-3 and the twenty-fifth bump 105-1-2-1.

[0170] For example, Fig.30As shown, the host chip 106-1 includes a computing unit core particle 106-1-1 and a storage unit core particle 106-1-2. The computing unit core particle 106-1-1 is bonded to the monolithic optoelectronic integrated adapter board 106-2 through the twenty-sixth bump 106-1-1-1, the storage unit core particle 106-1-2 is bonded to the monolithic optoelectronic integrated adapter board 106-2 through the twenty-seventh bump 106-1-2-1, the monolithic optoelectronic integrated adapter board 106-2 is bonded to the reconstruction adapter board 2 through the first bump 1-1, and the monolithic optoelectronic integrated chip serves as the monolithic optoelectronic integrated adapter board 106-2. The computing unit core particle 106-1-1 is electrically connected to the monolithic optoelectronic integrated chip through the twenty-sixth bump 106-1-1-1. The storage unit core particle 106-1-2 is electrically connected to the monolithic optoelectronic integrated chip through the twenty-seventh bump 106-1-2-1. The computing unit chip 106-1-1 can be electrically connected to the storage unit chip 106-1-2 through the twenty-sixth bump 106-1-1-1, the monolithic optoelectronic integrated adapter 106-2, and the twenty-seventh bump 106-1-2-1.

[0171] For example, Fig.31 As shown, the host chip 104-1 includes a computing unit core particle 104-1-1 and a storage unit core particle 104-1-2. The computing unit core particle 104-1-1 is hybrid bonded to the PIC adapter board 104-3, the storage unit core particle 104-1-2 is hybrid bonded to the PIC adapter board 104-3, the electronic integrated chip 104-2 is hybrid bonded to the PIC adapter board 104-3, and the PIC adapter board 104-3 is hybrid bonded to the reconstruction adapter board 2. The computing unit core particle 104-1-1 is electrically connected to the PIC adapter board 104-3, the storage unit core particle 104-1-2 is electrically connected to the PIC adapter board 104-3, and the electronic integrated chip 104-2 is electrically connected to the PIC adapter board 104-3. The computing unit core particle 104-1-1 is electrically connected to the storage unit core particle 104-1-2 through the PIC adapter board 104-3.

[0172] For example, Fig.32As shown, the host chip 105-1 includes a computing unit core particle 105-1-1 and a storage unit core particle 105-1-2. The computing unit core particle 105-1-1 is hybrid bonded on the EIC adapter board 105-3, the storage unit core particle 105-1-2 is hybrid bonded on the EIC adapter board 105-3, the photon integrated chip 105-2 is hybrid bonded on the EIC adapter board 105-3, and the EIC adapter board 105-3 is hybrid bonded on the reconstruction adapter board 2. The computing unit core particle 102-1-1 is electrically connected to the EIC adapter board 105-3, the storage unit core particle 102-1-2 is electrically connected to the EIC adapter board 105-3, and the photon integrated chip 105-2 is electrically connected to the EIC adapter board 105-3. The computing unit chip 105 - 1 - 1 is electrically connected to the storage unit chip 105 - 1 - 2 via the EIC adapter board 105 - 3 .

[0173] For example, Fig.33 As shown, the host chip 106-1 includes a computing unit core particle 106-1-1 and a storage unit core particle 106-1-2. The computing unit core particle 106-1-1 is hybrid bonded on the monolithic optoelectronic integrated adapter board 106-2, the storage unit core particle 106-1-2 is hybrid bonded on the monolithic optoelectronic integrated adapter board 106-2, the monolithic optoelectronic integrated adapter board 106-2 is hybrid bonded on the reconstruction adapter board 2, and the monolithic optoelectronic integrated chip serves as the monolithic optoelectronic integrated adapter board 106-2. The computing unit core particle 106-1-1 is electrically connected to the monolithic optoelectronic integrated chip. The storage unit core particle 106-1-2 is electrically connected to the monolithic optoelectronic integrated chip. The computing unit core particle 106-1-1 can be electrically connected to the storage unit core particle 106-1-2 through the monolithic optoelectronic integrated adapter board 106-2.

[0174] For example, Fig.34 As shown, the host chip 104-1 includes a computing unit core particle 104-1-1 and a storage unit core particle 104-1-2. The storage unit core particle 104-1-2 is bonded to the computing unit core particle 104-1-1 through the twenty-third bump 104-1-2-1, the computing unit core particle 104-1-1 is bonded to the PIC adapter board 104-3 through the twenty-second bump 104-1-2-1, the PIC adapter board 104-3 is bonded to the reconstruction adapter board 2 through the first bump 1-1, and the photon integrated chip serves as the PIC adapter board 104-3. The computing unit core particle 104-1-1 is electrically connected to the storage unit core particle 104-1-2 through the twenty-third bump 104-1-2-1, and the computing unit core particle 104-1-1 is electrically connected to the photon integrated chip through the twenty-second bump 104-1-2-1.

[0175] For example, Fig.35As shown, the host chip 105-1 includes a computing unit core particle 105-1-1 and a storage unit core particle 105-1-2. The storage unit core particle 105-1-2 is bonded to the computing unit core particle 105-1-1 through the twenty-fifth bump 105-1-2-1, the computing unit core particle 105-1-1 is bonded to the EIC adapter board 105-3 through the twenty-fourth bump 105-1-1-1, the EIC adapter board 105-3 is bonded to the reconstruction adapter board 2 through the first bump 1-1, and the electronic integrated chip serves as the EIC adapter board 105-3. The computing unit core particle 105-1-1 is electrically connected to the storage unit core particle 105-1-2 through the twenty-fifth bump 105-1-2-1, and the computing unit core particle 105-1-1 is electrically connected to the electronic integrated chip through the twenty-fourth bump 105-1-1-1.

[0176] For example, Fig.36 As shown, the host chip 106-1 includes a computing unit core particle 106-1-1 and a storage unit core particle 106-1-2. The storage unit core particle 106-1-2 is bonded to the computing unit core particle 106-1-1 through the twenty-seventh bump 106-1-2-1, the computing unit core particle 106-1-1 is bonded to the monolithic optoelectronic integrated adapter board 106-2 through the twenty-sixth bump 106-1-1-1, the monolithic optoelectronic integrated adapter board 106-2 is bonded to the reconstruction adapter board 2 through the first bump 1-1, and the monolithic optoelectronic integrated chip is used as the monolithic optoelectronic integrated adapter board 106-2. The computing unit core particle 106-1-1 is electrically connected to the storage unit core particle 106-1-2 through the twenty-seventh bump 106-1-2-1, and the computing unit core particle 106-1-1 is electrically connected to the monolithic optoelectronic integrated chip through the twenty-sixth bump 106-1-1-1.

[0177] On the basis of the above embodiments, further, the optoelectronic hybrid core 1 includes a passive adapter board, and the passive adapter board is used to carry the computing unit core and / or the storage unit core.

[0178] Specifically, the computing unit core particles and / or storage unit core particles included in the host chip can be bonded to the passive adapter board respectively, or integrated on the passive adapter board after three-dimensional stacking, and the passive adapter board is bonded to the active adapter board included in the optoelectronic hybrid core particle 1, and the active adapter board is an embedded PIC silicon bridge, an embedded EIC silicon bridge, or an embedded monolithic optoelectronic integrated silicon bridge. The passive adapter board can be bonded to the active adapter board through bumps or hybrid bonded to the active adapter board. The passive adapter board may include a rewiring layer, and the rewiring layer is arranged on the surface of the passive adapter board. The passive adapter board may include silicon through vias, and the computing unit core particles and / or storage unit core particles carried on the passive adapter board can be electrically connected to the photonic integrated chip, electronic integrated chip, or embedded monolithic optoelectronic integrated silicon bridge integrated in the active adapter board through the silicon through vias.

[0179] If the host chip includes a computing unit core grain and a storage unit core grain, the computing unit core grain and the storage unit core grain can be bonded to the passive adapter board through their corresponding bumps, the computing unit core grain and the storage unit core grain can be mixed bonded to the passive adapter board, or the computing unit core grain and the storage unit core grain can be three-dimensionally stacked and integrated on the passive adapter board. If the host chip includes multiple computing unit core grains, each computing unit core grain can be bonded to the passive adapter board through its corresponding bumps, each computing unit core grain can be mixed bonded to the passive adapter board, or multiple computing unit core grains can be three-dimensionally stacked and integrated on the passive adapter board. If the host chip includes multiple storage unit core grains, each computing unit core grain can be bonded to the passive adapter board through its corresponding bumps, each storage unit core grain can be mixed bonded to the passive adapter board, or multiple storage unit core grains can be three-dimensionally stacked and integrated on the passive adapter board.

[0180] For example, for the first optoelectronic hybrid core, the computing unit core and / or storage unit core included in the host chip can be bonded to the passive adapter board separately, or integrated on the passive adapter board after three-dimensional stacking, and the passive adapter board is bonded to the embedded PIC silicon bridge. For the second optoelectronic hybrid core, the computing unit core and / or storage unit core included in the host chip can be bonded to the passive adapter board separately, or integrated on the passive adapter board after three-dimensional stacking, and the passive adapter board is bonded to the embedded EIC silicon bridge. For the third optoelectronic hybrid core, the computing unit core and / or storage unit core included in the host chip can be bonded to the passive adapter board separately, or integrated on the passive adapter board after three-dimensional stacking, and the passive adapter board is bonded to the embedded monolithic optoelectronic integrated silicon bridge. For the fourth optoelectronic hybrid core, the computing unit core and / or storage unit core included in the host chip can be bonded to the passive adapter board separately, or integrated on the passive adapter board after three-dimensional stacking, and the passive adapter board is bonded to the PIC adapter board. For the fifth optoelectronic hybrid core, the computing unit core and / or storage unit core included in the host chip can be bonded to the passive adapter board separately, or integrated on the passive adapter board after three-dimensional stacking, and the passive adapter board is bonded to the EIC adapter board. For the sixth optoelectronic hybrid core, the computing unit core and / or storage unit core included in the host chip can be bonded to the passive adapter board separately, or integrated on the passive adapter board after three-dimensional stacking, and the passive adapter board is bonded to the monolithic optoelectronic integrated adapter board.

[0181] For example, Fig.37As shown, the host chip 101-1 includes a computing unit core 101-1-1 and a storage unit core 101-1-2. The computing unit core 101-1-1 is bonded to the passive adapter 101-5 through the seventh bump 101-1-1-1, the storage unit core 101-1-2 is bonded to the passive adapter 101-5 through the eighth bump 101-1-2-1, the passive adapter 101-5 is bonded to the embedded PIC silicon bridge 101-3 through the thirteenth bump 101-5-3, the electronic integrated chip 101-2 is bonded to the embedded PIC silicon bridge 101-3 through the third bump 101-2-1, the embedded PIC silicon bridge 101-3 is bonded to the reconstruction adapter 2 through the first bump 1-1, and the photonic integrated chip 101-4 is embedded in the embedded PIC silicon bridge 101-3. The passive adapter board 101-5 includes a redistribution layer 101-5-1, which is arranged on the surface of the passive adapter board 101-5, and a through silicon via 101-5-2 is arranged in the passive adapter board 101-5. The computing unit core grain 101-1-1 is electrically connected to the photon integrated chip 101-4 through the seventh bump 101-1-1-1, the redistribution layer 101-5-1, and the through silicon via 101-5-2, the storage unit core grain 101-1-2 is electrically connected to the photon integrated chip 101-4 through the eighth bump 101-1-2-1, the redistribution layer 101-5-1, and the through silicon via 101-5-2, and the electronic integrated chip 101-2 is electrically connected to the photon integrated chip 101-4 through the third bump 101-2-1. The computing unit chip 101-1-1 is electrically connected to the memory unit chip 101-1-2 through the seventh bump 101-1-1-1, the redistribution layer 101-5-1 and the eighth bump 101-1-2-1.

[0182] For example, Fig.38As shown, the host chip 102-1 includes a computing unit core 102-1-1 and a storage unit core 102-1-2. The computing unit core 102-1-1 is bonded to the passive adapter 102-5 through the ninth bump 102-1-1-1, the storage unit core 102-1-2 is bonded to the passive adapter 102-5 through the tenth bump 102-1-2-1, the passive adapter 102-5 is bonded to the embedded EIC silicon bridge 102-3 through the fourteenth bump 102-5-3, the photonic integrated chip 102-2 is bonded to the embedded EIC silicon bridge 102-3 through the fifth bump 102-2-1, the embedded EIC silicon bridge 102-3 is bonded to the reconstruction adapter 2 through the first bump 1-1, and the electronic integrated chip 102-4 is embedded in the embedded EIC silicon bridge 102-3. The passive adapter board 102-5 includes a redistribution layer 102-5-1, which is disposed on the surface of the passive adapter board 102-5, and a through silicon via 102-5-2 is disposed in the passive adapter board 102-5. The computing unit core grain 102-1-1 is electrically connected to the electronic integrated chip 102-4 through the ninth bump 102-1-1-1, the redistribution layer 102-5-1, and the through silicon via 102-5-2, the storage unit core grain 102-1-2 is electrically connected to the electronic integrated chip 102-4 through the tenth bump 102-1-2-1, the redistribution layer 102-5-1, and the through silicon via 102-5-2, and the photonic integrated chip 102-2 is electrically connected to the electronic integrated chip 102-4 through the fifth bump 102-2-1. The computing unit chip 102-1-1 is electrically connected to the memory unit chip 102-1-2 through the ninth bump 102-1-1-1, the redistribution layer 102-5-1 and the tenth bump 102-1-2-1.

[0183] For example, Fig.39As shown, the host chip 103-1 includes a computing unit core particle 103-1-1 and a storage unit core particle 103-1-2. The computing unit core particle 103-1-1 is bonded to the passive adapter board 103-4 through the eleventh bump 103-1-1-1, the storage unit core particle 103-1-2 is bonded to the passive adapter board 103-4 through the twelfth bump 103-1-2-1, the passive adapter board 103-4 is bonded to the embedded monolithic optoelectronic integrated silicon bridge 103-2 through the fifteenth bump 103-4-3, the embedded monolithic optoelectronic integrated silicon bridge 103-2 is bonded to the reconstruction adapter board 2 through the first bump 1-1, and the monolithic optoelectronic integrated chip 103-3 is embedded in the embedded monolithic optoelectronic integrated silicon bridge 103-2. The passive adapter board 103-4 includes a redistribution layer 103-4-1, the redistribution layer 104-4-1 is arranged on the surface of the passive adapter board 103-4, and a through silicon via 103-4-2 is arranged in the passive adapter board 103-4. The computing unit core grain 103-1-1 is electrically connected to the monolithic optoelectronic integrated chip 103-3 through the eleventh bump 103-1-1-1, the redistribution layer 104-4-1, and the through silicon via 103-4-2. The storage unit core grain 103-1-2 is electrically connected to the monolithic optoelectronic integrated chip 103-3 through the twelfth bump 103-1-2-1, the redistribution layer 104-4-1, and the through silicon via 103-4-2. The computing unit chip 103-1-1 may pass through the eleventh bump 103-1-1-1, the redistribution layer 104-4-1, the twelfth bump 103-1-2-1 and the memory unit chip 103-1-2.

[0184] For example, Fig.40As shown, the host chip 101-1 includes a computing unit core particle 101-1-1 and a storage unit core particle 101-1-2. The computing unit core particle 101-1-1 is hybrid bonded on the passive adapter board 101-5, the storage unit core particle 101-1-2 is hybrid bonded on the passive adapter board 101-5, the passive adapter board 101-5 is hybrid bonded on the embedded PIC silicon bridge 101-3, the electronic integrated chip 101-2 is hybrid bonded on the embedded PIC silicon bridge 101-3, the embedded PIC silicon bridge 101-3 is hybrid bonded on the reconstruction adapter board 2, and the photonic integrated chip 101-4 is embedded in the embedded PIC silicon bridge 101-3. The passive adapter board 101-5 includes a redistribution layer 101-5-1, which is disposed on the surface of the passive adapter board 101-5, and a through silicon via 101-5-2 is disposed in the passive adapter board 101-5. The computing unit core grain 101-1-1 is electrically connected to the photon integrated chip 101-4 through the redistribution layer 101-5-1 and the through silicon via 101-5-2, the storage unit core grain 101-1-2 is electrically connected to the photon integrated chip 101-4 through the redistribution layer 101-5-1 and the through silicon via 101-5-2, and the electronic integrated chip 101-2 is electrically connected to the photon integrated chip 101-4. The computing unit core grain 101-1-1 is electrically connected to the storage unit core grain 101-1-2 through the redistribution layer 101-5-1.

[0185] For example, Fig.41 As shown, the host chip 102-1 includes a computing unit core 102-1-1 and a storage unit core 102-1-2. The computing unit core 102-1-1 is hybrid bonded on the passive adapter 102-5, the storage unit core 102-1-2 is hybrid bonded on the passive adapter 102-5, the passive adapter 102-5 is hybrid bonded on the embedded EIC silicon bridge 102-3, the photonic integrated chip 102-2 is hybrid bonded on the embedded EIC silicon bridge 102-3, the embedded EIC silicon bridge 102-3 is hybrid bonded on the reconstruction adapter 2, and the electronic integrated chip 102-4 is embedded in the embedded EIC silicon bridge 102-3. The passive adapter board 102-5 includes a redistribution layer 102-5-1, which is disposed on the surface of the passive adapter board 102-5, and a through silicon via 102-5-2 is disposed in the passive adapter board 102-5. The computing unit core grain 102-1-1 is electrically connected to the electronic integrated chip 102-4 through the redistribution layer 102-5-1 and the through silicon via 102-5-2, the storage unit core grain 102-1-2 is electrically connected to the electronic integrated chip 102-4 through the redistribution layer 102-5-1 and the through silicon via 102-5-2, and the photonic integrated chip 102-2 is electrically connected to the electronic integrated chip 102-4. The computing unit core grain 102-1-1 is electrically connected to the storage unit core grain 102-1-2 through the redistribution layer 102-5-1.

[0186] For example, Fig.42 As shown, the host chip 103-1 includes a computing unit core particle 103-1-1 and a storage unit core particle 103-1-2. The computing unit core particle 103-1-1 is hybrid bonded on the passive adapter 103-4, the storage unit core particle 103-1-2 is hybrid bonded on the passive adapter 103-4, the passive adapter 103-4 is hybrid bonded on the embedded monolithic optoelectronic integrated silicon bridge 103-2, the embedded monolithic optoelectronic integrated silicon bridge 103-2 is hybrid bonded on the reconstructed adapter 2, and the monolithic optoelectronic integrated chip 103-3 is embedded in the embedded monolithic optoelectronic integrated silicon bridge 103-2. The passive adapter 103-4 includes a redistribution layer 103-4-1, the redistribution layer 104-4-1 is arranged on the surface of the passive adapter 103-4, and a through silicon via 103-4-2 is arranged in the passive adapter 103-4. The computing unit core particle 103-1-1 is electrically connected to the monolithic optoelectronic integrated chip 103-3 through the redistribution layer 104-4-1 and the silicon through via 103-4-2. The storage unit core particle 103-1-2 is electrically connected to the monolithic optoelectronic integrated chip 103-3 through the redistribution layer 104-4-1 and the silicon through via 103-4-2. The computing unit core particle 103-1-1 can be connected to the storage unit core particle 103-1-2 through the redistribution layer 104-4-1.

[0187] For example, Fig.43 As shown, the host chip 101-1 includes a computing unit core 101-1-1 and a storage unit core 101-1-2. The storage unit core 101-1-2 is bonded to the computing unit core 101-1-1 through the eighth bump 101-1-2-1, the computing unit core 101-1-1 is bonded to the passive adapter 101-5 through the seventh bump 101-1-1-1, the passive adapter 101-5 is bonded to the embedded PIC silicon bridge 101-3 through the thirteenth bump 101-5-3, the embedded PIC silicon bridge 101-3 is bonded to the reconstruction adapter 2 through the first bump 1-1, and the photonic integrated chip 101-4 is embedded in the embedded PIC silicon bridge 101-3. The passive adapter board 101-5 includes a redistribution layer 101-5-1, which is arranged on the surface of the passive adapter board 101-5, and a through silicon via 101-5-2 is arranged in the passive adapter board 101-5. The computing unit core grain 101-1-1 is electrically connected to the storage unit core grain 101-1-2 through the eighth bump 101-1-2-1, and the computing unit core grain 101-1-1 is electrically connected to the photon integrated chip 101-4 through the seventh bump 101-1-1-1, the redistribution layer 101-5-1, the through silicon via 101-5-2 and the thirteenth bump 101-5-3.

[0188] For example, Fig.44As shown, the host chip 102-1 includes a computing unit core 102-1-1 and a storage unit core 102-1-2. The storage unit core 102-1-2 is bonded to the computing unit core 102-1-1 through the tenth bump 102-1-2-1, the computing unit core 102-1-1 is bonded to the passive adapter 102-5 through the ninth bump 102-1-1-1, the passive adapter 102-5 is bonded to the embedded EIC silicon bridge 102-3 through the fourteenth bump 102-5-3, the embedded EIC silicon bridge 102-3 is bonded to the reconstruction adapter 2 through the first bump 1-1, and the electronic integrated chip 102-4 is embedded in the embedded EIC silicon bridge 102-3. The passive adapter 102-5 includes a redistribution layer 102-5-1, which is disposed on the surface of the passive adapter 102-5, and a through silicon via 102-5-2 is disposed in the passive adapter 102-5. The computing unit core grain 102-1-1 is electrically connected to the storage unit core grain 102-1-2 through the tenth bump 102-1-2-1, and the computing unit core grain 102-1-1 is electrically connected to the electronic integrated chip 102-4 through the ninth bump 102-1-1-1, the redistribution layer 102-5-1, the through silicon via 102-5-2 and the fourteenth bump 102-5-3.

[0189] For example, Fig.45 As shown, the host chip 103-1 includes a computing unit core particle 103-1-1 and a storage unit core particle 103-1-2. The storage unit core particle 103-1-2 is bonded to the computing unit core particle 103-1-1 through the twelfth bump 103-1-2-1, the computing unit core particle 103-1-1 is bonded to the passive adapter board 103-4 through the twelfth bump 103-1-1-1, the passive adapter board 103-4 is bump-bonded to the embedded monolithic optoelectronic integrated silicon bridge 103-2 through the fifteenth bump 103-4-3, the embedded monolithic optoelectronic integrated silicon bridge 103-2 is bonded to the reconstruction adapter board 2 through the first bump 1-1, and the monolithic optoelectronic integrated chip 103-3 is embedded in the embedded monolithic optoelectronic integrated silicon bridge 103-2. The passive adapter board 103-4 includes a redistribution layer 103-4-1, which is disposed on the surface of the passive adapter board 103-4, and a through silicon via 103-4-2 is disposed in the passive adapter board 103-4. The computing unit core grain 103-1-1 is electrically connected to the storage unit core grain 103-1-2 through the twelfth bump 103-1-2-1, and the computing unit core grain 103-1-1 is electrically connected to the monolithic optoelectronic integrated chip 103-3 through the eleventh bump 103-1-1-1, the redistribution layer 103-4-1, the through silicon via 103-4-2 and the fifteenth bump 103-4-3.

[0190] For example, Fig.46As shown, the host chip 104-1 includes a computing unit core 104-1-1 and a storage unit core 104-1-2. The computing unit core 104-1-1 is bonded to the passive adapter board 104-4 through the twenty-second bump 104-1-1-1, the storage unit core 104-1-2 is bonded to the passive adapter board 104-4 through the twenty-third bump 104-1-2-1, the passive adapter board 104-4 is bonded to the PIC adapter board 104-3 through the thirteenth bump 104-5-3, the electronic integrated chip 104-2 is bonded to the PIC adapter board 104-3 through the eighteenth bump 104-2-1, the PIC adapter board 104-3 is bonded to the reconstruction adapter board 2 through the first bump 1-1, and the photon integrated chip serves as the PIC adapter board 104-3. The passive adapter board 104-4 includes a redistribution layer 104-4-1, which is disposed on the surface of the passive adapter board 104-4, and a through silicon via 104-4-2 is disposed in the passive adapter board 104-4. The computing unit core grain 104-1-1 is electrically connected to the photon integrated chip through the twenty-second bump 104-1-1-1, the redistribution layer 104-4-1, and the through silicon via 104-4-2, the storage unit core grain 104-1-2 is electrically connected to the photon integrated chip through the twenty-third bump 104-1-2-1, the redistribution layer 104-4-1, and the through silicon via 104-4-2, and the electronic integrated chip 104-2 is electrically connected to the photon integrated chip through the eighteenth bump 104-2-1. The computing unit chip 104-1-1 is electrically connected to the memory unit chip 104-1-2 through the twenty-second bump 104-1-1-1, the redistribution layer 104-4-1 and the twenty-third bump 104-1-2-1.

[0191] For example, Fig.47As shown, the host chip 105-1 includes a computing unit core 105-1-1 and a storage unit core 105-1-2. The computing unit core 105-1-1 is bonded to the passive adapter board 105-4 through the twenty-fourth bump 105-1-1-1, the storage unit core 105-1-2 is bonded to the passive adapter board 105-4 through the twenty-fifth bump 105-1-2-1, the passive adapter board 105-4 is bonded to the EIC adapter board 105-3 through the fourteenth bump 105-4-3, the photon integrated chip 105-2 is bonded to the EIC adapter board 105-3 through the twentieth bump 105-2-1, the EIC adapter board 105-3 is bonded to the reconstruction adapter board 2 through the first bump 1-1, and the electronic integrated chip serves as the EIC adapter board. The passive adapter board 105-4 includes a redistribution layer 105-4-1, which is disposed on the surface of the passive adapter board 105-4, and a through silicon via 105-4-2 is disposed in the passive adapter board 105-4. The computing unit core grain 105-1-1 is electrically connected to the electronic integrated chip through the twenty-fourth bump 105-1-1-1, the redistribution layer 105-4-1, the through silicon via 105-4-2, and the fourteenth bump 105-4-3, and the storage unit core grain 105-1-2 is electrically connected to the electronic integrated chip through the twenty-fifth bump 105-1-2-1, the redistribution layer 105-4-1, the through silicon via 105-4-2, and the fourteenth bump 105-4-3. The computing unit chip 105-1-1 is electrically connected to the memory unit chip 105-1-2 through the twenty-fourth bump 105-1-1-1, the redistribution layer 105-4-1 and the twenty-fifth bump 105-1-2-1.

[0192] For example, Fig.48As shown, the host chip 106-1 includes a computing unit core particle 106-1-1 and a storage unit core particle 106-1-2. The computing unit core particle 106-1-1 is bonded to the passive adapter board 106-3 through the twenty-sixth bump 106-1-1-1, the storage unit core particle 106-1-2 is bonded to the passive adapter board 106-3 through the twenty-seventh bump 106-1-2-1, the passive adapter board 106-3 is bonded to the monolithic optoelectronic integrated adapter board 106-2 through the fifteenth bump 106-3-3, the monolithic optoelectronic integrated adapter board 106-2 is bonded to the reconstruction adapter board 2 through the first bump 1-1, and the monolithic optoelectronic integrated chip serves as the monolithic optoelectronic integrated adapter board 106-2. The passive adapter board 106-3 includes a redistribution layer 106-3-1, which is disposed on the surface of the passive adapter board 106-3, and a through silicon via 106-3-2 is disposed in the passive adapter board 106-3. The computing unit core grain 106-1-1 is electrically connected to the monolithic optoelectronic integrated chip through the twenty-sixth bump 106-1-1-1, the redistribution layer 106-3-1, and the through silicon via 106-3-2. The storage unit core grain 106-1-2 is electrically connected to the monolithic optoelectronic integrated chip through the twenty-seventh bump 106-1-2-1, the redistribution layer 106-3-1, and the through silicon via 106-3-2. The computing unit chip 106-1-1 may pass through the twenty-sixth bump 106-1-1-1, the redistribution layer 106-3-1, the twenty-seventh bump 106-1-2-1 and the memory unit chip 106-1-2.

[0193] For example, Fig.49As shown, the host chip 104-1 includes a computing unit core 104-1-1 and a storage unit core 104-1-2. The computing unit core 104-1-1 is hybrid bonded on the passive adapter 104-4, the storage unit core 104-1-2 is hybrid bonded on the passive adapter 104-4, the passive adapter 104-4 is hybrid bonded on the PIC adapter 104-3, the electronic integrated chip 104-2 is hybrid bonded on the PIC adapter 104-3, the PIC adapter 104-3 is hybrid bonded on the reconstruction adapter 2, and the photonic integrated chip serves as the PIC adapter 104-3. The passive adapter 104-4 includes a redistribution layer 104-4-1, the redistribution layer 104-4-1 is arranged on the surface of the passive adapter 104-4, and a through silicon via 104-4-2 is arranged in the passive adapter 104-4. The computing unit core particle 104-1-1 is electrically connected to the photon integrated chip through the redistribution layer 104-4-1 and the silicon through via 104-4-2, the storage unit core particle 104-1-2 is electrically connected to the photon integrated chip through the redistribution layer 104-4-1 and the silicon through via 104-4-2, and the electronic integrated chip 104-2 is electrically connected to the photon integrated chip. The computing unit core particle 104-1-1 is electrically connected to the storage unit core particle 104-1-2 through the redistribution layer 104-4-1.

[0194] For example, Fig.50 As shown, the host chip 105-1 includes a computing unit core 105-1-1 and a storage unit core 105-1-2. The computing unit core 105-1-1 is hybrid bonded on the passive adapter 105-4, the storage unit core 105-1-2 is hybrid bonded on the passive adapter 105-4, the passive adapter 105-4 is hybrid bonded on the EIC adapter 105-3, the photonic integrated chip 105-2 is hybrid bonded on the EIC adapter 105-3, the EIC adapter 105-3 is hybrid bonded on the reconstruction adapter 2, and the electronic integrated chip serves as the EIC adapter. The passive adapter 105-4 includes a redistribution layer 105-4-1, the redistribution layer 105-4-1 is arranged on the surface of the passive adapter 105-4, and a through silicon via 105-4-2 is arranged in the passive adapter 105-4. The computing unit core particle 105-1-1 is electrically connected to the electronic integrated chip through the redistribution layer 105-4-1 and the silicon through via 105-4-2, the storage unit core particle 105-1-2 is electrically connected to the electronic integrated chip through the redistribution layer 105-4-1 and the silicon through via 105-4-2, and the photonic integrated chip 105-2 is electrically connected to the electronic integrated chip. The computing unit core particle 105-1-1 is electrically connected to the storage unit core particle 105-1-2 through the redistribution layer 105-4-1.

[0195] For example, Fig.51As shown, the host chip 106-1 includes a computing unit core particle 106-1-1 and a storage unit core particle 106-1-2. The computing unit core particle 106-1-1 is hybrid bonded on the passive adapter 106-3, the storage unit core particle 106-1-2 is hybrid bonded on the passive adapter 106-3, the passive adapter 106-3 is hybrid bonded on the monolithic optoelectronic integrated adapter 106-2, the monolithic optoelectronic integrated adapter 106-2 is hybrid bonded on the reconstructed adapter 2, and the monolithic optoelectronic integrated chip serves as the monolithic optoelectronic integrated adapter 106-2. The passive adapter 106-3 includes a redistribution layer 106-3-1, the redistribution layer 106-3-1 is arranged on the surface of the passive adapter 106-3, and a through silicon via 106-3-2 is arranged in the passive adapter 106-3. The computing unit core particle 106-1-1 is electrically connected to the monolithic optoelectronic integrated chip through the redistribution layer 106-3-1 and the silicon through via 106-3-2. The storage unit core particle 106-1-2 is electrically connected to the monolithic optoelectronic integrated chip through the redistribution layer 106-3-1 and the silicon through via 106-3-2. The computing unit core particle 106-1-1 can be connected to the storage unit core particle 106-1-2 through the redistribution layer 106-3-1.

[0196] For example, Fig.52 As shown, the host chip 104-1 includes a computing unit core 104-1-1 and a storage unit core 104-1-2. The storage unit core 104-1-2 is bonded to the computing unit core 104-1-1 through the twenty-third bump 104-1-2-1, the computing unit core 104-1-1 is bonded to the passive adapter board 104-4 through the twenty-second bump 104-1-1-1, the passive adapter board 104-4 is bonded to the PIC adapter board 104-3 through the thirteenth bump 104-4-3, the PIC adapter board 104-3 is bonded to the reconstruction adapter board 2 through the first bump 1-1, and the photonic integrated chip serves as the PIC adapter board 104-3. The passive adapter board 104-4 includes a redistribution layer 104-4-1, which is disposed on the surface of the passive adapter board 104-4, and a through silicon via 104-4-2 is disposed in the passive adapter board 104-4. The computing unit core grain 104-1-1 is electrically connected to the storage unit core grain 104-1-2 through the twenty-third bump 104-1-2-1, and the computing unit core grain 104-1-1 is electrically connected to the photon integrated chip through the twenty-second bump 104-1-1-1, the redistribution layer 104-4-1, the through silicon via 104-4-2 and the thirteenth bump 104-4-3.

[0197] For example, Fig.53As shown, the host chip 105-1 includes a computing unit core 105-1-1 and a storage unit core 105-1-2. The storage unit core 105-1-2 is bonded to the computing unit core 105-1-1 through the twenty-fifth bump 105-1-2-1, the computing unit core 105-1-1 is bonded to the passive adapter 105-4 through the twenty-fourth bump 105-1-1-1, the passive adapter 105-4 is bonded to the EIC adapter 105-3 through the fourteenth bump 105-4-3, the EIC adapter 105-3 is bonded to the reconstruction adapter 2 through the first bump 1-1, and the electronic integrated chip serves as the EIC adapter 105-3. The passive adapter 105-4 includes a redistribution layer 105-4-1, which is disposed on the surface of the passive adapter 105-4, and a through silicon via 105-4-2 is disposed in the passive adapter 105-4. The computing unit core grain 105-1-1 is electrically connected to the storage unit core grain 105-1-2 through the twenty-fifth bump 105-1-2-1, and the computing unit core grain 105-1-1 is electrically connected to the electronic integrated chip through the twenty-fourth bump 105-1-1-1, the redistribution layer 105-4-1, the through silicon via 105-4-2 and the fourteenth bump 105-4-3.

[0198] For example, Fig.54 As shown, the host chip 106-1 includes a computing unit core particle 106-1-1 and a storage unit core particle 106-1-2. The storage unit core particle 106-1-2 is bonded to the computing unit core particle 106-1-1 through the twenty-seventh bump 106-1-2-1, the computing unit core particle 106-1-1 is bonded to the passive adapter board 106-3 through the twenty-sixth bump 106-1-1-1, the passive adapter board 106-3 is bump-bonded to the monolithic optoelectronic integrated adapter board 106-2 through the fifteenth bump 106-3-3, the monolithic optoelectronic integrated adapter board 106-2 is bonded to the reconstruction adapter board 2 through the first bump 1-1, and the monolithic optoelectronic integrated chip serves as the monolithic optoelectronic integrated adapter board 106-2. The passive adapter board 106-3 includes a redistribution layer 106-3-1, which is disposed on the surface of the passive adapter board 106-3, and a through silicon via 106-3-2 is disposed in the passive adapter board 106-3. The computing unit core grain 106-1-1 is electrically connected to the storage unit core grain 106-1-2 through the twenty-seventh bump 106-1-2-1, and the computing unit core grain 106-1-1 is electrically connected to the monolithic optoelectronic integrated chip through the twenty-sixth bump 106-1-1-1, the redistribution layer 106-3-1, the through silicon via 106-3-2 and the fifteenth bump 106-3-3.

[0199] like Figure 1 and Figure 2As shown, based on the above embodiments, further, the integrated passive devices (IPD) 2-4 are reconstructed on the adapter board 2. The integrated passive devices 2-4 may include components such as resistors, capacitors, and inductors. This can reduce the size and weight of the circuit, help to achieve the thinness of electronic equipment, and improve the electrical performance of the system.

[0200] On the basis of the above embodiments, further, the first substrate 2 - 2 is a molded or glass transfer plate.

[0201] Fig.55 is a structural schematic diagram of an optoelectronic co-packaging structure based on a reconstructed adapter board provided in the fifty-fifth embodiment of the present invention, such as Fig.55 As shown, on the basis of the above embodiments, further, the optoelectronic co-packaging structure based on the reconstructed adapter plate provided in the embodiment of the present invention further includes a second substrate 3 , and the reconstructed adapter plate 2 is arranged on the second substrate 3 .

[0202] Specifically, the reconstructed adapter board 2 is disposed on the second substrate 3, and a plurality of optoelectronic hybrid core particles 1 are disposed on the reconstructed adapter board 2. The reconstructed adapter board 2 is used to realize the communication connection of the plurality of optoelectronic hybrid core particles 1, and the reconstructed adapter board 2 can realize the integration of the plurality of optoelectronic hybrid core particles 1. The reconstructed adapter board 2 can be bonded to the second substrate 3 by bumps.

[0203] For example, Fig.55 As shown, a plurality of optoelectronic hybrid core particles 1 are arranged on the reconstruction adapter 2, each of which is bonded to the reconstruction adapter 2 through the corresponding first bump 1-1, and the reconstruction adapter 2 is bonded to the second substrate 3 through the sixteenth bump 2-0. The reconstruction adapter 2 includes a silicon bridge 2-1, a first substrate 2-2 and a rewiring layer 2-3, and the silicon bridge 2-1 is embedded in the first substrate 2-2. Each optoelectronic hybrid core particle 1 is connected to the communication through the corresponding first bump 1-1 and the silicon bridge 2-1.

[0204] The specific structure of the optoelectronic hybrid core particle 1 is described above and will not be repeated here.

[0205] The optoelectronic co-packaging structure based on the reconstructed adapter board proposed in the present application uses different integrated components or different structures to realize the interconnection between the EIC of the host chip or computing function and a photonic integrated chip, an electronic integrated chip or a monolithic optoelectronic integrated chip. The module is core-granulated and integrated as an optoelectronic hybrid core unit. An active or passive silicon bridge is embedded in the substrate, or a reconstructed adapter board is prepared in the wiring layer and the glass adapter board to realize the integration of multiple optoelectronic hybrid cores. The structure has good design flexibility, realizes the decoupling of computing and transmission resources, and expands the computing power of high-performance computing. At the same time, the active adapter board of the optoelectronic hybrid core is small in size, high in yield, and good in performance. The reconstructed adapter board is used to realize the large-area integration of multiple optoelectronic hybrid cores, and can integrate passive devices IPD, while ensuring the yield, reducing process costs, and improving system signal integrity and power integrity.

[0206] In the description of this specification, the description with reference to the terms "one embodiment", "a specific embodiment", "some embodiments", "for example", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0207] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An optoelectronic co-packaging structure based on a reconstructed adapter plate, characterized in that: It includes multiple optoelectronic hybrid chips and reconstruction adapter boards, including: A plurality of optoelectronic hybrid core particles are arranged on the reconfiguration adapter board, and the reconfiguration adapter board is used to realize the communication connection of the plurality of optoelectronic hybrid core particles; the optoelectronic hybrid core particles integrate a host chip, a photon integrated chip and an electronic integrated chip; The reconstructed adapter plate includes a silicon bridge and a first substrate, wherein the silicon bridge is embedded in the first substrate.

2. The optoelectronic co-packaging structure based on the reconstructed adapter plate according to claim 1, characterized in that: The plurality of optoelectronic hybrid core particles include at least one of a first optoelectronic hybrid core particle, a second optoelectronic hybrid core particle, a third optoelectronic hybrid core particle, a fourth optoelectronic hybrid core particle, a fifth optoelectronic hybrid core particle, and a sixth optoelectronic hybrid core particle.

3. The optoelectronic co-packaging structure based on the reconstructed adapter plate according to claim 2, characterized in that: The first optoelectronic hybrid core comprises a plurality of electronic integrated chips and an embedded PIC silicon bridge. The embedded PIC silicon bridge integrates a photonic integrated chip, and the plurality of electronic integrated chips are arranged on the embedded PIC silicon bridge.

4. The optoelectronic co-packaging structure based on a reconstructed adapter plate according to claim 2, characterized in that: The first optoelectronic hybrid core comprises a host chip, an electronic integrated chip and an embedded PIC silicon bridge. The embedded PIC silicon bridge integrates a photon integrated chip. The host chip and the electronic integrated chip are arranged on the embedded PIC silicon bridge.

5. The optoelectronic co-packaging structure based on a reconstructed adapter plate according to claim 2, characterized in that: The second optoelectronic hybrid core comprises a host chip, a photonic integrated chip and an embedded EIC silicon bridge. The embedded EIC silicon bridge integrates an electronic integrated chip. The host chip and the photonic integrated chip are arranged on the embedded EIC silicon bridge.

6. The optoelectronic co-packaging structure based on a reconstructed adapter plate according to claim 2, characterized in that: The third optoelectronic hybrid core comprises a host chip and an embedded monolithic optoelectronic integrated silicon bridge, the embedded monolithic optoelectronic integrated silicon bridge integrates a monolithic optoelectronic integrated chip, and the host chip is arranged on the embedded monolithic optoelectronic integrated silicon bridge.

7. The optoelectronic co-packaging structure based on a reconstructed adapter plate according to claim 2, characterized in that: The first optoelectronic hybrid core comprises a plurality of electronic integrated chips and a PIC adapter board, wherein the plurality of electronic integrated chips are arranged on the PIC adapter board.

8. The optoelectronic co-packaging structure based on a reconstructed adapter plate according to claim 2, characterized in that: The fourth optoelectronic hybrid core comprises a host chip, an electronic integrated chip and a PIC adapter board, wherein the host chip and the electronic integrated chip are arranged on the PIC adapter board.

9. The optoelectronic co-packaging structure based on a reconstructed adapter plate according to claim 2, characterized in that: The fifth optoelectronic hybrid core comprises a host chip, a photonic integrated chip and an EIC adapter board, and the host chip and the electronic integrated chip are arranged on the EIC adapter board.

10. The optoelectronic co-packaging structure based on a reconstructed adapter plate according to claim 2, characterized in that: The sixth optoelectronic hybrid core comprises a host chip and a monolithic optoelectronic integrated adapter board, and the host chip is arranged on the monolithic optoelectronic integrated adapter board.

11. The optoelectronic co-packaging structure based on a reconstructed adapter plate according to any one of claims 4 to 10, characterized in that: The host chip includes a computing unit chip and / or a storage unit chip.

12. The optoelectronic co-packaging structure based on a reconstructed adapter plate according to claim 11, characterized in that: The optoelectronic hybrid core comprises a passive adapter board, and the passive adapter board is used to carry the computing unit core and / or the storage unit core.

13. The optoelectronic co-packaging structure based on a reconstructed adapter plate according to claim 1, characterized in that: Passive components are integrated on the reconstruction adapter board.

14. The optoelectronic co-packaging structure based on a reconstructed adapter plate according to claim 1, characterized in that: The first substrate is a molded or glass transfer plate.

15. The optoelectronic co-packaging structure based on a reconstructed adapter plate according to claim 1, characterized in that: The device further includes a second substrate, and the reconstructed adapter plate is disposed on the second substrate.

Images