Level shifter and power converter

Abstract

A level converter and a power converter are provided. A level shifter for a power converter includes: a differential detector; a first transistor having a drain electrically connected to the first node of the differential detector, a gate electrically connected to ground or a fixed DC voltage, and a source; a second transistor having a drain electrically connected to the second node of the differential detector, a gate electrically connected to ground or a fixed DC voltage, and a source; a first circuit configured to dynamically control a voltage applied to a source of the first transistor based on a digital signal input to the level shifter; and a second circuit configured to dynamically control a voltage applied to a source of the second transistor based on the digital signal. The differential detector is configured to convert the digital signal to different voltage levels based on a differential current between the first transistor and the second transistor.

Description

Technical Field

[0001] The present invention relates to a level converter and a power converter. Background Art

[0002] Power converters such as half-bridge and full-bridge converters typically use a bootstrap technique that includes a bootstrap capacitor to create a floating voltage domain to drive one or more high-side power switches of the power converter. In a typical application of a DC-DC buck converter, there is a dead time when all power switches in the power switch are turned off during the time interval between the activation of the high-side power switch and the activation of the low-side power switch. During the dead time, the output inductor forces the current to flow, and therefore, the switch node of the power converter is forced to a negative value. If a silicon transistor is used to implement the power switch, the low-side power switch has a parasitic / body diode in place, and the negative voltage at the switch node is about -0.7V. If a GaN transistor is used to implement the low-side power switch, the low-side power switch has no body diode, but can conduct current if the voltage between the drain and the gate creates a channel. In this case, the switch node of the power converter is forced to a more negative voltage, such as in the range of -2V to -5V. Due to the presence of the bootstrap capacitor, the bootstrap node, which is the positive supply voltage of the high-side driver, follows the switch node of the power converter and drops to a level close to ground. To exit the dead time mode, the input control of the high-side driver switches, sending the signal from the low voltage input domain to the high-side domain through the level shifter, and finally switching the driver for the high-side power switch. Since both the switch node and the low voltage input domain of the power converter are close to 0V in this case, there is not enough headroom voltage for the level shifter to propagate the current signal.

[0003] Therefore, there is a need for a level shifter design with improved voltage margin for power converter applications. Summary of the invention

[0004] According to an embodiment of the level converter, the level converter includes: a differential detector; a first transistor having a drain electrically connected to a first node of the differential detector, a gate electrically connected to ground or a fixed DC voltage, and a source; a second transistor having a drain electrically connected to a second node of the differential detector, a gate electrically connected to ground or a fixed DC voltage that is the same as or different from that of the first transistor, and a source; a first circuit configured to dynamically control a voltage applied to the source of the first transistor based on a digital signal input to the level converter; and a second circuit configured to dynamically control a voltage applied to the source of the second transistor based on the digital signal, wherein the differential detector is configured to convert the digital signal into different voltage levels based on a differential current between the first transistor and the second transistor.

[0005] According to another embodiment of the level converter, the level converter includes: a differential detector; a first transistor having a drain electrically connected to a first node of the differential detector, a gate electrically connected to ground or a fixed DC voltage, and a source; a second transistor having a drain electrically connected to a second node of the differential detector, a gate electrically connected to ground or a fixed DC voltage that is the same as or different from the first transistor, and a source; a first capacitor having a first terminal and a second terminal, the second terminal being electrically connected to the source of the first transistor; a first switching device electrically connected between a first DC supply voltage or a ground reference and a first terminal of the first capacitor; a second switching device electrically connected between the first terminal of the first capacitor and the ground or a bootstrap node; a third switching device electrically connected between the second terminal of the first capacitor and the ground or the bootstrap node; a second capacitor having a first terminal and a second terminal, the second terminal being electrically connected to the source of the second transistor; a fourth switching device electrically connected between the second DC supply voltage or a ground reference and the first terminal of the second capacitor; a fifth switching device electrically connected between the first terminal of the second capacitor and the ground or the bootstrap node; and a sixth switching device electrically connected between the second terminal of the second capacitor and the ground or the bootstrap node.

[0006] According to an embodiment of the power converter, the power converter includes: a high-side power switching device; a gate driver configured to drive the gate of the high-side power switching device; and a level converter configured to convert a digital signal input to the level converter to a voltage domain of the gate driver, wherein the level converter includes: a differential detector; a first transistor having a drain electrically connected to a first node of the differential detector, a gate electrically connected to ground or a fixed DC voltage, and a source; a second transistor having a drain electrically connected to a second node of the differential detector, a gate electrically connected to ground or a fixed DC voltage that is the same as or different from the first transistor, and a source; a first circuit configured to dynamically control a voltage applied to the source of the first transistor based on a digital signal; and a second circuit configured to dynamically control a voltage applied to the source of the second transistor based on a digital signal, wherein the differential detector is configured to convert the digital signal to the voltage domain of the gate driver based on a differential current between the first transistor and the second transistor.

[0007] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The elements in the drawings are not necessarily to scale with respect to each other. The same reference numerals represent corresponding similar parts. Unless the features of the various illustrated embodiments exclude each other, they may be combined. The embodiments are depicted in the drawings and described in detail in the following description.

[0009] Figure 1 A circuit schematic diagram of a level up converter according to an embodiment is shown.

[0010] Figure 2 A circuit diagram of a level-down converter according to another embodiment is shown.

[0011] Figure 3 A circuit schematic diagram of a first switch network included in a level-up converter according to an embodiment is shown.

[0012] Figure 4 Shown with Figure 3 Various waveforms associated with the operation of the level-up converter.

[0013] Figure 5 A circuit schematic diagram of a first switch network included in a level-down converter according to an embodiment is shown.

[0014] Figure 6 A diode-based implementation of a level-up converter according to an embodiment is shown.

[0015] Figure 7 A diode-based implementation of a level-up converter according to another embodiment is shown.

[0016] Figure 8 Embodiments of a power converter including a level-up converter or a level-down converter as described herein are shown. DETAILED DESCRIPTION

[0017] Embodiments described herein provide a level converter with an increased voltage margin. The level converter can be used in power converter applications, such as half-bridge converters and full-bridge converters. The level converter uses a high voltage transistor and a differential circuit to send digital information from a low-side domain to a high-side domain. The high voltage transistor is controlled at its source terminal rather than its gate terminal. The gate terminal of the high voltage transistor is connected to ground or a DC voltage, such as close to ground, and the source terminal is switched in a complementary manner reflecting the low level or high level of the input digital signal. For example, a flying capacitor can be used to switch the source terminal of the high voltage transistor. In the first stage, the corresponding flying capacitor is precharged with a DC voltage to have the same voltage as the maximum gate-to-source voltage of the high voltage transistor coupled to the flying capacitor. When the input of the level converter is switched, the flying capacitor is connected to the source terminal of the high voltage transistor, thereby providing a negative voltage to the source terminal. The current generated by the high voltage transistor is detected by a high-side circuit, and a digital signal can be reconstructed. Another flying capacitor and a high voltage transistor operate in a complementary manner to realize a differential circuit.

[0018] Next, exemplary embodiments of a level converter and a power converter using the same are described with reference to the accompanying drawings.

[0019] Figure 1 1 shows a circuit diagram of a level converter 100 according to an embodiment. The level converter 100 includes a differential detector 102, a first transistor M1 and a second transistor M2, the first transistor M1 having a drain D1 electrically connected to a first node nd1 of the differential detector 102, and the second transistor M2 having a drain D2 electrically connected to a second node nd2 of the differential detector 102. The gate G1 of the first transistor M1 is electrically connected to the ground or a fixed DC voltage vb. The gate G2 of the second transistor M2 is also electrically connected to the ground or the fixed DC voltage vb. The fixed DC voltage vb can be the same or different for the first transistor M1 and the second transistor M2.

[0020] The level converter 100 also includes a first circuit 104 that dynamically controls the voltage applied to the source S1 of the first transistor M1 based on the digital signal pwm_i input to the level converter 100. The second circuit 106 of the level converter 100 dynamically controls the voltage applied to the source S2 of the second transistor M2 based on the digital signal pwm_i input to the level converter 100. The differential detector 102 converts the digital signal pwm_i into different voltage levels pwm_o based on the differential current between the first transistor M1 and the second transistor M2. The first transistor M1 and the second transistor M2 have a short pull-down current pulse. The differential detector 102 detects the difference and generates a pulse, which is latched so that the pulse remains valid before the next cycle. This enables the transistor M1 (or M2) to be turned off quickly, thereby reducing power loss and relaxing the reliability requirements for these transistors.

[0021] exist Figure 1 , the first circuit 104 includes a first flying capacitor C_fly_1 and a first switch network s1 to s3. In response to a first transition (low to high or high to low) of a digital signal pwm_i input to the level converter 100, the first switch network s1 to s3 connects the first flying capacitor C_fly_1 to the source S1 of the first transistor M1 so that a negative voltage is applied to the source S1 of the first transistor M1. After a rising or enabling transition of the digital signal pwm_i input to the level converter 100, the first switch network s1 to s3 precharges the first flying capacitor C_fly_1 for the next first transition of the digital signal pwm_i.

[0022] exist Figure 1, the second circuit 106 includes a second flying capacitor C_fly_2 and a second switch network s4 to s6. In response to a falling or disabling transition of the digital signal pwm_i input to the level converter 100 opposite to the first transition, the second switch network s4 to s6 connects the second flying capacitor C_fly_2 to the source S2 of the second transistor M2 so that a negative voltage is applied to the source S2 of the second transistor M2. After the second transition of the digital signal pwm_i input to the level converter 100, the second switch network s4 to s6 precharges the second flying capacitor C_fly_2 for the next second transition of the digital signal.

[0023] exist Figure 1 , the first switch network s1 to s3 includes a first switch device s1, a second switch device s2, and a third switch device s3. The first switch device s1 is electrically connected between the first DC supply voltage vdd_lv and the first terminal 108 of the first flying capacitor C_fly_1. The second switch device s2 is electrically connected between the first terminal 108 of the first flying capacitor C_fly_1 and the ground. The third switch device s3 is electrically connected between the second terminal 110 of the first flying capacitor C_fly_1 and the ground, wherein the second terminal 110 of the first flying capacitor C_fly_1 is also electrically connected to the source S1 of the first transistor M1. The second switch device s2 is turned on in response to the first transition of the digital signal pwm_i input to the level converter 100. When the second switch device s2 is turned on, the first switch device s1 and the third switch device s3 are both turned off. The second switch device s2 is turned off after a predefined time from the first transition of the digital signal pwm_i input to the level converter 100. When the second switching device s2 is turned off, the first switching device s1 and the third switching device s3 are both turned on.

[0024] exist Figure 1, the second switch network s4 to s6 includes a fourth switch device s4, a fifth switch device s5 and a sixth switch device s6. The fourth switch device s4 is electrically connected between the second DC supply voltage vdd_lv and the first terminal 112 of the second flying capacitor C_fly_2. The fifth switch device s5 is electrically connected between the first terminal 112 of the second flying capacitor C_fly_2 and the ground. The sixth switch device s6 is electrically connected between the second terminal 114 of the second flying capacitor C_fly_2 and the ground, and the second terminal 114 of the second flying capacitor C_fly_2 is also electrically connected to the source S2 of the second transistor M2. The fifth switch device s5 is turned on in response to the second transition of the digital signal pwm_i input to the level converter 100. When the fifth switch device s5 is turned on, the fourth switch device s4 and the sixth switch device s6 are both turned off. The fifth switch device s5 is turned off after a predefined time from the second transition of the digital signal pwm_i input to the level converter 100. When the fifth switching device s5 is turned off, the fourth switching device s4 and the sixth switching device s6 are both turned on.

[0025] exist Figure 1 In the embodiment, the level converter 100 is an up-level converter, which means that the level converter 100 converts the digital signal pwm_i input to the level converter 100 into a higher voltage level. In the case of the up-level converter, the differential detector 102 is coupled between the bootstrap node HB and the first transistor M1 and the second transistor M2, the first transistor M1 and the second transistor M2 are NMOS (n-channel metal oxide semiconductor) devices coupled between the differential detector 102 and the ground, and the differential detector 102 converts the digital signal pwm_i input to the level converter 100 into a higher voltage level based on the differential current between the first transistor M1 and the second transistor M2.

[0026] Figure 1 The level converter 100 in FIG. 1 is differential, wherein the operations on the left and right sides are complementary to each other. The switch devices s1, s2, s3 of the first switch network s1 to s3 are used to control the node ns1, which controls the current on the left side of the first transistor M1 and the level converter 100. The switch devices s4, s5, s6 of the second switch network s4 to s6 are used to control the node ns2, which controls the current on the right side of the second transistor M2 and the level converter 100.

[0027] In the non-switching state, the third switch device s3 and the sixth switch device s6 are turned on, thereby ensuring that the potential at the nodes ns1 and ns2 is connected to GND, and the transistors M1 and M2 are turned off. During this state, the first switch device s1 and the fourth switch device s4 are also turned on, thereby charging the flying capacitors C_fly_1 and C_fly_2 to have a voltage difference from vdd_lv to GND. In order to enable the flying capacitors C_fly_1 and C_fly_2 to be charged, the second switch device s2 and the fifth switch device s5 remain turned off. Since the transistors M1 and M2 are both turned off in this state, the differential detector 102 is latched to the last state level.

[0028] To latch the differential detector 102 to one position, the left side of the level shifter 100 is used. In this case, the first switching device s1 and the third switching device s3 are turned off, and the second switching device s2 is turned on, thereby connecting the first terminal 108 of the first flying capacitor C_fly_1 to ground and applying a negative voltage to the node ns1. Since the gate G1 of the first transistor M1 is connected to ground or close to ground potential, there is a voltage difference between the gate-to-source voltage (VGS) and the drain-to-source voltage (VDS) of the first transistor M1, which introduces current into the first (left) node nd1 of the differential detector 102. The differential detector 102 detects that current is flowing on the left side (from the transistor M1) and that no current is flowing on the right side (from the transistor M2), and in response, switches the output pwm_o of the level shifter 100 from low to high (or from high to low). The current flowing in M1 is provided by the first flying capacitor C_fly_1, which can be turned on for only a few nanoseconds (the turn-on time needs to be slightly higher than the propagation delay of the level converter). The size of the flying capacitors C_fly_1, C_fly_2 should be designed to ensure a small discharge during the turn-on period of the corresponding high voltage transistors M1, M2. After a predefined time, the switching devices s1, s2, s3 of the first switching network s1 to s3 are restored to their default state. Since there is no current difference between the first transistor M1 and the second transistor M2, the output of the differential detector 102 is latched.

[0029] In order to latch the differential detector 102 to the opposite position, the right side of the level converter 100 is used. In this case, the fourth switch device s4 and the sixth switch device s6 are turned off, and the fifth switch device s5 is turned on, thereby connecting the first terminal 112 of the second flying capacitor C_fly_2 to the ground and applying a negative voltage to the node ns2. Since the gate G2 of the second transistor M2 is connected to the ground or close to the ground potential, there is a voltage difference between the VGS and VDS of the second transistor M2, which introduces current into the second (right) node nd2 of the differential detector 102. The differential detector 102 detects that the current flows on the right side (from the transistor M2) and that there is no current flow on the left side (from the transistor M1), and in response, the output pwm_o of the level converter is switched from high to low (or from low to high). After a predefined time, the switch devices s4, s5, s6 of the second switch network s4 to s6 are restored to their default state. Since there is no difference in current between the first transistor M1 and the second transistor M2 , the output pwm_o of the differential detector 102 is latched.

[0030] Figure 2 FIG. 2 shows a circuit diagram of a level converter 200 according to another embodiment. Figure 2 The level converter 200 in FIG. Figure 1 The level converter 100 in FIG. Figure 2 , the level converter 200 is a down-level converter, meaning that the level converter 200 converts the digital signal pwm_i input to the level converter 200 into a lower voltage level. In the case of a down-level converter, the differential detector 102 is coupled between the ground and the first transistor M1 and the second transistor M2, the first transistor M1 and the second transistor M2 are PMOS (p-channel metal oxide semiconductor) devices coupled between the differential detector 102 and the bootstrap node HB, the switching devices sp1 to sp6 of the first circuit 104 and the second circuit 106 are also PMOS devices, and the differential detector 102 converts the digital signal pwm_i input to the level converter 200 into a lower voltage level based on the differential current between the first transistor M1 and the second transistor M2. The PMOS device type is indicated by including the letter "P" / "p" in the transistor and node labels.

[0031] exist Figure 2, a first switch device sp1 of a first switch network sp1 to sp3 is electrically connected between a first ground reference vssf and a first terminal 108 of a first flying capacitor C_fly_1. A second switch device sp2 of the first switch network sp1 to sp3 is electrically connected between a first terminal 108 of the first flying capacitor C_fly_1 and a bootstrap node HB. A third switch device sp3 of the first switch network sp1 to sp3 is electrically connected between a second terminal 110 of the first flying capacitor C_fly_1 and the bootstrap node HB. A fourth switch device sp4 of a second switch network sp4 to sp6 is electrically connected between a second ground reference vssf and a first terminal 112 of a second flying capacitor C_fly_2. A fifth switch device sp5 of the second switch network sp4 to sp6 is electrically connected between a first terminal 112 of the second flying capacitor C_fly_2 and the bootstrap node HB. A sixth switch device sp6 of the second switch network sp4 to sp6 is electrically connected between a second terminal 114 of the second flying capacitor C_fly_2 and the bootstrap node HB.

[0032] Figure 3 An embodiment of a first switching network s1 to s3 for an up-regulation level shifter embodiment is shown. Figure 3 , the first switching device s1 includes a first PMOS transistor M12 having a positive pulse gate input G12 electrically connected to the first terminal 108 of the first flying capacitor C_fly_1 via an inverter INV2 , a drain D12 electrically connected to the first DC supply voltage vdd_lv, and a source S12 . Figure 3 The first switching device s1 in the embodiment further includes a first inverter 300 formed by a second PMOS transistor M14 and a first NMOS transistor M15. The first inverter 300 has a positive pulse inputted via the inverter INV3 applied to the gate G14 of the second PMOS transistor M14 and the gate G15 of the first NMOS transistor M15. The drain D14 of the second PMOS transistor M14 is electrically coupled to the source S12 of the first PMOS transistor M12. The source S15 of the first NMOS transistor M15 is grounded.

[0033] Figure 3 The second switching device s2 in EMBODIMENT 1 comprises a second NMOS transistor M10 having a grounded gate input G10, a source S10 electrically connected to the source S1 of the first transistor M1 and the second terminal 110 of the first flying capacitor C_fly_1, and a drain D10. Figure 3The second switching device s2 in the embodiment further includes a third PMOS transistor M13 having a grounded gate input G13, a source S13 electrically connected to the output of the first inverter 300, and a drain D13 electrically connected to the drain D10 of the second NMOS transistor M10.

[0034] Figure 3 The third switching device s3 includes a third NMOS transistor M11 having a gate G11 electrically connected to the drain D13 of the third PMOS transistor P13 and the drain D10 of the second NMOS transistor M10, a source S11 electrically connected to the source S1 of the first transistor M1, and a drain D11 electrically connected to the ground.

[0035] like Figure 1 As shown in FIG. , the second switch network s4 to s6 and the first switch network s1 to s3 are symmetrical for the up-level converter. Therefore, Figure 3 Details of the second switch network s4 to s6 are not shown. Similar to the first switch device s1, the fourth switch device s4 includes: a fourth PMOS transistor having a positive pulse gate input electrically connected to the first terminal 112 of the second flying capacitor C_fly_2, a drain electrically connected to the second DC supply voltage vdd_lv, and a source; and a second inverter formed by a fifth PMOS transistor and a fourth NMOS transistor, the second inverter having a positive pulse input, the drain of the fifth PMOS transistor electrically coupled to the source of the fourth PMOS transistor, and the source of the fourth NMOS transistor grounded. Similar to the second switch device s2, the fifth switch device s5 includes: a fifth NMOS transistor having a grounded gate input, a source electrically connected to the source S2 of the second transistor M2 and the second terminal 114 of the second flying capacitor C_fly_2, and a drain; and a sixth PMOS transistor having a grounded gate input, a source electrically connected to the output of the second inverter, and a drain electrically connected to the drain of the fifth NMOS transistor. Similar to the third switching device s3, the sixth switching device s6 includes a sixth NMOS transistor having a gate electrically connected to the drain of the sixth PMOS transistor and the drain of the fifth NMOS transistor, a source electrically connected to the source S2 of the second transistor M2, and a drain electrically connected to ground.

[0036] Figure 4 Shown with Figure 3Various waveforms associated with the operation of the up-level converter implementation shown in . The pulse generator 302 generates a negative pulse output "npulse" based on the digital signal pwm_i input to the level converter 100. In a stable state, the negative pulse output npulse of the pulse generator 302 is fixed at a logic 1 level and the node n11 is at a DC supply voltage vdd_lv to charge the first flying capacitor C_fly_1. Grounding is provided to the node ns1 by the third NMOS transistor M11 of the third switching device s3. The gate G11 of the third NMOS transistor M11 is coupled to the node n13, and the node n13 is at a DC supply voltage vdd_lv delivered from the node n12 through the third PMOS transistor M13 of the second switching device s2. The potential of the node n12 is defined by the potentials of the nodes n11 and the node n10 sensed by the inverter INV2 of the control node n14.

[0037] When a negative edge occurs at the pulse output npulse of the pulse generator 302, the node n10 moves upward, which causes the node n12 to move downward immediately, and thus also causes the node n13 to move downward to near the threshold voltage Vt above ground (before the transistor M13 allows it). This causes the third NMOS transistor M11 of the third switch device s3 to be almost turned off. At this point, the node n13 becomes high ohmic, and the node ns1 becomes non-driven and is defined only by the charge state of the first flying capacitor C_fly_1 relative to the node n11. Turning off the transistor M11 before the ns1 node moves prevents the first flying capacitor C_fly_1 from being discharged unnecessarily through the transistor M11 during the period when the node ns1 moves below the ground potential.

[0038] Due to the engagement current on the first flying transistor M1, the upward movement of node n10 also causes node n11 to slowly move downward. The first flying capacitor C_fly_1 forces node ns1 to follow the movement of node n11, but node ns1 moves downward from ground potential to a negative value. Once node ns1 reaches a threshold voltage Vt below ground, the second NMOS transistor M10 of the second switching device s2 begins to conduct and connects nodes ns1 and n13 together, forcing the third NMOS transistor M11 of the third switching device s3 to remain off during the entire transition.

[0039] In this state, the first flying capacitor C_fly_1 delivers charge from the node n11 held at ground potential by the inverter INV1 to the source S1 of the first cross-domain transistor M1. The charge on the first flying capacitor C_fly_1 decays, causing the node ns1 to slowly move upward toward ground potential. The charge delivered by the first flying capacitor C_fly_1 is sufficient to be detected on the bootstrap node HB domain. Sufficient time is provided for the bootstrap node HB domain to reliably detect the pulse, while reducing the pulse width as much as possible to reduce power consumption.

[0040] When the digital signal pwm_i input to the level converter 100 starts the rising edge, the pulse output npulse of the pulse generator 302 ends the negative pulse. Then, the node n10 moves downward, so that the node n11 starts to move upward. The node ns1 follows the node n11 upward, while the third NMOS transistor M11 of the third switch device s3 remains turned off (the transistor M10 keeps the node n13 connected to the node ns1). When the node n11 moves to a high enough level, the inverter INV2 detects the situation and moves the node n14 downward, which makes the node n12 move upward. Once the node n12 voltage exceeds the threshold voltage Vt of the third PMOS transistor M13 of the second switch device s2, the node n13 begins to follow the node n12. This causes the enabling of the transistor M11, which provides a path for the first flying capacitor C_fly_1 to be recharged via the inverter INV1 and the transistor M11. The process returns to the initial position and is ready to repeat.

[0041] Figure 5 Shown with Figure 3 The same circuit, but implemented as a level-down level shifter 200. Figure 5 , the pulse generator 302 generates a positive pulse output "ppulse" based on the digital signal pwm_i input to the level converter 200. In addition, the first switching device s1 of the first switching network s1 to s3 includes a first NMOS transistor M21, the first NMOS transistor M21 having a negative pulse gate input G21 electrically connected to the first terminal 108 of the first flying capacitor C_fly_1 via an inverter INV21, a source S21 electrically connected to the first ground reference vssf, and a drain D21. The first switching device s1 also includes a first inverter 500 formed by a second NMOS transistor M25 and a first PMOS transistor M26. The first inverter 500 has a negative pulse input via an inverter INV23 applied to the gate G25 of the second NMOS transistor M25 and the gate G26 of the first PMOS transistor M26. The source S25 of the second NMOS transistor M25 is electrically coupled to the drain D21 of the first NMOS transistor M21. The drain D26 of the first PMOS transistor M26 is electrically connected to the bootstrap node HB.

[0042] Figure 5 The second switching device s2 in EMBODIMENT 1 includes a second PMOS transistor M24 having a gate G24 electrically connected to the bootstrap node HB, a source S24 electrically connected to the second terminal 110 of the first flying capacitor C_fly_1, and a drain D24. Figure 5 The second switching device s2 in further includes a third NMOS transistor M22 having a gate G22 electrically connected to the bootstrap node HB, a source S22 electrically connected to the output of the first inverter 500, and a drain D22 electrically connected to the drain D24 of the second PMOS transistor M24.

[0043] Figure 5 The third switching device s3 includes a third PMOS transistor M23 having a gate G23 electrically connected to the drain D22 of the third NMOS transistor M22 and the drain D24 of the second PMOS transistor M24, a source S23 electrically connected to the second terminal 110 of the first flying capacitor C_fly_1, and a drain electrically connected to the bootstrap node HB.

[0044] like Figure 2 As shown in FIG. 1 , for the case of a down-regulation level converter, the second switch network s4 to s6 and the first switch network s1 to s3 are symmetrical. Therefore, Figure 5Details of the second switch network s4 to s6 are not shown. Similar to the first switch device s1, the fourth switch device s4 includes a fourth NMOS transistor having a negative pulse gate input electrically connected to the first terminal 112 of the second flying capacitor C_fly_2, a source electrically connected to the first ground reference vssf, and a drain. The fourth switch device s4 also includes a second inverter formed by a fifth NMOS transistor and a fourth PMOS transistor, the second inverter having a negative pulse input, a source of the fifth NMOS transistor electrically coupled to the drain of the fourth NMOS transistor, and a drain of the fourth PMOS transistor electrically connected to the bootstrap node HB. Similar to the second switch device s2, the fifth switch device s5 includes a fifth PMOS transistor having a gate electrically connected to the bootstrap node HB, a source electrically connected to the second terminal 114 of the second flying capacitor C_fly_2, and a drain. The fifth switching device s5 further includes a sixth NMOS transistor having a gate electrically connected to the bootstrap node HB, a source electrically connected to the output of the second inverter, and a drain electrically connected to the drain of the fifth PMOS transistor. Similar to the third switching device s3, the sixth switching device s6 includes a sixth PMOS transistor having a gate electrically connected to the drain of the sixth NMOS transistor and the drain of the fifth PMOS transistor, a source electrically connected to the second terminal 114 of the second flying capacitor C_fly_2, and a drain electrically connected to the bootstrap node HB.

[0045] Figure 6 A diode-based implementation of the level-up converter 100 is shown. Figure 6 , the first circuit 104 of the level up converter 100 includes a first diode D1 having an anode A1 electrically connected to the source S1 of the first transistor M1 and a cathode C1 electrically connected to the ground. The negative pulse signal npulse obtained from the digital signal pwm_i input to the level up converter 100 is applied to the first terminal 108 of the first flying capacitor C_fly_1. The second terminal 110 of the first flying capacitor C_fly_1 is electrically connected to the source S1 of the first transistor M1 and the anode A1 of the first diode D1.

[0046] like Figure 1 As shown in FIG. 1 , for the case of the up-level converter, the first level converter circuit 104 and the second level converter circuit 106 are symmetrical. Therefore, Figure 6Details of the second level converter circuit 106 are not shown. Similar to the first level converter circuit 104, the second level converter circuit 106 includes a second diode having an anode electrically connected to the source S2 of the second transistor M2 and a cathode electrically connected to ground. The negative pulse signal npulse obtained from the digital signal pwm_i input to the level up converter 100 is applied to the first terminal 112 of the second flying capacitor C_fly_2. The second terminal 114 of the second flying capacitor C_fly_2 is electrically connected to the source S2 of the second transistor M2 and the anode of the second diode. Figure 6 In the embodiment, the gate G1 of the first transistor M1 and the gate G2 of the second transistor M2 are both electrically connected to a fixed DC voltage vb which is less than the diode voltage. The switching devices s1 and s2 are respectively the output PMOS and NMOS of the pulse generator 302. The switching device s3 corresponds to the first diode D1.

[0047] exist Figure 6 , node ns1 is connected only to the first diode D1 and the first flying capacitor C_fly_1 below the first transistor M1. When the pulse generator 302 applies vdd_lv to the first terminal 108 of the first flying capacitor C_fly_1, the first flying capacitor C_fly_1 is charged by the difference between vdd_lv and ground minus the voltage drop Vf across the first diode D1. Depending on the type of semiconductor technology used to implement the first diode D1, the voltage drop Vf across the first diode D1 is typically about 0.7V. In this case, considering that the fixed DC voltage vb is a voltage lower than one diode voltage, the VGS of the first transistor M1 is equal to or lower than 0V, so M1 is turned off. When the pulse generator 302 applies ground to the first terminal 108 of the first flying capacitor C_fly_1, the node ns1 is forced to a negative voltage, which produces VGS and VDS for the first transistor M1, so that current flows at the first node nd1 of the differential detector 102.

[0048] Figure 7 Another diode-based implementation of the level-up converter 100 is shown. Figure 7 In the embodiment, the gate G1 of the first transistor M1 and the gate G2 of the second transistor M2 are Figure 7 The node vb of is biased to have a diode voltage Vf. Figure 6 In the on state, the first transistor M1 has a VGS of (vdd_lv - ns1), where ns1 is typically about 0.7V. Figure 7In the example, the fixed DC voltage vb is biased to have a diode voltage. Therefore, when the first transistor M1 is turned on, the VGS of the first transistor M1 is the difference between the gate voltage (vb) and the source voltage (-vdd_lv+ns1). If ns1 and vb are equal, the VGS applied to the first transistor M1 is exactly the voltage vdd_lv, which is the same as Figure 6 This produces better performance than the simpler implementation shown in , but does require active control.

[0049] Figure 8 An embodiment of a power converter 800, such as a half-bridge converter, a full-bridge converter, etc., including the level converter 100 described herein is shown. The power converter 800 also includes a high-side power switch device MPHS and a (floating) gate driver 802 for driving the gate G_MPHS of the high-side power switch device MPHS. The level converter 100 converts the digital signal HI input to the level converter 100 to the voltage domain dr_hs of the high-side gate driver 802.

[0050] As described herein, the level converter 100 includes: a differential detector 102; a first transistor M1 having a drain D1 electrically connected to a first node nd1 / ndp1 of the differential detector 102, a gate G1 electrically connected to ground or a fixed DC voltage vb / vbp, and a source; a second transistor M2 having a drain D2 electrically connected to a second node nd2 / ndp2 of the differential detector 102, a gate G2 electrically connected to ground or a fixed DC voltage vb / vbp, and a source; a first circuit 104 for dynamically controlling a voltage applied to a source S1 of the first transistor M1 based on a digital input signal HI; and a second circuit 106 for dynamically controlling a voltage applied to a source S2 of the second transistor M2 based on the digital input signal HI. The fixed DC voltage vb / vbp may be the same or different for the first transistor M1 and the second transistor M2. The differential detector 102 of the level shifter 100 converts the digital input signal HI to a voltage domain dr_hs of the high-side gate driver 802 based on a differential current between the first transistor M1 and the second transistor M2 .

[0051] exist Figure 8In the embodiment, the power converter 800 has a buck converter topology. However, the power converter 800 can have different types of power converter topologies, such as boost, buck-boost, etc. In the case of a buck converter, the power converter 800 also includes a low-side power switch MPLS electrically connected to a high-side power switch MPHS in a half-bridge configuration. More particularly, the drain D_MPLS of the low-side power switch MPLS is electrically connected to the source S_MPHS of the high-side power switch MPHS, wherein the source S_IPLS of the low-side power switch MPLS is electrically connected to a reference potential VSS such as ground, and the drain D_MPHS of the high-side power switch MPHS is electrically connected to a voltage source VIN. A gate driver 804 is provided for driving the gate G_MPLS of the low-side power switch MPLS. In one embodiment, the drivers 802, 804 are GaN (gallium nitride) drivers.

[0052] The inductor L1 is electrically connected to a switch node SW between the low-side power switch device MPLS and the high-side power switch device MPHS. The bootstrap capacitor Cboot is electrically connected between the switch node SW and a bootstrap node HB, which provides a supply voltage for the gate driver 802 of the high-side power switch device MPHS. Figure 8 In FIG. 8 , the load powered by the power converter 800 is shown as a resistor Rload, where a capacitor C1 stabilizes the voltage Vout applied to the load Rload. The switching device “bootsw” recharges the bootstrap capacitor Cboot via the voltage source VCC of the high-side gate driver 802 .

[0053] In the case of an up-level converter, the differential detector 102 is coupled between the bootstrap node HB and the first transistor M1 and the second transistor M2 of the up-level converter 100, the first transistor M1 and the second transistor M2 of the up-level converter 100 are coupled between the differential detector 102 and the ground, and the differential detector 102 converts the digital input signal HI into a higher voltage level based on the differential current between the first transistor M1 and the second transistor M2 of the up-level converter 100.

[0054] In the case of a down-regulation level converter, the differential detector 102 is coupled between the ground and the first transistor M1 and the second transistor M2 of the down-regulation level converter 200, the first transistor M1 and the second transistor M2 of the down-regulation level converter 200 are coupled between the differential detector 102 and the bootstrap node HB, and the differential detector 102 converts the digital input signal HI into a lower voltage level based on the differential current between the first transistor M1 and the second transistor M2 of the down-regulation level converter 200.

[0055] like Figure 1As shown in , the first circuit 104 of the level converter 100 may include a first flying capacitor C_fly_1 and a first switch network s1 to s3, and the second circuit 106 of the level converter 100 may include a second flying capacitor C_fly_2 and a second switch network s4 to s6. In response to a first transition of the digital input signal HI of the high-side gate driver 802, the first switch network s1 to s3 connects the first flying capacitor C_fly_1 to the source S1 of the first transistor M1 so that a negative voltage is applied to the source S1 of the first transistor M1. After the first transition of the digital input signal HI of the high-side gate driver 802, the first switch network s1 to s3 pre-charges the first flying capacitor C_fly_1 for the next first transition of the digital input signal HI.

[0056] In response to the second transition opposite to the first transition of the digital input signal HI of the high-side gate driver 802, the second switch network s4 to s6 connects the second flying capacitor C_fly_2 to the source S2 of the second transistor M2 so that a negative voltage is applied to the source S2 of the second transistor M2. After the second transition of the digital input signal HI of the high-side gate driver 802, the second switch network s4 to s6 precharges the second flying capacitor C_fly_2 for the next second transition of the digital input signal H1. This enables the differential detector 102 to convert the digital input signal HI of the high-side gate driver 802 into different voltage levels (pwm_o) based on the differential current between the first transistor M1 and the second transistor M2. The level converter 200 can be used for the control of the high side and the level conversion from the VIN domain to the low side. That is, the level converter 200 can be connected to the input of the low-side gate driver 804.

[0057] Although the present disclosure is not limited in this regard, the following numbered examples illustrate one or more aspects of the present disclosure.

[0058] Example 1. A level converter comprises: a differential detector; a first transistor having a drain electrically connected to a first node of the differential detector, a gate electrically connected to ground or a fixed DC voltage, and a source; a second transistor having a drain electrically connected to a second node of the differential detector, a gate electrically connected to ground or a fixed DC voltage that is the same as or different from the first transistor, and a source; a first circuit configured to dynamically control a voltage applied to the source of the first transistor based on a digital signal input to the level converter; and a second circuit configured to dynamically control a voltage applied to the source of the second transistor based on the digital signal, wherein the differential detector is configured to convert the digital signal into different voltage levels based on a differential current between the first transistor and the second transistor.

[0059] Example 2. A level converter according to Example 1, wherein the first circuit includes a first capacitor and a first switch network, wherein the second circuit includes a second capacitor and a second switch network, wherein, in response to a first transition of the digital signal, the first switch network is configured to connect the first capacitor to the source of the first transistor so that a negative voltage is applied to the source of the first transistor, wherein, after the first transition of the digital signal, the first switch network is configured to pre-charge the first capacitor for a next first transition of the digital signal, wherein, in response to a second transition of the digital signal opposite to the first transition, the second switch network is configured to connect the second capacitor to the source of the second transistor so that a negative voltage is applied to the source of the second transistor, wherein, after the second transition of the digital signal, the second switch network is configured to pre-charge the second capacitor for a next second transition of the digital signal.

[0060] Example 3. A level converter according to Example 2, wherein the first switching network includes: a first switching device electrically connected between a first DC supply voltage or a first ground reference and a first terminal of a first capacitor; a second switching device electrically connected between the first terminal of the first capacitor and a ground or a bootstrap node; and a third switching device electrically connected between the second terminal of the first capacitor and the ground or the bootstrap node, wherein the second terminal of the first capacitor is electrically connected to the source of the first transistor, wherein the second switching network includes: a fourth switching device electrically connected between a second DC supply voltage or a second ground reference and the first terminal of the second capacitor; a fifth switching device electrically connected between the first terminal of the second capacitor and the ground or the bootstrap node; and a sixth switching device electrically connected between the second terminal of the second capacitor and the ground or the bootstrap node, wherein the second end of the second capacitor is electrically connected to the source of the second transistor.

[0061] Example 4. A level converter according to Example 3, wherein the second switching device is configured to be turned on in response to a first transition of the digital signal, and the first switching device and the third switching device are both configured to be turned off when the second switching device is turned on, wherein the second switching device is configured to be turned off after a predefined time from the first transition of the digital signal, and the first switching device and the third switching device are both configured to be turned on when the second switching device is turned off, wherein the fifth switching device is configured to be turned on in response to a second transition of the digital signal, and the fourth switching device and the sixth switching device are both configured to be turned off when the fifth switching device is turned on, wherein the fifth switching device is configured to be turned off after a predefined time from the second transition of the digital signal, and the fourth switching device and the sixth switching device are both configured to be turned on when the fifth switching device is turned off.

[0062] Example 5. A level converter according to any one of Examples 1 to 4, wherein a differential detector is coupled between a bootstrap node and a first transistor and a second transistor, wherein the first transistor and the second transistor are coupled between the differential detector and ground, and wherein the differential detector is configured to convert a digital signal into a higher voltage level based on a differential current between the first transistor and the second transistor.

[0063] Example 6. A level converter according to any one of Examples 1 to 4, wherein the differential detector is coupled between ground and the first transistor and the second transistor, wherein the first transistor and the second transistor are coupled between the differential detector and a bootstrap node, and wherein the differential detector is configured to convert the digital signal to a lower voltage level based on a differential current between the first transistor and the second transistor.

[0064] Example 7. A level converter according to any one of Examples 1 to 6, wherein the first circuit includes: a first diode having an anode electrically connected to the source of the first transistor and a cathode electrically connected to ground; and a first capacitor having a first terminal to which a pulse signal obtained from a digital signal is applied and a second terminal electrically connected to the source of the first transistor and the anode of the first diode, wherein the second circuit includes: a second diode having an anode electrically connected to the source of the second transistor and a cathode electrically connected to ground; and a second capacitor having a first terminal to which a converted version of the pulse signal is applied and a second terminal electrically connected to the source of the second transistor and the anode of the second diode.

[0065] Example 8. The level shifter of Example 7, wherein the gate of the first transistor is electrically connected to a fixed DC voltage less than the diode voltage, and wherein the gate of the second transistor is electrically connected to a fixed DC voltage less than the diode voltage.

[0066] Example 9. The level shifter of Example 7, wherein the gate of the first transistor is biased with a diode voltage, and wherein the gate of the second transistor is biased with a diode voltage.

[0067] Example 10. A level converter comprising: a differential detector; a first transistor having a drain electrically connected to a first node of the differential detector, a gate electrically connected to ground or a fixed DC voltage, and a source; a second transistor having a drain electrically connected to a second node of the differential detector, a gate electrically connected to ground or a fixed DC voltage that is the same as or different from that of the first transistor, and a source; a first capacitor having a first terminal and a second terminal, the second terminal being electrically connected to the source of the first transistor; a first switching device electrically connected between a first DC supply voltage or a first ground reference and a first terminal of the first capacitor; a second switching device electrically connected between the first terminal of the first capacitor and the ground or a bootstrap node; a third switching device electrically connected between the second terminal of the first capacitor and the ground or the bootstrap node; a second capacitor having a first terminal and a second terminal, the second terminal being electrically connected to the source of the second transistor; a fourth switching device electrically connected between a second DC supply voltage or a second ground reference and the first terminal of the second capacitor; a fifth switching device electrically connected between the first terminal of the second capacitor and the ground or the bootstrap node; and a sixth switching device electrically connected between the second terminal of the second capacitor and the ground or the bootstrap node.

[0068] Example 11. A level converter according to Example 10, wherein the first switching device includes: a first PMOS transistor having a positive pulse gate input electrically connected to the first terminal of the first capacitor, a drain electrically connected to the first DC supply voltage, and a source; and a first inverter formed by a second PMOS transistor and a first NMOS transistor, the first inverter having a positive pulse input, the drain of the second PMOS tube electrically coupled to the source of the first PMOS tube, and the source of the first NMOS transistor being grounded, wherein the second switching device includes: a second NMOS transistor having a grounded gate input, a source electrically connected to the source of the first transistor and the second terminal of the first capacitor, and a drain; and a third PMOS transistor having a grounded gate input, a source electrically connected to the output of the first inverter, and a drain electrically connected to the drain of the second NMOS transistor, wherein the third switching device includes: a third NMOS transistor having a gate electrically connected to the drain of the third PMOS tube and the drain of the second NMOS transistor, a source electrically connected to the source of the first transistor, and a drain electrically connected to ground.

[0069] Example 12. A level converter according to Example 11, wherein the fourth switching device includes: a fourth PMOS transistor having a positive pulse gate input electrically connected to the first terminal of the second capacitor, a drain electrically connected to the second DC supply voltage, and a source; and a second inverter formed by a fifth PMOS transistor and a fourth NMOS transistor, the second inverter having a positive pulse input, the drain of the fifth PMOS transistor electrically coupled to the source of the fourth PMOS transistor, and the source of the fourth NMOS transistor being grounded, wherein the fifth switching device includes: a fifth NMOS transistor having a grounded gate input, a source electrically connected to the source of the second transistor and the second terminal of the second capacitor, and a drain; and a sixth PMOS transistor having a grounded gate input, a source electrically connected to the output of the second inverter, and a drain electrically connected to the drain of the fifth NMOS transistor, wherein the sixth switching device includes: a sixth NMOS transistor having a gate electrically connected to the drain of the sixth PMOS transistor and the drain of the fifth NMOS transistor, a source electrically connected to the source of the second transistor, and a drain electrically connected to ground.

[0070] Example 13. A level converter according to Example 10, wherein the first switching device includes: a first NMOS transistor having a negative pulse gate input electrically connected to the first terminal of the first capacitor, a source electrically connected to the first ground reference, and a drain; and a first inverter formed by a second NMOS transistor and a first PMOS transistor, the first inverter having a negative pulse input, the source of the second NMOS tube electrically coupled to the drain of the first NMOS transistor, and the drain of the first PMOS tube electrically connected to the bootstrap node, wherein the second switching device includes: a second PMOS transistor having a gate electrically connected to the bootstrap node, a source electrically connected to the second terminal of the first capacitor, and a drain; and a third NMOS transistor having a gate electrically connected to the bootstrap node, a source electrically connected to the output of the first inverter, and a drain electrically connected to the drain of the second PMOS transistor, wherein the third switching device includes: a third PMOS transistor having a gate electrically connected to the drain of the third NMOS transistor and the drain of the second PMOS transistor, a source electrically connected to the second terminal of the first capacitor, and a drain electrically connected to the bootstrap node.

[0071] Example 14. A level converter according to Example 13, wherein the fourth switching device includes: a fourth NMOS transistor having a negative pulse gate input electrically connected to the first terminal of the second capacitor, a source electrically connected to the second ground reference, and a drain; and a second inverter formed by a fifth NMOS transistor and a fourth PMOS transistor, the second inverter having a negative pulse input, the source of the fifth NMOS transistor electrically coupled to the drain of the fourth NMOS transistor, and the drain of the fourth PMOS transistor electrically connected to the bootstrap node, wherein the fifth switching device includes: a fifth PMOS transistor having a gate electrically connected to the bootstrap node, a source electrically connected to the second terminal of the second capacitor, and a drain; and a sixth NMOS transistor having a gate electrically connected to the bootstrap node, a source electrically connected to the output of the second inverter, and a drain electrically connected to the drain of the fifth PMOS transistor, wherein the sixth switching device includes: a sixth PMOS transistor having a gate electrically connected to the drain of the sixth NMOS transistor and the drain of the fifth PMOS transistor, a source electrically connected to the second terminal of the second capacitor, and a drain electrically connected to the bootstrap node.

[0072] Example 15. A power converter comprising: a high-side power switching device; a gate driver configured to drive the gate of the high-side power switching device; and a level converter configured to convert a digital signal input to the level converter to a voltage domain of the gate driver, wherein the level converter comprises: a differential detector; a first transistor having a drain electrically connected to a first node of the differential detector, a gate electrically connected to ground or a fixed DC voltage, and a source; a second transistor having a drain electrically connected to a second node of the differential detector, a gate electrically connected to ground or a fixed DC voltage that is the same as or different from the first transistor, and a source; a first circuit configured to dynamically control a voltage applied to the source of the first transistor based on a digital signal; and a second circuit configured to dynamically control a voltage applied to the source of the second transistor based on the digital signal, wherein the differential detector is configured to convert the digital signal to the voltage domain of the gate driver based on a differential current between the first transistor and the second transistor.

[0073] Example 16. The power converter according to Example 15 further includes: a low-side power switching device electrically connected to the high-side power switching device in a half-bridge configuration; an inductor electrically connected to a switching node between the low-side power switching device and the high-side power switching device; and a capacitor electrically connected between the switching node and a bootstrap node that provides a supply voltage for a gate driver of the high-side power switching device.

[0074] Example 17. A power converter according to Example 16, wherein the differential detector is coupled between the bootstrap node and the first transistor and the second transistor of the level converter, wherein the first transistor and the second transistor of the level converter are coupled between the differential detector and ground, and wherein the differential detector is configured to convert the digital signal to a higher voltage level based on a differential current between the first transistor and the second transistor of the level converter.

[0075] Example 18. A power converter according to Example 16, wherein the differential detector is coupled between ground and a first transistor and a second transistor of the level converter, wherein the first transistor and the second transistor of the level converter are coupled between the differential detector and a bootstrap node, and wherein the differential detector is configured to convert the digital signal to a lower voltage level based on a differential current between the first transistor and the second transistor of the level converter.

[0076] Example 19. A power converter according to any one of Examples 15 to 18, wherein the first circuit of the level converter includes a first capacitor and a first switch network, wherein the second circuit of the level converter includes a second capacitor and a second switch network, wherein, in response to a first transition of the digital signal, the first switch network is configured to connect the first capacitor to the source of the first transistor so that a negative voltage is applied to the source of the first transistor, wherein, after the first transition of the digital signal, the first switch network is configured to pre-charge the first capacitor for a next first transition of the digital signal, wherein, in response to a second transition of the digital signal opposite to the first transition, the second switch network is configured to connect the second capacitor to the source of the second transistor so that a negative voltage is applied to the source of the second transistor, wherein, after the second transition of the digital signal, the second switch network is configured to pre-charge the second capacitor for a next second transition of the digital signal.

[0077] Example 20. A power converter according to Example 19, wherein the first switching network of the level converter includes: a first switching device electrically connected between a first DC supply voltage or a first ground reference and a first terminal of a first capacitor; a second switching device electrically connected between the first terminal of the first capacitor and ground; and a third switching device electrically connected between the second terminal of the first capacitor and ground, wherein the second terminal of the first capacitor is electrically connected to the source of the first transistor, wherein the second switching network of the level converter includes: a fourth switching device electrically connected between a second DC supply voltage or a second ground reference and the first terminal of the second capacitor; a fifth switching device electrically connected between the first terminal of the second capacitor and ground; and a sixth switching device electrically connected between the second terminal of the second capacitor and ground, wherein the second terminal of the second capacitor is electrically connected to the source of the second transistor.

[0078] Example 21. A power converter according to any one of Examples 15 to 20, wherein the first circuit of the level converter includes: a first diode having an anode electrically connected to the source of the first transistor and a cathode electrically connected to ground; and a first capacitor having a first terminal to which a pulse signal obtained from a digital signal is applied and a second terminal electrically connected to the source of the first transistor and the anode of the first diode, wherein the second circuit of the level converter includes: a second diode having an anode electrically connected to the source of the second transistor and a cathode electrically connected to ground; and a second capacitor having a first terminal to which a converted version of the pulse signal is applied and a second terminal electrically connected to the source of the second transistor and the anode of the second diode.

[0079] Terms such as "first", "second", etc. are used to describe various elements, regions, parts, etc., and are not intended to be limiting. Throughout the specification, similar terms refer to similar elements.

[0080] As used herein, the terms "having", "containing", "including", "comprising", etc. are open terms indicating the presence of stated elements or features, but not excluding other elements or features. Unless the context clearly indicates otherwise, the articles "a", "an", and "the" are intended to include the plural as well as the singular.

[0081] Unless otherwise expressly stated, the expression "and / or" should be interpreted as including all possible combinations and disjunctions. For example, the expression "A and / or B" should be interpreted as meaning only A, only B, or both A and B. Unless otherwise expressly stated, the expression "at least one" should be interpreted in the same manner as "and / or". For example, the expression "at least one of A and B" should be interpreted as meaning only A, only B, or both A and B.

[0082] It should be understood that the features of the various embodiments described herein may be combined with each other, unless specifically stated otherwise.

[0083] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various alternatives and / or equivalent implementations may be used to replace the specific embodiments shown and described without departing from the scope of the present invention. The present application is intended to cover any adaptation or variation of the specific embodiments discussed herein. Therefore, the present invention is intended to be limited only by the claims and their equivalents.

Claims

1. A level converter, comprising: Differential detector; a first transistor having a drain electrically connected to the first node of the differential detector, a gate electrically connected to ground or a fixed DC voltage, and a source; a second transistor having a drain electrically connected to the second node of the differential detector, a gate electrically connected to ground or a fixed DC voltage that is the same or different from the first transistor, and a source; a first circuit configured to dynamically control a voltage applied to a source of the first transistor based on a digital signal input to the level shifter; as well as a second circuit configured to dynamically control a voltage applied to a source of the second transistor based on the digital signal, The differential detector is configured to convert the digital signal into different voltage levels based on a differential current between the first transistor and the second transistor.

2. The level converter according to claim 1, in, The first circuit includes a first capacitor and a first switch network, wherein the second circuit comprises a second capacitor and a second switch network, wherein, in response to a first transition of the digital signal, the first switch network is configured to connect the first capacitor to the source of the first transistor so that a negative voltage is applied to the source of the first transistor, wherein, after the first transition of the digital signal, the first switch network is configured to pre-charge the first capacitor for a next first transition of the digital signal, wherein, in response to a second transition of the digital signal opposite to the first transition, the second switch network is configured to connect the second capacitor to the source of the second transistor so that a negative voltage is applied to the source of the second transistor, and Wherein, after the second transition of the digital signal, the second switch network is configured to pre-charge the second capacitor for a next second transition of the digital signal.

3. The level converter according to claim 2, in, The first switch network comprises: a first switching device electrically connected between a first DC supply voltage or a first ground reference and a first terminal of the first capacitor; a second switching device electrically connected between the first terminal of the first capacitor and ground or a bootstrap node; and a third switching device electrically connected between a second terminal of the first capacitor and ground or the bootstrap node, wherein the second terminal of the first capacitor is electrically connected to the source of the first transistor, and Wherein, the second switch network comprises: a fourth switching device electrically connected between a second DC supply voltage or a second ground reference and a first terminal of the second capacitor; a fifth switching device electrically connected between the first terminal of the second capacitor and ground or the bootstrap node; and a sixth switching device electrically connected between the second terminal of the second capacitor and ground or the bootstrap node, The second terminal of the second capacitor is electrically connected to the source of the second transistor.

4. The level converter according to claim 1, wherein: The differential detector is coupled between a bootstrap node and the first transistor and the second transistor, wherein the first transistor and the second transistor are coupled between the differential detector and ground, and wherein the differential detector is configured to convert the digital signal to a higher voltage level based on a differential current between the first transistor and the second transistor.

5. The level converter according to claim 1, wherein: The differential detector is coupled between ground and the first transistor and the second transistor, wherein the first transistor and the second transistor are coupled between the differential detector and a bootstrap node, and wherein the differential detector is configured to convert the digital signal to a lower voltage level based on a differential current between the first transistor and the second transistor.

6. The level converter according to claim 1, in, The first circuit includes: a first diode having an anode electrically connected to a source of the first transistor and a cathode electrically connected to ground; and a first capacitor having a first terminal to which a pulse signal derived from the digital signal is applied and a second terminal electrically connected to the source of the first transistor and the anode of the first diode, and Wherein, the second circuit includes: a second diode having an anode electrically connected to the source of the second transistor and a cathode electrically connected to the ground; and a second capacitor having a first terminal to which a converted version of the pulse signal is applied and a second terminal electrically connected to the source of the second transistor and the anode of the second diode.

7. The level converter according to claim 6, wherein: The gate of the first transistor is electrically connected to a fixed DC voltage that is less than a diode voltage, and wherein the gate of the second transistor is electrically connected to a fixed DC voltage that is less than a diode voltage.

8. The level converter according to claim 6, wherein: The gate of the first transistor is biased with a diode voltage, and wherein the gate of the second transistor is biased with a diode voltage.

9. A power converter comprising: High-side power switch device; a gate driver configured to drive a gate of the high-side power switch device; as well as a level converter configured to convert a digital signal input to the level converter into a voltage domain of the gate driver, Wherein, the level converter comprises: Differential detector; a first transistor having a drain electrically connected to the first node of the differential detector, a gate electrically connected to ground or a fixed DC voltage, and a source; a second transistor having a drain electrically connected to the second node of the differential detector, a gate electrically connected to ground or a fixed DC voltage that is the same or different from the first transistor, and a source; a first circuit configured to dynamically control a voltage applied to a source of the first transistor based on the digital signal; and a second circuit configured to dynamically control a voltage applied to a source of the second transistor based on the digital signal, The differential detector is configured to convert the digital signal into a voltage domain of the gate driver based on a differential current between the first transistor and the second transistor.

10. The power converter of claim 9, further comprising: a low-side power switch device electrically connected to the high-side power switch device in a half-bridge configuration; an inductor electrically connected to a switch node between the low-side power switch device and the high-side power switch device; as well as A capacitor is electrically connected between the switch node and a bootstrap node, the bootstrap node providing a supply voltage for a gate driver of the high-side power switch device.

11. The power converter according to claim 10, wherein: The differential detector is coupled between the bootstrap node and the first transistor and the second transistor of the level converter, wherein the first transistor and the second transistor of the level converter are coupled between the differential detector and ground, and wherein the differential detector is configured to convert the digital signal to a higher voltage level based on a differential current between the first transistor and the second transistor of the level converter.

12. The power converter according to claim 10, wherein: The differential detector is coupled between ground and the first transistor and the second transistor of the level converter, wherein the first transistor and the second transistor of the level converter are coupled between the differential detector and the bootstrap node, and wherein the differential detector is configured to convert the digital signal to a lower voltage level based on a differential current between the first transistor and the second transistor of the level converter.

13. The power converter according to claim 9, in, The first circuit of the level converter comprises a first capacitor and a first switch network, wherein the second circuit of the level converter comprises a second capacitor and a second switch network, wherein, in response to a first transition of the digital signal, the first switch network is configured to connect the first capacitor to the source of the first transistor so that a negative voltage is applied to the source of the first transistor, wherein, after the first transition of the digital signal, the first switch network is configured to pre-charge the first capacitor for a next first transition of the digital signal, wherein, in response to a second transition of the digital signal opposite to the first transition, the second switch network is configured to connect the second capacitor to the source of the second transistor so that a negative voltage is applied to the source of the second transistor, and Wherein, after the second transition of the digital signal, the second switch network is configured to pre-charge the second capacitor for a next second transition of the digital signal.

14. The power converter according to claim 13, in, The first switch network of the level converter comprises: a first switching device electrically connected between a first DC supply voltage or a first ground reference and a first terminal of the first capacitor; a second switching device electrically connected between the first terminal of the first capacitor and ground; and a third switching device electrically connected between the second terminal of the first capacitor and ground, wherein the second terminal of the first capacitor is electrically connected to the source of the first transistor, and Wherein, the second switch network of the level converter comprises: a fourth switching device electrically connected between a second DC supply voltage or a second ground reference and a first terminal of the second capacitor; a fifth switching device electrically connected between the first terminal of the second capacitor and ground; and a sixth switching device electrically connected between the second terminal of the second capacitor and ground, The second terminal of the second capacitor is electrically connected to the source of the second transistor.

15. The power converter according to claim 9, in, The first circuit of the level converter includes: a first diode having an anode electrically connected to the source of the first transistor and a cathode electrically connected to the ground; and a first capacitor having a first terminal to which a pulse signal derived from the digital signal is applied and a second terminal electrically connected to the source of the first transistor and the anode of the first diode, and Wherein, the second circuit of the level converter includes: a second diode having an anode electrically connected to the source of the second transistor and a cathode electrically connected to the ground; and a second capacitor having a first terminal to which a converted version of the pulse signal is applied and a second terminal electrically connected to the source of the second transistor and the anode of the second diode.

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