Hybrid modulation strategy for neutral-point voltage balance control and common-mode voltage suppression of three-level inverter

Abstract

The invention discloses a hybrid modulation strategy for neutral-point voltage balance control and common-mode voltage suppression of a three-level inverter, and belongs to the technical field of power electronics. In order to solve the problems that the neutral-point voltage of a three-level inverter is unbalanced and the common-mode voltage is large under traditional modulation, the invention provides a novel modulation strategy formed by mixing virtual space vector modulation and intermittent modulation, and according to virtual space vector modulation, space vectors with small common-mode voltage are selected to construct virtual small vectors and middle vectors; adjusting the midpoint current through the midpoint voltage control parameter; dPWMA capable of suppressing common-mode voltage is selected for intermittent modulation. According to the hybrid modulation strategy, common-mode voltage suppression can be kept, when the neutral-point voltage is balanced, DPWMA is selected to reduce switching loss, and when the neutral-point voltage is unbalanced, a modulation method which is more effective for recovering balance of the neutral-point voltage is selected to achieve the purpose of faster realization of neutral-point voltage balance.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronics, and in particular relates to a hybrid modulation strategy for midpoint voltage balance control and common mode voltage suppression of a three-level inverter. Background Art

[0002] When the DC side bus voltage is the same, compared with the two-level topology, the three-level topology has the characteristics of small voltage stress of switching devices, less output harmonic content, and small voltage jump. It is widely used in wind power, photovoltaics, and reactive power compensation.

[0003] In practical applications, the neutral point clamped (NPC) three-level topology is prone to imbalanced midpoint voltage due to differences in modulation strategies and DC side capacitor parameters, which in turn leads to poor output harmonic performance, uneven voltage on power devices, and affects system safety. The three-phase three-level inverter system using conventional modulation methods will generate a large common-mode (CM) voltage.

[0004] In three-level inverters, the applicable modulation strategies include carrier-based PWM (CBPWM) and space vector PWM (SVPWM). Many literatures have proved the intrinsic equivalence between CBPWM and SVPWM. Virtual Space Vector PWM (VSVPWM) modulation strategy synthesizes basic vectors into new virtual vectors based on SVPWM, and controls the midpoint voltage balance by adjusting the action time of the vector. Although this method can achieve midpoint voltage balance within the full modulation ratio and full power factor range, the switching loss is increased compared with SVPWM. Some literatures abandon the use of space vectors with large common-mode voltage, reduce the common-mode voltage to half of the original, and control the midpoint voltage balance by designing virtual vectors. Discontinuous PWM (DPWM) is based on CBPWM, and by injecting appropriate zero-sequence voltage, a certain phase in the switching cycle is clamped at a fixed level. Compared with the continuous modulation strategy, DPWM has fewer switching times and higher system efficiency, but it is difficult to control the midpoint balance in some cases. Some literature proposes a hybrid modulation strategy of DPWM1 and DPWM3 using hysteresis switching based on the opposite effects of different DPWM strategies, such as DPWM1 and DPWM3, on the midpoint voltage. In order to avoid additional switching actions caused by algorithm switching, the common vector of the two algorithms is selected as the switching vector.

[0005] For photovoltaic systems, there is parasitic capacitance between photovoltaic modules and the earth. The common-mode voltage generates leakage current through the parasitic capacitance, affecting the output waveform. For electric drive systems, the common-mode voltage generates shaft current on the motor shaft through the parasitic capacitance inside the motor, increasing mechanical wear and reducing reliability. In order to control the midpoint voltage balance and reduce the common-mode voltage generated by the three-level inverter, considering economy and practicality, it is often controlled through software methods such as modulation. Therefore, the midpoint voltage control and common-mode voltage suppression of the three-level inverter have important engineering significance. Summary of the invention

[0006] In view of the shortcomings of space vector PWM technology, the present invention proposes a VSVPWM method for suppressing common-mode voltage based on SVPWM, namely CMR-VSVPWM (Common-Mode Reduced VSVPWM), and can control the midpoint current; further, combined with the DPWMA method based on CBPWM, in order to reduce the switching loss of CMR-VSVPWM and keep the fundamental voltage amplitude consistent, a hybrid modulation strategy HPWM (Hybrid PWM) based on DPWMA space vectorization (Space Vector DPWMA, SVDPWMA) and CMR-VSVPWM is proposed, the purpose of which is to judge whether to switch in the next switching cycle according to the midpoint voltage and the amount of charge flowing through the midpoint, and to more effectively control the midpoint voltage balance on the basis of suppressing the common-mode voltage.

[0007] In order to achieve the above-mentioned purpose, the present invention adopts the following technical scheme:

[0008] The present invention proposes a hybrid modulation strategy for midpoint voltage balance control and common mode voltage suppression of a three-level inverter, which is applicable to a T-type three-level inverter. The topology of the T-type three-phase three-level inverter includes: each phase is composed of two horizontal switch tubes and two vertical switch tubes. C1 and C2 are DC bus capacitors, U dc is the DC side voltage, S xi is the driving signal of the ith switch tube of the xth phase, that is, x=a, b, c, i=1, 2, 3, 4. Assume that when S xi When it is 1, the corresponding switch tube is turned on, S xi When it is 0, the corresponding switch tube is turned off. Analysis shows that each phase can output three levels, namely U dc / 2, 0, -U dc / 2, the corresponding states are P, O, and N, and the corresponding switching functions are 1, 0, and -1.

[0009] Step 1: Determine the relationship between the common mode voltage and the space vector of the T-type three-level inverter and the analysis and balance control of the midpoint voltage of the three-level inverter:

[0010] According to the different phase sequences of the three-phase ABC, the three-phase voltage and current can be decomposed into positive sequence components, negative sequence components and zero sequence components, among which the zero sequence voltage is the common mode voltage, which will cause electromagnetic interference, etc.

[0011] Combining Kirchhoff's voltage law, the three-phase voltage balance equation can be listed, and equation (1) is obtained:

[0012]

[0013] In the formula, u XO is the voltage of the X-phase bridge arm output relative to the DC midpoint O, X = A, B, C, R load , L load is the load equivalent resistance and equivalent inductance, i X 、i x are the inverter side current and the load side current respectively.

[0014] When the three-phase load is balanced, the common-mode voltage expression can be obtained from equation (1) and the relationship between the switching state and the output level of the three-level inverter:

[0015]

[0016] Different switching states correspond to different common-mode voltage values. The common-mode voltage values ​​under 27 switching states of the three-level inverter can be obtained. According to the size of the vector, they can be divided into five categories:

[0017] The first type is called large vector, and its corresponding switch states are NPP, PNP, PPN with a common mode voltage of Udc / 6 and switch states are PNN, NPN, NNP with a common mode voltage of -Udc / 6;

[0018] The second type is called the neutral vector, and its corresponding switch states are PON, PNO, OPN, ONP, NOP, and NPO, and the common mode voltage is 0;

[0019] The third category is called positive small vector, and its corresponding switch states are PPO, POP, OPP with a common mode voltage of Udc / 3 and switch states are POO, OPO, OOP with a common mode voltage of Udc / 6;

[0020] The fourth category is called negative small vector, and its corresponding switch states are NNO, NON, ONN with a common mode voltage of -Udc / 3 and switch states are NOO, ONO, OON with a common mode voltage of -Udc / 6;

[0021] The fifth category is called the zero vector, and its corresponding switching state is OOO with a common mode voltage of 0, the switching state is PPP with a common mode voltage of Udc / 2, and the switching state is NNN with a common mode voltage of -Udc / 2.

[0022] Furthermore, the common mode voltage is suppressed, that is, the instantaneous value of the common mode voltage is discarded. dc / 2, ±U dc / 3 space vector, only the remaining 19 space vectors are used, and the maximum common mode voltage is increased from ±U dc / 2 suppression is ±U dc / 6, and eliminating redundant small vectors will not lead to the loss of corresponding vector positions.

[0023] Equations (3) and (4) are the relationship between the current of the DC side capacitor and the midpoint current:

[0024] i o =i cdc1 -i cdc2 (3)

[0025]

[0026] In the formula, i o is the midpoint current, i cdc1 is the current of the DC side capacitor C1, i cdc2 is the current of the DC side capacitor C2, u cdc1 is the voltage of the DC link capacitor C1, u cdc2 is the voltage of the DC link capacitor C2.

[0027] Formula (5) is the midpoint voltage assuming that the capacitance of the two capacitors on the DC side is equal, that is, C1 = C2 = C, and one switching cycle T s Internal output current i x The expression when the magnitude and direction of

[0028]

[0029] In the formula, Q is the amount of charge flowing into the midpoint O in one switching cycle. Therefore, if you want to keep the midpoint voltage balanced within one switching cycle, you need to make Q = 0.

[0030] Step 2: CMR-VSVPWM midpoint voltage control method:

[0031] Step 21, virtual vector synthesis method and area division;

[0032] Definition U ref is the reference voltage vector

[0033]

[0034] The present invention adopts a virtual space vector (hereinafter referred to as CMR-VSVPWM) for suppressing common mode voltage. Formula (7) is the definition of the virtual vector of CMR-VSVPWM in the first large sector. Formula (8) is the midpoint current generated by the virtual small vector and the virtual middle vector of CMR-VSVPWM in the first large sector. The same is true for the other large sectors.

[0035]

[0036] In the formula, K1, K m1 is the midpoint voltage control parameter. Let k N =1-K N , k mN =1-K mN , we know that k N , k mN ∈(0.5,1), where N=1, 2, 3, 4, 5, 6 represents large sectors.

[0037] For the division of small sectors in a large sector, the first large sector is taken as an example, and normalization is performed. In the gh coordinate system based on 60°, the straight line equation can be obtained according to different vector coordinates: 1- 15, and then divided into five small sectors by five straight line equations and the boundary line of the first large sector.

[0038] Step 22, determine the action time calculation and sequence allocation of each vector;

[0039] Determine the reference vector U ref After the area is located, the action time of each virtual vector is calculated according to the nearest three-vector method and the volt-second balance principle. Taking the first large sector and the first small sector as an example, the synthetic reference vector U ref Need U VS1 , U VM1 and U VZ Participate in synthesis, the calculation process is as shown in formula (9)

[0040]

[0041] Repeat the above steps to derive the action time of the remaining small sectors in the first large sector,

[0042] The first large sector and the first small sector, the action time of each vector t1, t2, t3 are respectively

[0043] The first large sector and the second small sector, the action time of each vector t1, t2, t3 are respectively

[0044] The first large sector and the third small sector, the action time of each vector t1, t2, t3 are respectively

[0045] The first large sector and the fourth small sector, the action time of each vector t1, t2, t3 are respectively

[0046] The first large sector and the fifth small sector, the action time of each vector t1, t2, t3 are respectively

[0047] The action time of other large sectors can be deduced by the same method as above.

[0048] Furthermore, after obtaining the action time of each virtual vector, the action order of each basic space vector is allocated. Considering factors such as output harmonic content and switching loss, the following principles should be followed when allocating the action order of the basic space vector:

[0049] (1) The same phase can only switch between PO and ON, but not PN direct switching, that is, PN switching must have a transition state O;

[0050] (2) Each time a switch state change occurs, only one phase of the switch state can change.

[0051] Taking the first large sector as an example, the action order of the CMR-VSVPWM small sector vectors in the first large sector is:

[0052] For the first small sector, the vector sequence is OOO-ONO-PNO-POO-PON-OON-OPN-OON;

[0053] For the second small sector, the vector sequence is OOO-OPO-OPN-OON-PON-POO-PNO-POO;

[0054] For the third small sector, the vector order is OON-OPN-OON-PON-PNN-PNO-POO-PNO-ONO;

[0055] For the 4th small sector, the vector sequence is POO-PNO-POO-PON-PPN-OPN-OON-OPN-OPO;

[0056] For the 5th small sector, the vector order is PNO-PNN-PON-PPN-OPN-PPN-PON-PNN-PNO.

[0057] Step 23: midpoint voltage control method;

[0058] Furthermore, taking the first large sector and the first small sector as an example, the reference voltage U refThe virtual vector is U VS1 , U VM1 and U VZ , U VS1 , U VM1 The amount of charge flowing through the midpoint in one switching cycle is

[0059]

[0060] From formula (10), we can know that the charge Q flowing through the midpoint in one switching cycle is related to the parameters K1 and K m1 , load current and virtual vector action time. The load current is uncontrollable and the vector action time is non-negative. Therefore, the parameters K1 and K can be changed according to the load current. m1 , and then control the midpoint current. Taking the first small sector as an example, let the midpoint voltage threshold be ±P, and assume that the midpoint voltage Δu>p. Knowing that K1 and K m1 ∈(0, 0.5), then K1, K m1 The value range is shown in the following table

[0061]

[0062] Step 3: Analysis and processing based on DPWMA technology:

[0063] Furthermore, compared with the seven-segment wave generation of traditional SVPWM, this method only has five segments, and the number of switching times is reduced by 1 / 3 compared with SVPWM. Among the common DPWM methods, only DPWMA can achieve common-mode voltage suppression. The SV-DPWMA method is similar to CMR-VSVPWM. First, the reference voltage vector is placed in the gh coordinate system and normalized to determine the large and small sectors.

[0064] Taking the first large sector as an example, the first large sector is divided into four small sectors by four identical equilateral triangles. From the origin outward, they are recorded as small sectors 1, 2, 3, and 4. Then, the vector is selected according to the principle of the nearest three vectors, the action time is calculated, and the action order is arranged to be the same as DPWMA, and finally the switching signal is output. Since similar analysis has been completed above, it will not be repeated here. The subsequent operations are the same as traditional SVPWM, so they will not be repeated, and only some results are given.

[0065] The action time of each small sector in the first large sector of SV-DPWMA is

[0066] In the first small sector, the action time t1, t2, and t3 of each vector are U POO :gT s , U OOO :(1-hg)T s , U OON :hT s ;

[0067] In the second small sector, the action time t1, t2, and t3 of each vector are U POO :(1-h)T s , U PON :(h+g-1)T s , U OON :(1-g)T s ;

[0068] In the third small sector, the action time of each vector t1, t2, and t3 are respectively POO :(2-hg)T s , U PON :hT s , U PNN :(g-1)T s ;

[0069] In the fourth small sector, the action time of each vector t1, t2, and t3 are respectively PPN :(h-1)T s , U PON :gT s , U OON :(2-hg)T s .

[0070] Furthermore, the vector order of each small sector is

[0071] For the first small sector, the vector sequence is POO-OOO-OON-OOO-POO;

[0072] For the second small sector, the vector sequence is POO-PON-OON-PON-POO;

[0073] For the third small sector, the vector order is POO-PON-PNN-PON-POO;

[0074] For the 4th small sector, the vector sequence is PPN-PON-OON-PON-PPN.

[0075] Step 4: Hybrid modulation scheme HPWM of CMR-VSVPWM and SV-DPWMA:

[0076] According to the midpoint voltage and the charge Q flowing through the midpoint of CMR-VSVPWM in one switching cycle CMR_VSV and the charge Q flowing through the midpoint of SV-DPWMA SV_D , determines the output of the next switching cycle.

[0077] Assume the midpoint voltage threshold u of the switching strategy limit The midpoint current and charge are positive when they flow out of the midpoint. At this time, the midpoint voltage Δu and ±u limitThere are two situations:

[0078] (1) When |Δu|>u limit , that is, the amplitude of the DC side capacitor voltage difference is greater than the midpoint voltage threshold. limit For example, at this time, the midpoint current is greater than zero. To ensure voltage balance, the upper capacitor C should be dc1 Discharge, lower capacitor C dc2 Charging, the amount of charge flowing out of the midpoint is less than zero. If the amount of charge Q flowing through the midpoint of CMR-VSVPWM in one switching cycle CMR_VSV Less than the charge Q flowing through the midpoint of SV-DPWMA SV_D , then the next switching cycle uses CMR-VSVPWM modulation; if the charge amount Q flowing through the midpoint of CMR-VSVPWM in a switching cycle CMR_VSV Greater than or equal to the charge Q flowing through the midpoint of SV-DPWMA SV_D , then the next switching cycle uses SV-DPWMA modulation, that is, the modulation method with small charge amount is selected for the next switching cycle modulation. Δu<-u limit Similarly;

[0079] (2) When |Δu|≤u limi t, there is no need to control the midpoint voltage at this time, and considering reducing the number of switching times, SV-DPWMA modulation is selected for the next switching cycle.

[0080] The hybrid modulation strategy of three-level inverter midpoint voltage balance control and common mode voltage suppression described in the present invention can be used in power conversion occasions such as multi-level frequency converters, photovoltaic inverters, energy storage converters, electric vehicle chargers and uninterruptible power supplies (UPS).

[0081] Compared with the prior art, the present invention has the following beneficial effects:

[0082] 1. On the basis of ensuring common-mode voltage suppression, compared with traditional VSVPWM, HPWM can effectively reduce the number of switches in a unit switching cycle and achieve midpoint voltage balance more quickly;

[0083] 2. Compared with SV-DPWMA, HPWM can achieve mid-point voltage balance and the mid-point voltage amplitude is smaller. BRIEF DESCRIPTION OF THE DRAWINGS

[0084] Figure 1 It is the topology diagram of T-type three-phase three-level inverter;

[0085] Figure 2 A schematic diagram of a hybrid modulation strategy control method for a three-level inverter applied by the present invention;

[0086] Figure 3It is the small sector division diagram of the first large sector of CMR-VSVPWM;

[0087] Figure 4 It is the DPWMA clamping area diagram;

[0088] Figure 5 It is the HPWM switching flow chart;

[0089] Figure 6 When the modulation ratio m=0.8, the simulated waveforms of the A-phase output voltage of the four modulation strategies are shown;

[0090] Figure 7 The CM voltage simulation waveforms of the four modulation strategies when the modulation ratio m=0.8;

[0091] Figure 8 is the change of NP voltage when the modulation ratio m=0.4;

[0092] Fig. 9 is the change of NP voltage when the modulation ratio m=0.8;

[0093] Fig.10 is the number of A-phase switches under different modulation ratios within the fundamental wave period. DETAILED DESCRIPTION

[0094] The specific implementation of the present invention will be described below in conjunction with the accompanying drawings.

[0095] Taking the T-NPC three-level topology as an example, the present invention analyzes the VSVPWM method for suppressing common-mode voltage based on SVPWM, namely CMR-VSVPWM, and the DPWMA method based on CBPWM. In order to reduce the switching loss of CMR-VSVPWM and keep the fundamental voltage amplitude consistent, DPWMA space vectorization and a hybrid modulation strategy HPWM of CMR-VSVPWM and SVDPWMA are proposed. This strategy determines whether to switch in the next switching cycle based on the midpoint voltage and the amount of charge flowing through the midpoint. Finally, the correctness and feasibility of the proposed modulation strategy are verified by simulation.

[0096] like Figure 1 The figure shows the topology of a T-type three-phase three-level inverter. Each phase consists of two horizontal switches and two vertical switches. C1 and C2 are DC bus capacitors. U dc is the DC side voltage, S xi is the driving signal of the ith switch tube of the xth phase, that is, x=a,b,c,i=1,2,3,4. Assume that when S xi When it is 1, the corresponding switch tube is turned on, S xi When it is 0, the corresponding switch tube is turned off. Analysis shows that each phase can output three levels, namely U dc / 2, 0, -U dc / 2, the corresponding states are P, O, and N, and the corresponding switching functions are 1, 0, and -1.

[0097] Figure 2 This is a schematic diagram of a three-level inverter hybrid modulation strategy control method applied by the present invention. The specific operation steps are as follows:

[0098] S1. Determine the relationship between the common mode voltage and the space vector of the T-type three-level inverter and the analysis and balance control of the midpoint voltage of the three-level inverter:

[0099] According to the different phase sequences of the three-phase ABC, the three-phase voltage and current can be decomposed into positive sequence components, negative sequence components and zero sequence components, among which the zero sequence voltage is the common mode voltage, which will cause electromagnetic interference, etc.

[0100] Combination Figure 1 The topological structure of the T-type three-phase three-level inverter and Kirchhoff's voltage law can list the three-phase voltage balance equation, and get equation (1):

[0101]

[0102] In the formula, u XO is the voltage of the X-phase bridge arm output relative to the DC midpoint O, X = A, B, C, R load , L load is the load equivalent resistance and equivalent inductance, i X 、i x are the inverter side current and the load side current respectively.

[0103] When the three-phase load is balanced, the common-mode voltage expression can be obtained from equation (1) and the relationship between the switching state and the output level of the three-level inverter:

[0104]

[0105] Different switching states correspond to different common-mode voltage values. The common-mode voltage values ​​of the three-level inverter under 27 switching states can be obtained. According to the size of the vector, the vector can be classified as shown in Table I below.

[0106]

[0107] Furthermore, the common mode voltage is suppressed, that is, the instantaneous value of the common mode voltage is discarded. dc / 2, ±U dc / 3 space vector, only the remaining 19 space vectors are used, and the maximum common mode voltage is increased from ±U dc / 2 suppression is ±U dc / 6, and eliminating redundant small vectors will not lead to the loss of corresponding vector positions.

[0108] The relationship between the current of the DC side capacitor and the midpoint current can be expressed as

[0109]

[0110] In the formula, i o is the midpoint current, i cdc1 is the current of the DC side capacitor C1, i cdc2 is the current of the DC side capacitor C2, u cdc1 is the voltage of the DC link capacitor C1, u cdc2 is the voltage of the DC link capacitor C2.

[0111] At the midpoint voltage, assume that the capacitance of the two capacitors on the DC side is equal, that is, C1 = C2 = C, and a switching cycle T s Internal output current i x The expression of the magnitude and direction approximation invariant

[0112]

[0113] In the formula, Q is the amount of charge flowing into the midpoint O in one switching cycle. Therefore, if you want to keep the midpoint voltage balanced within one switching cycle, you need to make Q = 0.

[0114] S2, CMR-VSVPWM midpoint voltage control method:

[0115] S21, virtual vector synthesis method and area division;

[0116] Definition U ref is the reference voltage vector

[0117]

[0118] The present invention adopts a virtual space vector to suppress the common mode voltage. Formula (6) is the definition of the virtual vector of CMR-VSVPWM in the first large sector. Formula (7) is the midpoint current generated by the virtual small vector and the virtual middle vector of CMR-VSVPWM in the first large sector. The same is true for the other large sectors.

[0119]

[0120] In the formula, K1, K m1 is the midpoint voltage control parameter. Let k N =1-K N , k mN =1-K mN , we know that k N , k mN ∈(0.5, 1), where N = 1, 2, 3, 4, 5, 6 represents a large sector.

[0121] Figure 3The CMR-VSVPWM is based on the gh coordinate system of 60°, and the small sectors of the first large sector are divided and normalized, where g and h are the coordinate components of the reference voltage vector in the gh coordinate system. The above processing is convenient for subsequent calculations and processing, which can not only reduce a large number of trigonometric function calculations in the conventional 90° coordinate system, but also make the vector coordinates clear and the small sector division simple. According to different vector coordinates, the linear equations l1-l5 are obtained to divide the small sectors.

[0122] S22, determining the action time calculation and sequence allocation of each vector;

[0123] Determine the reference vector U ref After the area is located, the action time of each virtual vector is calculated according to the nearest three-vector method and the volt-second balance principle. Taking the first large sector and the first small sector as an example, the synthetic reference vector U ref Need U VS1 , U VM1 and U VZ Participate in synthesis, the calculation process is as shown in formula (8)

[0124]

[0125] The action time of the remaining small sectors in the first large sector is derived, and the calculation results are shown in Table II below

[0126]

[0127] The action time of other large sectors can be deduced by the same method as above.

[0128] Furthermore, after obtaining the action time of each virtual vector, the action order of each basic space vector is allocated. Considering factors such as output harmonic content and switching loss, the following principles should be followed when allocating the action order of the basic space vector:

[0129] (1) The same phase can only switch between PO and ON, but not PN direct switching, that is, PN switching must have a transition state O;

[0130] (2) Each time a switch state change occurs, only one phase of the switch state can change.

[0131] Taking the first large sector as an example, the order of action of the CMR-VSVPWM small sector vectors in the first large sector is shown in Table III

[0132] Small sector Vector Order 1 OOO-ONO-PNO-POO-PON-OON-OPN-OON 2 OOO-OPO-OPN-OON-PON-POO-PNO-POO 3 OON-OPN-OON-PON-PNN-PNO-POO-PNO-ONO 4 POO-PNO-POO-PON-PPN-OPN-OON-OPN-OPO 5 PNO-PNN-PON-PPN-OPN-PPN-PON-PNN-PNO

[0133] S23, midpoint voltage control method;

[0134] Furthermore, taking the first large sector and the first small sector as an example, the reference voltage Uref The virtual vector is U VS1 , U VM1 and U VZ , U VS1 , U VM1 The amount of charge flowing through the midpoint in one switching cycle is

[0135]

[0136] From formula (9), we can know that the charge Q flowing through the midpoint in one switching cycle is related to the parameters K1 and K m1 , load current and virtual vector action time. The load current is uncontrollable and the vector action time is non-negative. Therefore, the parameters K1 and K can be changed according to the load current. m1 , and then control the midpoint current. Taking the first small sector as an example, let the midpoint voltage threshold be ±p, and assume that the midpoint voltage Δu>p. Knowing that K1 and K m1 ∈(0, 0.5), then K1, K m1 The value range is shown in Table IV below, and the same applies when the midpoint voltage Δu<-p.

[0137]

[0138] S3. Analysis and processing based on DPWMA technology:

[0139] Furthermore, compared with the traditional SVPWM's seven-segment wave generation, this method only has five segments, and the number of switching times is reduced by 1 / 3 compared with SVPWM. Among the common DPWM methods, only DPWMA can achieve common-mode voltage suppression. Figure 4 The SV-DPWMA method is similar to the CMR-VSVPWM method. First, the reference voltage vector is placed in the gh coordinate system and normalized to determine the large and small sectors.

[0140] Taking the first large sector as an example, the first large sector is divided into four small sectors by four identical equilateral triangles. From the origin outward, they are recorded as small sectors 1, 2, 3, and 4. Then, the vector is selected according to the principle of the nearest three vectors, the action time is calculated, and the action order is arranged to be the same as DPWMA, and finally the switching signal is output. Since similar analysis has been completed above, it will not be repeated here. The subsequent operation is the same as the traditional SVPWM, so it will not be repeated. Only some results are given as shown in Table V

[0141] Small sector <![CDATA[t1]]> <![CDATA[t2]]> <![CDATA[t3]]> Vector Order 1 <![CDATA[U POO :gT s ]]> <![CDATA[U OOO :(1-g-h)T s ]]> <![CDATA[U OON :hT s ]]> POO-OOO-OON-OOO-POO 2 <![CDATA[U POO :(1-h)T s ]]> <![CDATA[U PON :(g+h-1)T s ]]> <![CDATA[U OON :(1-g)T s ]]> POO-PON-OON-PON-POO 3 <![CDATA[U POO :(2-g-h)T s ]]> <![CDATA[U PON :hT s ]]> <![CDATA[U PNN :(g-1)T s ]]> POO-PON-PNN-PON-POO 4 <![CDATA[U PPN :(h-1)T s ]]> <![CDATA[U PON :gT s ]]> <![CDATA[U OON :(2-g-h)T s ]]> PPN-PON-OON-PON-PPN

[0142] Hybrid modulation scheme HPWM of S4, CMR-VSVPWM and SV-DPWMA:

[0143] According to the midpoint voltage and the charge Q flowing through the midpoint of CMR-VSVPWM in one switching cycle CMR _ VSV and the charge Q flowing through the midpoint of SV-DPWMA SV_D , determines the output of the next switching cycle.

[0144] Figure 5 This is the implementation flow chart of HPWM. Assume that the midpoint voltage threshold u of the switching strategy limit The midpoint current and charge are positive when they flow out of the midpoint. At this time, the midpoint voltage Δu and ±u limit There are two situations:

[0145] (1) When |Δu|>u limit , that is, the amplitude of the DC side capacitor voltage difference is greater than the midpoint voltage threshold. limit For example, at this time, the midpoint current is greater than zero. To ensure voltage balance, the upper capacitor C should be dc1 Discharge, lower capacitor C dc2 Charging, the amount of charge flowing out of the midpoint is less than zero. If the amount of charge Q flowing through the midpoint of CMR-VSVPWM in one switching cycle CMR_VVC Less than the charge Q flowing through the midpoint of SV-DPWMA SV_D , then the next switching cycle uses CMR-VSVPWM modulation; if the charge amount Q flowing through the midpoint of CMR-VSVPWM in a switching cycle CMR_VSV Greater than or equal to the charge Q flowing through the midpoint of SV-DPWMA SV_D , then the next switching cycle uses SV-DPWMA modulation, that is, the modulation method with small charge amount is selected for the next switching cycle modulation. Δu<-u limit Similarly;

[0146] (2) When |Δu|≤u limit At this time, there is no need to control the midpoint voltage. Consider reducing the number of switching times and choose to use SV-DPWMA modulation in the next switching cycle.

[0147] The hybrid modulation strategy of three-level inverter midpoint voltage balance control and common mode voltage suppression described in this embodiment can be used in power conversion occasions such as multi-level inverters, photovoltaic inverters, energy storage converters, electric vehicle chargers and uninterruptible power supplies (UPS).

[0148] Use Matlab / Simulink software to build a simulation model. The simulation parameters are shown in the following table VI.

[0149] Simulation parameters Numeric <![CDATA[DC-side voltage U dc > 600V <![CDATA[Switching frequency f s > 25kHz <![CDATA[DC-side capacitor C dc1 , C dc2 > 5000μF <![CDATA[Filter inductor L f > 4.5mH <![CDATA[Filter capacitor C f > 20μF Load resistance R 10Ω Load inductance L 2mH

[0150] Figure 6The A-phase output voltage waveforms of the four modulation strategies are shown when the modulation ratio m=0.8 and the input unit amplitude reference sine signal. It can be seen that under the same conditions, the output voltage amplitude of the SV-DPWMA strategy is about 1.15 times that of the CB-DPWMA strategy, which is consistent with the amplitude of the CMR-VSVPWM.

[0151] Figure 7 The CM voltage waveforms of the four modulation strategies are shown when m = 0.8. In practical applications, the states PPP and NNN are not used, which means that ±U d Therefore, the peak CM voltage of the conventional SVPWM is ±200V, that is, ±U dc / 3. For the three proposed modulation strategies, the peak CM voltage is limited to ±100V, which is equivalent to ±U dc / 6. This shows that all three proposed strategies effectively eliminate the fundamental vector with large CM voltage, thus reducing the CM voltage from ±U dc / 3 reduced to ±U d c / 6.

[0152] Figure 8 and Fig. 9 They represent the changes in NP voltage observed when the modulation ratio m is 0.4 and 0.8, starting from an initial deviation of 50V, and adding NP voltage control at t = 0s. In the CMR-VSVPWM method, when the NP voltage is unbalanced, the control parameter k N and k mN When set to 5 / 6 or 7 / 12, the NP voltage threshold p is 0.5V. For HPWM, the NP voltage threshold is 0.4V when m=0.4 and 1.5V when m=0.8. As can be seen from the figure, SV-DPWMA has very limited ability in NP voltage balancing. In contrast, CMR-VSVPWM and HPWM can achieve NP voltage balancing at different modulation ratios, where HPWM achieves a faster balancing speed than CMR-VSVPWM. However, due to the characteristics of DPWMA, HPWM introduces low-frequency harmonics in the NP voltage. When the initial value of the NP voltage is the same, a lower modulation ratio will result in a decrease in load current, thereby reducing the impact on the NP voltage. Therefore, the ability to adjust the NP voltage balance is weaker, resulting in a longer adjustment time.

[0153] Fig.10The switching times of the four switches in phase A for the three modulation strategies at different modulation ratios are shown when the initial NP voltage is zero. This indirectly reflects the switching loss of each modulation strategy. As shown in the figure, the proposed modulation strategy has significantly less switching action than CMR-VSVPWM at high modulation ratios, especially at high modulation ratios, with a reduction of up to 32%. Therefore, it can be concluded that under the same operating conditions, HPWM will produce lower switching losses.

[0154] The above specific implementation examples are ideal embodiments of the present invention. Through the above description, relevant personnel can make various changes and modifications without departing from the technical concept of the present invention. The protection scope of the present invention is limited only by the attached claims.

Claims

1. A hybrid modulation strategy for midpoint voltage balance control and common mode voltage suppression of a three-level inverter, characterized in that: The following steps are involved: Step 1: determining the relationship between the common mode voltage and the space vector of the T-type three-level inverter and the analysis and balance control of the midpoint voltage of the three-level inverter; Step 2: A midpoint voltage control method of a virtual space vector (CMR-VSVPWM) for suppressing common mode voltage, comprising: Step 21: Virtual vector synthesis method and area division Taking the first largest sector as an example, the virtual small vector is synthesized by the original small vector POO and its adjacent small vectors OON and ONO. After synthesis, the direction of the virtual small vector is the same as that of the original small vector POO; the virtual center vector is synthesized by the original center vector PON and its adjacent center vectors OPN and PNO. After synthesis, the direction of the virtual center vector is the same as that of the original center vector PON. Its definition is: The midpoint current generated by the virtual small vector and virtual middle vector of CMR-VSVPWM in the Ith largest sector is: In the formula, K1, K m1 is the midpoint voltage control parameter, let k N =1-K N , k mN =1-K mN , we know that k N , k mN ∈(0.5, 1), where N = 1, 2, 3, 4, 5, 6 represents a large sector; For the division of small sectors in a large sector, the first large sector is taken as an example and normalized. In the gh coordinate system based on 60°, the straight line equations l1-l5 can be obtained according to different vector coordinates. Then, the five straight line equations and the boundary line of the first large sector are used as boundaries to divide the small sectors. The same is true for the remaining large sectors. Step 22: Determine the calculation of the action time of each vector and the sequence allocation Determine the reference vector U ref After the area is located, the action time of each virtual vector is calculated according to the nearest three-vector method and the volt-second balance principle. Taking the first large sector and the first small sector as an example, the reference vector U ref Need U VS1 , U VM1 and U VZ Participate in the synthesis, the calculation process is as follows The action time of the remaining small sectors in the first large sector is derived, and the calculation results are shown in the following table The action time of other large sectors can be deduced in the same way as above steps; Furthermore, after obtaining the action time of each virtual vector, the action order of each basic space vector is allocated. Considering factors such as output harmonic content and switching loss, the following principles should be followed when allocating the action order of the basic space vector: (1) The same phase can only switch between PO and ON, but not PN direct switching, that is, PN switching must have a transition state O; (2) Each time a switch state change occurs, only one phase of the switch state can change; Taking the first large sector as an example, the action order of the CMR-VSVPWM small sector vectors in the first large sector is: For the first small sector, the vector sequence is OOO-ONO-PNO-POO-PON-OON-OPN-OON; For the second small sector, the vector sequence is OOO-OPO-OPN-OON-PON-POO-PNO-POO; For the third small sector, the vector order is OON-OPN-OON-PON-PNN-PNO-POO-PNO-ONO; For the 4th small sector, the vector sequence is POO-PNO-POO-PON-PPN-OPN-OON-OPN-OPO; For the 5th small sector, the vector sequence is PNO-PNN-PON-PPN-OPN-PPN-PON-PNN-PNO; Step 23: Midpoint voltage control method Taking the first large sector and the first small sector as an example, the reference voltage U ref The virtual vector is U VS1 , U VM1 and U VZ , U VS1 , U VM1 The amount of charge flowing through the midpoint in one switching cycle is From the above formula, we can know that the charge Q flowing through the midpoint in one switching cycle is related to the parameters K1 and K m1 , load current and virtual vector action time. The load current is uncontrollable and the vector action time is non-negative. Therefore, the parameters K1 and K can be changed according to the load current. m1 , and then control the midpoint current. Taking the first small sector as an example, the midpoint voltage threshold is set to ±p, and the midpoint voltage Δu>p is assumed. It is known that K1, K m1 ∈(0, 0.5), then K1, K m1 The value range is shown in the following table Step 3: Analysis and processing based on DPWMA technology Furthermore, compared with the seven-segment wave generation of traditional SVPWM, the DPWM technology has only five segments, and the number of switching times is reduced by 1 / 3 compared with SVPWM. Among the common DPWM methods, only DPWMA can achieve common-mode voltage suppression. The SV-DPWMA method is similar to CMR-VSVPWM. First, the reference voltage vector is placed in the gh coordinate system and normalized to determine the large and small sectors; Taking the first large sector as an example, the first large sector is divided into four small sectors by four identical equilateral triangles, which are recorded as small sectors 1, 2, 3, and 4 from the origin outward; then the vector is selected according to the principle of the nearest three vectors, the action time is calculated, and the action order is arranged to be the same as DPWMA, and finally the switching signal is output. Since similar analysis has been completed above, it will not be repeated here. The subsequent operations are the same as those of traditional SVPWM, so they will not be repeated, and only some results are given; The action time of each small sector in the first large sector of SV-DPWMA is In the first small sector, the action time t1, t2, and t3 of each vector are U POO :gT s , U OOO :(1-hg)T s , U OON :hT s ; In the second small sector, the action time t1, t2, and t3 of each vector are U POO :(1-h)T s , U PON :(h+g-1)T s , U OON :(1-g)T s ; In the third small sector, the action time of each vector t1, t2, and t3 are respectively POO :(2-hg)T s , U PON :hT s , U PNN :(g-1)T s ; In the fourth small sector, the action time of each vector t1, t2, and t3 are respectively PPN :(h-1)T s , U PON :gT s , U OON :(2-hg)T s ; Furthermore, the vector order of each small sector is For the first small sector, the vector sequence is POO-OOO-OON-OOO-POO; For the second small sector, the vector sequence is POO-PON-OON-PON-POO; For the third small sector, the vector order is POO-PON-PNN-PON-POO; For the 4th small sector, the vector sequence is PPN-PON-OON-PON-PPN; Step 4: Hybrid modulation scheme HPWM of CMR-VSVPWM and SV-DPWMA According to the midpoint voltage and the charge Q flowing through the midpoint of CMR-VSVPWM in one switching cycle CMR_VSV and the charge Q flowing through the midpoint of SV-DPWMA SV_D , determines the output of the next switching cycle, Assume the midpoint voltage threshold u of the switching strategy limit The midpoint current and charge are positive when they flow out of the midpoint. At this time, the midpoint voltage Δu and ±u limit There are two situations: (1) When |Δu|>u limit , that is, the amplitude of the DC side capacitor voltage difference is greater than the midpoint voltage threshold, with Δu>u limit For example, at this time, the midpoint current is greater than zero. To ensure voltage balance, the upper capacitor C should be dc1 Discharge, lower capacitor C dc2 Charging, the amount of charge flowing out of the midpoint is less than zero; if the amount of charge Q flowing through the midpoint of CMR-VSVPWM in one switching cycle CMR_VSV Less than the charge Q flowing through the midpoint of SV-DPWMA SV_D , then the next switching cycle uses CMR-VSVPWM modulation; if the charge amount Q flowing through the midpoint of CMR-VSVPWM in a switching cycle CMR_VSV Greater than or equal to the charge Q flowing through the midpoint of SV-DPWMA SV_D , then the next switching cycle uses SV-DPWMA modulation, that is, the modulation method with small charge amount is selected for the next switching cycle modulation; Δu<-u limit Similarly; (2) When |Δu|≤u limit At this time, there is no need to control the midpoint voltage. Consider reducing the number of switching times and choose to use SV-DPWMA modulation in the next switching cycle.

2. A hybrid modulation strategy for midpoint voltage balance control and common mode voltage suppression of a three-level inverter as claimed in claim 1, characterized in that: The step 1 comprises: According to the different phase sequences of the three phases ABC, the three phase voltage and current can be decomposed into positive sequence component, negative sequence component and zero sequence component. The zero sequence voltage is the common mode voltage, which will cause electromagnetic interference, etc. Combining Kirchhoff's voltage law, the three-phase voltage balance equation can be listed as follows: In the formula, u XO is the voltage of the X-phase bridge arm output relative to the DC midpoint O, X = A, B, C, R load , L load is the load equivalent resistance and equivalent inductance, i X 、i x are the inverter side current and the load side current respectively, When the three-phase load is balanced, the common-mode voltage expression can be obtained from the above formula and the relationship between the switching state and the output level of the three-level inverter: Different switching states correspond to different common-mode voltage values. The common-mode voltage values ​​under 27 switching states of the three-level inverter can be obtained. According to the size of the vector, they can be divided into five categories: Furthermore, the common mode voltage is suppressed, that is, the instantaneous value of the common mode voltage is discarded. dc / 2, ±U dc / 3 space vector, only the remaining 19 space vectors are used, and the maximum common mode voltage is increased from ±U dc / 2 suppression is ±U dc / 6, and eliminating redundant small vectors will not lead to the loss of corresponding vector positions, At the midpoint voltage, assume that the capacitance of the two capacitors on the DC side is equal, that is, C1 = C2 = C, and a switching cycle T s Internal output current i x The expression of the magnitude and direction approximation invariant In the formula, i cdc1 and u cdc1 are the current and voltage of the DC side capacitor C1, i cdc2 and u cdc2 are the current and voltage of the DC side capacitor C2 respectively, and Q is the amount of charge flowing into the midpoint O in one switching cycle. Therefore, if you want to keep the midpoint voltage balanced within a switching cycle, you need to make Q=0.

3. A multi-level inverter, a photovoltaic inverter, an energy storage converter, an electric vehicle charger and an uninterruptible power supply (UPS) using a hybrid modulation strategy of a three-level inverter midpoint voltage balance control and common mode voltage suppression as described in claim 1.

Images