Wafer-level packaging structure of filter and packaging method thereof

Abstract

The invention provides a filter wafer level packaging structure. The filter wafer level packaging structure comprises a substrate; the carrier structure comprises an interdigital transducer, a bonding pad metal layer, a passivation layer, a dry film and a cover plate which are sequentially arranged on one side of the substrate from bottom to top; the metal protection layer is coated on the carrier structure; the conductive connecting piece penetrates through the substrate from one side deviating from the carrier structure and is electrically connected with the interdigital transducer; the technical effects that the overall size of the filter wafer-level packaging structure is reduced, the reliability of the filter wafer-level packaging structure is improved, and the service life of the filter wafer-level packaging structure is prolonged are achieved.

Description

Technical Field

[0001] The present application relates to the field of device packaging technology, and in particular to a filter wafer-level packaging structure and a preparation method thereof. Background Art

[0002] This section is intended to provide a background or context to the embodiments of the present application that are recited in the claims. Nothing herein is admitted to be prior art by virtue of its inclusion in this section.

[0003] With the rapid development of 4G and 5G communications, RF devices - filters play a core role in the fields of mobile communications and automotive electronics, so the requirements for the reliability of SAW filters are becoming increasingly higher.

[0004] Current filters such as Figure 1 As shown in the figure, its packaging structure is as follows: a UBM layer is set to achieve a fixed connection between the solder ball / gold ball and the pad metal layer, and the outermost layer is set with a cover plate (also known as a PI layer) made of polyimide material to achieve packaging protection for the entire filter; however, the contact area between the PI layer and the gold ball is limited, so the reliability and stability of the connection between the solder ball / gold ball and the PI layer are poor, which makes the filter easy to damage and shortens its service life.

[0005] Therefore, there is an urgent need to propose a filter wafer-level packaging structure and a packaging method thereof that can solve the above technical problems. Summary of the Invention

[0006] Multiple aspects of the present application provide a filter wafer-level packaging structure and a preparation method thereof, so as to improve the reliability and stability of the filter wafer-level packaging structure and ensure the service life of the filter.

[0007] In one aspect of the present application, a filter wafer-level packaging structure is provided, the filter wafer-level packaging structure comprising:

[0008] substrate;

[0009] A carrier structure, the carrier structure comprising an interdigital transducer, a pad metal layer, a passivation layer, a dry film, and a cover plate, which are sequentially arranged on one side of the substrate from bottom to top;

[0010] A metal protective layer, covering the carrier structure;

[0011] A conductive connecting member passes through the substrate from a side facing away from the carrier structure and is electrically connected to the IDT.

[0012] Furthermore, the conductive connector includes: a conductive through-hole, which passes through the substrate from a side away from the carrier structure to the IDT; and a conductive bump, which is at least partially embedded in the conductive through-hole and electrically connected to the IDT.

[0013] Furthermore, the conductive via includes: a seed layer, which is arranged between the conductive bump and the substrate; wherein the seed layer is made of metal; and the thickness of the seed layer is 1 um to 20 um.

[0014] Furthermore, the IDT includes: a first interdigital electrode lead-out portion; a second interdigital electrode lead-out portion; and electrode fingers located between the first interdigital electrode lead-out portion and the second interdigital electrode lead-out portion.

[0015] Furthermore, the pad metal layer includes: a first pad metal layer, arranged on a side of the first interdigital electrode lead-out portion away from the substrate; and a second pad metal layer, arranged on a side of the second interdigital electrode lead-out portion away from the substrate.

[0016] Furthermore, the passivation layer includes: a first passivation layer covering the interdigital electrode; and a second passivation layer covering the first interdigital electrode lead-out portion and the second interdigital electrode lead-out portion.

[0017] Furthermore, the dry film is coated on the second passivation layer; the dry film, the cover plate and the first passivation layer define a cavity.

[0018] Furthermore, the cover plate and the dry film form a stepped structure.

[0019] Furthermore, the passivation layer is nitride oxide or silicon oxide.

[0020] In another aspect of the present application, a filter wafer-level packaging method is provided, the filter wafer-level packaging method comprising:

[0021] providing a substrate;

[0022] Generating a carrier structure on one side of the substrate, the carrier structure comprising an interdigital transducer, a pad metal layer, a passivation layer, a dry film and a cover plate sequentially arranged on one side of the substrate from bottom to top;

[0023] Coating the carrier structure with a metal protective layer;

[0024] A conductive connecting member is disposed on the substrate, and the conductive connecting member passes through the substrate from a side away from the carrier structure and is electrically connected to the IDT.

[0025] The present application proposes a filter wafer-level packaging structure and a packaging method thereof, the filter wafer-level packaging structure comprising: a substrate; a carrier structure, the carrier structure comprising an IDT, a pad metal layer, a passivation layer, a dry film, and a cover plate arranged sequentially from bottom to top on one side of the substrate; a metal protective layer covering the carrier structure; and a conductive connector passing through the substrate from the side away from the carrier structure and electrically connected to the IDT. Compared to the prior art, on the one hand, the filter wafer-level packaging structure proposed in the present application does not require forming a metal film layer (i.e., UBM layer) and dry film openings on the front surface of the wafer, thereby reducing the tape-out cost;

[0026] On the other hand, the filter wafer-level packaging structure described in the present application prevents external water vapor from entering the core working area of ​​the filter by sputtering a protective layer on the entire surface of the dry film, thereby improving the reliability performance of the filter; on the other hand, the substrate described in the present application uses through-silicon via technology (full name: Through Silicon Via; abbreviated as: TSV) to lead out pins to form conductive bumps, effectively reducing the size of the filter. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, a brief introduction will be given below to the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0028] Other features, objects and advantages of the present application will become more apparent upon reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0029] Figure 1 A schematic structural diagram of a filter in the prior art described in the background art;

[0030] Figure 2 A schematic structural diagram of a filter wafer-level packaging structure provided in one embodiment of the present application;

[0031] Figure 3 A schematic flow chart of a filter wafer-level packaging method provided in yet another embodiment of the present application;

[0032] Figures 4 to 7 A schematic structural diagram of each step of the carrier structure forming process described in the filter wafer-level packaging method provided in one embodiment of the present application;

[0033] The reference numerals are as follows:

[0034] 01-substrate; 03-dry film; 04-cover; 05-metal protective layer; 06-conductive via; 07-conductive bump; 08-seed layer; 09-first interdigitated electrode lead-out portion; 10-second interdigitated electrode lead-out portion; 11-interdigitated pole; 12-first pad metal layer; 13-second pad metal layer; 14-first passivation layer; 15-second passivation layer; 16-cavity; 17-UBM layer.

[0035] The same or similar reference numerals in the drawings represent the same or similar components. DETAILED DESCRIPTION

[0036] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0037] Example 1

[0038] Figure 2 A filter wafer-level packaging structure provided by an embodiment of the present application is shown, and the filter wafer-level packaging structure includes:

[0039] Substrate 01;

[0040] A carrier structure, the carrier structure comprising an interdigital transducer, a pad metal layer, a passivation layer, a dry film 03 and a cover plate 04 arranged sequentially from bottom to top on one side of the substrate 01;

[0041] A metal protective layer 05, covering the carrier structure;

[0042] A conductive connecting member passes through the substrate 01 from a side facing away from the carrier structure and is electrically connected to the IDT.

[0043] In the present invention, a metal protective layer 05 is introduced as the bonding part of the WLP (Wafer Level Package), and the interdigital electrode lead-out part (the first interdigital electrode lead-out part 09 or the second interdigital electrode lead-out part 10), the pad metal layer (the first pad metal layer 12 or the second pad metal layer 13), the passivation layer, the dry film 03 and the cover plate 04 of the interdigital transducer are stacked in sequence on the substrate 01, so as to form the purpose of bonding with the substrate 01.

[0044] Based on the inherent packaging form, this application coats a metal protective layer 05 on the outside of a carrier structure including a dry film 03. On the one hand, it solves the technical problem of poor filter reliability and stability caused by insufficient dry film support strength in the original single-layer dry film packaging structure. On the other hand, the packaging form of the metal protective layer enhances the airtightness of the entire filter device and avoids the occurrence of filter damage caused by external water vapor entering the interior of the filter.

[0045] In one embodiment, the substrate 01 includes a lithium tantalate (LT) substrate, a lithium niobate (LN) substrate, a POI substrate (prepared using a Smart-Cut process, consisting of a thin layer of piezoelectric single crystal material (such as single crystal lithium tantalate / lithium niobate), a silicon oxide layer and a high-resistance silicon substrate), a bonding substrate, etc.

[0046] In one embodiment, the conductive connector includes: a conductive through-hole 06, which passes through the substrate 01 from the side away from the carrier structure to the IDT; and a conductive bump 07, which is at least partially embedded in the conductive through-hole 06 and electrically connected to the IDT.

[0047] Compared with the original packaging structure in which the conductive bump 07 is set on the top of the pad metal layer by setting a UBM layer to improve the reliability and stability of the filter packaging structure; this application uses silicon through-via technology to embed the conductive connector part at the bottom of the substrate 01, which not only improves the working stability of the filter but also greatly reduces the overall size of the filter.

[0048] In one embodiment, the conductive bumps 07 include but are not limited to solder balls and gold balls.

[0049] In one embodiment, the conductive connection is prepared using through silicon via technology.

[0050] In one embodiment, the conductive via 06 includes: a seed layer 08 disposed between the conductive bump 07 and the substrate 01; wherein the seed layer is made of metal; and the thickness of the seed layer is 1 um to 20 um.

[0051] In one embodiment, the IDT includes: a first interdigital electrode lead-out portion 09 ; a second interdigital electrode lead-out portion 10 ; and electrode fingers located between the first interdigital electrode lead-out portion 09 and the second interdigital electrode lead-out portion 10 .

[0052] It is important to understand that Figure 2The structural schematic diagram shown is a cross-sectional view of the filter wafer-level packaging structure. For the sake of convenience, the interdigital electrode lead-out parts of the interdigital transducer are described as the first interdigital electrode lead-out part and the second interdigital electrode lead-out part. In actual applications, the number of interdigital electrode lead-out parts is one.

[0053] In one embodiment, the pad metal layer includes: a first pad metal layer 12, arranged on the side of the first interdigitated electrode lead portion 09 away from the substrate 01; and a second pad metal layer 13, arranged on the side of the second interdigitated electrode lead portion 10 away from the substrate 01.

[0054] It is important to understand that Figure 2 The structural schematic diagram shown is a cross-sectional view of the filter wafer-level packaging structure. For the sake of convenience, the pad metal layer is divided into a first pad metal layer and a second pad metal layer for explanation. In actual applications, the number of pad metal layers corresponding to the interdigitated electrode lead-out parts is consistent.

[0055] In one embodiment, the projection area of ​​the first pad metal layer 12 in the first direction is no larger than the projection area of ​​the first interdigital electrode lead portion 09 in the first direction; and the projection area of ​​the second pad metal layer 13 in the first direction is no larger than the projection area of ​​the second interdigital electrode lead portion 10 in the first direction. The first direction is a direction perpendicular to the plane of the substrate 01.

[0056] In one embodiment, the passivation layer includes: a first passivation layer 14, covering the interdigital electrode 11; a second passivation layer 15, covering the first interdigital electrode lead-out portion 09 and the second interdigital electrode lead-out portion 10; the passivation layer is provided to protect the interdigital transducer.

[0057] In one embodiment, the dry film 03 is coated on the second passivation layer 15 ; the dry film 03 , the cover plate 04 and the first passivation layer 14 define a cavity 16 .

[0058] In one embodiment, the cover plate 04 and the dry film 03 form a stepped structure. This step-like structure allows the metal protective layer 05 of the carrier structure covering the cover plate 04 and the dry film 03 to have a stepped structure, thereby improving the stability of the metal protective layer 05 and thereby increasing the reliability and service life of the entire filter.

[0059] In one embodiment, the metal protective layer 05 includes a target seed layer and a metal layer. By providing the metal protective layer 05, external water vapor is prevented from entering the interior of the filter and interfering with its core working area (interdigital transducer), thereby improving the product reliability and stability of the filter.

[0060] The target seed layer includes, but is not limited to, being generated by sputtering titanium tungsten or sputtering copper; the metal layer includes, but is not limited to, being generated by electroplating copper, nickel, or gold.

[0061] It should be understood that this application does not limit the thickness and number of target seed layers and metal layers. Those skilled in the art can adaptively adjust the thickness and number of target seed layers and metal layers according to actual application scenarios.

[0062] It should also be understood that the filter wafer-level packaging structure described in this application refers to a filter prepared based on a wafer-level packaging process; the filter described in this application includes but is not limited to a surface acoustic wave filter (full name in English: Surface Acoustic Wave Filter; abbreviated as: SAWF or SAW filter), a temperature-compensated surface acoustic wave filter (full name in English: Temperature Compensated Surface Acoustic Wave Filter; abbreviated as: TC-SAW) and a thin film surface acoustic wave filter (full name in English: Thin-Film Surface Acoustic Wave; abbreviated as: TF-SAW).

[0063] Example 2

[0064] Figure 3 The present application provides a filter wafer-level packaging method, which includes:

[0065] Step S201: providing a substrate;

[0066] Step S202 , generating a carrier structure on one side of the substrate, the carrier structure comprising an interdigital transducer, a pad metal layer, a passivation layer, a dry film, and a cover plate sequentially arranged on one side of the substrate from bottom to top;

[0067] Step S203: coating the carrier structure with a metal protective layer;

[0068] Step S204 : disposing a conductive connector on the substrate, wherein the conductive connector passes through the substrate from a side away from the carrier structure and is electrically connected to the IDT.

[0069] In one embodiment, coating the carrier structure with a metal protective layer includes: sputtering titanium tungsten and / or copper onto the carrier structure to form a seed layer; electroplating copper, nickel, and gold onto the seed layer to form a metal layer; the seed layer and the metal layer constitute a metal protective layer.

[0070] In one embodiment, providing the conductive connector on the substrate includes: forming a through hole on the substrate; forming a seed layer in the through hole; and forming a conductive bump in the seed layer, wherein the conductive bump is electrically connected to the IDT through the seed layer.

[0071] In one embodiment, generating a carrier structure on one side of a substrate includes:

[0072] Step S2031: Figures 4 to 6 As shown, an interdigital transducer, a pad metal layer, a passivation layer and a dry film are formed in sequence from bottom to top on one side of the substrate;

[0073] Step S2032: Figure 7 As shown, a cover plate is formed on the side of the dry film facing away from the substrate.

[0074] In one embodiment, step S2031 includes: forming an IDT on one side of a substrate; forming a passivation layer on a side of the IDT facing away from the substrate, wherein the passivation layer covers the IDT; and removing the dry film in a first area after forming a dry film on a side of the passivation layer facing away from the substrate; wherein the first area is an area on a side of the electrode fingers of the IDT facing away from the substrate.

[0075] In one embodiment, step S2032 includes: etching the edge of the cover plate so that the cover plate and the dry film form a stepped structure.

[0076] Example 3

[0077] The present application proposes a MEMS device, which includes the filter wafer-level packaging structure proposed in the first embodiment.

[0078] In one embodiment, the filter wafer-level packaging structure is prepared by the filter wafer-level packaging method described in Example 2.

[0079] Example 4

[0080] Based on the same inventive concept, an electronic device is also provided in an embodiment of the present application. The method corresponding to the electronic device may be the filter wafer-level packaging method in the aforementioned embodiment, and the principle of solving the problem is similar to that of the method. The electronic device provided in an embodiment of the present application includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the methods and / or technical solutions of the aforementioned multiple embodiments of the present application.

[0081] The electronic device may be a user device, or a device formed by integrating a user device and a network device through a network, or an application running on the above device, or a mobile communication component used in a vehicle. The user device includes but is not limited to various terminal devices such as computers, mobile phones, tablet computers, smart watches, and bracelets, and the network device includes but is not limited to network hosts, single network servers, multiple network server sets, or cloud computing-based computer collections, which can be used to implement some processing functions when setting an alarm. Here, the cloud is composed of a large number of hosts or network servers based on cloud computing (Cloud Computing), wherein cloud computing is a type of distributed computing, a virtual computer composed of a group of loosely coupled computer sets.

[0082] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

[0083] Furthermore, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or devices recited in a device claim may also be implemented by a single unit or device through software or hardware. Terms such as "first" and "second" are used to indicate names and do not imply any particular order.

Claims

1. A filter wafer level packaging structure, characterized in that: The filter wafer level packaging structure comprises: substrate; A carrier structure, the carrier structure comprising an interdigital transducer, a pad metal layer, a passivation layer, a dry film and a cover plate which are sequentially arranged on one side of the substrate from bottom to top; A metal protective layer, covering the carrier structure; A conductive connecting member penetrates the substrate from a side away from the carrier structure and is electrically connected to the IDT.

2. The filter wafer level packaging structure according to claim 1, characterized in that: The conductive connecting member comprises: A conductive through hole extending through the substrate from a side away from the carrier structure to the IDT; A conductive bump is at least partially embedded in the conductive through hole and electrically connected to the interdigital transducer.

3. The filter wafer level packaging structure according to claim 2, characterized in that: The conductive via comprises: A seed layer, disposed between the conductive bump and the substrate; Wherein, the seed layer is made of metal; the thickness of the seed layer is 1um to 20um.

4. The filter wafer level packaging structure according to claim 3, characterized in that: The interdigital transducer comprises: a first interdigital electrode lead-out portion; a second interdigital electrode lead-out portion; The electrode finger is located between the first interdigital electrode lead-out portion and the second interdigital electrode lead-out portion.

5. The filter wafer level packaging structure according to claim 4, characterized in that: The pad metal layer comprises: A first pad metal layer is disposed on a side of the first interdigitated electrode lead-out portion away from the substrate; The second pad metal layer is arranged on a side of the second interdigital electrode lead-out portion away from the substrate.

6. The filter wafer level packaging structure according to claim 5, characterized in that: The passivation layer comprises: A first passivation layer, covering the interdigital poles; The second passivation layer covers the first interdigital electrode lead-out portion and the second interdigital electrode lead-out portion.

7. The filter wafer level packaging structure according to claim 6, characterized in that: The dry film is coated on the second passivation layer; The dry film, the cover plate and the first passivation layer define a cavity.

8. The filter wafer level packaging structure according to claim 7, characterized in that: The cover plate and the dry film form a stepped structure.

9. The filter wafer level packaging structure according to claim 8, characterized in that: The passivation layer is nitride oxide or silicon oxide.

10. A filter wafer level packaging method, characterized in that: The filter wafer level packaging method comprises: providing a substrate; Generating a carrier structure on one side of the substrate, the carrier structure comprising an interdigital transducer, a pad metal layer, a passivation layer, a dry film and a cover plate sequentially arranged on one side of the substrate from bottom to top; Coating the carrier structure with a metal protective layer; A conductive connecting member is disposed on the substrate, and the conductive connecting member penetrates the substrate from a side away from the carrier structure and is electrically connected to the IDT.

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