Hysteresis comparator circuit and system

Abstract

The present application provides a hysteresis comparator circuit and system, which relates to the field of integrated circuit technology, and includes: a differential comparison module, a tail current bias module, an adaptive shunt module and an output module. The output end of the tail current bias module, the first port of the differential comparison module and the second port of the adaptive shunt module are all connected to the first node, and the second port of the differential comparison module is connected to the second port of the output module. When the common-mode input range is normal, the adaptive shunt module is turned off, and the bias current output by the tail current bias module flows to the first port of the differential comparison module. When the common-mode input range is abnormal, the adaptive shunt module is turned on, and the adaptive shunt module is used to extract part of the bias current output by the tail current bias module to reduce the current value flowing to the first port of the differential comparison module. Ensure that the current flowing to the first port of the differential comparison module is weakened by the change in common-mode voltage, thereby improving the common-mode input range of the hysteresis comparator.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more specifically, to a hysteresis comparator circuit and system. Background Technology

[0002] A hysteresis comparator gets its name from the lag between its forward and reverse flip-flop voltages. Because it has a dead-time voltage near zero, it is more suitable for noisy environments. The common-mode input range is a crucial parameter of a hysteresis comparator, affecting its dynamic operating state. The common-mode input range refers to the range of common-mode voltages within which the hysteresis comparator can operate normally; within this range, the comparator can accurately compare two input voltages and output the correct comparison result.

[0003] Existing hysteresis comparators only focus on the static operating state of the transistors, neglecting the dynamic operating state, i.e., whether the hysteresis comparator can switch correctly when the common-mode voltage changes. For example, when a hysteresis comparator is used in an undervoltage protection circuit in a noisy environment, a high switching voltage is required. However, an excessively high switching voltage will reduce the common-mode input range, leading to an abnormal common-mode input range. If the common-mode voltage deviates from this range, the hysteresis comparator will not function properly.

[0004] Therefore, how to improve the common-mode input range of the hysteresis comparator and ensure that the hysteresis comparator can work normally is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a hysteresis comparator circuit and system to improve the common-mode input range of the hysteresis comparator and ensure that the hysteresis comparator can work normally.

[0006] To achieve the above objectives, the technical solution adopted in this application is as follows:

[0007] On the one hand, this application provides a hysteresis comparator circuit, including: a differential comparator module, a tail current bias module, an adaptive shunt module, and an output module;

[0008] The first port of the tail current bias module, the first port of the adaptive shunt module, and the first port of the output module are all connected to the power supply; the output terminal of the tail current bias module, the first port of the differential comparator module, and the second port of the adaptive shunt module are all connected to the first node; the second port of the differential comparator module is connected to the second port of the output module; the third port of the differential comparator module, the third port of the adaptive shunt module, and the third port of the output module are all grounded.

[0009] The tail current bias module is used to provide bias current to the first port of the differential comparator module;

[0010] When the common-mode input range is normal, the adaptive current shunt module is turned off, and the bias current output by the tail current bias module flows to the first port of the differential comparator module.

[0011] When the common-mode input range is abnormal, the adaptive current shunting module is turned on. The adaptive current shunting module is used to extract part of the bias current output by the tail current biasing module to reduce the current value flowing to the first port of the differential comparator module.

[0012] Furthermore, the adaptive current shunt module includes a first current mirror and a second current mirror;

[0013] The first and second ports of the first current mirror are both connected to the power supply, the third port of the first current mirror is connected to the first node, the fourth port of the first current mirror is connected to the first port of the second current mirror, the second port of the second current mirror is connected to the first node, and the third and fourth ports of the second current mirror are both grounded.

[0014] When the common-mode input range is normal, both the first current mirror and the second current mirror are turned off, so that the bias current output by the tail current bias module flows to the first port of the differential comparator module.

[0015] When the common-mode input range is abnormal, both the first current mirror and the second current mirror are turned on. The second port of the second current mirror draws part of the bias current output by the tail current bias module to reduce the current value flowing to the first port of the differential comparator module.

[0016] Furthermore, the first current mirror includes a first PMOS transistor and a second PMOS transistor, and the second current mirror includes a first NMOS transistor and a second NMOS transistor;

[0017] The source of the first PMOS transistor and the source of the second PMOS transistor are both connected to the power supply. The drain of the first PMOS transistor is connected to the first node. The gate of the first PMOS transistor is connected to the drain of the first PMOS transistor and the gate of the second PMOS transistor, respectively.

[0018] The drain of the first NMOS transistor is connected to the drain of the second PMOS transistor, the gate of the first NMOS transistor is connected to the drain of the first NMOS transistor and the gate of the second NMOS transistor, respectively, and the drain of the second NMOS transistor is connected to the first node; the source of the first NMOS transistor and the source of the second NMOS transistor are both grounded.

[0019] Furthermore, the differential comparison module includes an inverting input unit, a non-inverting input unit, a third current mirror, and a fourth current mirror;

[0020] The first port of the inverting input unit and the first port of the non-inverting input unit are both connected to the first node; the first port of the third current mirror, the first port of the fourth current mirror, and the output terminal of the inverting input unit are all connected to the second node; the second port of the third current mirror, the second port of the fourth current mirror, and the output terminal of the non-inverting input unit are all connected to the third node; the third port of the third current mirror, the fourth port of the third current mirror, the third port of the fourth current mirror, and the fourth port of the fourth current mirror are all grounded.

[0021] Furthermore, the inverting input unit includes a third PMOS transistor, the source of which is connected to the first node, the drain of which is connected to the second node, and the gate of which is the inverting input terminal of the differential comparator module.

[0022] The non-inverting input unit includes a fourth PMOS transistor, the source of which is connected to the first node, the drain of which is connected to the third node, and the gate of which is the non-inverting input terminal of the differential comparator module.

[0023] Furthermore, the third current mirror includes a third NMOS transistor and a fourth NMOS transistor. The drain of the third NMOS transistor is connected to the second node, and the gate of the third NMOS transistor is connected to the drain of the third NMOS transistor and the gate of the fourth NMOS transistor, respectively. The drain of the fourth NMOS transistor is connected to the third node, and the sources of the third NMOS transistor and the fourth NMOS transistor are both grounded.

[0024] The fourth current mirror includes a fifth NMOS transistor and a sixth NMOS transistor. The drain of the fifth NMOS transistor is connected to the second node, and the gate of the fifth NMOS transistor is connected to both the drain and gate of the sixth NMOS transistor. The drain of the sixth NMOS transistor is connected to the third node, and the sources of both the fifth and sixth NMOS transistors are grounded.

[0025] Furthermore, the output module includes a fifth current mirror, a seventh NMOS transistor, and an eighth NMOS transistor;

[0026] Both the first port and the second port of the fifth current mirror are connected to the power supply.

[0027] The drain of the seventh NMOS transistor is connected to the third port of the fifth current mirror, the gate of the seventh NMOS transistor is connected to the second node, and the source of the seventh NMOS transistor is grounded.

[0028] The drain of the eighth NMOS transistor is connected to the fourth port of the fifth current mirror as the output terminal of the output module, the gate of the eighth NMOS transistor is connected to the third node, and the source of the eighth NMOS transistor is grounded.

[0029] Furthermore, the fifth current mirror includes a fifth PMOS transistor and a sixth PMOS transistor; the source of the fifth PMOS transistor and the source of the sixth PMOS transistor are both connected to the power supply, the drain of the fifth PMOS transistor is connected to the drain of the seventh NMOS transistor, the gate of the fifth PMOS transistor is connected to the drain of the fifth PMOS transistor and the gate of the sixth PMOS transistor respectively, and the drain of the sixth PMOS transistor is connected to the drain of the eighth NMOS transistor as the output terminal of the output module.

[0030] Furthermore, the tail current bias module includes a seventh PMOS transistor; the source of the seventh PMOS transistor is connected to the power supply, the drain of the seventh PMOS transistor is connected to the first node, and the gate of the seventh PMOS transistor serves as the bias voltage input terminal of the tail current bias module.

[0031] On the other hand, this application also provides a hysteresis comparator system, which includes a hysteresis comparator circuit as described in any of the foregoing embodiments.

[0032] Compared with the prior art, this application has the following advantages:

[0033] This application provides a hysteresis comparator circuit and system, including: a differential comparator module, a tail current bias module, an adaptive shunt module, and an output module. When the common-mode input range is normal, the common-mode voltage is within the common-mode input range. At this time, the adaptive shunt module is turned off, and all the bias current output by the tail current bias module flows to the first port of the differential comparator module, allowing the hysteresis comparator circuit to operate normally. When the common-mode input range is abnormal, i.e., when the common-mode input range decreases, the bias current output by the tail current bias module will increase. To stabilize the current flowing to the first port of the differential comparator module, the adaptive shunt module is turned on. The adaptive shunt module is used to extract a portion of the bias current output by the tail current bias module to reduce the current value flowing to the first port of the differential comparator module. This ensures that the current flowing to the first port of the differential comparator module is less affected by changes in the common-mode voltage, thereby ensuring that the hysteresis comparator circuit can operate normally and improving the common-mode input range of the hysteresis comparator. Attached Figure Description

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0035] Figure 1 A schematic diagram of an undervoltage protection circuit provided in this application;

[0036] Figure 2 One of the schematic diagrams of a hysteresis comparator circuit provided in this application;

[0037] Figure 3 A second schematic diagram of a hysteresis comparator circuit provided in this application;

[0038] Figure 4 A schematic diagram of the structure of a differential comparison module provided in this application;

[0039] Figure 5 A schematic diagram of the structure of an output module provided in this application;

[0040] Figure 6 One of the schematic diagrams of a hysteresis comparator circuit provided in this application;

[0041] Figure 7 This is the second schematic diagram of a hysteresis comparator circuit provided in this application.

[0042] Figure reference numerals: 10-Hysteresis comparator circuit; 100-Differential comparator module; 110-Inverting input unit; 120-Non-Inverting input unit; 130-Third current mirror; 140-Fourth current mirror; 200-Tail current bias module; 300-Adaptive shunt module; 310-First current mirror; 320-Second current mirror; 400-Output module; 410-Fifth current mirror. Detailed Implementation

[0043] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0044] In the description of this application, it should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The term "connection" should be interpreted broadly, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0045] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0046] As mentioned in the background section, hysteresis comparators are named for the lag between their forward and reverse flip-flop voltages. Most current hysteresis comparators are implemented using positive feedback loops, categorized as external or internal positive feedback. However, since external positive feedback requires resistors, and resistors in integrated circuits have large areas and lower accuracy, internal positive feedback hysteresis comparators are more widely used.

[0047] Because hysteresis comparators have a dead zone voltage near zero, they are suitable for various noise and interference environments, such as over-temperature protection and under-voltage protection circuits in GaN power device drive circuits.

[0048] like Figure 1 The diagram shows an undervoltage protection circuit using a hysteresis comparator and voltage divider resistors. COMP is the hysteresis comparator, and R1, R2, and R3 form a resistor divider network. The power supply voltage is V. DD The voltage is detected by a voltage divider formed by resistors R1, R2, and R3, with resistor R3 connected in parallel with MOSFET Q. The detected voltage is input to the inverting input of the hysteresis comparator COMP, and the reference voltage V generated by the bandgap is... REF The voltage is fed into the non-inverting input of the hysteresis comparator COMP. The hysteresis comparator COMP compares the two input voltages and outputs the comparison result.

[0049] It should be noted that the average value of the voltages at the two input terminals of a hysteresis comparator is called the common-mode voltage, and the difference between the two input voltages is called the differential-mode voltage. Only when the common-mode voltage is within the common-mode input range of the hysteresis comparator can the hysteresis comparator accurately compare the differential-mode voltage and output the correct comparison result.

[0050] When a hysteresis comparator is used in an undervoltage protection circuit in a noisy environment, a high switching voltage is required. However, an excessively high switching voltage will reduce the common-mode input range, causing an abnormal common-mode input range. If the common-mode voltage deviates from the common-mode input range at this time, the hysteresis comparator will not be able to output the correct comparison result, causing the chip to continue operating at high temperatures and resulting in irreversible damage.

[0051] Therefore, how to improve the common-mode input range of the hysteresis comparator and ensure that the hysteresis comparator can work normally is a technical problem that urgently needs to be solved by those skilled in the art.

[0052] To resolve the above technical issues, please refer to Figure 2 This application provides a hysteresis comparator circuit 10, including: a differential comparator module 100, a tail current bias module 200, an adaptive shunt module 300, and an output module 400.

[0053] Among them, the first port of the tail current bias module 200, the first port of the adaptive current shunt module 300, and the first port of the output module 400 are all connected to the power supply V. DD Connections. The output terminal of the tail current bias module 200, the first port of the differential comparator module 100, and the second port of the adaptive shunt module 300 are all connected to the first node N1. The second port of the differential comparator module 100 is connected to the second port of the output module 400. The third ports of the differential comparator module 100, the adaptive shunt module 300, and the output module 400 are all grounded.

[0054] The tail current bias module 200 is used to provide bias current for the differential comparator module 100.

[0055] The differential comparator module 100 is used to convert the voltage V at the non-inverting input terminal. inp and the inverting input voltage V inn The differential signal is compared and output to the second port of the output module 400.

[0056] Output module 400 is used to convert differential signals into single-stage output signals, ultimately outputting a digital signal of high or low level V. out .

[0057] When the common-mode input range is normal, i.e., the common-mode voltage (V) inp With V innWhen the average value of the current is within the common-mode input range, the adaptive shunt module 300 is turned off (i.e., I0). C =0). At this time, the bias current output by the tail current bias module 200 flows entirely to the first port (i.e., I) of the differential comparator module 100. B =I A The differential comparator module 100 operates at a bias current I. A Under its function, the output module 400 can ensure that the correct comparison result V is output. out .

[0058] If the hysteresis comparator circuit 10 is applied in a noisy environment, a higher switching voltage is required. However, a higher switching voltage will reduce the common-mode input range, resulting in an abnormal common-mode input range, and will also cause the bias current I output by the tail current bias module 200 to increase. A Increase.

[0059] To stabilize the current I flowing to the first port of the differential comparator module 100 B In this embodiment of the application, when the common-mode input range is abnormal, the adaptive shunt module 300 is turned on (i.e., I...). C ≠0), and the adaptive current shunt module 300 can extract a portion of the bias current I output by the tail current bias module 200. A To reduce the current value flowing to the first port of the differential comparator module 100 (i.e., I0). B =I A -I C This causes the current value I at the first port of the differential comparator module 100 to... B The influence of common-mode voltage changes is reduced, and a stable I is achieved. B The purpose of size.

[0060] In other words, compared to when the common-mode input range is normal, when the common-mode input range is abnormal, although I A It will increase, but since the adaptive current splitter module 300 is turned on at this time, I B The value remains basically unchanged, thus avoiding the comparison result error caused by the sudden change in the common-mode voltage of the hysteresis comparator and improving the common-mode input range of the hysteresis comparator.

[0061] To better understand the technical solution of this application, please refer to Figure 3 In this embodiment of the application, the adaptive current shunt module 300 includes a first current mirror 310 and a second current mirror 320.

[0062] Among them, the first port and the second port of the first current mirror 310 are both connected to the power supply V. DDThe first current mirror 310 is connected to the first node N1, the fourth port of the first current mirror 310 is connected to the first port of the second current mirror 320, the second port of the second current mirror 320 is connected to the first node N1, and both the third and fourth ports of the second current mirror 320 are grounded.

[0063] It should be noted that the first and second ports of the first current mirror 310 are the first ports of the adaptive current shunt module 300, the third port of the first current mirror 310 and the second port of the second current mirror 320 are the second ports of the adaptive current shunt module 300, and the third and fourth ports of the second current mirror 320 are the third ports of the adaptive current shunt module 300.

[0064] When the common-mode input range is normal, both the first current mirror 310 and the second current mirror 320 are turned off, so that all the bias current output by the tail current bias module 200 flows to the first port of the differential comparator module 100, i.e., I. total =I p7 .

[0065] An abnormal common-mode input range will cause I... p7 Increase, in order to stabilize I total The size of the first current mirror 310 and the second current mirror 320 are both turned on. The second port of the second current mirror 320 extracts part of the bias current I output by the tail current bias module 200. p7 (The magnitude of the extracted current is I) n2 This reduces the current flowing to the first port of the differential comparator module 100, i.e., I. total =I p7 -I n2 .

[0066] Furthermore, the first current mirror 310 includes a first PMOS transistor PM1 and a second PMOS transistor PM2, and the second current mirror 320 includes a first NMOS transistor NM1 and a second NMOS transistor NM2.

[0067] In this configuration, the source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are both connected to the power supply V. DD The drain of the first PMOS transistor PM1 is connected to the first node N1, and the gate of the first PMOS transistor PM1 is connected to the drain of the first PMOS transistor PM1 and the gate of the second PMOS transistor PM2.

[0068] The drain of the first NMOS transistor NM1 is connected to the drain of the second PMOS transistor PM2. The gate of the first NMOS transistor NM1 is connected to the drain of the first NMOS transistor NM1 and the gate of the second NMOS transistor NM2. The drain of the second NMOS transistor NM2 is connected to the first node N1. The sources of the first NMOS transistor NM1 and the source of the second NMOS transistor NM2 are both grounded.

[0069] Optionally, the tail current bias module 200 includes a seventh PMOS transistor PM7. The source of the seventh PMOS transistor PM7 is connected to the power supply V. DD The drain of the seventh PMOS transistor PM7 is connected to the first node N1, and the gate of the seventh PMOS transistor PM7 serves as the bias voltage input terminal of the tail current bias module 200, used to receive the bias voltage V. bias .

[0070] Among them, the drain current I of the seventh PMOS transistor PM7 p7 The size is:

[0071]

[0072] Where, k′ p7 =μ np7 C oxp7 μ np7 C represents the carrier mobility of the seventh PMOS transistor PM7. oxp7 This represents the gate oxide capacitance per unit area of ​​the seventh PMOS transistor, PM7. (W / L) p7 V is the quotient of the channel width and channel length of the seventh PMOS transistor PM7. thp7 λ is the threshold voltage of the seventh PMOS transistor PM7. p7 The channel length modulation parameter is for the seventh PMOS transistor PM7.

[0073] When the common-mode input range is abnormal (i.e., when the common-mode input range decreases), the first node voltage V N1 The voltage decreases. Since the gate and drain of the first PMOS transistor PM1 are both connected to the first node N1, the first PMOS transistor PM1 is turned on. According to the current mirror effect of the first PMOS transistor PM1 and the second PMOS transistor PM2, the second PMOS transistor PM2 is also turned on (i.e., the first current mirror 310 is turned on).

[0074] After the second PMOS transistor PM2 is turned on, it charges the gate and drain of the first NMOS transistor NM1, causing the first NMOS transistor NM1 to turn on. Due to the current mirror effect of the first NMOS transistor NM1 and the second NMOS transistor NM2, the second NMOS transistor NM2 also turns on (i.e., the second current mirror 320 turns on).

[0075] From formula (1), we can see that Ip7 With V N1 Inversely proportional, when V N1 When I decreases p7 It will increase. However, since the second NMOS transistor NM2 is turned on, the drain of the second NMOS transistor NM2 will draw a portion of I. p7 That is, the current I flowing through the second NMOS transistor NM2 n2 It will increase, making I p7 and I n2 The tail current I obtained after subtraction total The influence of common-mode voltage changes is reduced, stabilizing I. total The size of the value ensures that the hysteresis comparator circuit 10 can output the correct comparison result when the common-mode voltage changes dynamically, thereby improving the common-mode input range of the hysteresis comparator circuit 10.

[0076] To better understand the overall working principle of the hysteresis comparator circuit 10, please refer to [link / reference]. Figure 4 The specific structure of the differential comparison module 100 will be explained below.

[0077] In this embodiment, the differential comparison module 100 includes an inverting input unit 110, a non-inverting input unit 120, a third current mirror 130, and a fourth current mirror 140.

[0078] The first port of the inverting input unit 110 and the first port of the non-inverting input unit 120 are both connected to the first node N1. The first port of the third current mirror 130, the first port of the fourth current mirror 140, and the output terminal of the inverting input unit 110 are all connected to the second node N2. The second port of the third current mirror 130, the second port of the fourth current mirror 140, and the output terminal of the non-inverting input unit 120 are all connected to the third node N3. The third port of the third current mirror 130, the fourth port of the third current mirror 130, the third port of the fourth current mirror 140, and the fourth port of the fourth current mirror 140 are all grounded.

[0079] Furthermore, the inverting input unit 110 includes a third PMOS transistor PM3, the source of which is connected to the first node N1, the drain of which is connected to the second node N2, and the gate of which is the inverting input terminal of the differential comparator module 100.

[0080] The non-inverting input unit 120 includes a fourth PMOS transistor PM4. The source of the fourth PMOS transistor PM4 is connected to the first node N1, the drain of the fourth PMOS transistor PM4 is connected to the third node N3, and the gate of the fourth PMOS transistor PM4 is the non-inverting input terminal of the differential comparator module 100.

[0081] The third current mirror 130 includes a third NMOS transistor NM3 and a fourth NMOS transistor NM4. The drain of the third NMOS transistor NM3 is connected to the second node N2. The gate of the third NMOS transistor NM3 is connected to the drain of the third NMOS transistor NM3 and the gate of the fourth NMOS transistor NM4, respectively. The drain of the fourth NMOS transistor NM4 is connected to the third node N3. The sources of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are both grounded.

[0082] The fourth current mirror 140 includes a fifth NMOS transistor NM5 and a sixth NMOS transistor NM6. The drain of the fifth NMOS transistor NM5 is connected to the second node N2. The gate of the fifth NMOS transistor NM5 is connected to the drain and gate of the sixth NMOS transistor NM6, respectively. The drain of the sixth NMOS transistor NM6 is connected to the third node N3. The sources of the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are both grounded.

[0083] The specific structure of the output module 400 is as follows: Figure 5 As shown in the embodiment of this application, the output module 400 includes a fifth current mirror 410, a seventh NMOS transistor NM7, and an eighth NMOS transistor NM8.

[0084] Among them, the first and second ports of the fifth current mirror 410 are both connected to the power supply V. DD Connections: The drain of the seventh NMOS transistor NM7 is connected to the third port of the fifth current mirror 410, the gate of the seventh NMOS transistor NM7 is connected to the second node N2, and the source of the seventh NMOS transistor NM7 is grounded. The drain of the eighth NMOS transistor NM8 is connected to the fourth port of the fifth current mirror 410 as the output terminal of the output module 400, the gate of the eighth NMOS transistor NM8 is connected to the third node N3, and the source of the eighth NMOS transistor NM8 is grounded.

[0085] Furthermore, the fifth current mirror 410 includes a fifth PMOS transistor PM5 and a sixth PMOS transistor PM6. The source of both the fifth PMOS transistor PM5 and the source of the sixth PMOS transistor PM6 are connected to the power supply V. DD The drain of the fifth PMOS transistor PM5 is connected to the drain of the seventh NMOS transistor NM7. The gate of the fifth PMOS transistor PM5 is connected to the drain of the fifth PMOS transistor PM5 and the gate of the sixth PMOS transistor PM6. The drain of the sixth PMOS transistor PM6 is connected to the drain of the eighth NMOS transistor NM8 as the output terminal of the output module 400.

[0086] Based on the above design, the overall structure of the hysteresis comparator circuit 10 is as follows: Figure 6 and Figure 7As shown in the diagram, this circuit has two feedback loops: one is the series current negative feedback introduced through the common source node of PM3 and PM4 (i.e., the first node N1), and the other is the parallel voltage positive feedback introduced through NM4 and NM5. The hysteresis comparator will only exhibit a hysteresis effect, and the forward and reverse flip-flop voltages will be different, when the positive feedback effect is greater than the negative feedback effect.

[0087] To analyze the forward flip voltage behavior of the hysteresis comparator circuit, please refer to... Figure 6 Assume V inn >>V inp And the bias current I output by PM7 p7 If all the flow is directed to the first port of the differential comparator module 100, then PM3 is turned off and PM4 is turned on. p7 All of it flows through PM4. That is, I p4 =I p7 , I p3 =0, and V N2 <V N3 .

[0088] Due to the gate voltage V of NM6 N3 The voltage rises, therefore NM6 conducts. Since NM5 and NM6 form a current mirror relationship, and NM8 and NM5 also form a current mirror relationship, NM5, NM6, and NM8 are all conducting. At this time, the second node voltage V... N2 The drain current of NM5 pulls it to ground, i.e., V. N2 =0.

[0089] Due to V N2 =0, and NM3 and NM4 form a current mirror relationship, as do NM7 and NM4. Therefore, NM3, NM4, and NM7 are all turned off. At this time, since NM8 is turned on and NM7 is turned off, the output of the hysteresis comparator circuit is pulled down to ground by NM8, i.e., V out =0.

[0090] If V inn The bias current I begins to decrease, at which point it partially decreases. p7 It begins to flow through PM3, i.e., I p3 Starting from 0 and increasing, I p4 It begins to decrease. When I p3 =I n5 At this point, the inverter structure composed of PM3 and NM5 reaches the flip point. Since NM4 is still in the off state, I... p4 =I n6 .

[0091] That is, when I p3 =I n5 When the following formula is satisfied:

[0092]

[0093] I p3 +I p4 =I p7 (3)

[0094] At this time, I p3 The size is:

[0095]

[0096] The second node voltage V is obtained from formulas (2), (3), and (4). N2 The potential is:

[0097]

[0098] If V N2 If the voltage is high enough to form an inversion layer (i.e., NM3 changes from its off state to its on state), then NM3, NM4, and NM7 will all be turned on, and the positive feedback loop composed of NM4 and NM5 will be activated. Therefore, V N2 and V N3 The polarity will reverse (i.e., V) N2 >V N3 At this time, NM5, NM6, and NM8 are all off. Since NM7 is on, PM5 and PM6 are both on, and the output signal V of the hysteresis comparator circuit is... out From 0 to V DD .

[0099] Ignoring channel length modulation effects, the forward switching voltage of the hysteresis comparator circuit can be obtained from formulas (2), (3), and (4). for:

[0100]

[0101] Among them, V gsp4 V is the gate-source voltage of PM4. gsp3 The gate-source voltage of PM3 is given, and the gate of PM4 is the non-inverting input of the hysteresis comparator, while the gate of PM3 is the inverting input of the hysteresis comparator.

[0102] At this point, the hysteresis comparator circuit has completed a normal comparison. According to formula (6), the switching voltage of the hysteresis comparator circuit is... Proportional to the common-mode input range of the hysteresis comparator, excessively high switching voltage will reduce the common-mode input range of the hysteresis comparator.

[0103] The common-mode input range is a crucial parameter of a hysteresis comparator, significantly influencing its application scenarios. The common-mode input range of a hysteresis comparator is defined as the range within which all transistors are in saturation. Based on this definition, Figure 6 The common-mode input range of the circuit shown is:

[0104] -V gsp3 =V N1 -V cm ≥|V thp3 | (7)

[0105] V cm +∣V thp3 |≥V thn3 (8)

[0106] V thn3 -|V thp3 |≤V cm ≤V DD -V OV_P7 -|V thp3 | (9)

[0107] Among them, V cm For common-mode voltage, V thp3 V is the threshold voltage for PM3. thn3 V is the threshold voltage of NM3. OV_P7 This is the overdrive voltage of PM7.

[0108] The common-mode input range affects the dynamic operating state of the hysteresis comparator. As mentioned above, only when V... N2 The hysteresis comparator state will only be flipped when the NM3 is high enough to form an inversion layer.

[0109]

[0110] That is, when V N2 When the above formula (10) is satisfied, the positive feedback loop composed of NM4 and NM5 is activated, and V N2 and V N3 The polarity must be reversed for the hysteresis comparator to function properly.

[0111] From formula (10), we can see that V N2 With V N1 Proportional, and V N2 with I p7 Inversely proportional. From formula (1), we know that I... p7 With V N1 Inversely proportional.

[0112] When a hysteresis comparator is used in noisy environments, a relatively large switching voltage is required. However, a large switching voltage will reduce the common-mode input range, causing the common-mode voltage to deviate from the common-mode input range. N1 Decrease, I p7 Increase, V N2 Decrease. At this time, V N2 The value is too low to meet the conditions in formula (10), causing the positive feedback loop composed of NM4 and NM5 to fail to start. N2 Unable to rise, V N3 The inability to pull the value low ultimately causes the hysteresis comparator to fail to output the correct comparison result.

[0113] To ensure the hysteresis comparator functions correctly in noisy environments, please refer to [link / reference]. Figure 7 In this embodiment of the application, when the common-mode voltage deviates from the common-mode input range, causing V N1 During the descent, since the gate and drain of PM1 in the adaptive shunt module 300 are both connected to the first node N1, V N1 PM1 conducts during descent.

[0114] At this time, the current I flowing through PM1 p1 Size:

[0115]

[0116] Based on the current mirror relationship between PM1 and PM2, PM2 is also turned on, charging the gate and drain of NM1, thus turning on NM1. Based on the current mirror relationship between NM1 and NM2, NM2 is also turned on.

[0117] At this time, the current I flowing through NM2 n2 Size:

[0118]

[0119]

[0120] Since the drain of NM2 is connected to the first node N1 (equivalent to the drain of PM7), NM2 will draw a portion of the bias current I output from PM7. p7 The magnitude of the extracted current is I. n2 At this time, the bias current I flowing to the first port of the differential comparator module 100... total The size is:

[0121] I total =I p7 -I n2 (14)

[0122] At this point, the condition for the hysteresis comparator to function normally is:

[0123]

[0124] According to formulas (11) and (13), I n2 With V N1 They are inversely proportional. According to formula (1), I p7 With V N1 Inversely proportional.

[0125] Based on the above design, when the common-mode voltage deviates from the common-mode input range, causing V N1 When I decreases p7 Increase, but at the same time I n2 It will also increase, therefore, according to formula (14), I p7 and I n2 The tail current I obtained after subtraction total The influence of common-mode voltage changes is reduced, and a stable tail current I is achieved. total The purpose. V in formula (15) N2 Compared to V in formula (10) N2 It has a stronger ability to suppress input common-mode changes, thereby avoiding comparison result errors caused by common-mode voltage mutations in hysteresis comparators, improving the common-mode input range of hysteresis comparators, and broadening the application range of hysteresis comparators.

[0126] Optionally, embodiments of this application also provide a hysteresis comparator system, which includes a hysteresis comparator circuit as described in any of the foregoing embodiments.

[0127] In summary, this application provides a hysteresis comparator circuit and system, including: a differential comparator module, a tail current bias module, an adaptive shunt module, and an output module. The first port of the tail current bias module, the first port of the adaptive shunt module, and the first port of the output module are all connected to a power supply. The output terminal of the tail current bias module, the first port of the differential comparator module, and the second port of the adaptive shunt module are all connected to a first node, and the second port of the differential comparator module is connected to the second port of the output module. The third port of the differential comparator module, the third port of the adaptive shunt module, and the third port of the output module are all grounded.

[0128] When the common-mode input range is normal, the common-mode voltage is within the common-mode input range. At this time, the adaptive shunt module is turned off, and the bias current output by the tail current bias module flows entirely to the first port of the differential comparator module, so the hysteresis comparator circuit can work normally.

[0129] When the common-mode input range is abnormal (i.e., when the common-mode input range decreases), the bias current output by the tail current bias module will increase. To stabilize the current flowing to the first port of the differential comparator module, the adaptive shunt module is activated. The adaptive shunt module draws a portion of the bias current output by the tail current bias module to reduce the current flowing to the first port of the differential comparator module. This ensures that the current flowing to the first port of the differential comparator module is less affected by changes in the common-mode voltage, thereby ensuring the hysteresis comparator circuit can operate normally and improving the common-mode input range of the hysteresis comparator.

[0130] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0131] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A hysteresis comparator circuit, characterized in that, The hysteresis comparator circuit includes: a differential comparator module, a tail current bias module, an adaptive shunt module, and an output module; The first port of the tail current bias module, the first port of the adaptive shunt module, and the first port of the output module are all connected to the power supply; the output terminal of the tail current bias module, the first port of the differential comparator module, and the second port of the adaptive shunt module are all connected to the first node; the second port of the differential comparator module is connected to the second port of the output module; the third port of the differential comparator module, the third port of the adaptive shunt module, and the third port of the output module are all grounded. The adaptive current shunt module includes a first current mirror and a second current mirror; the first current mirror includes a first PMOS transistor and a second PMOS transistor, and the second current mirror includes a first NMOS transistor and a second NMOS transistor; The source of the first PMOS transistor and the source of the second PMOS transistor are both connected to the power supply. The drain of the first PMOS transistor is connected to the first node. The gate of the first PMOS transistor is connected to the drain of the first PMOS transistor and the gate of the second PMOS transistor, respectively. The drain of the first NMOS transistor is connected to the drain of the second PMOS transistor, the gate of the first NMOS transistor is connected to the drain of the first NMOS transistor and the gate of the second NMOS transistor, respectively, and the drain of the second NMOS transistor is connected to the first node; the source of the first NMOS transistor and the source of the second NMOS transistor are both grounded. The tail current bias module is used to provide bias current to the first port of the differential comparator module; When the common-mode input range is normal, both the first current mirror and the second current mirror are turned off, so that the bias current output by the tail current bias module flows to the first port of the differential comparator module. When the common-mode input range is abnormal, the voltage of the first node decreases, the bias current output by the tail current bias module increases, both the first current mirror and the second current mirror are turned on, and the drain of the second NMOS transistor draws part of the bias current output by the tail current bias module to reduce the current value flowing to the first port of the differential comparator module.

2. The hysteresis comparator circuit according to claim 1, characterized in that, The differential comparison module includes an inverting input unit, a non-inverting input unit, a third current mirror, and a fourth current mirror; The first port of the inverting input unit and the first port of the non-inverting input unit are both connected to the first node; the first port of the third current mirror, the first port of the fourth current mirror, and the output terminal of the inverting input unit are all connected to the second node; the second port of the third current mirror, the second port of the fourth current mirror, and the output terminal of the non-inverting input unit are all connected to the third node; the third port of the third current mirror, the fourth port of the third current mirror, the third port of the fourth current mirror, and the fourth port of the fourth current mirror are all grounded.

3. The hysteresis comparator circuit according to claim 2, characterized in that, The inverting input unit includes a third PMOS transistor, the source of which is connected to the first node, the drain of which is connected to the second node, and the gate of which is the inverting input terminal of the differential comparator module. The non-inverting input unit includes a fourth PMOS transistor, the source of which is connected to the first node, the drain of which is connected to the third node, and the gate of which is the non-inverting input terminal of the differential comparator module.

4. The hysteresis comparator circuit according to claim 2, characterized in that, The third current mirror includes a third NMOS transistor and a fourth NMOS transistor. The drain of the third NMOS transistor is connected to the second node. The gate of the third NMOS transistor is connected to the drain of the third NMOS transistor and the gate of the fourth NMOS transistor, respectively. The drain of the fourth NMOS transistor is connected to the third node. The sources of the third NMOS transistor and the fourth NMOS transistor are both grounded. The fourth current mirror includes a fifth NMOS transistor and a sixth NMOS transistor. The drain of the fifth NMOS transistor is connected to the second node, and the gate of the fifth NMOS transistor is connected to both the drain and gate of the sixth NMOS transistor. The drain of the sixth NMOS transistor is connected to the third node, and the sources of both the fifth and sixth NMOS transistors are grounded.

5. The hysteresis comparator circuit according to claim 4, characterized in that, The output module includes a fifth current mirror, a seventh NMOS transistor, and an eighth NMOS transistor; Both the first port and the second port of the fifth current mirror are connected to the power supply. The drain of the seventh NMOS transistor is connected to the third port of the fifth current mirror, the gate of the seventh NMOS transistor is connected to the second node, and the source of the seventh NMOS transistor is grounded. The drain of the eighth NMOS transistor is connected to the fourth port of the fifth current mirror as the output terminal of the output module, the gate of the eighth NMOS transistor is connected to the third node, and the source of the eighth NMOS transistor is grounded.

6. The hysteresis comparator circuit according to claim 5, characterized in that, The fifth current mirror includes a fifth PMOS transistor and a sixth PMOS transistor; The source of the fifth PMOS transistor and the source of the sixth PMOS transistor are both connected to the power supply. The drain of the fifth PMOS transistor is connected to the drain of the seventh NMOS transistor. The gate of the fifth PMOS transistor is connected to the drain of the fifth PMOS transistor and the gate of the sixth PMOS transistor. The drain of the sixth PMOS transistor is connected to the drain of the eighth NMOS transistor as the output terminal of the output module.

7. The hysteresis comparator circuit according to claim 1, characterized in that, The tail current biasing module includes a seventh PMOS transistor; The source of the seventh PMOS transistor is connected to the power supply, the drain of the seventh PMOS transistor is connected to the first node, and the gate of the seventh PMOS transistor serves as the bias voltage input terminal of the tail current bias module.

8. A hysteresis comparator system, characterized in that, The hysteresis comparator system includes the hysteresis comparator circuit as described in any one of claims 1-7.

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