Voltage phase locking method, phase locking system, charger and vehicle
By performing the first-stage phase locking process on the mains voltage signal after de-DC biasing, the problem of insufficient phase locking accuracy in the prior art is solved, and higher phase locking accuracy and lower hardware costs are achieved.
Patent Information
- Application Number
- CN202311289752.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-28
- Publication Date
- 2025-03-28
AI Technical Summary
In the phase locking control of mains voltage, the phase locking accuracy is insufficient and complex hardware and theoretical calculations are required, which increases costs and overhead.
By performing de-DC biasing on the mains voltage signal, subtracting the average value of the power frequency period and the first-order filtered DC bias, the first-stage phase lock is performed to improve the phase locking accuracy.
Improves phase locking accuracy, reduces hardware costs and overhead, simplifies software implementation, and enhances circuit stability and security.
Smart Images
Figure CN119727710A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of electronic technology, and in particular to a voltage phase-locking method, a phase-locking system, a charger and a vehicle. Background Art
[0002] For the phase-locked control of the mains, zero-crossing detection is usually used to obtain the period and phase information of the mains voltage, thereby completing the phase-locking of the mains voltage. For example, zero-crossing detection is performed through digital signal processing (DSP) to generate a primary phase-locked signal, or the mains phase-locking is performed through a more complex theoretical calculation. However, DSP requires the use of hardware peripheral circuits, and the phase-locking of the mains based on this will result in insufficient phase-locking accuracy. Summary of the invention
[0003] The present application provides a voltage phase locking method, a phase locking system, a charger and a vehicle, which can improve the accuracy of phase locking.
[0004] In a first aspect, an embodiment of the present application provides a voltage phase-locking method, which includes acquiring a mains voltage signal; performing a DC bias removal process on the mains voltage signal; and performing a primary phase-locking process on the DC bias-removed mains voltage signal.
[0005] Since DC bias will affect the phase-locking accuracy of the phase-locked circuit, at the beginning of phase locking, the embodiment of the present application can improve the phase-locking accuracy by first removing the DC bias from the AC voltage signal and then performing a first-level phase locking on the AC voltage without the DC bias.
[0006] In some embodiments, before removing the DC bias from the mains voltage signal, the method further comprises: filtering the mains voltage signal and performing power frequency cycle average value processing to obtain a mains voltage signal without DC bias from the mains voltage signal.
[0007] In some embodiments, the filtering of the mains voltage signal and the processing of the power frequency cycle average value to obtain the mains voltage signal without DC bias, includes: taking the power frequency cycle average value of the mains voltage signal; performing first-order filtering on the mains voltage signal and subtracting the power frequency cycle average value to obtain the mains voltage signal without DC bias.
[0008] In some embodiments, performing primary phase locking on the DC bias-removed mains voltage signal includes: performing primary phase locking on the DC bias-removed mains voltage signal based on one power frequency cycle or half a power frequency cycle.
[0009] In some embodiments, the method also includes: obtaining at least one of the effective value of the mains voltage and the frequency of the mains voltage obtained after the first-level phase locking; performing secondary phase locking on the mains voltage signal after the first-level phase locking when at least one of the effective value of the mains voltage is greater than or equal to a first threshold and the frequency of the mains voltage is greater than or equal to a second threshold is satisfied.
[0010] In some embodiments, performing secondary phase locking on the primary phase-locked mains voltage signal includes: performing secondary phase locking on the primary phase-locked mains voltage signal based on one power frequency cycle or half a power frequency cycle.
[0011] In a second aspect, an embodiment of the present application provides a voltage phase-locking system, which may include:
[0012] The acquisition module is used to acquire the mains voltage signal;
[0013] The DC bias removal module is used to remove the DC bias from the mains voltage signal; and
[0014] The primary phase-locking module is used to perform primary phase-locking on the DC bias-free mains voltage signal.
[0015] In some embodiments, the DC bias removal module is further used to filter the mains voltage signal and perform power frequency cycle average value processing on the mains voltage signal before performing DC bias removal processing on the mains voltage signal to obtain a DC bias-free mains voltage signal.
[0016] In some embodiments, the DC bias removal module filters the mains voltage signal and processes the power frequency cycle average value to obtain a mains voltage signal without DC bias of the mains voltage signal, specifically for:
[0017] The mains voltage signal is taken as an average value of the power frequency cycle; the mains voltage signal is first-order filtered and the average value of the power frequency cycle is subtracted to obtain a mains voltage signal without direct current bias.
[0018] In some embodiments, the primary phase-locking module performs primary phase-locking on the DC-biased mains voltage signal, specifically for: performing primary phase-locking on the DC-biased mains voltage signal based on one power frequency cycle or half a power frequency cycle.
[0019] In some embodiments, the phase locking system further comprises:
[0020] A detection module is used to obtain at least one of the effective value of the mains voltage and the frequency of the mains voltage obtained after the first-level phase locking; when at least one of the effective value of the mains voltage is greater than or equal to the first threshold and the frequency of the mains voltage is greater than or equal to the second threshold, the mains voltage signal after the first-level phase locking is subjected to second-level phase locking.
[0021] In some embodiments, the phase locking system further comprises:
[0022] The secondary phase-locking module is used to perform secondary phase-locking on the mains voltage signal after primary phase-locking based on one power frequency cycle or half a power frequency cycle.
[0023] In a third aspect, an embodiment of the present application provides a charger, which includes a phase-locking system as described in the second aspect, and the phase-locking system is used to implement the phase-locking method described in the first aspect or any one embodiment of the first aspect.
[0024] In a fourth aspect, an embodiment of the present application provides a vehicle, comprising the charger as described in the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0026] Figure 1 A flow chart of a voltage phase locking method provided in one embodiment of the present application;
[0027] Figure 2 A flow chart of a voltage phase locking method provided in one embodiment of the present application;
[0028] Figure 3 A schematic diagram of the structure of a voltage phase-locked system provided in one embodiment of the present application;
[0029] Figure 4 A schematic diagram of the structure of a vehicle provided in accordance with an embodiment of the present application. DETAILED DESCRIPTION
[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0031] It should be noted that when a component is considered to be "coupled" to another component, it can be directly or indirectly connected to the other component.
[0032] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in this application and in the specification are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used in this application includes any and all combinations of one or more of the related listed items.
[0033] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.
[0034] In the existing phase-locked control, the DSP is usually used to perform zero-crossing detection to generate a first-level phase-locked signal or to perform mains phase-locking through more complex theoretical calculations. Among them, since the DSP needs to be used with hardware peripheral circuits, the actual cost of the hardware is increased. The phase-locked loop (PLL) is used to calculate the grid voltage, grid frequency and grid phase. The amount of calculation for each phase-locking is large, and the central processing unit (CPU) overhead is large in engineering practice. In addition, the mains phase-locking through more complex theories will increase the overhead of the actual circuit core. Too high a core overhead will reduce the reliability of software engineering.
[0035] The embodiment of the present application provides a voltage phase-locking method. Since the DC bias will affect the phase-locking accuracy of the phase-locking circuit, the embodiment of the present application can first remove the DC bias of the mains voltage signal, and then perform a first-level phase lock on the mains voltage without the DC bias, thereby improving the phase-locking accuracy. Secondly, the software implementation of the embodiment of the present application is simple, does not require complex theoretical calculations, and can also perform abnormal diagnosis on the input voltage to improve the stability and safety of the circuit.
[0036] See also Figure 1 , Figure 1 This is a flow chart of a voltage phase locking method provided in one embodiment of the present application. Figure 1 As shown, the phase locking method may include the following steps:
[0037] S101: Acquire a mains voltage signal.
[0038] For the mains voltage signal, DSP can be used to sample the mains voltage signal in real time. For example, a periodic sine wave can be detected, from negative to positive or from positive to negative, so as to determine the entry into the positive half cycle of the mains or the negative half cycle of the mains or a new cycle, so as to collect the mains voltage signal. A possible implementation method is to collect the mains voltage signal in real time.
[0039] S102: performing a DC bias removal process on the mains voltage signal.
[0040] Before the acquired mains voltage signal is subjected to DC bias removal processing, the mains voltage signal can be first filtered and the power frequency cycle average value processed to obtain the mains voltage signal with DC bias removed. Specifically, the power frequency cycle average value can be taken for the mains voltage signal first; the mains voltage signal is first-order filtered and the power frequency cycle average value is subtracted to obtain the mains voltage signal with DC bias removed. Example:
[0041] Assume the mains voltage is:
[0042]
[0043] Among them, u m1 Indicates the effective value of the mains voltage, U dc Indicates the DC bias voltage, U mi Indicates the effective value of the high-frequency component voltage;
[0044] Take the average value of the power frequency cycle for the mains voltage signal:
[0045] u(t) avg =U dc
[0046] Perform a first-order filter on the mains voltage signal and subtract the average value of the power frequency cycle to obtain a mains voltage signal without DC bias:
[0047]
[0048] The obtained mains voltage is filtered and processed with the power frequency cycle average value, where the power frequency cycle average value can be understood as the DC bias in the mains voltage. The DC bias will affect the phase-locked accuracy of the phase-locked loop. Therefore, at the beginning of the phase-locked loop, the DC bias can be removed to improve the phase-locked accuracy.
[0049] S103: performing primary phase locking on the AC voltage signal after the DC bias is removed.
[0050] After the AC voltage signal is subjected to DC bias removal processing to obtain the DC bias-free AC voltage signal, the DC bias-free AC voltage signal can be subjected to primary phase locking. A possible implementation method is to perform primary phase locking on the DC bias-free AC voltage signal based on one power frequency cycle or half a power frequency cycle. Among them, the power frequency cycle can be understood as the cycle of the AC power. Phase locking can be understood as locking the waveform and phase of the input voltage. For example, the power grid has a cycle of 0.02s (seconds). Phase locking can be used to determine how much deviation the parameters such as the amplitude, frequency value, and phase angle error value of the input AC voltage in this cycle have from the previous cycle. Performing primary phase locking through one power frequency cycle or half a power frequency cycle can further improve the accuracy and reliability of the phase-locked link.
[0051] In the embodiment of the present application, since the DC bias will affect the phase-locking accuracy of the phase-locked circuit, in the initial stage of phase locking, the embodiment of the present application can first remove the DC bias of the AC voltage signal, and then perform a first-level phase lock on the AC voltage without the DC bias, thereby improving the phase-locking accuracy. In addition, unlike the prior art that requires an additional hardware circuit to perform zero-crossing detection to generate a first-level phase-locked signal, the present application does not require a hardware circuit for voltage zero-crossing detection, which can reduce hardware costs.
[0052] See also Figure 2 , Figure 2 This is a flow chart of a voltage phase locking method provided in one embodiment of the present application. Figure 2 As shown, the phase locking method may include the following steps:
[0053] S201: Acquire a mains voltage signal.
[0054] S202: performing DC bias removal processing on the mains voltage signal.
[0055] S203: performing primary phase locking on the AC voltage signal after the DC bias is removed.
[0056] It can be understood that steps S201-S203 correspond to the above-mentioned steps S101-S103. The specific description of steps S201-S203 can refer to steps S101-S103, which will not be repeated here.
[0057] S204: Obtain at least one of the effective value and frequency of the mains voltage obtained after the first-level phase locking, and detect whether the first-level phase locking is successful. If so, step S205 can be executed, if not, step S206 can be executed.
[0058] After the mains voltage signal of the DC bias is phase-locked, at least one of the effective value and frequency of the mains voltage can be obtained, and whether the primary phase lock is successful can be detected according to at least one of the effective value and frequency of the mains voltage. For example, a possible implementation method, if the effective value of the mains voltage is greater than or equal to (or greater than) the first threshold, it can be determined that the primary phase lock is successful, or if the frequency of the mains voltage is greater than or equal to (or greater than) the second threshold, it can be determined that the primary phase lock is successful, or if the effective value of the mains voltage is greater than or equal to (or greater than) the first threshold and if the frequency of the mains voltage is greater than or equal to (or greater than) the second threshold, it can be determined that the primary phase lock is successful. For example, if the frequency of the mains voltage is 50Hz, and the frequency after the primary phase lock exceeds the second threshold, it can be determined that the mains voltage is abnormal, the primary phase lock fails, and a fault is reported. It can be understood that the first threshold and the second threshold can be predefined values, and the first threshold and the second threshold can be the same or different. The specific numerical values of the first threshold and the second threshold are not limited in the embodiment of the present application. Secondly, in the above possible implementations, it can be understood that greater than or equal to (or greater than) can also be less than or equal to (or less than), and can be equivalently replaced without changing the implementation of the technical solution.
[0059] If the first-level phase locking is successful, step S205 may be executed; if the first-level phase locking fails, step S206 may be executed.
[0060] S205: Perform secondary phase locking on the mains voltage signal after the primary phase locking.
[0061] In the case where the primary phase locking is successful, the secondary phase locking can be performed on the mains voltage signal after the primary phase locking. For example, assuming that the primary phase locking is successful, the following relationship may exist:
[0062] ω1≈ω2
[0063] Further simplification gives:
[0064]
[0065] A possible implementation method is to perform secondary phase locking on the AC voltage signal after primary phase locking based on one power frequency cycle or half a power frequency cycle. Performing secondary phase locking on one power frequency cycle or half a power frequency cycle can further improve the accuracy and reliability of the phase locking link.
[0066] S206: Report the fault.
[0067] If the primary phase lock fails, a fault report can be performed. For example, an indication message can be reported to indicate that the primary phase lock failed. Further, optionally, the cause of the fault and the fault parameter (such as at least one of the effective value and frequency of the mains voltage obtained by the primary phase lock) can also be reported, and the controller determines whether to re-phase lock, or re-phase lock after adjusting the parameters according to the cause of the fault and the fault parameter.
[0068] A possible implementation method is that when the grid-side power quality is poor, the harmonic content is high, the grid-side voltage exceeds the standard, etc., the first-level phase locking in the phase locking method can detect the positive and negative half-cycle duration of the grid side in real time, and the input abnormality can be determined without waiting for a power frequency cycle to calculate the input frequency. For the abnormal duration, corresponding logical processing can be performed, the fault can be reported, and the corresponding protection and control strategies can be enabled, such as shutting down or adjusting the input adaptability of the power factor correction (PFC) link, such as adjusting from weak adaptability to strong adaptability.
[0069] One possible implementation method is that when the grid-side voltage is missing a phase, such as a line L or N is broken, the primary phase lock fails, the fault can be reported and the corresponding protection and control strategy can be enabled.
[0070] In one possible implementation, when the grid-side voltage is short-circuited (such as a phase-to-phase short-circuit) and the primary phase lock fails, the fault can be reported and the corresponding protection and control strategies can be enabled.
[0071] In the embodiment of the present application, the fault diagnosis of the mains voltage based on the first-level phase lock can be used to detect whether it is abnormal before the second-level phase lock, so that the fault of the first-level phase lock can be diagnosed as soon as possible, which is simple and reliable and has a fast response speed.
[0072] Optionally, after performing secondary phase locking on the primary phase-locked mains voltage signal, the following steps may also be included:
[0073] S207: Calculate the phase angle step length according to the phase angle error obtained after the secondary phase locking, and perform phase angle compensation according to the phase angle step length.
[0074] In the above step S205, after performing secondary phase locking on the mains voltage signal after primary phase locking, the phase angle error of the phase-locked loop can be obtained, and the phase angle step length can be further calculated based on the phase angle error obtained by the secondary phase locking, and the phase angle compensation can be performed based on the phase angle step length. Specifically:
[0075] Assuming that the DC-biased mains voltage signal is a sinusoidal signal, the effective value of the mains voltage output by the primary phase-locked output or the cosine value of the frequency can be multiplied by the DC-biased mains voltage signal, and the power frequency cycle integration is performed to obtain the phase angle error, exemplarily:
[0076]
[0077] Among them, u m1 represents the effective value of the mains voltage, and T represents the period. Since the mains voltage signal has harmonics, the interference of the harmonics with too high or too low frequency can be removed by integration.
[0078] The output phase angle step of the secondary phase lock can be expressed as θ steo =(2π-Δθ) / Freq.
[0079] In the actual operation of generating a sine wave, a table lookup method can be used. Since the index of the data table is an integer, the output of the secondary phase-locked circuit can be converted to a type, thereby reducing the control accuracy of the secondary phase-locked circuit. Therefore, phase angle compensation can be performed according to the phase angle step.
[0080] One possible implementation method is to first determine the cycle. For example, 4096 points can be sampled in one cycle, and the cosine can be divided into 600 equal points to obtain the phase angle error for phase angle compensation. A cosine can be obtained by looking up a table to achieve real-time phase angle compensation, which is simple and reliable to implement and has a fast response speed. For example:
[0081] The working principle of phase angle compensation can be as follows:
[0082]
[0083] θ step_comp =nθ step_err / n
[0084] Calculate the decimal part of the phase angle compensation, n is the set compensation accuracy, and get the phase angle step error. If the phase angle error does not exceed the preset range, it means that the secondary phase locking is successful.
[0085] Further optionally, if the secondary phase lock fails, a fault report may also be performed. For specific implementation, reference may be made to the description of detecting whether the primary phase lock is successful in the above step S204. In a possible implementation, if the phase angle error value output by the secondary phase lock is abnormal, a fault report may be performed. For example, when the phase angle error value output by the secondary phase lock is greater than or equal to 180, it may be determined that the mains voltage is abnormal, and a fault report may be performed.
[0086] See also Figure 3 , Figure 3 This is a schematic diagram of a voltage phase-locked system provided in one embodiment of the present application. Figure 3As shown, the phase-locking system 300 may include an acquisition module 301, a DC bias removal module 302, a primary phase-locking module 303, a detection module 304, a secondary phase-locking module 305, and a phase angle compensation module 306, wherein the output end of the acquisition module 301 is connected to the input end of the DC bias removal module 302, the output end of the DC bias removal module 302 is connected to the input end of the primary phase-locking module 303, the input end of the detection module 304 may be connected to the output ends of the primary phase-locking module 303, the secondary phase-locking module 305, and the phase angle compensation module 306, the input end of the secondary phase-locking module 305 is connected to the output end of the primary phase-locking module 303, and the input end of the phase angle compensation module 306 is connected to the output end of the secondary phase-locking module 305. Specifically:
[0087] The acquisition module 301 is used to acquire a mains voltage signal;
[0088] The DC bias removal module 302 is used to remove the DC bias of the mains voltage signal;
[0089] The primary phase locking module 303 is used to perform primary phase locking on the DC bias-free mains voltage signal.
[0090] In some embodiments, the DC bias removal module 302 is further used to filter the mains voltage signal and perform power frequency cycle average processing on the mains voltage signal before performing DC bias removal processing on the mains voltage signal to obtain a DC bias-free mains voltage signal.
[0091] In some embodiments, the DC bias removal module 302 filters the mains voltage signal and processes the power frequency cycle average value to obtain a mains voltage signal without DC bias. It is specifically used to: take the power frequency cycle average value of the mains voltage signal; perform first-order filtering on the mains voltage signal and subtract the power frequency cycle average value to obtain a mains voltage signal without DC bias.
[0092] In some implementations, the primary phase locking module 303 performs primary phase locking on the DC bias-free mains voltage signal, specifically for: performing primary phase locking on the DC bias-free mains voltage signal based on one power frequency cycle or half a power frequency cycle.
[0093] In some embodiments, the phase locking system further comprises:
[0094] The detection module 304 is used to obtain at least one of the effective value of the mains voltage and the frequency of the mains voltage obtained after the first-level phase locking; when the effective value of the mains voltage is greater than or equal to the first threshold and the frequency of the mains voltage is greater than or equal to at least one of the second threshold, the mains voltage signal after the first-level phase locking is subjected to second-level phase locking.
[0095] In some embodiments, the phase locking system further comprises:
[0096] The secondary phase locking module 305 is used to perform secondary phase locking on the primary phase locked mains voltage signal based on one power frequency cycle or half a power frequency cycle.
[0097] Optionally, in some embodiments, the phase locking system may further include:
[0098] The phase angle compensation module 306 is used to calculate the phase angle step length according to the phase angle error obtained by the secondary phase locking after performing the secondary phase locking on the mains voltage signal after the primary phase locking, and perform phase angle compensation according to the phase angle step length.
[0099] about Figure 3 The specific implementation of the phase-locked system shown can refer to the above Figure 1 and Figure 2 The detailed description steps of the phase-locking method are omitted here.
[0100] An embodiment of the present application further provides a charger, which may include the voltage phase-locking system described in any embodiment of the present application.
[0101] See also Figure 4 , Figure 4 A schematic diagram of the structure of a vehicle provided in one embodiment of the present application. Figure 4 As shown, the vehicle may include the charger described in any embodiment of the present application.
[0102] The embodiment of the present application also provides an energy storage device, which may include the voltage phase-locked system described in any embodiment of the present application. The energy storage device may be a power station storage, a grid-side storage, such as a grid-connected system, or other types of energy storage products, which are not limited in the present application.
[0103] In the description of the embodiments of the present application, it should be noted that the terms "first", "second", etc. are used to distinguish between identical or similar items having substantially the same functions. Those skilled in the art can understand that the terms "first", "second", etc. do not limit the quantity and execution order, and the terms "first", "second", etc. do not necessarily limit the differences, and therefore cannot be understood as limiting the present application.
[0104] What is disclosed above is only a preferred embodiment of the present application, and it certainly cannot be used to limit the scope of rights of the present application. Ordinary technicians in this field can understand that all or part of the processes of implementing the above embodiment and equivalent changes made according to the claims of the present application are still within the scope covered by the present application.
Claims
1. A voltage phase-locking method, characterized in that: include: Obtaining the mains voltage signal; Performing a DC bias removal process on the mains voltage signal; The DC bias-free AC voltage signal is phase-locked in the first level.
2. The phase locking method according to claim 1, characterized in that: Before the DC bias removal process is performed on the mains voltage signal, the method further includes: The mains voltage signal is filtered and processed with an average value of a power frequency cycle to obtain a mains voltage signal with a DC bias removed.
3. The phase locking method according to claim 2, characterized in that: The filtering of the mains voltage signal and the processing of the power frequency period average value to obtain the mains voltage signal without direct current bias comprises: Taking the power frequency period average value of the mains voltage signal; The mains voltage signal is first-order filtered and the average value of the power frequency cycle is subtracted to obtain a mains voltage signal without direct current bias.
4. The phase locking method according to any one of claims 1 to 3, characterized in that: The first-level phase locking of the DC bias-free mains voltage signal comprises: Based on one power frequency cycle or half a power frequency cycle, the DC bias-free AC voltage signal is phase-locked in the first level.
5. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: Acquire at least one of the effective value of the mains voltage and the frequency of the mains voltage obtained after the first-level phase locking; When at least one of the effective value of the mains voltage is greater than or equal to a first threshold and the frequency of the mains voltage is greater than or equal to a second threshold is satisfied, secondary phase locking is performed on the mains voltage signal after primary phase locking.
6. The phase locking method according to claim 5, characterized in that: The second-level phase locking of the mains voltage signal after the first-level phase locking comprises: Based on one power frequency cycle or half a power frequency cycle, the mains voltage signal after the primary phase locking is subjected to secondary phase locking.
7. A voltage phase-locked system, characterized in that: include: An acquisition module, used for acquiring a mains voltage signal; A DC bias removal module, used for performing DC bias removal processing on the mains voltage signal; as well as The primary phase-locking module is used to perform primary phase-locking on the DC bias-free AC voltage signal.
8. The phase-locked system according to claim 7, characterized in that: The system further comprises: The secondary phase locking module is used to perform secondary phase locking on the mains voltage signal after the primary phase locking.
9. A charger, characterized in that: Comprising a phase-locked system as described in any one of claims 7-8.
10. A vehicle, characterized in that: Comprising the charger as claimed in claim 9.