Single-slope analog-to-digital converter, reading method thereof and image sensor

Abstract

The invention provides a single-slope analog-to-digital converter, a reading method thereof and an image sensor. The single-slope analog-to-digital converter comprises a comparator, a logic control circuit and a counter, a first input end of the comparator accesses a reset signal or a most significant bit signal according to a logic control signal, and a second input end accesses a ramp signal and a pixel signal; the input end of the logic control circuit is connected with the output end of the comparator so as to generate a logic control signal according to the analog signal output by the comparator; the input end of the counter is connected with the output end of the logic control circuit so as to carry out quantitative counting according to the output of the logic control circuit. By combining the most significant bit technology and the comparator fixed input level flipping technology, the high-speed operation of the single-slope analog-to-digital converter can be ensured, and the DCDS function can be adapted, so that the FPN of the single-slope analog-to-digital converter is effectively reduced, and the reliability of the single-slope analog-to-digital converter is improved. The problem that an existing two-step single-slope analog-to-digital converter cannot adapt to digital correlated double sampling, and consequently noise of output signals is large is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a single-slope analog-to-digital converter and a readout method thereof, and an image sensor. Background Art

[0002] Image sensors usually use analog-to-digital converters (ADCs) to quantify photoelectric signals. For ADCs, commonly used circuit structures include single-slope ADCs (SS ADCs), successive approximation ADCs (SAR ADCs), and cyclic ADCs.

[0003] Among them, the conversion essence of SS ADC is the conversion from voltage domain to time domain and then to digital domain. According to the pixel data readout method, each column or row uses a comparator and counter, and the entire array shares a ramp signal generation circuit. The circuit is simple, so its power consumption is low and the occupied area is small. It is an ADC architecture suitable for array applications such as image sensors. However, the conversion time of traditional SS ADC increases exponentially with the increase of ADC bit number, which leads to its conversion speed being too slow, greatly limiting the application of SS ADC.

[0004] In order to improve the conversion speed of SS ADC, a two-step quantization method is usually used to reduce the cycle of SS ADC. However, the existing two-step quantization method is difficult to combine with the digital correlated double sampling (DCDS) operation. Therefore, when a two-step quantized SS ADC is used, DCDS cannot be used to reduce the fixed pattern noise (FPN) caused by charge injection, comparator adaptation and response delay, resulting in a large noise in the output signal, affecting the image quality. Moreover, the coarse quantization process and the fine quantization process in the existing two-step quantization method need to match different ramp signals, thereby increasing the corresponding circuits and signals, and the routing is complicated, which makes the device area of ​​SS ADC larger and the linearity poorer.

[0005] In addition, due to the mismatch of device parameters, the existing SS ADC structure using a two-step quantization method usually introduces errors in the transmission of the coarse quantization residual voltage and the fine quantization reference voltage, which will cause problems such as missing or repeated codes in the ADC, thereby seriously affecting the imaging quality of the image sensor. Summary of the invention

[0006] The object of the present invention is to provide a single slope analog-to-digital converter and a readout method thereof, and an image sensor, so as to at least solve the problem that the existing two-step single slope analog-to-digital converter cannot adapt to digital correlated double sampling, resulting in large output signal noise.

[0007] In order to solve the above technical problems, the present invention provides a single-slope analog-to-digital converter, including a comparator, a logic control circuit and a counter; the first input end of the comparator is connected to a reset signal or a most significant bit signal through a first switch, and the first switch is controlled by a logic control signal; the second input end of the comparator is connected to a ramp signal and a pixel signal through a second switch, and the second switch is controlled by a sampling control signal; the first input end and the second input end of the comparator are connected through a reset switch, and the reset switch is controlled by a reset control signal; the output end of the comparator is connected to the input end of the logic control circuit, and the logic control circuit is used to generate a logic control signal according to the analog signal output by the comparator; the output end of the logic control circuit is connected to the input end of the counter, and the counter is used to perform quantization counting according to the output result of the logic control circuit to convert the analog signal into a digital signal.

[0008] Optionally, in the single-slope analog-to-digital converter, the second input terminal of the comparator is connected to the second switch via a first coupling capacitor; and the second input terminal of the comparator is connected to the ramp signal via the first coupling capacitor and the second coupling capacitor.

[0009] Optionally, in the single-slope analog-to-digital converter, the single-slope analog-to-digital converter also includes a memory; the input end of the memory is connected to the output end of the logic control circuit, and is used to store the highest bit value in the most significant bit signal.

[0010] Optionally, in the single-slope analog-to-digital converter, the first input terminal of the comparator is an inverting input terminal, and the second input terminal is a non-inverting input terminal.

[0011] In order to solve the above technical problems, the present invention further provides a readout method of a single slope analog-to-digital converter, which is applied to the single slope analog-to-digital converter as described in any one of the above items, and the readout method comprises: Reset quantization: The first input terminal of the comparator is connected to the reset signal, and the second input terminal is connected to the input signal after the pixel signal and the ramp signal are coupled. At this time, the pixel signal is the pixel reset signal; Pre-comparison: The first input terminal of the comparator is connected to the most significant bit signal, and the logic control circuit generates a logic control signal according to the analog signal output by the comparator; Signal quantization: The first input terminal of the comparator selects the input signal according to the logic control signal, and the second input terminal receives the input signal after the pixel signal and the ramp signal are coupled. At this time, the pixel signal is the pixel photosensitivity signal.

[0012] Optionally, in the readout method of the single slope analog-to-digital converter, before performing the reset quantization, the readout method further includes: Comparator reset: The reset switch is closed by the reset control signal to reset the comparator.

[0013] Optionally, in the readout method of the single slope analog-to-digital converter, the method of resetting quantization includes: The first input terminal of the comparator is connected to the reset signal, the second switch is closed, and the ramp enable signal is invalid, so that the second input terminal of the comparator samples the pixel signal. At this time, the pixel signal is a pixel reset signal; When the sampling is completed, the second switch is turned off, and the ramp enable signal is valid, so as to couple the sampled pixel signal with the ramp signal to obtain an input signal; The comparator compares the input signal with the reset signal. When the input signal is less than the reset signal, the analog signal output by the comparator is low level and the counter starts counting.

[0014] Optionally, in the readout method of the single slope analog-to-digital converter, the pre-comparison method includes: The first input terminal of the comparator is connected to the most significant bit signal, the second switch is closed, and the ramp enable signal is invalid, so that the second input terminal of the comparator samples the pixel signal; When the sampling is completed, the second switch is disconnected, and the comparator compares the pixel signal and the most significant bit signal: when the pixel signal is greater than the most significant bit signal, the analog signal output by the comparator is a high level, and the logic control signal generated by the logic control circuit is used to control the first input terminal of the comparator to access the reset signal during the signal quantization stage; when the pixel signal is less than the most significant bit signal, the analog signal output by the comparator is a low level, and the logic control signal generated by the logic control circuit is used to control the first input terminal of the comparator to access the most significant bit signal during the signal quantization stage.

[0015] Optionally, in the readout method of the single slope analog-to-digital converter, the pre-comparison method further comprises: When the analog signal output by the comparator is at a high level, the highest bit value stored is 0; when the analog signal output by the comparator is at a low level, the highest bit value stored is 1.

[0016] Optionally, in the readout method of the single slope analog-to-digital converter, the signal quantization method includes: The second switch is closed, and the ramp enable signal is invalid, so that the second input terminal of the comparator samples the pixel signal. At this time, the pixel signal is a pixel light-sensing signal; When the sampling is completed, the second switch is turned off, and the ramp enable signal is valid, so as to couple the sampled pixel signal with the ramp signal to obtain an input signal; When the first input terminal of the comparator is connected to the reset signal, the comparator compares the input signal with the reset signal. When the input signal is less than the reset signal, the analog signal output by the comparator is low level, and the counter starts counting. When the first input terminal of the comparator is connected to the most significant bit signal, the comparator compares the input signal with the most significant bit signal. When the input signal is less than the most significant bit signal, the analog signal output by the comparator is low level and the counter starts counting.

[0017] In order to solve the above technical problem, the present invention further provides an image sensor, comprising the single slope analog-to-digital converter as described in any one of the above items.

[0018] Optionally, in the image sensor, the image sensor also includes a pixel array and a ramp generator; the pixel array is used to provide a pixel signal, and the pixel signal includes a pixel reset signal and a pixel photosensitivity signal; the ramp generator is used to provide a ramp signal.

[0019] The single-slope analog-to-digital converter and its readout method, and image sensor provided by the present invention include a comparator, a logic control circuit, and a counter; the first input end of the comparator is connected to a reset signal or a most significant bit signal through a first switch, and the first switch is controlled by a logic control signal; the second input end of the comparator is connected to a ramp signal, and is connected to a pixel signal through a second switch, and the second switch is controlled by a sampling control signal; the first input end and the second input end of the comparator are connected through a reset switch, and the reset switch is controlled by a reset control signal; the output end of the comparator is connected to the input end of the logic control circuit, and the logic control circuit is used to generate a logic control signal according to the analog signal output by the comparator; the output end of the logic control circuit is connected to the input end of the counter, and the counter is used to perform quantization counting according to the output result of the logic control circuit to convert the analog signal into a digital signal. By making the comparator compare the pixel signal with the reset signal and the most significant bit signal, and combining the most significant bit technology with the comparator fixed input level flipping technology, not only can the high-speed operation of the single-slope analog-to-digital converter be guaranteed, but also the DCDS function can be adapted, thereby effectively reducing the FPN of the single-slope analog-to-digital converter and solving the problem of large output signal noise caused by the inability of the existing two-step single-slope analog-to-digital converter to adapt to digital correlated double sampling. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of the circuit structure of a single slope analog-to-digital converter provided in this embodiment; Figure 2A flow chart of a readout method of a single slope analog-to-digital converter provided in this embodiment; Figure 3 A schematic diagram of a waveform of a ramp signal provided in this embodiment; Figure 4 A readout timing diagram of the single slope analog-to-digital converter provided in this embodiment when a low voltage difference pixel signal is input; Figure 5 This is a readout timing diagram of the single-slope analog-to-digital converter provided in this embodiment when a high-voltage difference pixel signal is input. DETAILED DESCRIPTION

[0021] The single slope analog-to-digital converter and its readout method and image sensor proposed in the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the accompanying drawings is often a part of the actual structure. In particular, the emphasis of each accompanying drawing is different, and sometimes different proportions are used.

[0022] It should be noted that the terms "first", "second", etc. in the specification, claims and drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, rather than to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0023] This embodiment provides a single slope analog-to-digital converter, such as Figure 1 As shown, it includes a comparator, a logic control circuit and a counter. The first input terminal IN- of the comparator is connected to the reset signal V through the first switch K1. RST Or the most significant bit signal V REF The first switch K1 is controlled by a logic control signal ΨN; the second input terminal IN+ of the comparator is connected to a ramp signal V RAMP and access the pixel signal V through the second switch K2 PIX, the second switch K2 is controlled by a sampling control signal ΨP; the first input terminal IN- and the second input terminal IN+ of the comparator are connected through a reset switch K3, and the reset switch K3 is controlled by a reset control signal Ψrst; the output terminal of the comparator is connected to the input terminal of the logic control circuit, and the logic control circuit is used to generate a logic control signal ΨN according to the analog signal Comp_out output by the comparator; the output terminal of the logic control circuit is connected to the input terminal of the counter, and the counter is used to perform quantization counting according to the output result of the logic control circuit to convert the analog signal into a digital signal Dout.

[0024] The single-slope analog-to-digital converter provided in this embodiment combines the most significant bit technology (Most Significant Bit, MSB) and the comparator fixed input level flipping technology by making the comparator compare the pixel signal with the reset signal and the most significant bit signal. This can not only ensure the high-speed operation of the single-slope analog-to-digital converter, but also adapt to the DCDS function, thereby effectively reducing the FPN of the single-slope analog-to-digital converter and solving the problem of large output signal noise caused by the inability of the existing two-step single-slope analog-to-digital converter to adapt to digital correlated double sampling.

[0025] Specifically, in this embodiment, the first switch K1 is a single-pole double-throw switch, and the two branches are respectively connected to the reset signal V RST and the most significant bit signal V REF , thereby controlling the switching of the two branches of the first switch K1 through the logic control signal ΨN, realizing the switching of the two signals, so that the first input terminal IN- of the comparator is connected to the required signal. For example, when the logic control signal ΨN is at a high level, the control access reset signal V RST The branch is turned on; when the logic control signal ΨN is low, the control access to the most significant bit signal V REF The branch is conductive.

[0026] Of course, in another embodiment, the first switch K1 may also be two parallel single-pole single-throw switches, and the two sub-switches are controlled by the same logic control signal ΨN. The logic control signal ΨN may be a digital signal, so that when the logic control signal ΨN is at a high level, the control access reset signal V RST The switch is closed, and the most significant bit signal V REF The switch is disconnected, and when the logic control signal ΨN is low, the control access reset signal V RST The switch is disconnected and the most significant bit signal V REF The switch is closed, thereby switching between the two signals.

[0027] Of course, in other embodiments, the logic control signal ΨN may also include two inverted logic control signals ΨN+ and ΨN-, both of which are high level valid, and respectively control the closing / opening of a sub-switch.

[0028] It should be noted that, in practical applications, those skilled in the art can set the specific circuit structure of the first switch K1 and the implementation method of controlling the first switch K1 by the logic control signal ΨN according to actual needs, and the present application does not limit this.

[0029] Furthermore, in order to realize the pixel signal V PIX In this embodiment, the second input terminal IN+ of the comparator is connected to the second switch K2 through the first coupling capacitor C1; the second input terminal IN+ of the comparator is connected to the ramp signal V through the first coupling capacitor C1 and the second coupling capacitor C2. RAMP That is to say, the second coupling capacitor C2 is connected in parallel with the second switch K2 and connected to the first coupling capacitor C1. In this way, the two coupling capacitors can not only filter out the pixel signal V PIX and the ramp signal V RAMP The noise in the pixel signal V PIX and the ramp signal V RAMP Coupling is performed to facilitate the comparison of signals by the subsequent comparator.

[0030] Preferably, in this embodiment, since the MSB technology is used, the value of the most significant bit needs to be retained for easy retrieval, so the single-slope analog-to-digital converter also includes a memory; the input end of the memory is connected to the output end of the logic control circuit, and is used to store the highest bit value in the most significant bit signal.

[0031] In this embodiment, the first input terminal of the comparator is the inverting input terminal IN-, and the second input terminal is the non-inverting input terminal IN+. Thus, when the signal input to the second input terminal IN+ is smaller than the signal input to the first input terminal IN-, the analog signal Comp_out output by the comparator is at a low level.

[0032] This embodiment also provides a readout method of a single slope analog-to-digital converter, which is applied to the single slope analog-to-digital converter as described above. Figure 2 As shown, the reading method includes: Reset quantization: The first input terminal of the comparator is connected to the reset signal, and the second input terminal is connected to the input signal after the pixel signal and the ramp signal are coupled. At this time, the pixel signal is the pixel reset signal; Pre-comparison: The first input terminal of the comparator is connected to the most significant bit signal, and the logic control circuit generates a logic control signal according to the analog signal output by the comparator; Signal quantization: The first input terminal of the comparator selects the input signal according to the logic control signal, and the second input terminal receives the input signal after the pixel signal and the ramp signal are coupled. At this time, the pixel signal is the pixel photosensitivity signal.

[0033] The readout method of the single slope analog-to-digital converter provided in this embodiment quantizes the pixel reset signal in the reset quantization stage; in the pre-comparison stage, the input pixel signal is compared with the most significant bit signal (most significant bit value, the voltage value corresponding to the MSB bit) by using the binary division method, so as to divide the pixel signal into a low voltage difference pixel signal and a high voltage difference pixel signal; in the signal quantization stage, the low voltage difference pixel signal and the high voltage difference pixel signal are quantized respectively according to the result of the pre-comparison stage. In this way, by dividing the pixel signal in the pre-comparison stage, the conversion time of the signal quantization stage can be halved, that is, the quantization process of the single slope analog-to-digital converter with N-bit resolution is divided into 1-bit MSB and (N-1)-bit quantization processes. In the signal quantization stage, for low-voltage difference pixel signals, when the comparator output is flipped, the signal voltage connected to the two input terminals of the comparator is equal to the comparator reset voltage, so it has the same response delay as the reset quantization stage, so that the DCDS function can be used to reduce noise; for high-voltage difference pixel signals, when the comparator output is flipped, the signal voltage connected to the two input terminals of the comparator is equal to the highest bit value, so the high-voltage difference pixel signals have the same response delay. Although the delay is different from the response delay in the reset quantization stage, the delay can be eliminated by fixing the error, so it can also adapt to the DCDS function.

[0034] Furthermore, the readout method of the single slope analog-to-digital converter provided in this embodiment uses a ramp signal such as Figure 3 As shown in the figure, the waveform of the ramp signal is divided into three parts according to the reset quantization stage, the pre-comparison stage and the signal quantization stage. RR Indicates the voltage value of the initial ramp signal, corresponding to the voltage value of the ramp signal when the comparator is reset and the pre-comparison stage; in the reset quantization stage, the ramp signal V RAMP The peak voltage is V peak1 , the lowest voltage is 0; in the signal quantization stage, the ramp signal V RAMP The peak voltage is V peak2 , the minimum voltage is 0.

[0035] Compared with the traditional SS ADC circuit, the voltage height required for the ramp signal of the single slope analog-to-digital converter provided by the present embodiment is reduced, so the power consumption and area of ​​the ramp generator will be reduced; at the same time, the single slope analog-to-digital converter provided by the present embodiment only needs one ramp generator to generate the ramp signal to meet the functional requirements, and only two switches are added, so that while having no significant impact on the circuit area, it not only has lower power consumption but also has higher linearity; in addition, the comparator in the single slope analog-to-digital converter provided by the present embodiment has a fixed input level (reset signal V RST Or the most significant bit signal V REF ) is flipped at the position of the ADC, so that the FPN is smaller and thus has better linearity. In this way, the single slope analog-to-digital converter provided by the embodiment effectively solves the problems of large area, high power consumption and poor linearity of the traditional two-step SS ADC.

[0036] Preferably, in this embodiment, before performing the reset quantization, the readout method further includes: comparator reset: controlling the reset switch to close by a reset control signal to reset the comparator.

[0037] Specifically, in this embodiment, the reset control signal Ψrst is effective at a high level. Figure 1 As shown, the reset switch K3 is closed by controlling the high-level reset control signal Ψrst, thereby short-circuiting the first input terminal IN- and the second input terminal IN+ of the comparator. At the same time, the first input terminal IN- of the comparator is controlled by the logic control signal ΨN to access the reset signal, thereby resetting the comparator.

[0038] It should be noted that the reset switch K3 is in a closed state only in the comparator reset phase, and in other working phases, the reset switch K3 is in an open state.

[0039] Further, in this embodiment, refer to Figure 4 and Figure 5 The readout method of the single slope analog-to-digital converter provided in this embodiment is described in detail. The sampling control signal ΨP is effective at a high level, and ΨP+ controls the second switch K2 to close; the logic control signal ΨN is effective at a high level, and ΨN+ controls the first input terminal IN- of the comparator to access the reset signal V RST ; The ramp enable signal EN_RAMP is valid at high level, controlling the ramp generator to send out the ramp signal V RAMP . Figure 4 and Figure 5 The comparator first input terminal IN- receives the signal V IN- The dashed line indicates the signal V connected to the second input terminal IN+. IN+ Is a solid line.

[0040] Specifically, in this embodiment, the method for resetting quantization includes: S11, the logic control signal ΨN controls the state of the first switch K1, so that the first input terminal IN- of the comparator is connected to the reset signal V RST , the sampling control signal ΨP is at a high level (ΨP+), the second switch K2 is controlled to close, and the ramp enable signal EN_RAMP is invalid, so that the second input terminal IN+ of the comparator is sensitive to the pixel signal V PIX Sampling is performed. At this time, the pixel signal V PIX is the pixel reset signal; S12, when the sampling is completed, the sampling control signal ΨP is at a low level, the second switch K2 is disconnected, and the pixel signal V PIX stored at the first coupling capacitor C1; S13, when the ramp enable signal EN_RAMP is valid, the ramp generator generates a ramp signal V RAMP , the sampled pixel signal V PIX With the ramp signal V RAMP The input signal V is coupled IN+ ; S14, the comparator responds to the input signal V IN+ and reset signal V RST (V IN- ) is compared, when the input signal V IN+ Less than the reset signal V RST When , the analog signal Comp_out output by the comparator is at a low level, and the counter starts counting; S15, when the ramp enable signal EN_RAMP is invalid, the counter stops counting, and the counting result obtained at this time is recorded as D out1 . D out1 It is expressed as:

[0041] in, is the counting clock frequency of the counter, S is the slope of the ramp signal, is the comparator mismatch voltage, The comparator input voltage V RST Response delay when flipping.

[0042] And, in this embodiment, the pre-comparison method includes: S21, the logic control signal ΨN controls the state of the first switch K1, so that the first input terminal IN- of the comparator is connected to the most significant bit signal V REF , the sampling control signal ΨP is at a high level (ΨP+), the second switch K2 is controlled to close, and the ramp enable signal EN_RAMP is invalid, so that the second input terminal IN+ of the comparator is sensitive to the pixel signal VPIX Sampling is performed, and the pixel signal at this time can be recorded as V SIG ; S22, when the sampling is completed, the sampling control signal ΨP is at a low level, and the second switch K2 is controlled to be disconnected. At this time, the actual pixel difference is (V RST -V SIG ); S23, the comparator performs a comparison on the pixel signal V SIG and the most significant bit signal V REF For comparison: like Figure 4 As shown, when the pixel signal V SIG Greater than the most significant bit signal V REF When the analog signal Comp_out output by the comparator is high level, the judgment (V RST -V SIG ) signal is a low voltage difference pixel signal, and the memory stores the highest bit value D msb =0; the logic control circuit generates a logic control signal ΨN according to the high-level analog signal Comp_out, which is used to control the first input terminal IN- of the comparator to access the reset signal V in the signal quantization stage RST .

[0043] like Figure 5 As shown, when the pixel signal V SIG Less than the most significant bit signal V REF When the analog signal Comp_out output by the comparator is low level, the judgment (V RST -V SIG ) signal is a high-voltage difference pixel signal, and the memory stores the highest bit value D msb =1; the logic control circuit generates a logic control signal ΨN according to the low-level analog signal Comp_out, which is used to control the first input terminal IN- of the comparator to access the most significant bit signal V in the signal quantization stage. REF .

[0044] And, in this embodiment, similar to the reset quantization process, the signal quantization method includes: S31, the sampling control signal ΨP is at a high level (ΨP+), the second switch K2 is controlled to be closed, and the ramp enable signal EN_RAMP is invalid, so that the second input terminal IN+ of the comparator is sensitive to the pixel signal V PIX Sampling is performed. At this time, the pixel signal V PIX is the pixel light-sensing signal V SIG ; S32, when the sampling is completed, the sampling control signal ΨP is at a low level, the second switch K2 is disconnected, and the ramp enable signal EN_RAMP is valid to convert the sampled pixel signal V PIX With the ramp signal VRAMP The input signal V is coupled IN+ ; S33-1, such as Figure 4 As shown, when the first input terminal IN- of the comparator is connected to the reset signal V RST When the comparator responds to the input signal V IN+ and reset signal V RST When the input signal V IN+ Less than the reset signal V RST When , the analog signal output by the comparator is low level Comp_out, and the counter starts counting; S33-2, such as Figure 5 As shown, when the first input terminal IN- of the comparator is connected to the most significant bit signal V REF When the comparator responds to the input signal V IN+ and the most significant bit signal V REF When the input signal V IN+ Less than the most significant bit signal V REF When , the analog signal output by the comparator is low level Comp_out, and the counter starts counting; S34, when the ramp enable signal EN_RAMP is invalid, the counter stops counting, and the counting result obtained at this time is recorded as D out2 .

[0045] In step S33-1, when the first input terminal IN- of the comparator is connected to the reset signal V RST When D out2 It is expressed as:

[0046] At this time, the final quantized output digital signal D out (corresponding to the pixel difference (V RST -V SIG )) can be expressed as:

[0047] For step S33-2, when the first input terminal IN- of the comparator is connected to the most significant bit signal V REF When D out2 It is expressed as:

[0048] in, is the value corresponding to the highest bit, The comparator input voltage V REF Response delay when flipping.

[0049] At this time, the final quantized output digital signal Dout (corresponding to the pixel difference (V RST -V SIG )) can be expressed as:

[0050] In actual application, the reset voltage V of the comparator can be designed. RST and reference voltage (most significant bit signal) V REF season:

[0051] Then, we can get:

[0052] In this way, the digital signal after analog-to-digital conversion can be accurately obtained.

[0053] The readout method of the single slope analog-to-digital converter provided in this embodiment only needs to change the height of the ramp signal from (V peak1 +V msb ) drops to 0; while the traditional SS ADC needs to go from (V peak1 +2×V msb ) drops to 0. Therefore, the number of row conversion clock pulses saved by the single slope analog-to-digital converter provided by this embodiment compared with the traditional SS ADC is:

[0054] It can be seen from the above formula that the number of clock pulses saved by the single-slope analog-to-digital converter provided by the present embodiment increases exponentially with the increase of the number of bits of the ADC compared to the existing single-slope analog-to-digital converter, that is, when the number of bits of the ADC is large, the single-slope analog-to-digital converter provided by the present embodiment can save more clock pulses; and the voltage height of the ramp signal required by the single-slope analog-to-digital converter provided by the present embodiment is lower, so the area and power consumption of the ramp generator are smaller. In addition, the single-slope analog-to-digital converter provided by the present embodiment only requires one ramp generator, so it has higher linearity and lower power consumption. In addition, the comparator in the single-slope analog-to-digital converter provided by the present embodiment flips at a fixed input level with the same corresponding delay, so the FPN of the ADC is smaller.

[0055] This embodiment also provides an image sensor, comprising the single-slope analog-to-digital converter as described above.

[0056] Specifically, in actual application, the image sensor further includes a pixel array and a ramp generator; the pixel array is used to provide a pixel signal, and the pixel signal includes a pixel reset signal and a pixel photosensitivity signal; the ramp generator is used to provide a ramp signal.

[0057] The image sensor provided by the present embodiment, wherein the single slope analog-to-digital converter and the readout method thereof, by adding switches and reference voltages in the SSADC circuit, combines the pre-quantized MSB technology with the comparator fixed input level flipping technology, and can adapt to DCDS while improving the conversion speed of the SS ADC, thereby reducing the FPN of the analog-to-digital converter; at the same time, this method also solves the problem of different response delays when the comparator flips under different pixel input voltages, and realizes the design of a high-speed SS ADC by using only one ramp generator. The SS ADC has the advantages of high linearity, low power consumption, etc., so that the image sensor using it has high output efficiency while ensuring high output image quality.

[0058] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.

[0059] The single-slope analog-to-digital converter and its readout method, and image sensor provided in this embodiment include a comparator, a logic control circuit, and a counter; the first input end of the comparator is connected to a reset signal or a most significant bit signal through a first switch, and the first switch is controlled by a logic control signal; the second input end of the comparator is connected to a ramp signal and a pixel signal through a second switch, and the second switch is controlled by a sampling control signal; the first input end and the second input end of the comparator are connected through a reset switch, and the reset switch is controlled by a reset control signal; the output end of the comparator is connected to the input end of the logic control circuit, and the logic control circuit is used to generate a logic control signal according to the analog signal output by the comparator; the output end of the logic control circuit is connected to the input end of the counter, and the counter is used to perform quantization counting according to the output result of the logic control circuit to convert the analog signal into a digital signal. By making the comparator compare the pixel signal with the reset signal and the most significant bit signal, and combining the most significant bit technology with the comparator fixed input level flipping technology, not only can the high-speed operation of the single-slope analog-to-digital converter be guaranteed, but also the DCDS function can be adapted, thereby effectively reducing the FPN of the single-slope analog-to-digital converter and solving the problem of large output signal noise caused by the inability of the existing two-step single-slope analog-to-digital converter to adapt to digital correlated double sampling.

[0060] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A single slope analog-to-digital converter, characterized in that: It comprises a comparator, a logic control circuit and a counter; the first input end of the comparator is connected to a reset signal or a most significant bit signal through a first switch, and the first switch is controlled by a logic control signal; the second input end of the comparator is connected to a ramp signal, and is connected to a pixel signal through a second switch, and the second switch is controlled by a sampling control signal; the first input end and the second input end of the comparator are connected through a reset switch, and the reset switch is controlled by a reset control signal; the output end of the comparator is connected to the input end of the logic control circuit, and the logic control circuit is used to generate a logic control signal according to the analog signal output by the comparator; The output end of the logic control circuit is connected to the input end of the counter, and the counter is used to perform quantitative counting according to the output result of the logic control circuit to convert the analog signal into a digital signal.

2. The single slope analog-to-digital converter according to claim 1, characterized in that: The second input terminal of the comparator is connected to the second switch through the first coupling capacitor; the second input terminal of the comparator is connected to the ramp signal through the first coupling capacitor and the second coupling capacitor.

3. The single slope analog-to-digital converter according to claim 1, characterized in that: The single slope analog-to-digital converter also includes a memory; the input end of the memory is connected to the output end of the logic control circuit and is used to store the highest bit value in the most significant bit signal.

4. The single slope analog-to-digital converter according to claim 1, characterized in that: The first input terminal of the comparator is an inverting input terminal, and the second input terminal is a non-inverting input terminal.

5. A readout method of a single slope analog-to-digital converter, applied to the single slope analog-to-digital converter according to any one of claims 1 to 4, characterized in that: The reading method comprises: Reset quantization: The first input terminal of the comparator is connected to the reset signal, and the second input terminal is connected to the input signal after the pixel signal and the ramp signal are coupled. At this time, the pixel signal is the pixel reset signal; Pre-comparison: The first input terminal of the comparator is connected to the most significant bit signal, and the logic control circuit generates a logic control signal according to the analog signal output by the comparator; Signal quantization: The first input terminal of the comparator selects the input signal according to the logic control signal, and the second input terminal receives the input signal after the pixel signal and the ramp signal are coupled. At this time, the pixel signal is the pixel photosensitivity signal.

6. The readout method of the single slope analog-to-digital converter according to claim 5, characterized in that: Before performing the resetting quantization, the readout method further includes: Comparator reset: The reset switch is closed by the reset control signal to reset the comparator.

7. The readout method of the single slope analog-to-digital converter according to claim 5, characterized in that: The method for resetting quantization comprises: The first input terminal of the comparator is connected to the reset signal, the second switch is closed, and the ramp enable signal is invalid, so that the second input terminal of the comparator samples the pixel signal. At this time, the pixel signal is a pixel reset signal; When the sampling is completed, the second switch is turned off, and the ramp enable signal is valid, so as to couple the sampled pixel signal with the ramp signal to obtain an input signal; The comparator compares the input signal with the reset signal. When the input signal is less than the reset signal, the analog signal output by the comparator is low level and the counter starts counting.

8. The readout method of the single slope analog-to-digital converter according to claim 5, characterized in that: The pre-comparison method comprises: The first input terminal of the comparator is connected to the most significant bit signal, the second switch is closed, and the ramp enable signal is invalid, so that the second input terminal of the comparator samples the pixel signal; When the sampling is completed, the second switch is disconnected, and the comparator compares the pixel signal and the most significant bit signal: when the pixel signal is greater than the most significant bit signal, the analog signal output by the comparator is a high level, and the logic control signal generated by the logic control circuit is used to control the first input terminal of the comparator to access the reset signal during the signal quantization stage; when the pixel signal is less than the most significant bit signal, the analog signal output by the comparator is a low level, and the logic control signal generated by the logic control circuit is used to control the first input terminal of the comparator to access the most significant bit signal during the signal quantization stage.

9. The readout method of the single slope analog-to-digital converter according to claim 8, characterized in that: The pre-comparison method further comprises: When the analog signal output by the comparator is at a high level, the highest bit value stored is 0; when the analog signal output by the comparator is at a low level, the highest bit value stored is 1.

10. The readout method of the single slope analog-to-digital converter according to claim 5, characterized in that: The signal quantization method comprises: The second switch is closed, and the ramp enable signal is invalid, so that the second input terminal of the comparator samples the pixel signal. At this time, the pixel signal is a pixel light-sensing signal; When the sampling is completed, the second switch is turned off, and the ramp enable signal is valid, so as to couple the sampled pixel signal with the ramp signal to obtain an input signal; When the first input terminal of the comparator is connected to the reset signal, the comparator compares the input signal with the reset signal. When the input signal is less than the reset signal, the analog signal output by the comparator is at a low level, and the counter starts counting. When the first input terminal of the comparator is connected to the most significant bit signal, the comparator compares the input signal with the most significant bit signal. When the input signal is less than the most significant bit signal, the analog signal output by the comparator is low level and the counter starts counting.

11. An image sensor, characterized in that: It comprises a single slope analog-to-digital converter as described in any one of claims 1 to 4.

12. The image sensor according to claim 11, characterized in that The image sensor further comprises a pixel array and a ramp generator; the pixel array is used to provide a pixel signal, wherein the pixel signal comprises a pixel reset signal and a pixel light-sensing signal; the ramp generator is used to provide a ramp signal.

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