Digital-to-analog converter chip and DAC converter

Abstract

The invention discloses a digital-to-analog converter chip and a DAC (Digital-to-Analog Converter). The chip comprises a resistance conversion network; a first buffer; a switch control unit; a sampling capacitor; the conversion control unit is configured to respectively generate a switch input logic control signal and a clock control signal according to a digital input signal and an enable signal, and the clock control signal is used for controlling the switch control unit to be disconnected when the resistance conversion network starts digital-to-analog conversion, so that the analog signal output end keeps a voltage value of a previous state; and when the holding time is over, the switch control unit is controlled to be closed, so that the sampling capacitor samples the voltage converted by the resistance conversion network. The chip generates the switch input logic control signal and the clock control signal based on the digital input signal and the enable signal, the requirement for synchronization of the clock control signal and the switch input logic control signal is easily met, and meanwhile the output short-time burr pulse phenomenon of the digital-to-analog converter is improved by setting the holding time.

Description

Technical Field

[0001] The invention relates to the technical field of DAC (Digital to Analog Converter), and in particular to a digital to analog converter chip and a DAC converter. Background Art

[0002] At the main carry transition point of the DAC, when the most significant bit changes from low to high, the lower bits change from high to low. During the digital signal conversion, it is easy to observe that the dynamic output of the DAC is nonlinear, among which short-term glitch pulses are one of the important influencing factors.

[0003] In the related art, a technical solution of adding a first-order low-pass filter to the output end of the digital-to-analog converter is usually adopted to achieve the purpose of improving or eliminating short-time glitch pulses. However, when adopting the above technical solution, since the glitch pulse energy will not be lost, the stabilization time of the digital-to-analog converter is prolonged, which has an adverse effect on the working performance of the digital-to-analog converter. Summary of the invention

[0004] The present invention aims to solve one of the technical problems in the related art to at least a certain extent. To this end, one purpose of the present invention is to provide a digital-to-analog converter chip, which generates a switch input logic control signal and a clock control signal based on a digital input signal and an enable signal, and is easy to meet the requirement of synchronization between the clock control signal and the switch input logic control signal. At the same time, by setting the holding time, it can ensure to a certain extent that the main carry conversion of the digital-to-analog converter is completed, thereby improving the short-term glitch pulse phenomenon of the output of the digital-to-analog converter without increasing the stabilization time of the digital-to-analog converter.

[0005] A second objective of the present invention is to provide a DAC converter.

[0006] The digital-to-analog converter chip of the embodiment of the present invention includes: a resistor conversion network; a first buffer, the input end of the first buffer is connected to the output end of the resistor conversion network; a switch control unit, the first end of the switch control unit is connected to the output end of the first buffer, and the second end of the switch control unit is used as an analog signal output end; a sampling capacitor, one end of the sampling capacitor is connected to the second end of the switch control unit, and the other end of the sampling capacitor is grounded; a conversion control unit is configured to generate a switch input logic control signal and a clock control signal according to a digital input signal and an enable signal, respectively, wherein the switch input logic control signal is used to control the resistor conversion network to perform digital-to-analog conversion, and the clock control signal is used to control the switch control unit to be disconnected when the resistor conversion network starts digital-to-analog conversion, so that the analog signal output end maintains the voltage value of the previous state, and controls the switch control unit to be closed when the holding time ends, so that the sampling capacitor samples the voltage converted by the resistor conversion network.

[0007] According to the digital-to-analog converter chip of the embodiment of the present invention, the input end of the first buffer is connected to the output end of the resistance conversion network, the first end of the switch control unit is connected to the output end of the first buffer, the second end of the switch control unit is used as the analog signal output end, one end of the sampling capacitor is connected to the second end of the switch control unit, and the other end of the sampling capacitor is grounded, and the conversion control unit generates a switch input logic control signal and a clock control signal according to the digital input signal and the enable signal, respectively, wherein the switch input logic control signal is used to control the resistance conversion network to perform digital-to-analog conversion, and the clock control signal is used to control the switch control unit to be disconnected when the resistance conversion network starts digital-to-analog conversion, so that the analog signal output end maintains the voltage value of the previous state, and controls the switch control unit to be closed at the end of the holding time, so that the sampling capacitor samples the voltage after the resistance conversion network is converted. Thus, the chip generates the switch input logic control signal and the clock control signal based on the digital input signal and the enable signal, and it is easy to meet the requirements of synchronization between the clock control signal and the switch input logic control signal. At the same time, by setting the holding time, it can ensure that the main carry conversion of the digital-to-analog converter is completed to a certain extent, so that the output short-time glitch pulse phenomenon of the digital-to-analog converter is improved without increasing the stabilization time of the digital-to-analog converter.

[0008] In addition, the digital-to-analog converter chip according to the above embodiment of the present invention may also have the following additional technical features:

[0009] According to one embodiment of the present invention, the holding time is shorter than the sampling time.

[0010] According to one embodiment of the present invention, the conversion control unit includes: an inverting module, the input end of the inverting module is connected to an enable signal; a first NAND gate, the first input end of the first NAND gate is connected to a digital input signal, and the second input end of the first NAND gate is connected to the output end of the inverting module; a second buffer, the input end of the second buffer is connected to the output end of the first NAND gate; a first inverter, the input end of the first inverter is connected to the output end of the second buffer, and the output end of the first inverter is suitable for outputting a switch input logic control signal to a resistor conversion network; a trigger module, the first input end of the trigger module is connected to the output end of the inverting module, and the second input end of the trigger module is connected to the digital input signal; a first OR gate, the input end of the first OR gate is connected to the output end of the trigger module; a third buffer, the input end of the third buffer is connected to the output end of the first OR gate, and the output end of the third buffer is suitable for outputting a sampling signal; a second inverter, the input end of the second inverter is connected to the output end of the third buffer, and the output end of the second inverter is suitable for outputting a clock control signal.

[0011] According to one embodiment of the present invention, the inverting module includes: a third inverter, the input end of the third inverter serves as the input end of the inverting module; a fourth inverter, the input end of the fourth inverter is connected to the output end of the third inverter, and the output end of the fourth inverter serves as the output end of the inverting module.

[0012] According to an embodiment of the present invention, the trigger module includes a plurality of trigger circuits, and the number of the trigger circuits is the same as the number of conversion bits of the resistance conversion network.

[0013] According to one embodiment of the present invention, the number of input terminals of the first OR gate is the same as the number of the flip-flop circuits.

[0014] According to one embodiment of the present invention, each trigger circuit includes: a first trigger sub-circuit, configured to generate a rising edge signal based on a digital input signal and an enable signal; a second trigger sub-circuit, configured to generate a falling edge signal based on the digital input signal and the enable signal; a second OR gate, wherein the first input terminal of the second OR gate is connected to the output terminal of the first trigger sub-circuit, and the second input terminal of the second OR gate is connected to the output terminal of the second trigger sub-circuit; and a fourth buffer, wherein the input terminal of the fourth buffer is connected to the output terminal of the second OR gate, and the output terminal of the fourth buffer serves as the output terminal of the trigger circuit.

[0015] According to one embodiment of the present invention, the first trigger subcircuit includes: a fifth inverter, the input end of the fifth inverter is connected to the digital input signal; a first D flip-flop, the first input end of the first D flip-flop is grounded, the second input end of the first D flip-flop is connected to the output end of the fifth inverter, and the third input end of the first D flip-flop is a set end; a first MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) tube, the gate of the first MOS tube is connected to the enable signal, the source of the first MOS tube is connected to the reference power supply, and the drain of the first MOS tube is connected to the first output end of the first D flip-flop; a first delay module, one end of the first delay module is connected to the first output end of the first D flip-flop; a fifth buffer, the input end of the fifth buffer is connected to the other end of the first delay module, and the output end of the fifth buffer is connected to the third input end of the first D flip-flop; a sixth buffer, the input end of the sixth buffer is connected to the second output end of the first D flip-flop, and the output end of the sixth buffer is suitable for outputting a rising edge signal.

[0016] According to one embodiment of the present invention, the second trigger subcircuit includes: a second D flip-flop, a first input terminal of the second D flip-flop is grounded, a second input terminal of the second D flip-flop is connected to a digital input signal, and a third input terminal of the second D flip-flop is a set terminal; a second MOS tube, a gate of the second MOS tube is connected to an enable signal, a source of the second MOS tube is connected to a reference power supply, and a drain of the second MOS tube is connected to a first output terminal of the second D flip-flop; a second delay module, one end of the second delay module is connected to a first output terminal of the second D flip-flop; a seventh buffer, an input terminal of the seventh buffer is connected to the other end of the second delay module, and an output terminal of the seventh buffer is connected to a third input terminal of the second D flip-flop; an eighth buffer, an input terminal of the eighth buffer is connected to a second output terminal of the second D flip-flop, and an output terminal of the eighth buffer is suitable for outputting a falling edge signal.

[0017] According to an embodiment of the present invention, the resistance conversion network is an R-2R type resistance network.

[0018] According to one embodiment of the present invention, the conversion bit number of the R-2R type resistor network is 8 bits.

[0019] According to one embodiment of the present invention, the R-2R type resistor network uses a Poly resistor.

[0020] According to one embodiment of the present invention, the first buffer includes an operational amplifier, a non-inverting input terminal of the operational amplifier is connected to the output terminal of the resistance conversion network, and an inverting input terminal of the operational amplifier is connected to the output terminal of the operational amplifier.

[0021] According to an embodiment of the present invention, the sampling capacitor is a MOM (Metal-Oxide-Metal) capacitor, and the capacitance is less than a preset threshold.

[0022] To achieve the above objective, a second embodiment of the present invention provides a DAC converter.

[0023] The DAC converter of the embodiment of the present invention includes the above digital-to-analog converter chip.

[0024] According to the DAC converter of the embodiment of the present invention, based on the above-mentioned digital-to-analog converter chip, the short-term glitch pulse phenomenon of the output of the digital-to-analog converter is improved, thereby ensuring the working performance of the DAC converter.

[0025] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a block diagram of a digital-to-analog converter chip according to an embodiment of the present invention;

[0027] Figure 2 is a circuit diagram of an R-2R type resistor network in the related art;

[0028] Figure 3 A circuit diagram of a resistance conversion network, a first buffer and a switch control unit according to a specific embodiment of the present invention;

[0029] Figure 4 is a circuit diagram of a conversion control unit according to a specific embodiment of the present invention;

[0030] Figure 5 is a circuit diagram of a trigger module according to a specific embodiment of the present invention;

[0031] Figure 6 is an output waveform diagram of a trigger module according to a specific embodiment of the present invention;

[0032] Figure 7 is a waveform diagram of a sample signal output by a second buffer according to an embodiment of the present invention;

[0033] Figure 8 The output signal waveform diagrams of the clock control signal, the R-2R digital-to-analog conversion circuit in the related art, and the digital-to-analog conversion chip in one embodiment of the present invention;

[0034] Fig. 9 The output voltage simulation result of the R-2R digital-to-analog conversion circuit in the related art;

[0035] Fig.10 is an output voltage simulation result of a digital-to-analog conversion chip according to a specific embodiment of the present invention;

[0036] Fig.11 is a block diagram of a DAC converter according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0038] The digital-to-analog converter chip and the DAC converter according to the embodiments of the present invention are described below with reference to the accompanying drawings.

[0039] During the operation of the DAC, when the most significant bit changes from low to high, the lower bits change from high to low. The most significant bit refers to the n-1 bit in an n-bit binary number, which has the highest weight 2^(n-1), that is, the leftmost bit in the binary. During the conversion of digital signals, the analog signal output by the DAC is nonlinear, among which short-term glitch pulses are one of the important influencing factors.

[0040] The occurrence of short-term glitch pulse phenomenon is mainly because the internal switches of the digital-to-analog converter cannot achieve very precise synchronous control during the digital-to-analog conversion process. This asynchrony of the internal switches will cause all switches to be high or low for a short period of time. After a period of time, when the switches are restored, the digital-to-analog converter will output short-term glitch pulses in the opposite direction.

[0041] In order to solve the problem of short-time glitch pulses, a method of adding a first-order low-pass filter at the output end of the digital-to-analog converter, or a method of sampling / holding capacitors and amplifiers at the output end of the digital-to-analog converter is usually adopted to achieve the purpose of improving or eliminating short-time glitch pulses.

[0042] However, if a technical solution of adding a first-order low-pass filter to the output end of the digital-to-analog converter is adopted, the energy of the generated glitch pulse will not be lost, resulting in a longer stabilization time of the digital-to-analog converter; if a technical solution of sampling / holding capacitors and amplifiers at the output end of the digital-to-analog converter is adopted, it is necessary to sample in the middle of the digital input signal, so the sampling time is short and the holding time is long, and a larger sampling capacitor needs to be selected. In addition, a switch controlled by a clock control signal needs to be added, and the clock control signal must be synchronized with the digital input signal, which will occupy a larger module area.

[0043] In summary, how to eliminate short-term glitch pulses without increasing the stabilization time and greatly increasing the module area of ​​the digital-to-analog converter has become an urgent problem to be solved.

[0044] In order to solve the above problems, the present application proposes a digital-to-analog converter chip. The digital-to-analog converter chip of the present application is described in detail below with reference to the accompanying drawings.

[0045] Figure 1 is a block diagram of a digital-to-analog converter chip according to an embodiment of the present invention.

[0046] like Figure 1 As shown, the digital-to-analog converter chip of the embodiment of the present invention may include: a resistance conversion network 10 , a first buffer 20 , a switch control unit 30 , a sampling capacitor C and a conversion control unit 40 .

[0047] The input end of the first buffer 20 is connected to the output end of the resistance conversion network 10. The first end of the switch control unit 30 is connected to the output end of the first buffer 10, and the second end of the switch control unit 30 is used as the analog signal output end. One end of the sampling capacitor C is connected to the second end of the switch control unit 30, and the other end of the sampling capacitor C is grounded. The conversion control unit 40 is configured to generate a switch input logic control signal d<7:0> and a clock control signal CK according to the digital input signal DIN<7:0> and the enable signal EN, respectively, wherein the switch input logic control signal d<7:0> is used to control the resistance conversion network 10 to perform digital-to-analog conversion, and the clock control signal CK is used to control the switch control unit 30 to be disconnected when the resistance conversion network 10 starts digital-to-analog conversion, so that the analog signal output end maintains the voltage value of the previous state, and controls the switch control unit 30 to be closed at the end of the holding time, so that the sampling capacitor C samples the voltage after the resistance conversion network 10 is converted.

[0048] Specifically, the resistance conversion network 10 is used to convert and output analog signals. For example, an inverted T-type resistance network, a weighted resistance network, etc. may be used, and the specific selection may be made according to actual conditions.

[0049] The resistance conversion network 10 is Figure 2 Take the R-2R resistor network shown in the figure, where the conversion bit number of the R-2R resistor network is 8 bits, for example, the R-2R resistor network can use Poly resistors. Figure 2 In the resistor conversion network 10 shown in FIG. 1 , one end of each resistor pair is input with a logic control signal (d <0> ,d <1> ,……,d <6> ) for control. Figure 2As shown, one end of the resistor pair is connected to the drain of a PMOS tube and the drain of an NMOS tube, wherein the source of the NMOS tube is grounded, the source of the PMOS tube is connected to a preset power supply, and the gate of the PMOS tube and the gate of the NMOS tube are used to receive the corresponding switch input logic control signal and perform on-off control based on the received switch input logic control signal. <0> For example, when the switch inputs the logic control signal d <0> When the switch input logic control signal d <0> When it is at a low level, the NMOS tube is disconnected and the PMOS tube is turned on. The resistor pair is connected to the preset power supply through the turned-on PMOS tube. By analogy, the eight resistor pairs of the R-2R type resistor network are connected and controlled based on the 8-bit switch input logic control signal d<7:0> to establish a corresponding circuit, thereby outputting a corresponding voltage signal. Thus, the R-2R type resistor network completes the digital-to-analog conversion based on the switch input logic control signal d<7:0> and outputs the corresponding analog signal. At the same time, the analog signal output by the resistor conversion network 10 is output through the first buffer 20 and the switch control unit 30.

[0050] During the digital-to-analog conversion process, the conversion control unit 40 generates an eight-bit switch input logic control signal d<7:0> and a clock control signal CK for controlling the resistance conversion network 10 according to the received eight-bit digital input signal DIN<7:0> and the enable signal EN. The eight-bit switch input logic control signal d<7:0> is used to control the eight resistor pairs of the resistance conversion network 10 respectively, so as to control the resistance conversion network 10 to perform digital-to-analog conversion. The clock control signal CK is input to the control end of the switch control unit 30 to control the switch control unit 30 to be closed or opened.

[0051] Taking the case where the switch control unit 30 is disconnected when the clock control signal CK is at a high level and is closed when the clock control signal CK is at a low level as an example, when the conversion control unit 40 receives the eight-bit digital input signal DIN<7:0>, it first generates an eight-bit switch input logic control signal d<7:0> according to the eight-bit digital input signal DIN<7:0> and the enable signal EN, and outputs it to the resistor conversion network 10 through the eight-bit switch input logic control signal d<7:0>. When the resistor conversion network 10 starts digital-to-analog conversion, the conversion control unit 40 outputs a high-level clock control signal CK to the switch control unit 30 to control the switch control unit 30 to disconnect, so that the analog signal output terminal maintains the voltage value of the previous state. At the end of the hold time, the conversion control unit 40 outputs a low-level clock control signal CK to control the switch control unit 30 to close, and the analog signal converted by the resistor conversion network 10 is output through the switch control unit 30, and the sampling capacitor C samples the voltage converted by the resistor conversion network 10. During the sampling phase of the sampling capacitor C, the switch control unit 30 is always in a closed state, and the analog signal converted by the resistance conversion network 10 is output through the switch control unit 30 until the digital input signal DIN<7:0> changes, that is, the next conversion starts, and the switch control unit 30 is disconnected. The holding time can be set according to actual conditions. In one embodiment of the present invention, the holding time is less than the sampling time.

[0052] This embodiment does not need to access the clock control signal CK separately, but uses the digital input signal DIN<7:0> and the enable signal EN to generate it. While ensuring the synchronization of the clock control signal CK with the digital input signal DIN<7:0>, it also saves the chip area of ​​the digital-to-analog converter chip. At the same time, this embodiment generates the switch input logic control signal and the clock control signal based on the digital input signal and the enable signal, which is easy to meet the requirement of synchronization between the clock control signal and the switch input logic control signal. In addition, by setting the holding time, the digital-to-analog converter controls the switch control unit 30 to be disconnected at the beginning of the digital-to-analog conversion, and controls the switch control unit 30 to be closed after a period of time from the beginning of the digital-to-analog conversion, that is, the holding time, so that the short-term glitch pulse phenomenon of the digital-to-analog converter output is improved.

[0053] Further, the technical solution of sampling / holding capacitor and amplifier at the output end of the digital-to-analog converter adopted in the related art is to sample in the middle of the digital input signal, so the holding time is long and the sampling time is short, so that the capacitance demand of the sampling capacitor is relatively large. The technical solution provided by the present application is to sample in the early stage of analog-to-digital conversion, with a short holding time and a long sampling time. While ensuring sufficient sampling, a sampling capacitor C with a smaller capacitance value can also be selected. In one embodiment of the present invention, the sampling capacitor adopts a MOM capacitor, and the capacitance value is less than a preset threshold value. The MOM capacitor is more compact than the traditional multilayer ceramic capacitor type, so it can provide a higher capacitance value at the same size, and at the same time, the temperature coefficient of the MOM capacitor is lower, with better stability and a higher Q value.

[0054] It should be noted that, in addition to the above-mentioned control method in which the switch control unit 30 is disconnected when the clock control signal CK is at a high level and the switch control unit 30 is closed when the clock control signal CK is at a low level, the switch control unit 3 can also be controlled to be in an open state when the clock control signal CK is at a low level, and the analog signal output terminal maintains the voltage value of the previous state; when the clock control signal CK is at a high level, the switch control unit 3 is in a closed state, and the analog signal output terminal updates the output value under the action of the sampling capacitor C.

[0055] Combination Figure 3 As shown, in one embodiment of the present invention, the first buffer 20 includes an operational amplifier, the non-inverting input terminal of the operational amplifier is connected to the output terminal of the resistance conversion network 10, and the inverting input terminal of the operational amplifier is connected to the output terminal of the operational amplifier. In other words, the first buffer 20 of this embodiment is composed of an operational amplifier, the output terminal of the operational amplifier is connected to its inverting input terminal, and mainly plays the role of a voltage follower to improve the driving ability of the analog signal. At the same time, the output terminal of the first buffer 20 is connected to the switch control module 30.

[0056] It should be noted that the above-mentioned eight-bit R-2R digital-to-analog converter as the resistance conversion network 10 is only one implementable method of the present application, which can be applied according to actual conditions and is not limited here. For example, a ten-bit digital input signal can also be selected.

[0057] Combination Figure 4 As shown, in one embodiment of the present invention, the conversion control unit 40 includes: an inversion module 41, a first NAND gate 42, a second buffer 43, a first inverter 44, a trigger module 45, a first OR gate 46, a third buffer 47 and a second inverter 48.

[0058] Among them, the input end of the inverting module 41 is connected to the enable signal EN. The first input end of the first NAND gate 42 is connected to the digital input signal DIN<7:0>, and the second input end of the first NAND gate 42 is connected to the output end of the inverting module 41. The input end of the second buffer 43 is connected to the output end of the first NAND gate 42. The input end of the first inverter 44 is connected to the output end of the second buffer 43, and the output end of the first inverter 44 is suitable for outputting the switch input logic control signal d<7:0> to the resistor conversion network 10. The first input end of the trigger module 45 is connected to the output end of the inverting module 41, and the second input end of the trigger module 45 is connected to the digital input signal DIN<7:0>. The input end of the first OR gate 46 is connected to the output end of the trigger module 45. The input end of the third buffer 47 is connected to the output end of the first OR gate 46, and the output end of the third buffer 47 is suitable for outputting the sampling signal. The input end of the second inverter 48 is connected to the output end of the third buffer 47, and the output end of the second inverter 48 is suitable for outputting the clock control signal CK.

[0059] Specifically, the enable signal EN is input to the second output terminal of the first NAND gate 42 after passing through the inversion module 41, and the digital input signal DIN<7:0> is input to the first output terminal of the first NAND gate 42. The first NAND gate 42 compares the digital input signal DIN<7:0> with the output signal of the inversion module 41 to obtain a corresponding output signal, and sequentially outputs the signal through the second buffer 43 and the first inverter 44. The output signal of the first inverter 44 is the switch input logic control signal d<7:0>. Taking the signal output by the inversion module 41 as a high level 1 as an example, if the digital input signal DIN<7:0> is 11010011, the output after passing through the first NAND gate 42 is 00101100, and the switch input logic control signal d<7:0> obtained after the inversion module 41 is inverted after passing through the second buffer 43 is 11010011. At this time, the switch input logic control signal d<7:0> corresponds to the digital input signal DIN<7:0>. The main purpose of this embodiment is to filter out short-term glitch pulses from the digital input signal source through a series of logic gates. In addition, if the signal output by the inverting module 41 is a low level 0, and the digital input signal DIN<7:0> is 11010011, then after passing through the first NAND gate 42, the output is 11111111, and after passing through the second buffer 43, the inverting module 41 inverts and outputs the switch input logic control signal d<7:0> to be 00000000, at this time, no analog-to-digital conversion is performed.

[0060] At the same time, the output signal of the inverting module 41 and the digital input signal DIN<7:0> are input to the trigger module 45, and the corresponding output signal is obtained after data processing by the trigger module 45. The output signal passes through the first OR gate 46 and the second buffer 47 to obtain the sample signal, and the sample signal passes through the second inverter 48 to obtain the clock control signal CK to control the closing or opening of the switch control module 30. Specifically, based on the logical function of the OR gate, when one of its input terminals is at a high level, its output terminal is a high level 1; when all input terminals are at a low level, its output terminal is 0. Therefore, the trigger module 45 can generate multiple output signals based on the output signal of the inverting module 41 and the digital input signal DIN<7:0>, and input them to each input terminal of the first OR gate 46 respectively, so as to control the output of the first OR gate 46. Assuming that the output of the first OR gate 46 is a high level, the clock control signal CK output through the second buffer 47 and the second inverter 48 is a low level; if the output of the first OR gate 46 is a low level, the clock control signal CK output through the second buffer 47 and the second inverter 48 is a high level, thereby controlling the switch control unit 30.

[0061] and Figure 2 compared to, Figure 4 The circuit can ensure to a certain extent that the main carry conversion of the digital-to-analog converter is completed by holding time, that is, the opening and disconnection of all switches inside the digital-to-analog converter are completed, thereby improving the short-term glitch pulse phenomenon of the digital-to-analog converter output to a certain extent.

[0062] In one embodiment of the present invention, the inverting module 41 includes: a third inverter 411, the input end of the third inverter 411 serves as the input end of the inverting module 41; a fourth inverter 412, the input end of the fourth inverter 412 is connected to the output end of the third inverter 411, and the output end of the fourth inverter 412 serves as the output end of the inverting module 41.

[0063] Specifically, in this embodiment, the third inverter 411 and the fourth inverter 412 are connected in series to form the inversion module 41. During operation, the third inverter 411 inverts the enable signal EN, and the fourth inverter 412 inverts the inverted enable signal EN again, that is, returns to the signal direction of the original enable signal EN, and realizes the functions of shaping and balancing signal delay.

[0064] In one embodiment of the present invention, the trigger module 45 includes a plurality of trigger circuits 451 , and the number of the trigger circuits 451 is the same as the number of conversion bits of the resistance conversion network 10 .

[0065] In one embodiment of the present invention, the number of input terminals of the first OR gate 46 is the same as the number of the flip-flop circuits 451 .

[0066] That is to say, the eight-bit digital input signal DIN<7:0> is respectively input into the eight flip-flop circuits 451 to obtain corresponding output signals respectively. The output signals obtained by the eight flip-flop circuits 451 are respectively input into the eight input terminals of the first OR gate 46. After the first OR gate 46 performs logic processing on the eight output signals, a sample signal is obtained through the second buffer 47. The sample signal is passed through the second inverter 48 to obtain the clock control signal CK to control the closing or opening of the switch control module 30.

[0067] In one embodiment of the present invention, each trigger circuit 451 includes: a first trigger sub-circuit 4511, configured to generate a rising edge signal based on a digital input signal DIN<7:0> and an enable signal EN; a second trigger sub-circuit 4512, configured to generate a falling edge signal based on a digital input signal DIN<7:0> and an enable signal EN; a second OR gate 4513, wherein a first input terminal of the second OR gate 4513 is connected to an output terminal of the first trigger sub-circuit 4511, and a second input terminal of the second OR gate 4513 is connected to an output terminal of the second trigger sub-circuit 4512; and a fourth buffer 4514, wherein an input terminal of the fourth buffer 4514 is connected to an output terminal of the second OR gate 4513, and an output terminal of the fourth buffer 4514 serves as an output terminal of the trigger circuit 451.

[0068] That is to say, when performing digital-to-analog conversion, the rising edge signal generated by the first trigger sub-circuit 4511 and the falling edge signal generated by the second trigger sub-circuit 4512 constitute a corresponding pulse output signal, and the pulse output signal is logically judged by the second OR gate 4513 and the output signal is sent to one of the input terminals of the first OR gate 46 through the fourth buffer 4514.

[0069] In one embodiment of the present invention, the first trigger subcircuit 4511 includes: a fifth inverter 11, the input end of the fifth inverter 11 is connected to the digital input signal DIN<7:0>; a first D flip-flop 12, the first input end of the first D flip-flop 12 is grounded, the second input end of the first D flip-flop 12 is connected to the output end of the fifth inverter 11, and the third input end of the first D flip-flop 12 is a set end; a first MOS transistor M1, the gate g of the first MOS transistor M1 is connected to the enable signal EN, the source s of the first MOS transistor M1 is connected to the reference power supply VCC, and the A drain d of a MOS tube M1 is connected to a first output terminal of a first D flip-flop 12; a first delay module 13, one end of the first delay module 13 is connected to a first output terminal of the first D flip-flop 12; a fifth buffer 14, an input terminal of the fifth buffer 14 is connected to the other end of the first delay module 13, and an output terminal of the fifth buffer 14 is connected to a third input terminal of the first D flip-flop 12; a sixth buffer 15, an input terminal of the sixth buffer 15 is connected to a second output terminal of the first D flip-flop 12, and an output terminal of the sixth buffer 15 is suitable for outputting a rising edge signal.

[0070] In one embodiment of the present invention, the second trigger subcircuit 4512 includes: a second D flip-flop 16, wherein a first input terminal of the second D flip-flop 16 is grounded, a second input terminal of the second D flip-flop 16 is connected to a digital input signal, and a third input terminal of the second D flip-flop 16 is a set terminal; a second MOS transistor M2, wherein a gate g of the second MOS transistor M2 is connected to an enable signal, a source s of the second MOS transistor M2 is connected to a reference power supply, and a drain d of the second MOS transistor M2 is connected to a first output terminal of the second D flip-flop 16; a second delay module 17, wherein one end of the second delay module 17 is connected to a first output terminal of the second D flip-flop 16; a seventh buffer 18, wherein an input terminal of the seventh buffer 18 is connected to the other end of the second delay module 17, and an output terminal of the seventh buffer 18 is connected to a third input terminal of the second D flip-flop 16; and an eighth buffer 19, wherein an input terminal of the eighth buffer 19 is connected to a second output terminal of the second D flip-flop 16, and an output terminal of the eighth buffer 19 is suitable for outputting a falling edge signal.

[0071] Among them, the first input terminal of the first D flip-flop 12 and the second D flip-flop 16 is an input terminal, and since the first input terminal is grounded, it is always at a low level; the second input terminal of the first D flip-flop 12 and the second D flip-flop 16 is a clock signal input terminal, and the output signals of the first D flip-flop 12 and the second D flip-flop 16 are flipped at the edge of the second input terminal; the third input terminal of the first D flip-flop 12 and the second D flip-flop 16 is a set terminal; the first output terminal of the first D flip-flop 12 and the second D flip-flop 16 is a positive output terminal, and the second output terminal of the first D flip-flop 12 and the second D flip-flop 16 is a negative output terminal.

[0072] The delay time of the first delay module 13 and the second delay module 17 is the holding time, which can be set by referring to the formula t=1 / 2πRC, where t is the delay time, R is the output resistance of the digital-to-analog converter, and C is the parasitic capacitance of the digital-to-analog converter. In addition, the delay time can be adjusted according to different application requirements through registers to meet different application scenarios.

[0073] Taking the first MOS tube M1 and the second MOS tube M2 as PMOS tubes as an example, when the enable signal EN is at a high level, the first MOS tube M1 and the second MOS tube M2 are disconnected; when the enable signal EN is at a low level, the first MOS tube M1 and the second MOS tube M2 are turned on.

[0074] When receiving a digital input signal, taking the case where the digital input signal DIN is received at a low level as an example, the enable signal EN is at a high level, and the first MOS tube M1 is disconnected and does not work. The fifth inverter 11 outputs a high level, and the second input end of the first D flip-flop 12 generates a rising edge, wherein the first input end of the first D flip-flop 12 is a signal input end, which is at a low level, then the first output end of the first D flip-flop 12 outputs a low level, and the second output end of the first D flip-flop 12 outputs a high level. Among them, the high level output by the second output end of the first D flip-flop 12 is output through the sixth buffer 15, thereby generating a rising edge and inputting it into the second OR gate 4513. In addition, the low level of the first output end of the first D flip-flop 12 enters the third input end of the first D flip-flop 12 through the first delay module 13 and the fifth buffer 14, and after a certain delay time, the set end is set to zero. At the same time, since the second input end of the second D flip-flop 16 is at a low level and no rising edge is generated, the second D flip-flop 16 does not output.

[0075] In this embodiment, the first D flip-flop 12 and the second D flip-flop 16 respectively flip the edge of the signal received at the second input terminal, and their inverting output terminals, i.e., the second output terminals, respectively output rising edge signals and falling edge signals through the sixth buffer 15 and the eighth buffer 19, and output them through the second OR gate 4513 and the fourth buffer 4514, which are the output signals of the trigger circuit 451.

[0076] In the conversion control unit 40, the enable signal EN passes through the third inverter 411 and the fourth inverter 412, and is connected from the output end of the fourth inverter 412 to the enable end of the trigger module 45 (i.e., the control end of the first MOS transistor M1 and the second MOS transistor M2 in each trigger circuit 451), and the digital input signal DIN<7:0> is connected to the input end of the trigger module 45, and the output end of the trigger module 45 is connected to the input end of the eight-input first OR gate 46. The eight-input first OR gate 46 performs logic judgment on the eight received signals, and then outputs the corresponding signal to the second buffer 47, and further performs signal inversion through the second inverter 48 to output the clock control signal CK to control the switch control module 30. This clock control signal CK is low level at the beginning of analog-to-digital conversion, that is, the switch control module 30 is in the disconnected state, and the output end of the digital-to-analog converter continues to maintain the voltage value of the previous state before the conversion occurs. After a period of holding time is completed, the clock control signal CK becomes high level, the switch control module 30 is closed, and the sampling capacitor C starts to sample the converted voltage, thereby updating the output voltage value of the digital-to-analog conversion.

[0077] Furthermore, the present application adds a first buffer 20, a switch control unit 30 and a sampling capacitor C, and controls the switch control unit 30 based on the clock control signal CK, so that when the digital-to-analog conversion starts, the switch control unit 30 is in an open state, and the output end of the digital-to-analog conversion still maintains the voltage value of the previous state; after the holding time ends, the switch control unit 30 is controlled to be closed, and the sampling capacitor C starts to sample the voltage after the digital-to-analog conversion. In the sampling stage of the sampling capacitor C, the switch control unit 30 is always in a closed state until the digital input signal changes, that is, the next conversion starts, and the switch control unit 30 is controlled to be open.

[0078] As a specific embodiment of the present application, the waveform output by the trigger module 45 is as follows: Figure 6 As shown, the signal obtained after passing through the first OR gate 46 and the second buffer 47 is as follows Figure 7 As shown, after being inverted by the second inverter 48, the clock control signal CK is as follows: Figure 8 As shown, when the clock control signal CK is at a low level, the switch control unit 30 is controlled to be disconnected; when the clock control signal CK is at a high level, the switch control unit 30 is controlled to be closed.

[0079] like Figure 8 As shown, CK is a clock control signal, and VOUT1 is an output signal of an R-2R digital-to-analog conversion circuit in the related art (such as Figure 2 As shown in FIG. 1 , VOUT2 is the output signal of the digital-to-analog conversion chip of an embodiment of the present invention. After simulation output, the output signal of the R-2R digital-to-analog conversion circuit in the related art is as follows: Fig. 9As shown, the short-term glitch pulse of its output is obvious, and the output signal of the digital-to-analog conversion chip of the present application is as follows Fig.10 As shown, the short-term glitch pulse output by the present application is significantly improved. Therefore, based on the simulation results, the present application improves the short-term glitch pulse phenomenon of the output of the digital-to-analog converter by setting the holding time.

[0080] In summary, according to the digital-to-analog converter chip of the embodiment of the present invention, the input end of the first buffer is connected to the output end of the resistance conversion network, the first end of the switch control unit is connected to the output end of the first buffer, the second end of the switch control unit serves as the analog signal output end, one end of the sampling capacitor is connected to the second end of the switch control unit, and the other end of the sampling capacitor is grounded, and the conversion control unit generates a switch input logic control signal and a clock control signal according to the digital input signal and the enable signal, respectively, wherein the switch input logic control signal is used to control the resistance conversion network to perform digital-to-analog conversion, and the clock control signal is used to control the switch control unit to disconnect when the resistance conversion network starts digital-to-analog conversion, so that the analog signal output end maintains the voltage value of the previous state, and controls the switch control unit to close at the end of the holding time, so that the sampling capacitor samples the voltage converted by the resistance conversion network. Therefore, the chip generates a switch input logic control signal and a clock control signal based on the digital input signal and the enable signal, which can easily meet the requirement of synchronization between the clock control signal and the switch input logic control signal. At the same time, the switch control module is controlled to be disconnected when the digital-to-analog conversion starts, and the switch control module is controlled to be closed after the holding time ends. By setting the holding time, it can be ensured to a certain extent that the switch control module is closed after the main carry conversion of the digital-to-analog converter is completed, thereby improving the short-term glitch pulse phenomenon of the output of the digital-to-analog converter without increasing the stabilization time of the digital-to-analog converter.

[0081] Corresponding to the above embodiment, the present invention further proposes a DAC converter.

[0082] like Fig.11 As shown, the DAC converter 100 according to the embodiment of the present invention includes a digital-to-analog converter chip 110 .

[0083] According to the DAC converter of the embodiment of the present invention, based on the above-mentioned digital-to-analog converter chip, a switch input logic control signal and a clock control signal are generated based on a digital input signal and an enable signal. While meeting the synchronization requirements of the clock control signal and the switch input logic control signal, by setting the holding time, it can ensure to a certain extent that the switch control module is closed after the main carry conversion of the digital-to-analog converter is completed, thereby improving the short-term glitch pulse phenomenon of the output of the digital-to-analog converter without increasing the stabilization time of the digital-to-analog converter, thereby ensuring the working performance of the DAC converter.

[0084] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0085] In addition, the terms "first", "second", etc. used in the embodiments of the present invention are only used for descriptive purposes and should not be understood as indicating or implying relative importance, or implicitly indicating the number of technical features indicated in the present embodiment. Therefore, the features defined by the terms "first", "second", etc. in the embodiments of the present invention can explicitly or implicitly indicate that the embodiment includes at least one of the features. In the description of the present invention, the word "multiple" means at least two or two or more, such as two, three, four, etc., unless otherwise clearly and specifically defined in the embodiments.

[0086] In the present invention, unless otherwise clearly specified or limited in the embodiments, the terms "installed", "connected", "connected" and "fixed" etc. in the embodiments should be understood in a broad sense. For example, the connection can be a fixed connection, a detachable connection, or an integrated connection. It can be understood that it can also be a mechanical connection, an electrical connection, etc.; of course, it can also be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two elements, or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to the specific implementation situation.

[0087] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A digital-to-analog converter chip, characterized in that: include: Resistor conversion network; A first buffer, wherein an input terminal of the first buffer is connected to an output terminal of the resistance conversion network; A switch control unit, wherein a first end of the switch control unit is connected to an output end of the first buffer, and a second end of the switch control unit is used as an analog signal output end; A sampling capacitor, one end of which is connected to the second end of the switch control unit, and the other end of which is grounded; A conversion control unit is configured to generate a switch input logic control signal and a clock control signal according to a digital input signal and an enable signal, respectively, wherein the switch input logic control signal is used to control the resistance conversion network to perform digital-to-analog conversion, and the clock control signal is used to control the switch control unit to be disconnected when the resistance conversion network starts digital-to-analog conversion, so that the analog signal output terminal maintains a voltage value of a previous state, and controls the switch control unit to be closed at the end of the holding time, so that the sampling capacitor samples the voltage converted by the resistance conversion network.

2. The digital-to-analog converter chip according to claim 1, characterized in that: The holding time is less than the sampling time.

3. The digital-to-analog converter chip according to claim 1, characterized in that: The conversion control unit comprises: An inverting module, an input end of which is connected to the enable signal; A first NAND gate, wherein a first input terminal of the first NAND gate is connected to the digital input signal, and a second input terminal of the first NAND gate is connected to an output terminal of the inverting module; a second buffer, wherein an input terminal of the second buffer is connected to an output terminal of the first NAND gate; A first inverter, wherein an input terminal of the first inverter is connected to an output terminal of the second buffer, and an output terminal of the first inverter is suitable for outputting the switch input logic control signal to the resistance conversion network; A trigger module, wherein a first input terminal of the trigger module is connected to the output terminal of the inverting module, and a second input terminal of the trigger module is connected to the digital input signal; A first OR gate, wherein an input end of the first OR gate is connected to an output end of the trigger module; a third buffer, wherein an input end of the third buffer is connected to an output end of the first OR gate, and an output end of the third buffer is suitable for outputting a sampling signal; A second inverter, wherein an input terminal of the second inverter is connected to an output terminal of the third buffer, and an output terminal of the second inverter is suitable for outputting the clock control signal.

4. The digital-to-analog converter chip according to claim 3, characterized in that: The inverting module comprises: A third inverter, wherein an input end of the third inverter serves as an input end of the inverting module; A fourth inverter, wherein the input end of the fourth inverter is connected to the output end of the third inverter, and the output end of the fourth inverter serves as the output end of the inverting module.

5. The digital-to-analog converter chip according to claim 3, characterized in that: The trigger module includes a plurality of trigger circuits, and the number of the trigger circuits is the same as the number of conversion bits of the resistance conversion network.

6. The digital-to-analog converter chip according to claim 5, characterized in that: The number of input terminals of the first OR gate is the same as the number of the trigger circuits.

7. The digital-to-analog converter chip according to claim 5, characterized in that: Each of the trigger circuits comprises: A first trigger sub-circuit, configured to generate a rising edge signal according to the digital input signal and the enable signal; A second trigger sub-circuit, configured to generate a falling edge signal according to the digital input signal and the enable signal; a second OR gate, wherein a first input terminal of the second OR gate is connected to an output terminal of the first trigger sub-circuit, and a second input terminal of the second OR gate is connected to an output terminal of the second trigger sub-circuit; A fourth buffer, wherein the input end of the fourth buffer is connected to the output end of the second OR gate, and the output end of the fourth buffer serves as the output end of the trigger circuit.

8. The digital-to-analog converter chip according to claim 7, characterized in that: The first trigger sub-circuit comprises: a fifth inverter, wherein an input terminal of the fifth inverter is connected to the digital input signal; A first D flip-flop, wherein a first input terminal of the first D flip-flop is grounded, a second input terminal of the first D flip-flop is connected to an output terminal of the fifth inverter, and a third input terminal of the first D flip-flop is a set terminal; a first MOS transistor, wherein a gate of the first MOS transistor is connected to the enable signal, a source of the first MOS transistor is connected to a reference power supply, and a drain of the first MOS transistor is connected to a first output terminal of the first D flip-flop; A first delay module, one end of the first delay module is connected to the first output end of the first D trigger; a fifth buffer, wherein an input end of the fifth buffer is connected to the other end of the first delay module, and an output end of the fifth buffer is connected to the third input end of the first D flip-flop; A sixth buffer, wherein the input end of the sixth buffer is connected to the second output end of the first D flip-flop, and the output end of the sixth buffer is suitable for outputting the rising edge signal.

9. The digital-to-analog converter chip according to claim 7, characterized in that: The second trigger sub-circuit comprises: A second D flip-flop, wherein a first input terminal of the second D flip-flop is grounded, a second input terminal of the second D flip-flop is connected to the digital input signal, and a third input terminal of the second D flip-flop is a set terminal; a second MOS transistor, wherein a gate of the second MOS transistor is connected to the enable signal, a source of the second MOS transistor is connected to a reference power supply, and a drain of the second MOS transistor is connected to a first output terminal of the second D flip-flop; A second delay module, one end of the second delay module is connected to the first output end of the second D flip-flop; a seventh buffer, wherein an input end of the seventh buffer is connected to the other end of the second delay module, and an output end of the seventh buffer is connected to the third input end of the second D flip-flop; An eighth buffer, wherein the input end of the eighth buffer is connected to the second output end of the second D flip-flop, and the output end of the eighth buffer is suitable for outputting the falling edge signal.

10. The digital-to-analog converter chip according to any one of claims 1 to 9, characterized in that: The resistance conversion network is an R-2R type resistance network.

11. The digital-to-analog converter chip according to claim 10, characterized in that: The conversion bit number of the R-2R type resistor network is 8 bits.

12. The digital-to-analog converter chip according to claim 10, characterized in that: The R-2R type resistor network adopts Poly resistor.

13. The digital-to-analog converter chip according to any one of claims 1 to 9, characterized in that: The first buffer comprises an operational amplifier, a non-inverting input terminal of the operational amplifier is connected to the output terminal of the resistance conversion network, and an inverting input terminal of the operational amplifier is connected to the output terminal of the operational amplifier.

14. The digital-to-analog converter chip according to any one of claims 1 to 9, characterized in that: The sampling capacitor adopts a MOM capacitor, and the capacitance is smaller than a preset threshold.

15. A DAC converter, characterized in that: Comprising a digital-to-analog converter chip according to any one of claims 1-14.

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