3D nor flash memory structure

Abstract

The application relates to a 3D NOR flash memory structure, comprising a substrate, a step structure, a lead structure and a signal line structure. The step structure is arranged on the substrate and comprises a plurality of semiconductor doped layers which are stacked and spaced apart, and the step structure has a non-step area and a step area arranged along a first direction, the step area exposes part of the upper surface of each semiconductor doped layer to form a step plane. The lead structure comprises a plurality of contact hole structures arranged on each layer step plane respectively, and a transition line layer comprising a plurality of first transition lines, and the contact hole structure on each layer step plane is connected with the same first transition line. The signal line structure comprises an interconnection hole structure comprising a plurality of first interconnection structures arranged on each first transition line respectively, and the first interconnection structures on each first transition line are arranged staggeredly in a second direction; and a signal line layer comprising a plurality of first signal lines, and the plurality of first signal lines are connected with different first interconnection structures respectively. The embodiment of the application is convenient for leading out signal lines.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a 3D NOR flash memory structure. Background Art

[0002] NOR flash memory, with its advantages of high speed, high reliability, and long lifespan, plays an irreplaceable role in fields such as artificial intelligence, automotive electronics, and industry. With the development of semiconductor technology, three-dimensional (3D) NOR flash memory devices have emerged, which can effectively increase memory integration density and storage capacity.

[0003] However, the increase in the number of stacked layers in the device will cause difficulties in routing signal lines (bit lines and select lines). Summary of the Invention

[0004] Based on this, an embodiment of the present application provides a 3D NOR flash memory structure to facilitate the extraction of signal lines.

[0005] A 3D NOR flash memory structure, comprising:

[0006] substrate;

[0007] a step structure located on the substrate, comprising a plurality of stacked and spaced semiconductor doping layers, wherein adjacent semiconductor doping layers respectively constitute a source region and a drain region of a memory cell, and wherein the step structure comprises a non-step region and a step region arranged along a first direction, wherein the step region has multiple steps, and wherein the step region exposes a portion of an upper surface of each of the semiconductor doping layers to constitute a step plane of the step;

[0008] Lead structure, including:

[0009] A plurality of contact hole structures are respectively arranged on the step planes of each layer, and at least one contact hole structure is provided on each step plane;

[0010] A transfer line layer, comprising a plurality of first transfer lines, wherein the contact hole structure on each step plane is connected to the same first transfer line;

[0011] Signal line structure, including:

[0012] an interconnection hole structure, comprising a plurality of first interconnection structures respectively provided on each of the first adapter wires, wherein the first interconnection structures on each of the first adapter wires are staggered in a second direction, and the second direction intersects the first direction;

[0013] The signal line layer includes a plurality of first signal lines arranged along the second direction, the plurality of first signal lines are respectively connected to different first interconnect structures, and each of the first signal lines extends along the first direction.

[0014] In one embodiment, the first transfer lines connected to the contact hole structures on each step plane extend along the second direction.

[0015] In one embodiment, a plurality of contact hole structures arranged along the second direction are provided on each layer of the step plane.

[0016] In one embodiment, on the same side of the non-step area, the first interconnect structures corresponding to the steps from bottom to top are sequentially arranged along a third direction, and the third direction is located between the second direction and the first direction;

[0017] One end of the first signal line close to the non-step region is connected to the first interconnection structure.

[0018] In one embodiment,

[0019] A contact hole structure is provided on each layer of the step plane, and the contact hole structures located on each layer of the step plane are arranged in sequence along the first direction.

[0020] In one embodiment,

[0021] The first patch cords corresponding to the steps of the odd-numbered layers extend along a fourth direction, and the fourth direction is located between the positive direction of the second direction and the positive direction of the first direction;

[0022] The first connecting lines corresponding to the steps of the even-numbered layers extend along a fifth direction, and the fifth direction is located between the negative direction of the second direction and the positive direction of the first direction;

[0023] Furthermore, one end of each first transfer line close to the non-step area is connected to the contact hole structure.

[0024] In one embodiment, in the first direction, the step regions are provided on both sides of the non-step region, and the signal line structures are centrally symmetrically arranged on both sides of the non-step region.

[0025] In one embodiment, the non-step region has a word line extending from the step structure to the substrate.

[0026] In one embodiment, the non-step region is provided with a plurality of word lines.

[0027] The transfer line layer further includes a plurality of second transfer lines, each of which is connected to a different word line, and each of the second transfer lines extends along the first direction;

[0028] The signal line layer further includes a plurality of second signal lines, the second signal lines extend along the second direction, and the plurality of second signal lines are arranged along the first direction;

[0029] The interconnection hole structure further includes a plurality of second interconnection structures arranged between the second adapter line and the second signal line, and the second interconnection structures on the second adapter line are staggered in the first direction, and the second adapter line and the second signal line are connected one-to-one through the second interconnection structures.

[0030] In one embodiment,

[0031] The base is provided with a plurality of step structures spaced apart along the second direction, and an isolation structure is provided between adjacent step structures.

[0032] The same second signal line connects a plurality of the word lines located in different stepped structures.

[0033] In one embodiment, the step structure further includes a plurality of isolation layers, and the semiconductor doping layers and the isolation layers are alternately stacked on the substrate.

[0034] The 3D NOR flash memory structure further includes:

[0035] A storage structure, extending from the step structure to the substrate and surrounding the word line;

[0036] The channel layer is located between adjacent semiconductor doping layers, surrounds the storage structure, and is surrounded by the isolation layer.

[0037] In one embodiment, the material of the channel layer is the same as the material of the semiconductor doping layer.

[0038] In one embodiment, the 3D NOR flash memory structure further includes a metal silicide, the metal silicide is located on the step plane, and the contact hole structure contacts the metal silicide.

[0039] In one embodiment, the memory structure includes a tunneling layer, a charge trapping layer, a blocking layer, and a high dielectric constant layer sequentially arranged from the channel layer to the word line.

[0040] In one embodiment, a dummy word line is further provided in the step region.

[0041] The 3D NOR flash memory structure described above connects the contact hole structures on each step plane via a first jumper wire, and connects the first jumper wire to the first signal line via a first interconnect structure. Furthermore, the first interconnect structures corresponding to the steps are staggered in the second direction, and the first signal lines are arranged along the direction (the first direction) in which the non-step regions and step regions are aligned. This allows multiple first signal lines to be arranged along the second direction, effectively leading out bit line signal lines and select line signal lines.

[0042] At the same time, because the first signal line extends along the direction (first direction) in which the non-step region and the step region are arranged, the first signal line with a lower number of corresponding semiconductor doping layers has a shorter effective signal transmission path, thereby effectively compensating for the resistance difference caused by the length difference of the contact hole structure on each semiconductor doping layer. This can make the timing of the bit line signal (or select line signal) transmitted on each memory cell more consistent. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 A schematic diagram of a partial three-dimensional structure of a 3D NOR flash memory structure provided in one embodiment;

[0045] Figure 2 is a schematic diagram of a partial cross-sectional structure of a 3D NOR flash memory structure along a first direction provided in one embodiment;

[0046] Figure 3 is a schematic diagram of a partial cross-sectional structure of a 3D NOR flash memory structure along a second direction provided in one embodiment;

[0047] Figure 4 A schematic diagram of a partial top view of a 3D NOR flash memory structure provided in one embodiment;

[0048] Figure 5 A schematic diagram of a partial top view of a 3D NOR flash memory structure provided in another embodiment;

[0049] Figure 6 for Figure 2 Schematic diagram of the structure expansion of the dotted box part;

[0050] Figure 7 for Figure 4 A schematic diagram of a top view of a part of the structure;

[0051] Figure 8 FIG. 1 is a schematic diagram of a partial top view of a 3D NOR flash memory structure provided in yet another embodiment.

[0052] Description of reference numerals:

[0053] 100-substrate, 200-step structure, 210-semiconductor doping layer, 220-isolation layer, 300-lead structure, 310-contact hole structure, 311-word line connection structure, 320-switch line layer, 321-first switch line, 322-second switch line, 400-signal line structure, 410-interconnection hole structure, 411-first interconnection structure, 412-second interconnection structure, 420-signal line layer, 421-first signal line Line, 4211-bit line signal line, 4212-select line signal line, 422-second signal line, 500-first passivation layer, 510-filling dielectric layer, 520-passivation dielectric layer, 530-isolation structure, 610-word line, 620-dummy word line, 700-storage structure, 710-tunneling layer, 720-charge trapping layer, 730-blocking layer, 740-high dielectric constant layer, 800-channel layer, 900-metal silicide. DETAILED DESCRIPTION

[0054] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0056] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0057] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0058] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0059] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present application.

[0060] In one embodiment, see Figures 1 to 4 , provides a 3D NOR flash memory structure, including a substrate 100, a step structure 200, a lead structure 300 and a signal line structure 400.

[0061] The base 100 may include a substrate. The substrate may be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. For example, the substrate may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate may also include a Si / SiGe, Si / SiC, a silicon-on-insulator (SOI) substrate, or a silicon germanium-on-insulator substrate.

[0062] The stepped structure 200 includes a plurality of stacked and spaced apart semiconductor doping layers 210. The semiconductor doping layers 210 may be conductive, and the material may include but is not limited to doped silicon or silicon germanium.

[0063] As an example, see Figures 1 to 3 The step structure 200 may further include a plurality of isolation layers 220. The material of the isolation layer may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON). The semiconductor doped layers 210 and the isolation layers 220 may be alternately stacked on the substrate 100. In this case, in addition to the isolation layers 220, channel layers may be provided on the sidewalls of the isolation layers 220 between adjacent semiconductor doped layers 210.

[0064] As another example, the stepped structure 200 may also include a plurality of semiconductor doping layers 210 and a plurality of semiconductor active layers (not shown). The semiconductor doping layers 210 and the semiconductor active layers may be alternately stacked on the substrate 100.

[0065] At the same time, the stepped structure 200 has a non-step region and a step region arranged along a first direction. The non-step region can be used to form a memory cell. The adjacent semiconductor doped layers 210 can respectively constitute the source and drain of the memory cell. The step region has multiple steps. The step region exposes a portion of the upper surface of each semiconductor doped layer 210 to form a step plane.

[0066] See also Figures 1 to 4 The lead structure 300 includes a plurality of contact hole structures 310 and a transfer line layer 320 .

[0067] The material of the contact hole structure 310 may include, but is not limited to, tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), or aluminum (Al).

[0068] As an example, the 3D NOR flash memory structure may further include a first passivation layer 500. The first passivation layer 500 covers the stepped structure 200. The contact hole structure 310 may be disposed in a contact hole penetrating the first passivation layer 500.

[0069] A plurality of contact hole structures 310 can be arranged on each step plane to electrically connect the source and drain of each layer of memory cells. The number of contact hole structures 310 on each step plane can be one or more.

[0070] The material of the transfer line layer 320 may include, but is not limited to, metal materials such as Co, Ni, Ti, W, Cu, and Al.

[0071] The transfer line layer 320 includes a plurality of first transfer lines 321. The first transfer lines 321 can cover the contact hole structure 310. The contact hole structure 310 on each step plane is connected to the same first transfer line 321, so that each step can be provided with a corresponding first transfer line 321.

[0072] The signal line structure 400 includes a plurality of interconnection hole structures 410 and a signal line layer 420 .

[0073] The material of the interconnection hole structure 410 may include, but is not limited to, tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), or aluminum (Al).

[0074] As an example, the 3D NOR flash memory structure may further include a second passivation layer (not shown). The second passivation layer may cover the first passivation layer 500 and the transfer line layer 320. The interconnection hole structure 410 may be disposed in an interconnection hole penetrating the second passivation layer.

[0075] The interconnect hole structure 410 includes a plurality of first interconnect structures 411. The plurality of first interconnect structures 411 are disposed on each first patch line 321. Each first patch line 321 may have a corresponding first interconnect structure 411, such that each step may have a corresponding first interconnect structure 411. The first interconnect structures 411 on each first patch line 321 are staggered in the second direction, such that the first interconnect structures 411 corresponding to each step are staggered in the second direction. The second direction intersects the first direction. For example, the second direction may be perpendicular to the first direction.

[0076] The signal line layer 420 includes a plurality of first signal lines 421. The material of the first signal lines 421 may include, but is not limited to, metal materials such as Co, Ni, Ti, W, Cu, and Al.

[0077] Each first signal line 421 extends along the first direction. In addition, the plurality of first signal lines 421 are arranged along the second direction, and may include bit line signal lines 4211 and selection line signal lines 4212 alternately arranged along the second direction.

[0078] The plurality of first signal lines 421 are respectively connected to different first interconnect structures 411 staggered in the second direction, so that the plurality of first signal lines 421 can be arranged along the second direction, thereby effectively leading out the bit line signal lines 4211 and the selection line signal lines 4212 .

[0079] In this embodiment, the contact hole structures 310 on each layer of the stepped plane are connected via the first jumper lines 321, and the first jumper lines 321 are connected to the first signal lines 421 via the first interconnect structures 411. Furthermore, the first interconnect structures 411 corresponding to the steps are staggered in the second direction, and the first signal lines 421 are extended along the direction (the first direction) in which the non-step regions and the step regions are arranged. This allows the plurality of first signal lines 421 to be arranged along the second direction, effectively leading out the bit line signal lines 4211 and the select line signal lines 4212.

[0080] At the same time, since the first signal line 421 extends along the direction (first direction) in which the non-step region and the step region are arranged, the first signal line 421 has a shorter effective signal transmission path for the corresponding semiconductor doping layer 210 with a lower number of layers, thereby effectively compensating for the resistance difference caused by the length difference of the contact hole structure on each semiconductor doping layer 210. This can make the timing of the bit line signal (or select line signal) transmitted on each memory cell more consistent.

[0081] In one embodiment, see Figure 4 The first transfer lines 321 connected to the contact hole structures 310 located on each step plane all extend along the second direction.

[0082] In this case, as an example, a plurality of contact hole structures 310 arranged along the second direction may be provided on each step plane. The plurality of contact hole structures 310 may be evenly arranged along the second direction at different positions of the first patch line 321 in the second direction, thereby ensuring uniform signal at each position of the first patch line 321 in the second direction.

[0083] As another example, while all first transition lines 321 extend along the second direction, each step plane may have only one contact hole structure 310. In this case, for example, the contact hole structure 310 may be connected to the center of the first transition line 321. There is no limit on the number of contact hole structures 310 on each step plane.

[0084] In this embodiment, the first interconnection structures 411 can be flexibly arranged at any position of the first transition lines 321 in the second direction, so as to facilitate staggered arrangement of the first interconnection structures 411 on each layer of the first transition lines 321 in the second direction.

[0085] In one embodiment, see Figure 4 While the first jumper wires 321 connected to the contact hole structures 310 on each stepped plane extend along the second direction, the first interconnect structures 411 corresponding to each step from bottom to top are sequentially arranged along the third direction on the same side of the non-stepped area. In this case, the orthographic projections of the first interconnect structures 411 on the substrate are connected by a straight line.

[0086] The third direction is located between the second direction and the first direction. As an example, the angle between the first direction and the second direction may be 90°, and the angle between the third direction and the first direction may be 45°.

[0087] At the same time, one end of the first signal line 421 close to the non-step region may be arranged to contact the first interconnection structure 411 .

[0088] At this time, the lengths of the first signal lines 421 arranged along the second direction corresponding to the steps of the step structure 200 change sequentially, thereby facilitating design and preparation.

[0089] In other embodiments, the first interconnect structures 411 corresponding to the steps from bottom to top are not arranged sequentially along the third direction. For example, the orthographic projections of the first interconnect structures 411 on the substrate may be connected as curves or irregular lines.

[0090] Furthermore, in other embodiments, different first signal lines 421 may be provided to connect to the first interconnect structure 411 at different locations. The lengths of the first signal lines 421 may also be set to be equal, which is not limited here.

[0091] In one embodiment, see Figure 5 A contact hole structure 310 is provided on each step plane, and the contact hole structures 310 located on each step plane are sequentially arranged along the first direction.

[0092] At this time, the contact hole structure 310 can simply and symmetrically connect the source and drain (two adjacent semiconductor doping layers 210 ) of the memory cell.

[0093] As an example, the first patch lines 321 corresponding to odd-numbered steps extend along a fourth direction, which is between the positive direction of the second direction and the positive direction of the first direction. The first patch lines 321 corresponding to even-numbered steps extend along a fifth direction, which is between the negative direction of the second direction and the positive direction of the first direction.

[0094] As an example, see Figure 5 , the left-right direction in the figure can be set as the second direction, and the left direction can be set as the positive direction of the second direction, and the right direction can be set as the negative direction of the second direction. At the same time, the up-down direction in the figure can be set as the first direction, and the upward direction can be set as the positive direction of the first direction, and the downward direction can be set as the negative direction of the first direction.

[0095] At this time, the first transfer lines 321 corresponding to the odd-numbered steps and the first transfer lines 321 corresponding to the even-numbered steps extend in different directions, so that the first interconnection structures 411 corresponding to the odd-numbered steps and the first interconnection structures 411 corresponding to the even-numbered steps are staggered in the second direction.

[0096] At the same time, one end of each first transfer line 321 close to the non-step area is connected to the contact hole structure 310, thereby ensuring that the first transfer lines 321 corresponding to the odd-numbered steps do not intersect with the first transfer lines 321 corresponding to the even-numbered steps.

[0097] In one embodiment, see Figure 4 In the first direction, both sides of the non-step region are provided with step regions. Also, on both sides of the non-step region, the signal line structure 400 is centrally symmetrically arranged.

[0098] At this time, the first interconnect structures 411 corresponding to each step and located on both sides of the non-step region are symmetrically arranged about the center of the non-step region, and the first signal lines 421 corresponding to each step and located on both sides of the non-step region are symmetrically arranged about the center of the non-step region. Therefore, the same semiconductor doped layer 210 is simultaneously powered by the signal line structures 400 on both sides of the non-step region, and the power supply paths on both sides are symmetrically arranged, thereby achieving a more uniform voltage distribution on the semiconductor doped layer 210.

[0099] In one embodiment, the non-step region has a word line 610 extending from the step structure 200 to the substrate 100. The word line 610 can increase the gate voltage of the memory cell.

[0100] In one embodiment, see Figures 1 to 3 The stepped structure includes a plurality of semiconductor doping layers 210 and a plurality of isolation layers 220 . The semiconductor doping layers 210 and the isolation layers 220 are alternately stacked on the substrate 100 .

[0101] Meanwhile, the 3D NOR flash memory structure further includes a storage structure 700 of a memory cell and a channel layer 800 .

[0102] The memory structure 700 and the word line 610 are both formed by the stepped structure 200 and penetrate the substrate 100 , and the memory structure 700 surrounds the word line 610 . The channel layer 800 is located between adjacent semiconductor doping layers 210 and is surrounded by the isolation layer 220 .

[0103] At this point, as an example, during the preparation of a 3D NOR flash memory structure, an alternating stacking structure of semiconductor doped layers 210 and isolation layers 220 can be first formed. The stacking structure is then etched to form a step structure 200. The step area of ​​the step structure 200 can then be filled with a filling dielectric layer 510. Thereafter, the semiconductor doped layers 210 and the isolation layers 220 can be etched back to form wordline holes. The isolation layer 220 can then be etched back through the wordline holes to form side holes surrounding the wordline holes on the sidewalls of the wordline holes. Thereafter, the side holes can be filled with a channel layer 800. Thereafter, a storage structure 700 can be formed on the sidewalls of the wordline holes after the channel layer 800 is formed. After the storage structure 700 is formed, a word line 610 can be formed to fill the wordline holes.

[0104] Alternatively, as an example, during the fabrication of a 3D NOR flash memory structure, a stepped framework structure comprising alternating stacked semiconductor doped layers 210 and semiconductor sacrificial layers may be first formed. The stepped regions of the stepped framework structure may then be filled with a filling dielectric layer 510. The semiconductor doped layers 210 and the semiconductor sacrificial layers may then be etched back through the wordline holes to form side holes surrounding the wordline holes. The side holes may then be filled with a channel layer 800. A storage structure 700 may then be formed on the side walls of the wordline holes after the channel layer 800 is formed. After forming the storage structure 700, word lines 610 may be formed to fill the wordline holes. After forming the word lines 610, the semiconductor sacrificial layers may be removed, and an isolation layer 220 may be filled within the region of the semiconductor sacrificial layers, so that the isolation layer 220 and the semiconductor doped layers 210 form a stepped structure 200.

[0105] When forming the stepped architecture, for example, a single crystal silicon substrate or a silicon germanium substrate can be used as the base 100. A doped silicon layer is then formed on the base 100 through an epitaxial process to serve as the semiconductor doped layer 210. A silicon germanium layer is then formed on the doped silicon layer through an epitaxial process to serve as the semiconductor sacrificial layer. Subsequently, the steps of epitaxially growing the semiconductor doped layer 210 based on the semiconductor sacrificial layer and then epitaxially growing the semiconductor sacrificial layer based on the semiconductor doped layer 210 are repeated to form an alternating stack of semiconductor doped layers 210 and semiconductor sacrificial layers. The stacked structure is then etched to form the stepped architecture.

[0106] Subsequently, when forming the channel layer 800, a channel material layer can be formed by epitaxial growth based on the semiconductor doped layer 210 (doped silicon layer) and the semiconductor sacrificial layer (germanium silicon layer). The channel material layer outside the side holes is then removed to form the channel layer 800. At this point, the semiconductor doped layer 210 and the semiconductor sacrificial layer are formed by epitaxial growth based on a single crystal silicon substrate, and the channel layer 800 is epitaxially grown based on the semiconductor doped layer 210 and the semiconductor sacrificial layer, thereby facilitating the formation of a single crystal channel layer 800, thereby effectively improving the performance of the channel layer 800.

[0107] As an example, see Figure 6 The memory structure 700 may include a tunneling layer 710 , a charge trapping layer 720 , a blocking layer 730 and a high dielectric constant layer 740 , which are sequentially arranged from the channel layer 800 to the word line 610 .

[0108] The material of the tunneling layer 710 may include, but is not limited to, an oxide. The material of the charge trapping layer 720 may include, but is not limited to, a nitride. The material of the blocking layer 730 may include, but is not limited to, an oxide. The material of the high dielectric constant layer 740 may include, but is not limited to, aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3).

[0109] Of course, the structure of the storage structure 700 may be different from this. For example, the barrier layer 730 and the high dielectric constant layer 740 may be the same film layer. The specific structure of the storage structure 700 is not limited here.

[0110] As an example, the material of the channel layer 800 may be the same as that of the semiconductor doping layer 210 , so that the channel layer 800 is in good contact with the semiconductor doping layer 210 serving as a source or drain of a memory cell.

[0111] As an example, the 3D NOR flash memory structure may further include a metal silicide 900 located on the step plane. The contact hole structure 310 contacts the metal silicide 900. The metal silicide 900 can effectively reduce the resistance between the semiconductor doping layer 210 and the contact hole structure 310.

[0112] During the formation of metal silicide 900, sidewall spacers can be first formed on the step sidewalls. A metal material layer is then formed on the surface of the resulting structure after the sidewall spacers are formed. Subsequently, thermal annealing is performed to react the metal material layer with the semiconductor doping layer 210 located on the step plane, thereby forming metal silicide 900. Excess metal material layer is then removed.

[0113] In one embodiment, see Figure 7 as well as Figure 4 The non-step region is provided with a plurality of word lines 610. The transfer line layer 320 further includes a plurality of second transfer lines 322. The plurality of second transfer lines 322 are respectively connected to different word lines 610. Each second transfer line 322 is connected to a corresponding word line 610.

[0114] The signal line layer 420 further includes a plurality of second signal lines 422. The second signal lines 422 may be word line signal lines, which extend along the second direction. The plurality of second signal lines 422 are arranged along the first direction.

[0115] The interconnection hole structure 410 further includes a second interconnection structure 412 disposed between the second patch line 322 and the second signal line 422. The second patch line 322 and the second signal line 422 are connected in a one-to-one correspondence through the second interconnection structure 412.

[0116] At this time, as an example, during the fabrication process of the 3D NOR flash memory structure, after forming the memory structure 700 and the word line 610, a passivation dielectric layer 520 can be formed to cover the stepped structure 200, the filling dielectric layer 510, the memory structure 700, and the word line 610. The passivation dielectric layer 520 and the filling dielectric layer 510 can together constitute the first passivation layer 500 covering the stepped structure 200.

[0117] Afterwards, the first passivation layer 500 can be etched to form contact holes extending from the first passivation layer 500 to each step plane (or the metal silicide 900 on each step plane). Simultaneously, etching the first passivation layer 500 can also form word line connection holes extending from the first passivation layer 500 to the word lines 610.

[0118] Then, a first conductive material layer may be deposited to cover the contact holes and word line connection holes and the upper surface of the first passivation layer 500. Then, a chemical mechanical polishing (CMP) process is performed to remove the first conductive material layer on the upper surface of the first passivation layer 500, thereby forming a contact hole structure 310 located in the contact hole and a word line connection structure 311 located in the word line connection hole.

[0119] After forming the contact hole structure 310 and the word line connection structure 311, a transfer line material layer can be formed first, and then the transfer line material layer can be patterned to form a transfer line layer 320 including a first transfer line 321 and a second transfer line 322. At this time, the first transfer line 321 covers the contact hole structure 310, and the second transfer line 322 covers the word line connection structure 311, so that the second transfer line 322 is connected to the word line 610 through the word line connection structure 311. Of course, the transfer line layer 320 can also be formed using other processes such as damascene.

[0120] After forming the transfer line layer 320, a second passivation layer (not shown) can be formed to cover the transfer line layer 320 and the first passivation layer 500. The second passivation layer is then etched to form interconnect holes within the second passivation layer. The interconnect holes are then filled to form an interconnect hole structure 410. The interconnect hole structure 410 can include a first interconnect structure 411 and a second interconnect structure 412. The first interconnect structure 411 can extend to and connect to the first transfer line 321, and the second interconnect structure 412 can extend to and connect to the second transfer line 322.

[0121] Afterwards, a signal line material layer may be formed to cover the second passivation layer and the interconnection hole structure 410 . The signal line material layer is then patterned to form a signal line layer 420 including a first signal line 421 and a second signal line 422 .

[0122] In this embodiment, the second jumper wires 322 extend along the first direction, so that the second jumper wires 322 connected to different word lines 610 can connect to the second interconnect structure 412 at different positions. In this case, the second interconnect structures 412 corresponding to different word lines 610 have different positions in the first direction, and can thus connect to different second signal lines 422 arranged in the first direction. In this way, different word lines 610 correspond to different second signal lines 422, so that different memory cells can obtain different word line signals.

[0123] In one embodiment, see Figure 4A plurality of stepped structures 200 are arranged along the second direction at intervals on the substrate 100, and an isolation structure 530 is provided between adjacent stepped structures 200. In addition, the same second signal line 422 connects a plurality of word lines 610 located in different stepped structures 200.

[0124] The material of the isolation structure 530 may include, but is not limited to, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), or silicon oxynitride (SiON), etc. The material of the isolation structure 530 may be the same as or different from the material of the isolation layer 220 .

[0125] During the fabrication of the 3D NOR flash memory structure, a plurality of stepped structures 200 may be formed simultaneously on the substrate 100 .

[0126] As an example, in the process of preparing a 3D NOR flash memory structure, a semiconductor doping layer 210 and an isolation layer 220 (or a semiconductor sacrificial layer) can first be alternately stacked and deposited on a substrate 100 to form a step initial material layer. Then, the step initial material layer is etched to form a step initial structure having multiple steps and including multiple step structures 200 (or including multiple step frame structures). Then, the step area of ​​the platform step initial structure can be filled by filling the dielectric layer 510. Thereafter, the step initial structure and the filling dielectric layer 510 can be etched to form a plurality of isolation trenches extending along the first direction and arranged along the second direction. The isolation trenches can separate the multiple step structures 200. Thereafter, the isolation structure 530 can be filled in the isolation trenches. After the isolation structure 530 is formed, a word line hole and a side hole can be formed. A channel layer 800 is formed in the side hole, and a storage structure 700 and a word line 610 are formed in the word line hole. Then, a passivation dielectric layer 520 may be formed to cover the stepped structure 200, the filling dielectric layer 510, the isolation structure 530, the storage structure 700, and the word line 610. At this time, the passivation dielectric layer 520, the filling dielectric layer 510, and the isolation structure 530 may together constitute the first passivation layer 500 covering the stepped structure 200.

[0127] Of course, the formation method of the filling dielectric layer 510, the isolation structure 530 and the passivation dielectric layer 520 in the first passivation layer 500 is not limited to this. For example:

[0128] As another example, in the process of preparing a 3D NOR flash memory structure, semiconductor doping layers 210 and isolation layers 220 (or semiconductor sacrificial layers) can first be alternately stacked and deposited on the substrate 100 to form a step initial material layer. The step initial material layer is then etched to form a step initial structure having multiple steps and including multiple step structures 200 (or including multiple step frame structures). The step initial structure can then be etched to form multiple isolation trenches arranged along the second direction. The isolation trenches separate the multiple step structures 200. Thereafter, an insulating material layer can be deposited and chemical mechanical polishing (CMP) can be performed on the insulating material layer. The remaining insulating material layer simultaneously forms a filling dielectric layer 510 that fills the step area of ​​the step structure and an isolation structure 530 that fills the isolation trench. Thereafter, a word line hole and a side hole can be formed. A channel layer 800 is formed in the side hole, and a storage structure 700 and a word line 610 are formed in the word line hole. Thereafter, a passivation dielectric layer 520 covering the stepped structure 200 , the filling dielectric layer 510 , the isolation structure 530 , the memory structure 700 , and the word line 610 may be formed.

[0129] As another example, in the process of preparing a 3D NOR flash memory structure, semiconductor doping layers 210 and isolation layers 220 (or semiconductor sacrificial layers) can first be alternately stacked and deposited on the substrate 100 to form a step initial material layer. The step initial material layer is then etched to form an isolation trench. The isolation trench isolates the step initial material layer, thereby defining the area where the step structure is located. A filled isolation structure 530 can then be formed in the isolation trench. The step initial structure after the isolation trench is formed can then be etched to form a plurality of step structures 200 (or step frame structures). Thereafter, the step area of ​​the step structure 200 (or step frame structure) can be filled with a filling dielectric layer 510. Thereafter, a word line hole and a side hole can be formed. A channel layer 800 is formed in the side hole, and a storage structure 700 and a word line 610 are formed in the word line hole. Thereafter, a passivation dielectric layer 520 covering the stepped structure 200 , the filling dielectric layer 510 , the isolation structure 530 , the memory structure 700 , and the word line 610 may be formed.

[0130] In this embodiment, while the multiple step structures 200 isolated by the isolation structure 530 are arranged at intervals along the second direction, the same second signal line 422 extending along the second direction is provided to connect the multiple word lines 610 located in different step structures 200, so that the storage cells in different step structures 200 can share the word lines.

[0131] In one embodiment, see Figure 8 A dummy word line 620 is further provided in the step region. The dummy word line 620 can be formed simultaneously with the word line 610.

[0132] For example, a dummy word line hole can be formed in the step region while a word line hole is formed in the non-step region, and then a dummy word line 620 is filled in the dummy word line hole while a word line 610 is filled in the word line hole.

[0133] In one embodiment, a 3D NOR flash memory structure is provided, which includes a substrate 100, a step structure 200, a first passivation layer 500, a word line 610, a storage structure 700, a channel layer 800, a lead structure 300, a second passivation layer (not shown), and a signal line structure 400.

[0134] A plurality of stepped structures 200 are provided on the substrate 100, spaced apart along the second direction. Each stepped structure 200 includes a plurality of alternating stacked semiconductor doped layers 210 and isolation layers 220. Each stepped structure 200 has a non-stepped region and a stepped region arranged along the first direction. The stepped region has multiple steps, and the stepped region exposes a portion of the upper surface of each semiconductor doped layer 210 to form a stepped plane.

[0135] The first passivation layer 500 covers each stepped structure 200 and may include a filling dielectric layer 510 , a passivation dielectric layer 520 and an isolation structure 530 .

[0136] The filling dielectric layer 510 can fill the step area of ​​each step structure 200. The isolation structure 530 can be located between adjacent step structures 200.

[0137] Multiple word lines 610 may be provided on each stepped structure 200. The word lines 610 and the memory structure 700 may extend from the stepped structure 200 to the substrate 100. The memory structure 700 surrounds the word lines 610. The channel layer 800 is located between adjacent semiconductor doped layers 210 and is surrounded by the isolation layer 220. The memory structure 700 may include a tunneling layer 710, a charge trapping layer 720, a blocking layer 730, and a high dielectric constant layer 740, arranged in sequence from the channel layer 800 to the word lines 610.

[0138] The passivation dielectric layer 520 may cover the stepped structure 200 , the filling dielectric layer 510 , the isolation structure 530 , the memory structure 700 , and the word line 610 .

[0139] The lead structure 300 includes a plurality of contact hole structures 310 and a transfer line layer 320 .

[0140] A plurality of contact hole structures 310 may penetrate the first passivation layer 500 (penetrate the passivation dielectric layer 520 and the filling dielectric layer 510 ) and be arranged on each step plane, respectively. Each step plane is provided with at least one contact hole structure 310 .

[0141] The patch cord layer 320 includes a plurality of first patch cords 321 and a plurality of second patch cords 322 .

[0142] Each first transfer line 321 may extend along the second direction, and multiple first transfer lines 321 are arranged along the first direction. The contact hole structure 310 on each step plane is connected to the same first transfer line 321, and the contact hole structures 310 on different step planes are connected to different first transfer lines 321.

[0143] Each second transfer line 322 may extend along the first direction, and a plurality of second transfer lines 322 may be arranged along the second direction. Different word lines 610 on the same stepped structure 200 are connected to different second transfer lines 322 .

[0144] The signal line structure 400 includes an interconnection hole structure 410 and a signal line layer 420 .

[0145] The interconnection hole structure 410 includes a plurality of first interconnection structures 411 and a plurality of second interconnection structures 412 .

[0146] The plurality of first interconnecting structures 411 are respectively disposed on each first transition line 321. The first interconnecting structures 411 on the first transition line 321 are staggered in a second direction, and the second direction intersects the first direction.

[0147] The plurality of second interconnecting structures 412 are respectively disposed on each second transition line 322. The second interconnecting structures 412 on the second transition line 322 are staggered in the first direction.

[0148] The signal line layer 420 includes a plurality of first signal lines 421 extending along a first direction and a plurality of second signal lines 422 extending along a second direction.

[0149] The plurality of first signal lines 421 are arranged along the second direction and are respectively connected to different first interconnect structures 411. The plurality of first signal lines 421 may include bit line signal lines 4211 and select line signal lines 4212 alternately arranged along the second direction.

[0150] The plurality of second signal lines 422 are arranged along the first direction and are respectively connected to different second interconnect structures 412. The second signal lines 422 may be word line signal lines.

[0151] In this embodiment, the contact hole structures 310 on each layer of the stepped plane are connected via the first jumper lines 321, and the first jumper lines 321 are connected to the first signal lines 421 via the first interconnect structures 411. Furthermore, the first interconnect structures 411 corresponding to the steps are staggered in the second direction, and the first signal lines 421 are extended along the direction (the first direction) in which the non-step regions and the step regions are arranged. This allows the plurality of first signal lines 421 to be arranged along the second direction, effectively leading out the bit line signal lines 4211 and the select line signal lines 4212.

[0152] At the same time, each word line 610 is connected via a second transfer line 322, and the second transfer line 322 is connected to the second signal line 422 via a second interconnect structure 412. Furthermore, the second interconnect structures 412 corresponding to each word line 610 are staggered in the first direction, and the second signal line 422 is extended along the second direction. This allows multiple second signal lines 422 to be arranged along the first direction, effectively leading out word line signal lines.

[0153] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0154] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A 3D NOR flash memory structure, characterized in that: include: substrate; a step structure located on the substrate, comprising a plurality of stacked and spaced semiconductor doping layers, wherein adjacent semiconductor doping layers respectively constitute a source region and a drain region of a memory cell, and wherein the step structure comprises a non-step region and a step region arranged along a first direction, wherein the step region has multiple steps, and wherein the step region exposes a portion of an upper surface of each of the semiconductor doping layers to constitute a step plane of the step; Lead structure, including: A plurality of contact hole structures are respectively arranged on the step planes of each layer, and at least one contact hole structure is provided on each step plane; A transfer line layer, comprising a plurality of first transfer lines, wherein the contact hole structure on each step plane is connected to the same first transfer line; Signal line structure, including: an interconnection hole structure, comprising a plurality of first interconnection structures respectively provided on each of the first adapter wires, wherein the first interconnection structures on each of the first adapter wires are staggered in a second direction, and the second direction intersects the first direction; a signal line layer, comprising a plurality of first signal lines arranged along the second direction, the plurality of first signal lines respectively connected to different first interconnect structures, and each of the first signal lines extending along the first direction; The non-step area has a word line extending from the step structure to the substrate; The step structure further includes a plurality of isolation layers, and the semiconductor doping layers and the isolation layers are alternately stacked on the substrate; The 3D NOR flash memory structure further includes: A storage structure, extending from the step structure to the substrate and surrounding the word line; The channel layer is located between adjacent semiconductor doping layers, surrounds the storage structure, and is surrounded by the isolation layer.

2. The 3D NOR flash memory structure according to claim 1, wherein: The first transfer lines connected to the contact hole structures on each layer of the stepped plane all extend along the second direction.

3. The 3D NOR flash memory structure according to claim 2, wherein: A plurality of contact hole structures arranged along the second direction are provided on each step plane.

4. The 3D NOR flash memory structure according to claim 2, wherein: On the same side of the non-step area, first interconnect structures corresponding to the steps from bottom to top are sequentially arranged along a third direction, and the third direction is located between the second direction and the first direction; One end of the first signal line close to the non-step region is connected to the first interconnection structure.

5. The 3D NOR flash memory structure according to claim 1, wherein: A contact hole structure is provided on each layer of the step plane, and the contact hole structures located on each layer of the step plane are arranged in sequence along the first direction.

6. The 3D NOR flash memory structure according to claim 5, characterized in that: The first patch cords corresponding to the steps of the odd-numbered layers extend along a fourth direction, and the fourth direction is located between the positive direction of the second direction and the positive direction of the first direction; The first connecting lines corresponding to the steps of the even-numbered layers extend along a fifth direction, and the fifth direction is located between the negative direction of the second direction and the positive direction of the first direction; Furthermore, one end of each first transfer line close to the non-step area is connected to the contact hole structure.

7. The 3D NOR flash memory structure according to claim 1, wherein: In the first direction, the step regions are provided on both sides of the non-step region, and the signal line structures are centrally symmetrically arranged on both sides of the non-step region.

8. The 3D NOR flash memory structure according to claim 1, wherein: The non-step area is provided with a plurality of word lines. The transfer line layer further includes a plurality of second transfer lines, each of which is connected to a different word line, and each of the second transfer lines extends along the first direction; The signal line layer further includes a plurality of second signal lines, the second signal lines extend along the second direction, and the plurality of second signal lines are arranged along the first direction; The interconnection hole structure further includes a plurality of second interconnection structures arranged between the second adapter line and the second signal line, and the second interconnection structures on the second adapter line are staggered in the first direction, and the second adapter line and the second signal line are connected one-to-one through the second interconnection structures.

9. The 3D NOR flash memory structure according to claim 8, wherein: The base is provided with a plurality of step structures spaced apart along the second direction, and an isolation structure is provided between adjacent step structures. The same second signal line connects a plurality of the word lines located in different stepped structures.

10. The 3D NOR flash memory structure according to claim 1, wherein: The material of the channel layer is the same as that of the semiconductor doping layer.

11. The 3D NOR flash memory structure according to claim 1, wherein: The 3D NOR flash memory structure further includes a metal silicide, the metal silicide is located on the step plane, and the contact hole structure contacts the metal silicide.

12. The 3D NOR flash memory structure according to claim 1, wherein: The storage structure includes a tunneling layer, a charge trapping layer, a blocking layer and a high dielectric constant layer which are sequentially arranged from the channel layer to the word line.

13. The 3D NOR flash memory structure according to claim 1, wherein: A dummy word line is also provided in the step area.

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