Polycrystalline silicon carbide (SiC) substrate having high resistivity and method for manufacturing same

Abstract

The present disclosure relates to a polycrystalline silicon carbide (SiC) substrate having high resistivity and a method for manufacturing the same. A polycrystalline SiC wafer or substrate with high resistivity facilitates the functionality of a high power electronic device or system in which the polycrystalline SiC wafer or substrate is present, or the polycrystalline SiC wafer or substrate is used to fabricate the high power electronic device or system. At least one embodiment of the wafer includes a polycrystalline SiC wafer or substrate having a high resistivity (e.g., equal to or greater than 1 * 105 or 1E + 5 ohm-cm) and a low warpage. Electronic devices or components made using or from wafers including high resistivity polycrystalline SiC wafers or substrates are further optimized at the time of use and have fewer to none crystal defects. The wafers formed according to the embodiments of the present disclosure have high or very high resistivity compared to existing polycrystalline SiC wafers or substrates.

Description

Technical Field

[0001] The present disclosure relates to a high-resistivity polycrystalline substrate and a method for manufacturing the high-resistivity polycrystalline substrate. Background Art

[0002] The semiconductor industry has shown great interest in silicon carbide (SiC), particularly for the fabrication of devices or components (eg, radar, diodes, transistors, or other similar or like applications).

[0003] The development and manufacture of silicon carbide-based electronic devices is limited by factors such as the electrical and mechanical properties from the formed silicon carbide wafers. Many of the manufactured silicon carbide wafers have low resistivity, which is beneficial for the final product. Another issue is the amount of warpage from wafer manufacturing. Lower resistivity allows electrical signals to pass through the silicon carbide wafer more easily, but limits the ability of silicon carbide wafers to be used in high-power applications (e.g., radar) where high resistivity is desired instead. In addition, higher warpage leads to defects such as from the polishing process when manufacturing the final electronic device, or leads to an increase in the number of wafers or substrates that are cracked or broken during handling and manufacturing.

[0004] These polycrystalline SiC wafers can be manufactured by bonding a single crystal (i.e., single crystal) wafer to a polycrystalline SiC wafer. For example, there is a wafer manufacturing method in which a polycrystalline SiC wafer and a single crystal (i.e., single crystal) SiC wafer are bonded and integrated together by direct bonding. In power devices, these crystal defects, low resistivity, and high warpage can cause problems for high power applications because these factors limit the functionality of the power device, causing the power device to operate outside the selected tolerance. In these cases, these devices may be disposed of (e.g., thrown away), which increases manufacturing costs due to reduced production. Summary of the invention

[0005] A polycrystalline SiC wafer or substrate with high resistivity is beneficial to the functionality of a high-power electronic device or system, in which the polycrystalline SiC wafer or substrate is present, or in which the polycrystalline SiC wafer or substrate is used to manufacture the high-power electronic device or system. The present disclosure is directed to providing at least one embodiment of a wafer including a polycrystalline SiC wafer or substrate having a high resistivity (e.g., equal to or greater than 1*10^5 or 1E+5 ohm-cm) and low warpage. Electronic devices or components made using or from wafers including high-resistivity polycrystalline SiC wafers or substrates are further optimized when used and have fewer or even no crystal defects. Compared to existing polycrystalline SiC wafers or substrates, wafers formed according to embodiments of the present disclosure have high or very high resistivity.

[0006] At least one embodiment of the present disclosure is summarized as including: a polycrystalline silicon carbide (SiC) base substrate, which includes: a first surface, a second surface opposite to the first surface, a resistivity greater than or equal to 1*10^5 or 1E+5 ohm-cm, and a grain size equal to or greater than 0.5 millimeters (mm).

[0007] In some embodiments, a single crystal silicon carbide (SiC) substrate is coupled to a first surface of a polycrystalline silicon carbide (SiC) base substrate. The single crystal silicon carbide (SiC) may have a resistivity similar to or equal to that of the polycrystalline silicon carbide substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to better understand the embodiments, reference will now be made to the accompanying drawings by way of example. In the accompanying drawings, unless the context otherwise indicates, the same reference numerals represent the same or similar elements or behaviors. The sizes and relative proportions of the elements in the accompanying drawings are not necessarily drawn to scale. For example, some of these elements may be enlarged and placed to improve the readability of the accompanying drawings.

[0009] Figure 1 a perspective side view of an embodiment of a wafer according to the present disclosure;

[0010] Figure 2 A perspective view of an alternative embodiment of a wafer for the present disclosure;

[0011] Figure 3A A top view of another alternative embodiment of a wafer according to the present disclosure;

[0012] Figure 3B For the disclosure Figure 3A A perspective side view of another alternative embodiment of a wafer shown in;

[0013] Figure 3C According to another embodiment of the wafer disclosed herein, Figure 3A An enlarged enhanced view of section 3C-3C shown in FIG.

[0014] Figure 4A Yes Figure 1 and Figure 2 A flow chart of a method for manufacturing an embodiment of a wafer of the present disclosure shown in;

[0015] Figure 4B As disclosed herein Figure 3A-3C A flowchart of a method for manufacturing another embodiment of a wafer shown in;

[0016] Figure 4C As disclosed herein Figure 3A-3C A flow chart of an alternative method of manufacturing another embodiment of the wafer shown in; and

[0017] Figure 5A-5C is used to manufacture the Figure 1 and Figure 2 The embodiment of the wafer shown in FIG. Figure 4A 0014] Figure 2 is a side view of at least some steps of an embodiment of a manufacturing method shown in FIG. DETAILED DESCRIPTION

[0018] In the following description, certain details are set forth in order to provide a thorough understanding of various embodiments of devices, methods, and articles. However, those skilled in the art will appreciate that other embodiments may be practiced without these details. In other cases, well-known structures and methods associated with, for example, silicon carbide substrates or layers (e.g., polycrystalline silicon carbide, single crystal silicon carbide, etc.), semiconductor manufacturing processes, etc., are not shown or described in detail in some figures to avoid unnecessarily obscuring the description of the embodiments.

[0019] Unless the context requires otherwise, throughout the following specification and claims, the word "comprise" and variations such as "include" and "including" are to be interpreted in an open, inclusive sense, ie, "including, but not limited to."

[0020] Reference throughout the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout the specification are not necessarily referring to the same embodiment or all embodiments. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments to obtain further embodiments.

[0021] Headings are provided for convenience only and do not interpret the scope or meaning of the disclosure or the claims.

[0022] The sizes and relative positions of the elements in the drawings are not necessarily drawn to scale. For example, the shapes of various elements and angles may not be drawn to scale, and some of these elements may be enlarged and positioned to improve the readability of the drawings.

[0023] The use of "transverse" means that a surface, sidewall, or similar or similar structure or feature is at an angle relative to another corresponding surface, sidewall, or similar or similar corresponding structure or feature. For example, if a first surface is transverse to a first sidewall, then the first surface may be at an angle equal to 25 degrees, 35 degrees, 45 degrees, 75 degrees, 90 degrees, 120 degrees, etc.

[0024] Generally speaking, polycrystalline silicon carbide (SiC) substrates, wafers or layers have been used in a variety of electronic devices and components (e.g., semiconductor dies, semiconductor packages, semiconductor transistors, etc.). These polycrystalline SiC substrates, wafers or layers have a resistivity that causes resistance to exist along an electrical path through or along the polycrystalline SiC substrate, wafer or layer. This resistance hinders an electrical signal as it passes through or along the electrical path and is referred to as on-resistance (R on The on-resistance (R on ) is typically high when used in high power and high frequency applications (e.g., radar or other similar or similar type of RF applications or devices operating at relatively high gigahertz (GHz) frequencies compared to other situations). For example, when the on-resistance (R on ) Because the polycrystalline SiC substrate has a high resistivity (e.g., greater than or equal to 1*10^5 or 1E+5 ohm-cm), the polycrystalline SiC substrate with high and stable resistivity provides good electrical performance and reduced insertion loss, so that the use of the polycrystalline SiC substrate in high power and high frequency applications is optimized. In the industry, single crystal SiC substrates with high resistivity have been manufactured for such high frequency and high power applications, but manufacturing single crystal SiC substrates is significantly more expensive and more costly than manufacturing polycrystalline SiC substrates. In view of this, the present disclosure is directed to one or more embodiments of a polycrystalline SiC substrate with high resistivity optimized for use in high power and high frequency applications, and a method of manufacturing a polycrystalline SiC substrate with high resistivity.

[0025] A polycrystalline SiC substrate or wafer with high resistivity for a high-power and high-frequency electronic device, in which the polycrystalline SiC substrate or wafer is present. The present disclosure is directed to providing at least one embodiment of a wafer or substrate including a polycrystalline SiC substrate or wafer having high resistivity and low warpage. Electronic devices or components made of or including a polycrystalline SiC substrate or wafer having high resistivity and low warpage operate stably at high power and high frequency. Since these embodiments of the polycrystalline SiC substrate or wafer of the present disclosure have fewer crystal defects, the embodiments of the polycrystalline SiC substrate or wafer of the present disclosure are further optimized. Compared with existing polycrystalline SiC substrates or wafers that are typically manufactured to have a resistivity far less than 1*10^5 or 1E+5 ohm-cm, the polycrystalline SiC substrate or wafer has a high or very high resistivity. Furthermore, the low amount of warpage in embodiments of the polycrystalline SiC substrates or wafers of the present disclosure prevents or reduces the likelihood of defects such as from the polishing process when manufacturing the final electronic device, or reduces the number of polycrystalline SiC wafers or substrates that are cracked or broken during handling and manufacturing.

[0026] Figure 11 is a side view of an embodiment of a wafer 100 of the present disclosure. The wafer 100 includes a first side 102 and a second side 104 opposite the first side 102. The wafer 100 also includes a polycrystalline silicon carbide (SiC) layer 106, a bonding region 108, and a single crystal silicon carbide (SiC) layer 110 bonded to the polycrystalline silicon carbide layer 106 at the bonding region 108. The polycrystalline silicon carbide layer 106 may be referred to as a polycrystalline silicon carbide substrate, a polycrystalline silicon carbide wafer, a polycrystalline silicon carbide layer, or may be referred to in some other suitable manner. The single crystal silicon carbide (SiC) layer 110 may be referred to as a single crystal silicon carbide substrate, a single crystal silicon carbide wafer, a single crystal silicon carbide layer, or may be referred to in some other suitable manner. The polycrystalline silicon carbide (SiC) layer 106 may be referred to as the polycrystalline layer 106 hereinafter within the present disclosure, and the single crystalline silicon carbide (SiC) layer 110 may be referred to as the single crystalline layer 110 hereinafter within the present disclosure.

[0027] The polycrystalline layer 106 has a high resistivity, for example, a resistivity greater than or equal to 1*10^5 or 1E+5 ohm-cm. The high resistivity of the polycrystalline layer 106 allows high-power and high-frequency (for example, gigahertz (GHz) frequency) electrical signals (for example, electrons) to stably pass through the polycrystalline layer 106 at high power and high frequency, so that the electrical signals can stably pass through the polycrystalline layer 106 and can reach their destination, and their strength and precision are more accurate and stable than when the polycrystalline layer 106 is changed to have a low resistivity. In other words, when the on-resistance (R on ) is high (i.e., high resistivity), high power and high frequency electrical signals will more easily and stably pass through the polycrystalline layer 106 without creating inaccuracies as the high power and high frequency electrical signals pass through the polycrystalline layer 106 to their destination within a high power and high frequency electronic device (e.g., a radar, a semiconductor package, a semiconductor die, or some other similar or analogous high power and high frequency electronic device where the polycrystalline layer 106 may be present).

[0028] The polycrystalline layer 106 includes a first surface 112 and a second surface 114 opposite the first surface 112. The first surface 112 of the polycrystalline layer 106 is located at the second side 104 of the wafer 100. The single crystal layer 110 includes a third surface 116 and a fourth surface 118 opposite the third surface 116. The fourth surface 118 of the single crystal layer 110 is located at the first side 102 of the wafer 100.

[0029] The polycrystalline layer 106 has a first thickness T1, which may be referred to as a first dimension. The first thickness T1 extends from the first surface 112 of the polycrystalline layer 106 to the second surface 114 of the polycrystalline layer 106. In some embodiments, the first thickness T1 may be in the range of 150-1000 microns (μm) or equal to the upper and lower ends of the range (e.g., the first thickness T1 may be equal to 150 microns (μm) or may be equal to 1000 microns (μm)). In some embodiments, the first thickness T1 may be less than or equal to 1 millimeter (mm).

[0030] The single crystal layer 110 has a second thickness T2, which may be referred to as a second dimension. The second thickness T2 extends from the third surface 116 of the single crystal layer 110 to the fourth surface 118 of the single crystal layer 110. The second thickness T2 of the single crystal layer 110 may be less than the first thickness T1 of the polycrystalline layer 106. The second thickness T2 of the single crystal layer 110 may be in the range of 0.3-2 micrometers (μm) or equal to the upper and lower ends of the range (for example, the second thickness T2 may be equal to 0.3 micrometers (μm) or may be equal to 2 micrometers (μm)). In some embodiments, the second thickness T2 may be in the range of 0.3-1 micrometers (μm) or equal to the upper and lower ends of the range (for example, the second thickness T2 may be equal to 0.3 micrometers (μm) or may be equal to 1 micrometer (μm)). In some embodiments, the second thickness T2 of the single crystal layer 110 may be equal to 0.5 micrometers (μm). In some embodiments, the second thickness T2 may be less than or equal to 20-200 micrometers (μm) or equal to the upper and lower ends of the range (for example, the second thickness T2 may be equal to 20 micrometers (μm) or may be equal to 200 micrometers (μm)). In some embodiments, the second thickness T2 may be equal to 120 micrometers (μm).

[0031] The resistivity of the single crystal layer 110 may be between 1E5 (1*10^5) and 1E12 (1*10^12) ohm-cm or equal to the upper and lower ends of the range.

[0032] In such Figure 1In the embodiment of the wafer 100 shown in FIG. 1 , a bonding region 108 exists between a first surface 112 of the polycrystalline layer 106 and a second surface 114 of the single crystal layer 110, and the bonding region 108 is a location where the second surface 114 of the polycrystalline layer 106 is directly bonded to the single crystal layer 110. In some embodiments, the single crystal layer 110 is directly bonded to the polycrystalline layer 106 using a surface activated bonding (SAB) technique. In other words, there is no material (e.g., adhesive) between the single crystal layer 110 and the polycrystalline layer 106. For example, in the surface activation bonding technique, the second surface 114 of the polycrystalline layer 106 and the third surface 116 of the single crystal layer 110 may be bombarded with argon (Ar) ions or neutral atoms (e.g., a particle beam of argon (Ar), a particle beam of neutral atoms, or a particle beam of some other similar or similar type of potentially suitable particles or atoms) under ultra-high vacuum to clean and activate the second surface 114 of the polycrystalline layer 106 and the third surface 116 of the single crystal layer 110. After cleaning and activating the second surface 114 of the polycrystalline layer 106 and the third surface 116 of the single crystal layer 110, the second surface 114 of the polycrystalline layer 106 and the third surface 116 of the single crystal layer 110 are spontaneously bonded by bringing the second surface 114 of the polycrystalline layer 106 into contact with the third surface 116 of the single crystal layer 110. Such contact of the second surface 114 of the polycrystalline layer 106 and the third surface 116 of the single crystal layer 110 may be accomplished without heat treatment.

[0033] Wafer 100 also includes at least one sidewall 120 (e.g., Figure 1 ), along which at least one first sidewall 120a of the polycrystalline layer 106 and at least one second sidewall 120b of the single crystal layer 110 are respectively coplanar and flush with each other. In other words, at least one sidewall 120 includes and is defined by the corresponding sidewalls of the polycrystalline layer 106, the bonding layer 202, and the single crystal layer 110. The bonding layer 202 includes a sidewall 120c coplanar with the sidewall 120a of the polycrystalline layer 106 and the sidewall 120b of the single crystal layer 110.

[0034] As discussed previously herein, the polycrystalline layer 106 has a high resistivity, for example, a resistivity greater than or equal to 1*10^5 or 1E+5 ohm-cm. In some alternative embodiments, the polycrystalline layer 106 has a high resistivity in the range of 1*10^5 (1E+5) to 1*10^12 (1E+12) ohm-cm, or equal to the upper and lower ends of the range. In some alternative embodiments, the polycrystalline layer 106 has a high resistivity in the range of 1*10^5 to 1*10^9 ohm-cm, or equal to the upper and lower ends of the range. In some alternative embodiments, the polycrystalline layer 106 has a high resistivity in the range of 1*10^9 (1E9) to 1*10^12 (1E+12) ohm-cm, or equal to the upper and lower ends of the range. This high resistivity of the polycrystalline layer 106 allows electrical signals (e.g., electrons) to stably pass through the polycrystalline layer 106 (without becoming inaccurate when passing through the polycrystalline layer 106), so that high-power and high-frequency electrical signals can stably pass through the polycrystalline layer 106 and reach their destination with a higher level of accuracy than when the polycrystalline layer 106 instead has a low resistivity (e.g., less than 1*10^5 or 1E+5 ohm-cm). In other words, when the on-resistance (R on ) is high (i.e., high resistivity), the electrical signal will more stably and accurately pass through the polycrystalline layer 106, rather than becoming inaccurate when reaching its destination through the polycrystalline layer 106 within an electronic device (e.g., a semiconductor package, a semiconductor die, or some other similar or analogous electronic device where the polycrystalline layer 106 may be present).

[0035] Although Figure 1 Not shown, but in some alternative embodiments of wafer 100 , a silicon oxide (eg, SiO 2 ) layer may be present at bonding region 108 , such that the silicon oxide layer is located between polycrystalline layer 106 and single crystal layer 110 .

[0036] Wafer 100 has a diameter D1 extending from opposite points along a peripheral edge of wafer 100. Diameter D1 may be in the range of 150 to 300 millimeters (mm) and may be equal to the upper and lower limits of the range.

[0037] Embodiments of the wafer 100 may have some warp, which may be some curvature or bowing within embodiments of the wafer 100, which may cause the second surface 114 of the polycrystalline layer 106 to be slightly curved or have a slight curvature. However, while there may be some warp in the wafer 100, the warp in the wafer 100 is less than or equal to 75 micrometers (μm) or may be less than or equal to 45 micrometers (μm). The warp may be measured as the distance from a center point of the wafer to a point at or near an edge of the wafer in a direction transverse to the second surface 114 of the wafer.

[0038] The second surface 114 of the polycrystalline layer 106 may have a thickness less than or equal to 20 angstroms. In some embodiments, the roughness of the second surface 114 of the polycrystalline layer 106 may be between 1 and 5 angstroms. and can be equal to the lower and upper ends of the range (for example, the roughness can be equal to 1 angstrom Or it can be equal to 5 angstroms ). Such roughness of the second surface 114 can be obtained by polishing the second surface 114.

[0039] The third surface 116 of the single crystal layer 110 may have a thickness less than or equal to 20 angstroms. In some embodiments, the roughness of the third surface 116 of the single crystal layer 110 may be between 1 and 5 angstroms. and can be equal to the lower and upper ends of the range (for example, the roughness can be equal to 1 angstrom Or it can be equal to 5 angstroms ). Such roughness of the third surface 116 can be obtained by polishing the third surface 116.

[0040] The fourth surface 118 of the single crystal layer 110 may have a thickness less than or equal to 20 angstroms. In some embodiments, the roughness of the fourth surface 118 of the single crystal layer 110 may be between 1 and 5 angstroms. and can be equal to the lower and upper ends of the range (for example, the roughness can be equal to 1 angstrom Or it can be equal to 5 angstroms ). The roughness of the fourth surface 118 may be obtained by polishing or planarizing the fourth surface 116. In some embodiments, the roughness at the first surface 112 of the polycrystalline layer 106 may be greater than or equal to the roughness of the second surface 114 of the polycrystalline layer 106. The roughness of the first surface 112 may be obtained by polishing or planarizing the first surface 112.

[0041] Figure 2 A perspective side view of an alternative embodiment of wafer 200 having the same Figure 1 The same or similar features of the embodiment of wafer 100 shown in FIG. The same or similar features of wafer 200 relative to wafer 100 have the same or similar reference numerals. Figure 2 Discussion of alternative embodiments of the wafer 200 shown in FIG. 2 will focus on the embodiment of the wafer 200 shown in FIG. Figure 1 Different or additional features or details compared to the embodiment of wafer 100 shown in FIG.

[0042] With Figure 1Unlike the embodiment of the wafer 100 in which the second surface 114 of the polycrystalline layer 106 is directly bonded to the third surface 116 of the single crystal layer 110 as shown in FIG. Figure 2 In the embodiment of the wafer 200 shown in , the bonding layer 202 is present at the bonding region 108 and couples the polycrystalline layer 106 with the single crystal layer 110. For example, before performing the surface activated bonding (SAB) technique discussed earlier herein, a first conductive layer can be formed on the second surface 114 of the polycrystalline layer 106, and a second conductive layer can be formed on the third surface 116 of the single crystal layer 110. The first conductive layer and the second conductive layer can be made of the same or different conductive materials suitable for being bonded together using the SAB technique. In some embodiments, the first conductive layer and the second conductive layer can be formed on the second surface 114 of the polycrystalline layer 106 and the third surface 116 of the single crystal layer 110, respectively, by sputtering techniques or by some other techniques suitable for forming the first conductive layer and the second conductive layer on the second surface 114 of the polycrystalline layer 106 and the third surface 116 of the single crystal layer 110, respectively.

[0043] After forming the first conductive layer and the second conductive layer on the second surface 114 of the polycrystalline layer 106 and the third surface 116 of the single crystal layer 110, respectively, a surface activation bonding technique is performed, so that the first conductive layer and the second conductive layer are bombarded by argon (Ar) ions or neutral atoms (for example, a particle beam of argon (Ar), a particle beam of neutral atoms, or a particle beam of some other similar or similar types of potentially suitable particles or atoms) in an ultra-high vacuum to clean and activate the first conductive layer and the second conductive layer on the second surface 114 of the polycrystalline layer 106 and the third surface 116 of the single crystal layer 110, respectively. After cleaning and activating the first conductive layer and the second conductive layer, by contacting the first conductive layer on the second surface 114 of the polycrystalline layer 106 with the second conductive layer on the third surface 116 of the single crystal layer 110, the first conductive layer on the second surface 114 of the polycrystalline layer 106 and the second conductive layer on the third surface 116 of the single crystal layer 110 are spontaneously bonded. This contact of the first conductive layer on the second surface 114 of the polycrystalline layer 106 and the second conductive layer on the third surface 116 of the single crystal layer 110 can be completed without heat treatment. When the first conductive layer on the second surface 114 of the polycrystalline layer 106 and the second conductive layer on the third surface 116 of the single crystal layer 110 are bonded, a bonding layer 202 between the polycrystalline layer 106 and the single crystal layer 110 is formed.

[0044] In some alternative embodiments, instead of forming both the first conductive layer and the second conductive layer as discussed above, only one of the first conductive layer or the second conductive layer is formed on only one of the second surface 114 of the polycrystalline layer 106 or the third surface 116 of the single crystal layer 110. After forming only one of the first conductive layer or the second conductive layer, the SAB technique is performed in a manner similar to that previously described with respect to Figure 1 or Figure 2 The same or similar manner as discussed is performed, except that at least one of the second surface 114 of the polycrystalline layer 106 or the third surface 116 of the single crystal layer 110 remains uncovered and exposed to the argon or neutral atom beam.

[0045] When the first material of the polycrystalline layer 106 is incompatible with the second material directly bonded to the single crystal layer 110, either the first conductive layer and the second conductive layer are formed, or at least one of the first conductive layer or the second conductive layer is formed. In other words, when the first material of the polycrystalline layer 106 is incompatible with the second material of the single crystal layer 110, either the first conductive layer and the second conductive layer are formed, or at least one of the first conductive layer or the second conductive layer is formed to facilitate coupling the polycrystalline layer 106 and the single crystal layer 110 together.

[0046] When the bonding layer 202 is present between the second surface 114 of the polycrystalline layer 106 and the third surface of the single crystal layer 110, the bonding layer 202 has a third thickness T3, which may be referred to as a third size. The third thickness T3 extends from the second surface 114 of the polycrystalline layer 106 to the third surface 116 of the single crystal layer 110. The third thickness T3 may be less than the first thickness T1. The third thickness T3 of the bonding layer 202 may be in the range of 0.2-5 microns (μm) and may be equal to the upper and lower ends of the range (for example, the third thickness T3 may be equal to 0.2 microns (μm) or may be equal to 5 microns (μm)). In some embodiments, the third thickness may be equal to 0.5 microns (μm).

[0047] Alternative embodiments of the wafer 200 may have some warpage, which may be some curvature or bowing within the alternative embodiments of the wafer 200, which may cause the second surface 114 of the polycrystalline layer 106 to be slightly curved or have a slight curvature. However, while some warpage may exist in the alternative embodiments of the wafer 200, the warpage in the alternative embodiments of the wafer 200 may be less than or equal to 75 micrometers (μm) or may be less than or equal to 45 micrometers (μm).

[0048] The second surface 114 of the polycrystalline layer 106 may have a thickness less than or equal to 20 angstroms. In some embodiments, the roughness of the second surface 114 of the polycrystalline layer 106 may be between 1 and 5 angstroms. and can be equal to the lower and upper ends of the range (for example, the roughness can be equal to 1 angstrom Or it can be equal to 5 angstroms ). Such roughness of the second surface 114 can be obtained by polishing the second surface 114.

[0049] The third surface 116 of the single crystal layer 110 may have a thickness less than or equal to 20 angstroms. In some embodiments, the roughness of the third surface 116 of the single crystal layer 110 may be between 1 and 5 angstroms. and can be equal to the lower and upper ends of the range (for example, the roughness can be equal to 1 angstrom Or it can be equal to 5 angstroms ). Such roughness of the third surface 116 can be obtained by polishing the third surface 116.

[0050] The fourth surface 118 of the single crystal layer 110 may have a thickness less than or equal to 20 angstroms. In some embodiments, the roughness of the fourth surface 118 of the single crystal layer 110 may be between 1 and 5 angstroms. and can be equal to the lower and upper ends of the range (for example, the roughness can be equal to 1 angstrom Or it can be equal to 5 angstroms ). Such roughness of the fourth surface 118 can be obtained by polishing or planarizing the fourth surface 116.

[0051] In some embodiments, the roughness at the first surface 112 of the polycrystalline layer 106 may be greater than or equal to the roughness of the second surface 114 of the polycrystalline layer 106. Such roughness of the first surface 112 may be obtained by polishing or planarizing the first surface 112.

[0052] Figure 3A FIG. 4 is a top view of an embodiment of a polycrystalline substrate 300. Figure 3A As shown in FIG. 1 , the grains 301 of the polycrystalline substrate 300 are easily visible at the second surface 304 opposite to the first surface 302 (see FIG. 10 ). Figure 3B The first surface 302 and the second surface 304 in the embodiment of the present invention are shown in Figure 3. The average grain size of the grains 301 is greater than 0.5 millimeters (mm). In some embodiments, the average grain size is greater than 1 millimeter (mm). In some embodiments, the grain size is in the range of 0.5 to 2 millimeters (mm), or the average grain size is equal to the upper and lower ends of the range. In some embodiments, the grain size is in the range of 1 to 2 millimeters (mm), or the average grain size is equal to the upper and lower ends of the range.

[0053] The average grain size can be determined using a line intercept technique or model. In this technique, a random straight line is drawn through a microscopic image of a selected area of ​​the substrate. When a random straight line is selected, the number of grain boundaries intersected by the random straight line is counted. When the number of grain boundaries intersected by the random straight line is determined, the length of the random straight line is divided by the number of intersected grain boundaries. Alternatively, the process can be completed with multiple random straight lines, the number of intersections of these multiple random straight lines with grain boundaries is counted, and then the sum of the lengths of the multiple straight lines is divided by the total number of intersected grain boundaries to obtain the average grain size of the grains of the substrate.

[0054] Figure 3B is a perspective side view of an embodiment of a polycrystalline substrate 300, which may be a polycrystalline wafer before a single crystal substrate or wafer (e.g., single crystal layer 110) has been coupled or bonded to the polycrystalline substrate 300. The polycrystalline substrate 300 has a diameter D1. The polycrystalline substrate 300 may be used to form the polycrystalline layer 106 of the embodiment of the wafer 100 and the alternative embodiment of the wafer 200. The polycrystalline substrate 300 includes a first surface 302, a second surface 304 opposite the first surface 302, and a sidewall 306 extending from the first surface 302 to the second surface 304 and transverse to the first surface 302 and the second surface 304. The second surface 304 of the polycrystalline substrate 300 may correspond to the second surface 114 of the polycrystalline layer 106 of the embodiment of the wafer 100 and the alternative embodiment of the wafer 200. The sidewall 306 of the polycrystalline substrate 300 may correspond to the at least one first sidewall 120 a of the polycrystalline layer 106 as in the embodiment of wafer 100 and the alternative embodiment of wafer 200 .

[0055] The fourth thickness T4 of the polycrystalline substrate 300 extends from the first surface 302 to the second surface 304 of the polycrystalline substrate 300. The fourth thickness T4 may be greater than or equal to the third thickness T3 of the polycrystalline layer 106 as in the embodiment of the wafer 100 and the alternative embodiment of the wafer 200. The fourth thickness T4 may be in a range of 150 micrometers (μm) to 1000 micrometers (μm), or may be equal to the lower end and the upper end of the range.

[0056] The polycrystalline substrate 300 has a high resistivity, for example, a resistivity greater than or equal to 1*10^5 or 1E+5 ohm-cm.

[0057] Embodiments of the polycrystalline substrate 300 may have some warp, which may be some curvature or bowing within embodiments of the polycrystalline substrate 300, which may cause the second surface 304 of the polycrystalline layer 106 to be slightly curved or have a slight curvature. However, while some warp may exist in the polycrystalline substrate 300, the warp in the polycrystalline substrate 300 may be less than or equal to 75 micrometers (μm) or may be less than or equal to 45 micrometers (μm).

[0058] The second surface 304 of the polycrystalline substrate 300 may have a thickness less than or equal to 20 angstroms. In some embodiments, the roughness of the second surface 304 of the polycrystalline substrate 300 may be between 1 and 5 angstroms. and can be equal to the lower and upper ends of the range (for example, the roughness can be equal to 1 angstrom Or it can be equal to 5 angstroms ). Such roughness of the second surface 304 can be obtained by polishing the second surface 304.

[0059] In at least one embodiment, the size of the grains 301 at the first surface 302 is the same or similar in size to the size of the grains 301 at the second surface 304. In at least one embodiment, the average size of the grains 301 at the first surface 302 is the same (i.e., equal) or similar to the average size of the grains 301 at the second surface 304.

[0060] In at least one embodiment, the average grain sizes of the grains 301 taken at multiple locations (i.e., slices) along the thickness T4 of the polycrystalline substrate 300 remain the same (i.e., equal) or similar to each other. For example, if the polycrystalline substrate 301 is cut close to the first surface 302 and the average grain size is measured, the average grain size at the slice close to the first surface 302 will be the same or similar to the average grain size at the second surface 304, or the same or similar to the average grain size measured at a slice taken anywhere else along the thickness T4 of the polycrystalline substrate 300. In other words, the average grain size taken along any slice at any location at or between the first surface 302 and the second surface 304 is the same (i.e., equal) or similar to the average grain size at any other slice at any other location at or between the first surface 302 and the second surface 304, so that the average grain size is uniform throughout the thickness T4 of the polycrystalline substrate 300.

[0061] Figure 3C Yes Figure 3A The embodiment of the polycrystalline substrate 300 shown in FIG. Figure 3A The polycrystalline substrate 300 includes grains 402 of silicon carbide (e.g., SiC, SiC2, etc.) that may be bonded together (see the disclosure of the present invention). Figure 4A ).like Figure 3C The grain 402 shown in FIG. Figure 3A The same as the grain 301 shown in FIG. Figure 3C This magnified enhanced view shown in FIG. 3 may represent the grain structure of the polycrystalline substrate 300 (see FIG. 300 of the present disclosure). Figure 3A and Figure 3B) or the grain structure of the polycrystalline layer 106 of the wafer 100, 200 (see the disclosure of Figure 1 and Figure 2 ). The polycrystalline substrate 300 is a non-columnar type polycrystalline material, such that the polycrystalline substrate 300 has random or amorphous oriented grains and does not have a columnar type structure. These random and amorphous oriented grains and non-columnar structures of the polycrystalline substrate 300 may be referred to as a non-oriented grain structure. Such a non-oriented grain structure may help increase the overall resistivity of the polycrystalline substrate 300. The polycrystalline substrate 300 may include micro-pores 404, which may exist along grain boundaries 406 between grains 402. The grain boundaries 406 are located between adjacent pairs of corresponding grains in the grains 402. Carbon may be present at the grain boundaries 406 to adhere the grains 402 to each other in the polycrystalline layer 106. The grains 402 may have a size less than or equal to 1 millimeter (mm).

[0062] As discussed previously herein, the polycrystalline layer 106 has a high resistivity, which can be formed using a polycrystalline substrate 300 that also has a high resistivity. The polycrystalline substrate 300 can have a high resistivity by reducing or limiting the number of micropores 404 between the grains 402 along the grain boundaries 406, such that the polycrystalline substrate 300 has a resistivity greater than or equal to 1×10^5 ohm-cm. In some embodiments, the polycrystalline substrate 300 can have a low amount of nitrogen (N) doped within the polycrystalline substrate 300 to reduce and offset the effects of the presence of the micropores 404 within the polycrystalline layer 106. For example, in some embodiments, the polycrystalline layer 106 can be doped with a low amount of nitrogen, such that the concentration of nitrogen (N) in the polycrystalline substrate 300 is less than or equal to 1×10^5 ohm-cm per cm. 3 1E+16 atoms (i.e., 1x10 16 atoms / cm 3 The polycrystalline substrate 300 may be manufactured to have such a low concentration of nitrogen by utilizing a source gas having a purity of 99.9% purity or better, or alternatively by using a high purity solid source to reduce the concentration of nitrogen (N) present in the polycrystalline substrate 300 after it is formed.

[0063] In at least one embodiment, the polycrystalline substrate 300 has a thickness greater than or equal to 1×10 7 In at least one embodiment, the polycrystalline substrate 300 has a resistivity greater than or equal to 1×10 8 Resistivity in ohm-cm.

[0064] In view of the above discussion, by reducing the impact of micropores 404 or by preventing the formation of micropores 404 in the polycrystalline substrate 300, and providing relatively large grains 402 (i.e., see the previous discussion on the grain size of the grains 402) and large grain boundaries 406, the resistivity of the polycrystalline substrate 300 is increased. In at least some embodiments, the porosity of the polycrystalline substrate 300 ranges from 0 to 2%, or is equal to the upper and lower ends of the range. In at least some embodiments, the porosity of the polycrystalline substrate 300 is less than or equal to 2%. In at least some embodiments, the porosity of the polycrystalline substrate 300 is less than or equal to 1%. In other words, ideally, the polycrystalline substrate 300 has no micropores 404, and it is desirable to avoid the presence of micropores 404 in the polycrystalline substrate 300 so that the polycrystalline substrate 300 has no porosity.

[0065] In at least some embodiments, the polycrystalline substrate 300 has a silicon carbide (SiC) purity greater than or equal to 98%. In at least some embodiments, the polycrystalline substrate has a silicon carbide (SiC) purity ranging from 99% to 100%, or it is equal to the upper and lower ends of the range. In at least one embodiment of the polycrystalline substrate 300, the polycrystalline substrate 300 does not contain any metal or additive materials and is entirely composed of silicon carbide (SiC). In other words, given these purity ranges and the discussion of the purity of the polycrystalline substrate 300, in an ideal case, the polycrystalline substrate 300 is 100% pure silicon carbide (SiC) and does not contain any additives (i.e., metal particles).

[0066] The density of the polycrystalline substrate 300 is 98% higher than that of a single crystal SiC layer or substrate having a high resistivity. The polycrystalline substrate 300 having such a much higher density further prevents lower resistance points compared to a single crystal layer or substrate having a similarly high resistivity, thereby allowing conduction to occur between the grains 402 with less resistance. In at least one embodiment, the polycrystalline substrate 300 has a density ranging from 3.14 g / cm^3 (i.e., grams per cubic centimeter) to 3.21 g / cm^3, or has a density equal to the upper and lower ends of the range. In at least some embodiments, the polycrystalline substrate 300 has a density greater than or equal to 3.19 g / cm^3.

[0067] In at least one embodiment, the polycrystalline substrate 300 has a thermal conductivity ranging from 250 W / (m*K) (i.e., Watts per meter Kelvin) to 350 W / (m*K) or equal to the upper and lower ends of the range. In at least one embodiment, the polycrystalline substrate 300 has a thermal conductivity greater than or equal to 300 W / (m*K). In other words, the polycrystalline substrate 300 has a relatively high thermal conductivity, which allows the polycrystalline substrate 300 to dissipate thermal energy or heat more effectively than a corresponding polycrystalline substrate with a lower thermal conductivity. Since the polycrystalline substrate 300 has a high resistivity (which is caused by relatively large grains 301, 402, relatively large grain boundaries 406, and a low number of micropores 404 or no micropores 404), and has a high thermal conductivity, the polycrystalline substrate 300 is effective and can be used in high power and high frequency applications.

[0068] In at least one embodiment, the polycrystalline substrate 300 has a transparency ranging from 97.5% to 99.5% or equal to the upper and lower ends of the range. In at least one embodiment, the polycrystalline substrate has a transparency greater than or equal to 98%.

[0069] In at least one embodiment, the polycrystalline substrate 300 has a crystal orientation of 111. In at least one embodiment, the polycrystalline substrate 300 has a crystal orientation of 111 in 60% to 90% of the grains or equal to the upper and lower ends of the range.

[0070] Figure 4A For the disclosure Figure 1 Flowchart 500 of an embodiment of a method for manufacturing an embodiment of wafer 100 is shown in FIG. Figure 5A-5C A side view of steps 502 , 504 , 506 , and 508 in a flowchart 500 of an embodiment of a method for manufacturing an embodiment of the wafer 100 of the present disclosure.

[0071] In the polycrystalline substrate forming step 502, a polycrystalline substrate 300 having a high resistivity is formed. In the single crystal substrate forming step 504, a single crystal substrate 600 is formed. The polycrystalline substrate forming step 502 of forming the polycrystalline substrate 300 and the single crystal substrate forming step 504 of forming the single crystal substrate 600 may be performed simultaneously in a semiconductor fabrication facility (FAB), or may be performed at different times in the FAB.

[0072] The polycrystalline substrate forming step 502 for forming the polycrystalline substrate 300 having a high resistivity may be performed using Figure 4B The chemical vapor deposition (CVD) flow chart 502a shown in FIG. Figure 4C The method of forming the polycrystalline substrate 300 may be implemented by using at least one embodiment of the high temperature chemical vapor deposition (HTCVD) flow chart 502 b shown in FIG.

[0073] When using Figure 4B When forming a polycrystalline substrate 300 by the method in the CVD flow chart 502a shown in FIG. 5 , in a first step 510, a carrier (e.g., a disk made of graphite, a simulated silicon substrate, or some other suitable type of carrier or temporary carrier on which polycrystalline silicon carbide (SiC) can be formed) is inserted or introduced into a chamber of a CVD tool configured to perform or implement a CVD process to form the polycrystalline substrate 300. The carrier can be a plate, can be a carrier substrate, or can be some other suitable type of carrier on which the polycrystalline substrate is formed. The carrier can be a polycrystalline carrier substrate or plate, can be a graphite carrier substrate or plate, or can be some other suitable type of carrier substrate or plate on which the polycrystalline substrate 300 is formed.

[0074] After the first step 510 of inserting or introducing the carrier into the chamber of the CVD tool, in a second step 512, the chamber is sealed and a carrier gas is introduced into the chamber of the CVD tool. The carrier gas can be hydrogen. In some embodiments, the carrier gas can be some other type of inert gas (e.g., argon, helium, etc.). The carrier gas is introduced at a flow rate of 100 liters per minute (l / min). The carrier gas is configured or selected to enhance the chemical reaction within the chamber of the furnace of the CVD tool to grow polycrystalline silicon carbide (SiC) on the carrier in the chamber of the furnace of the CVD tool. In some embodiments, during the second step 512, the chamber of the furnace of the CVD tool can be heated in a range of 1250 to 1350 degrees Celsius (°C), or can be heated to a temperature equal to the upper and lower ends of the range (e.g., a temperature equal to 1250 degrees Celsius (°C) or a temperature equal to 1350 degrees Celsius (°C)). In some alternative embodiments, during the second step 512, the chamber of the furnace of the CVD tool may be heated to a temperature equal to 1320 degrees Celsius (°C).

[0075] After the second step 512 in which the carrier gas has been introduced into the chamber of the furnace of the CVD tool and the chamber of the furnace of the CVD tool has been heated or heating has been initiated, in a third step 514, source gas is introduced into the chamber of the furnace of the CVD tool. The source gas includes a carbon gas or a carbon-based gas (e.g., ethylene) and a silicon-containing gas or a silicon-based gas (e.g., silane, trichlorosilane (TCS), or some other similar silicon-containing gas or silicon-based gas). When the source gas includes ethylene gas and silane gas, the ethylene gas is introduced at a rate of 60 milliliters per minute (ml / min), and the silane gas is introduced at a rate of 80 milliliters per minute (ml / min). For example, a carbon gas or a carbon-based gas (in this example, ethylene gas) can be introduced into the chamber of the furnace of the CVD tool by introducing a solid source of ethylene into the chamber of the furnace of the CVD tool, and a silicon-containing gas or a silicon-based gas (in this example, silane gas) can be introduced into the chamber of the furnace of the CVD tool by introducing a solid source of silane into the chamber of the furnace of the CVD tool. Alternatively, a corresponding fluid passage in fluid communication with the chamber of the furnace of the CVD tool can be opened to introduce a carbon gas or a carbon-based gas (i.e., ethylene gas) and a silicon-containing gas or a silicon-based gas (i.e., silane gas). When these corresponding gases are introduced into the chamber of the CVD tool at this stage, these corresponding gases chemically react with each other, resulting in polycrystalline silicon carbide (SiC) being formed and deposited on the carrier, resulting in polycrystalline silicon carbide being formed on the carrier surface of the carrier. When the carrier is a polycrystalline silicon carbide carrier substrate or plate, the polycrystalline silicon carbide formed by the reaction in the chamber of the CVD tool is deposited on the polycrystalline silicon carbide carrier substrate or plate. When the carrier is a graphite carrier substrate or plate, polycrystalline silicon carbide formed by the reaction in the chamber of the CVD tool is deposited onto the graphite carrier substrate or plate. The carrier has a polycrystalline structure so that a polycrystalline substrate 300 can be formed on a corresponding surface of the carrier. The corresponding surface of the carrier has a roughness less than or equal to 5 nm (i.e., nanometers). The corresponding surface of the carrier has a structure that is the same or similar to the polycrystalline substrate 300 to be formed and grown on the carrier. In some cases, before forming or growing the polycrystalline substrate 300 on the carrier, the corresponding surface of the carrier is treated by a surface treatment process. When polycrystalline silicon carbide is formed in the chamber of the CVD tool, a polycrystalline silicon carbide substrate is formed. In some embodiments, the polycrystalline silicon carbide may be doped with a small amount of nitrogen (e.g., less than or equal to 1x10 16 Atom / cm 3 concentration of nitrogen).

[0076] The third step 514 of the process is performed for between 1 and 4 hours, for 1 hour, or for 4 hours to form polycrystalline silicon carbide of a selected thickness on the carrier. Performing the third step 514 for between 1 and 4 hours, for 1 hour, or for 4 hours results in the formation of polycrystalline silicon carbide having a thickness between 350 and 500 micrometers (μm), or at the upper and lower ends of the range.

[0077] After the third step 514 of introducing a carbon gas or a carbon-based gas (i.e., an ethylene gas) and a silicon-containing gas or a silicon-based gas (i.e., a silane gas) into the chamber of the furnace of the CVD tool while heating it to form polycrystalline silicon carbide on the carrier, in a fourth step 516, the chamber of the CVD tool and the polycrystalline substrate 300 formed on the carrier are allowed to cool to room temperature. As the polycrystalline substrate 300 cools on the carrier, the difference in thermal conductivity between the polycrystalline substrate 300 and the carrier may cause some warping in the polycrystalline substrate 300. However, such warping of the polycrystalline substrate 300 is less than or equal to 75 micrometers (μm), or may be less than or equal to 45 micrometers (μm). When cooled to room temperature, the polycrystalline substrate 300 coupled to the carrier and the carrier are removed from the chamber of the CVD tool. After the polycrystalline substrate 300 and the carrier are removed from the chamber, the polycrystalline substrate 300 can be removed from the carrier and then further processed (e.g., polishing techniques, planarization techniques, etc.), a portion of the polycrystalline substrate 300 can be cut from the polycrystalline substrate 300 while coupled to the carrier or after being removed from the carrier or before or after further processing to form the polycrystalline layer 106, or the polycrystalline substrate can undergo other suitable types of processing techniques to further refine or process the polycrystalline substrate 300 to form a variety of electronic devices or components.

[0078] After the polycrystalline substrate 300 is formed, the polycrystalline substrate 300 may be used to form Figure 1 The embodiment of the wafer 100 shown in FIG. Figure 2 For example, in at least one case, the second surface 304 of the polycrystalline substrate 300 is polished or planarized so that the second surface 304 of the polycrystalline substrate 300 has a surface area of ​​less than or equal to 20 angstroms. In some embodiments, the second surface 304 of the polycrystalline substrate 300 has a roughness of 1-5 angstroms. or having a roughness equal to the lower or upper end of the range (for example, the roughness may be equal to 1 angstrom Or it can be equal to 5 angstroms After the second surface 304 of the polycrystalline substrate 300 has been polished or planarized, the polycrystalline substrate 300 may then be used to form a Figure 1 The embodiment of the wafer 100 shown in FIG. Figure 2 An alternative embodiment of wafer 200 is shown in FIG.

[0079] When the polycrystalline substrate 300 is formed using a method using a CVD tool as shown in flowchart 502a, the polycrystalline substrate 300 is mostly made of a polycrystalline structure of a 3C-SiC polytype. For example, in some embodiments, 80% of the crystal structure of the polycrystalline substrate 300 is made of a 3C-SiC polytype. In some embodiments, 50% to 100% of the crystal structure of the polycrystalline substrate 300 or can be equal to the upper and lower ends of the range (e.g., equal to 50% or equal to 100%) is made of a 3C-SiC polytype. The polycrystalline substrate 300 has a high resistivity greater than 1x10^5 or 1E+5 ohm-cm.

[0080] When using Figure 4C When forming a polycrystalline substrate 300 according to the method in the HTCVD flow chart 502b shown in , in a first step 518, a carrier (e.g., a disk made of graphite, a simulated silicon substrate, or some other suitable type of carrier or temporary carrier on which polycrystalline silicon carbide (SiC) can be formed) is inserted or introduced into a chamber of an HTCVD tool, which is configured to perform or implement an HTCVD process to form a polycrystalline substrate 300. The carrier can be a plate, can be a carrier substrate, or can be some other suitable type of carrier on which a polycrystalline substrate is formed. The carrier can be a polycrystalline carrier substrate or plate, can be a graphite carrier substrate or plate, or can be some other suitable type of carrier substrate or plate on which a polycrystalline substrate is formed. The carrier has a polycrystalline structure so that the polycrystalline substrate 300 can be formed on a corresponding surface of the carrier. The corresponding surface of the carrier has a roughness less than or equal to 5nm (i.e., nanometers). The corresponding surface of the carrier has a structure that is the same or similar to the polycrystalline substrate 300 to be formed and grown on the carrier. In some cases, prior to forming or growing the polycrystalline substrate 300 on the carrier, the corresponding surface of the carrier is treated by a surface treatment process.

[0081] After the first step 518 of inserting or introducing the carrier into the chamber of the HTCVD tool, in a second step 520, the chamber is sealed and a carrier gas is introduced into the chamber of the HTCVD tool. The carrier gas may be argon, helium, or hydrogen. In some embodiments, the carrier gas may be some other type of inert gas. The carrier gas is introduced at a flow rate of 100 liters per minute (l / min). The carrier gas is configured or selected to enhance the chemical reaction within the chamber of the furnace of the HTCVD tool to grow polycrystalline silicon carbide (SiC) on the carrier in the chamber of the furnace of the HTCVD tool. In some embodiments, during the second step 520, the chamber of the furnace of the HTCVD tool may be heated in a range from 2000 to 2500 degrees Celsius (°C), or may be heated to a temperature equal to the upper and lower ends of the range (e.g., a temperature equal to 2000 degrees Celsius (°C) or a temperature equal to 2500 degrees Celsius (°C)). In some alternative embodiments, during the second step 520 , the chamber of the furnace of the HTCVD tool may be heated to a temperature equal to 2250 degrees Celsius (° C.).

[0082] After the second step 520 in which the carrier gas has been introduced into the chamber of the furnace of the HTCVD tool and the chamber of the furnace of the HTCVD tool has been heated or heating has been initiated, in a third step 522, source gases are introduced into the chamber of the furnace of the CVD tool. The source gases include a carbon gas or a carbon-based gas (e.g., ethylene) and a silicon-containing gas or a silicon-based gas (e.g., silane, trichlorosilane (TCS), or some other similar silicon-containing gas or a silicon-based gas). When the source gases include ethylene gas and silane gas, the ethylene gas is introduced at a rate of 46.7 milliliters per minute (ml / min), and the silane gas is introduced at a rate of 350 milliliters per minute (ml / min). For example, a carbon gas or a carbon-based gas (in this example, ethylene gas) can be introduced into the chamber of the furnace of the HTCVD tool by introducing a solid source of ethylene into the chamber of the furnace of the HTCVD tool, and a silicon-containing gas or a silicon-based gas (in this example, silane gas) can be introduced into the chamber of the furnace of the HTCVD tool by introducing a solid source of silane into the chamber of the furnace of the HTCVD tool. Alternatively, corresponding fluid passages in fluid communication with the chamber of the furnace of the HTCVD tool can be opened to introduce the carbon gas or a carbon-based gas (i.e., ethylene gas) and the silicon-containing gas or a silicon-based gas (i.e., silane gas). When these corresponding gases are introduced into the chamber of the HTCVD tool at this stage, these corresponding gases chemically react with each other, resulting in polycrystalline silicon carbide (SiC) being formed and deposited onto the carrier, resulting in polycrystalline silicon carbide being formed on the carrier surface of the carrier. When the carrier is a polycrystalline silicon carbide carrier substrate or plate, the polycrystalline silicon carbide formed by the reaction in the chamber of the HTCVD tool is deposited onto the polycrystalline silicon carbide carrier substrate or plate. When the carrier is a graphite carrier substrate or plate, the polycrystalline silicon carbide formed by the reaction in the chamber of the HTCVD tool is deposited onto the graphite carrier substrate or plate. When the polycrystalline silicon carbide is formed in the chamber of the HTCVD tool, a polycrystalline silicon carbide substrate is formed. In some embodiments, the polycrystalline silicon carbide may be doped with a small amount of nitrogen, which is less than or equal to 1×10 16 Atom / cm 3 .

[0083] The third step 522 of the process is performed for between 1 and 4 hours, for 1 hour, or for 4 hours to form polycrystalline silicon carbide of a selected thickness on the carrier. Performing the third step 522 for between 1 and 4 hours, for 1 hour, or for 4 hours produces polycrystalline silicon carbide with a thickness between 350 and 500 micrometers (μm), or the thickness can be equal to the upper and lower ends of the range.

[0084] After the third step 522 of introducing a carbon gas or a carbon-based gas (i.e., an ethylene gas) and a silicon-containing gas or a silicon-based gas (i.e., a silane gas) into the chamber of the furnace of the HTCVD tool while heating it to form polycrystalline silicon carbide on the carrier, in a fourth step 524, the chamber of the HTCVD tool and the polycrystalline substrate 300 formed on the carrier are allowed to cool to room temperature. As the polycrystalline substrate 300 cools on the carrier, the difference in thermal conductivity between the polycrystalline substrate 300 and the carrier may cause some warping in the polycrystalline substrate 300. However, such warping of the polycrystalline substrate 300 is less than or equal to 75 micrometers (μm) or may be less than or equal to 45 micrometers (μm). When cooled to room temperature, the polycrystalline substrate 300 coupled to the carrier and the carrier are removed from the chamber of the HTCVD tool. After the polycrystalline substrate 300 and the carrier are removed from the chamber, the polycrystalline substrate 300 can be removed from the carrier and then further processed (e.g., polishing techniques, planarization techniques, etc.), a portion of the polycrystalline substrate 300 can be cut from the polycrystalline substrate 300 while coupled to the carrier or after being removed from the carrier or before or after further processing to form the polycrystalline layer 106, or the polycrystalline substrate can undergo other suitable types of processing techniques to further refine or process the polycrystalline substrate 300 to form a variety of electronic devices or components.

[0085] After the polycrystalline substrate 300 is formed, the polycrystalline substrate 300 may be used to form Figure 1 The embodiment of the wafer 100 shown in FIG. Figure 2 For example, in at least one case, the second surface 304 of the polycrystalline substrate 300 is polished or planarized so that the second surface 304 of the polycrystalline substrate 300 has a thickness less than or equal to 20 angstroms. In some embodiments, the second surface 304 of the polycrystalline substrate 300 has a roughness of 1-5 angstroms. The roughness of the substrate may be within the range or have a roughness equal to the lower or upper end of the range (for example, the roughness may be equal to 1 angstrom Or it can be equal to 5 angstroms After the second surface 304 of the polycrystalline substrate 300 has been polished or planarized, the polycrystalline substrate 300 may then be used to form a Figure 1 The embodiment of the wafer 100 shown in FIG. Figure 2 An alternative embodiment of wafer 200 is shown in FIG.

[0086] In the single crystal substrate forming step 504, a single crystal substrate 600 may be formed using a method known in the semiconductor industry (see Figure 5B ). For example, the single crystal substrate 600 may be formed by melting high purity semiconductor grade silicon and then utilizing a seed crystal to initiate the formation of the single crystal substrate.

[0087] When forming the polycrystalline substrate 300 and the single crystal substrate 600, in the coupling or bonding step 506 of the flowchart 500 of the embodiment for forming the wafer 100, the second surface 304 of the polycrystalline substrate 300 is bonded to the third surface 602 of the single crystal substrate 600 using a surface activated bonding (SAB) technique. The third surface 602 of the single crystal substrate 600 may correspond to the third surface 116 of the single crystal layer 110 of the wafer 100.

[0088] When the SAB technique is used, the second surface 304 of the polycrystalline substrate 300 is exposed to a neutral atom beam or an argon (Ar) atom beam (eg, Figure 5A ) to activate and clean the second surface 304 of the polycrystalline substrate 300. The second surface 304 of the polycrystalline substrate 300 may have been planarized to be substantially flat and level, and polished to have a surface roughness less than or equal to 20 angstroms. In some embodiments, before being exposed to the neutral atom beam or the argon (Ar) atom beam, the second surface 304 of the polycrystalline substrate 300 may have a roughness of 1-5 angstroms. or equal to the lower and upper ends of the range (for example, the roughness may be equal to 1 angstrom Or it can be equal to 5 angstroms ).

[0089] When the SAB technique is used, the third surface 602 of the single crystal substrate 600 is exposed to a neutral atom beam or an argon (Ar) atom beam (not shown) to activate and clean the third surface 602 of the single crystal substrate 600. The third surface 602 of the single crystal substrate 600 may have been planarized to be substantially flat and level, and polished to have a surface roughness less than or equal to 20 angstroms. In some embodiments, before being exposed to the neutral atom beam or the argon (Ar) atom beam, the third surface 602 of the single crystal substrate 600 may have a roughness of 1-5 angstroms. or equal to the lower and upper ends of the range (for example, the roughness may be equal to 1 angstrom Or it can be equal to 5 angstroms ).

[0090] The fourth surface 610 of the second portion 600b of the single crystal substrate 600 may have a thickness less than or equal to 20 angstroms. In some embodiments, the fourth surface 610 of the second portion 600b of the single crystal substrate 600 may have a roughness of 1-5 angstroms. and can be equal to the roughness at the lower and upper ends of the range (for example, the roughness can be equal to 1 angstrom Or it can be equal to 5 angstroms ). Such roughness of the fourth surface 610 may be obtained by polishing or planarizing the fourth surface 610.

[0091] In some embodiments, the roughness at the first surface 302 of the polycrystalline substrate 300 may be greater than or equal to the roughness of the second surface 304 of the polycrystalline substrate 300. Such roughness of the first surface 302 may be obtained by polishing or planarizing the first surface 302.

[0092] After cleaning and activating the second surface 304 of the polycrystalline substrate 300 and the third surface 602 of the single crystal substrate 600, the single crystal substrate 600 is flipped over, and the cleaned and activated third surface 602 of the single crystal substrate 600 is brought into contact with the cleaned and activated second surface 304 of the polycrystalline substrate 300, so that the cleaned and activated second surface 304 and the cleaned and activated third surface 602 are spontaneously bonded, resulting in the single crystal substrate 600 being bonded to the polycrystalline substrate 300 at the bonding region 604. When the single crystal substrate 600 is bonded to the polycrystalline substrate 300, the sidewall 606 of the single crystal substrate 600 is flush with the sidewall 306 of the polycrystalline substrate 300. The single crystal substrate 600 has a fifth thickness T5 extending from the third surface 602 of the single crystal substrate 600 to a fourth surface 608 of the single crystal substrate 600 opposite to the third surface 602 of the single crystal substrate 600.

[0093] After the bonding step 506 of bonding the single crystal substrate 600 to the polycrystalline substrate 300, the first portion 600a is removed from the second portion 600b of the single crystal substrate 600 in a removing step 508. The first portion 600a may be removed from the second portion 600b by cutting the single crystal substrate 600 forming the first portion 600a and the second portion 600b. After the second portion 600b has been removed from the first portion 600a, the second portion 600b of the single crystal substrate 600 may be reused to form another wafer that is the same as or similar to the wafer 100, for example, by performing the bonding step 506 and the removing step 508 of the manufacturing method in the flowchart 500. Removing the first portion 600a from the second portion 600b results in the sidewall 606 being decomposed into the first sidewall 606a of the first portion 600a and the second sidewall 606b of the second portion 600b. After the first portion 600a is removed, the second sidewall 606b of the second portion 600b remains coplanar and flush with the sidewall 306 of the polycrystalline substrate 300. After the first portion 600a is removed, the second portion 600b remains bonded to the polycrystalline substrate 300 at the bonding area 604. After the first portion 600a is removed from the second portion 600b, the second portion 600b has a second thickness T2 extending between a third surface 602 of the second portion 600b and a fourth surface 610 of the second portion 600b formed by removing the first portion 600a from the second portion 600b. After the first portion 600a is removed from the second portion 600b, the first portion has a sixth thickness T6 extending from the fourth surface 608 of the first portion 600a to a fifth surface 612 of the first portion 600a opposite the fourth surface of the first portion 600a. The sixth thickness T6 is less than the fifth thickness T5.

[0094] The second portion 600b of the single crystal substrate 600 may correspond to the single crystal layer 110 of the wafer 100, the polycrystalline substrate 300 may correspond to the polycrystalline layer 106 of the wafer 100, and the bonding region 604 may correspond to the bonding region 108 of the wafer 100. In other words, in some embodiments, after the first portion 600a is removed from the second portion 600b, the wafer 100 has been manufactured. In some alternative embodiments, some further processing steps (such as grinding the first surface 302 of the polycrystalline substrate 300) may be performed to complete the manufacturing of the wafer 100.

[0095] Since the manufacturing of the single crystal substrate 600 is generally more expensive than the polycrystalline substrate 300, bonding the single crystal substrate 600 to the high resistivity polycrystalline substrate 300 as a support and removing the first portion 600a from the second portion 600b reduces the manufacturing cost because the single crystal substrate 600 can be used to form multiple wafers 100. In other words, although the cost of manufacturing a single crystal substrate may be expensive, the cost of manufacturing the single crystal substrate 600 can be spread over multiple wafers 100 manufactured using the manufacturing method in the flowchart 500.

[0096] In an alternative embodiment of the manufacturing method in flowchart 500, the first portion 600a of the single crystal substrate 600 may be removed from the second portion 600b of the single crystal substrate 600 before bonding the single crystal substrate 600 to the multicrystalline substrate 300. After the first portion 600a has been removed from the second portion 600b, the third surface 602 of the second portion 600b of the single crystal substrate 600 is bonded to the second surface 304 of the multicrystalline substrate 300. In other words, in this alternative embodiment of the manufacturing method of the wafer 100, the removing step 508 occurs before the bonding step 506.

[0097] Although the above Figure 4A The method discussed in detail in the flowchart in FIG. 1 describes forming wafer 100, but the above description of Figure 4A The method discussed in detail in the flowchart 500 in FIG. 1 can be modified by forming a first conductive layer on the second surface 304 of the polycrystalline substrate 300, forming a second conductive layer on the third surface 602 of the single crystal substrate 600, or forming only one of the first conductive layer and the second conductive layer using a sputtering technique, and then coupling the polycrystalline substrate 300 to the single crystal substrate 600 using both the first conductive layer and the second conductive layer or only one of the first conductive layer or the second conductive layer. The sputtering step can be performed in the embodiment of FIG. Figure 4A The method discussed in detail in the flowchart 500 of FIG. 5 is performed or implemented between the first step 502 and the second step 504. When the sputtering step is performed or implemented, the sputtering step is formed. Figure 2 An alternative embodiment of wafer 200 is fabricated by using bonding layer 202 as shown in FIG.

[0098] Although not shown, Figure 5CThe wafer 100 shown in FIG. 1 can be further processed and refined (e.g., forming additional layers (e.g., conductive and non-conductive) on the single crystal layer 110, singulation of the wafer 100, back grinding the wafer 100, etc.) for forming electronic devices and components, such as, for example, semiconductor packages or semiconductor devices. For example, a first electrode can be formed on a first side 102 of the wafer 100, and a second electrode can be formed on a second side 104 of the wafer 100, so that current can pass through the wafer 100, and the wafer 100 having a high resistivity allows the wafer 100 to be used in high power and high frequency applications.

[0099] At least one embodiment of the device of the present disclosure is summarized as including: a polycrystalline silicon carbide (SiC) base substrate, which includes: a first surface; a second surface opposite to the first surface; a resistivity greater than or equal to 1*10^5 ohm-centimeter (ohm-cm); and a grain size equal to or greater than 0.5 millimeters (mm); and a single crystal silicon carbide (SiC) substrate directly coupled to the first surface of the polycrystalline silicon carbide (SiC) base substrate.

[0100] The single crystal silicon carbide (SiC) substrate may have a thickness of at least one of: less than 1 micrometer (μm) and equal to 1 micrometer (μm).

[0101] The polycrystalline silicon carbide (SiC) base substrate may have a thickness greater than or equal to 300 micrometers (μm).

[0102] The polycrystalline silicon carbide (SiC) base substrate may have a thickness of at least one of: between 300 and 500 micrometers (μm), equal to 300 micrometers (μm), and equal to 500 micrometers (μm).

[0103] The resistivity of the polycrystalline silicon carbide (SiC) base substrate may be at least one of: between 1*10^5 ohm-cm and 1*10^12 ohm-cm, equal to 1*10^5 ohm-cm, and equal to 1*10^12 ohm-cm.

[0104] The resistivity of the polycrystalline silicon carbide (SiC) base substrate may be at least one of: between 1*10^5 ohm-cm and 1*10^9 ohm-cm, equal to 1*10^5 ohm-cm, and equal to 1*10^8 ohm-cm.

[0105] The first surface may have a thickness less than or equal to 5 angstroms. Roughness.

[0106] The grain size may be less than or equal to 5 millimeters (mm).

[0107] At least one embodiment of the device of the present disclosure is summarized as including: a polycrystalline silicon carbide (SiC) substrate, which includes: a first surface; a second surface opposite to the first surface; a resistivity greater than or equal to 1*10^5ohm-cm; and a grain size equal to or greater than 0.5 millimeters (mm).

[0108] The polycrystalline silicon carbide (SiC) substrate may have a thickness greater than or equal to 300 micrometers (μm).

[0109] The polycrystalline silicon carbide (SiC) substrate may have a thickness of at least one of: between 300 and 500 micrometers (μm), equal to 300 micrometers (μm), and equal to 500 micrometers (μm).

[0110] The resistivity of the polycrystalline silicon carbide (SiC) substrate may be at least one of: between 1*10^5 ohm-cm and 1*10^12 ohm-cm, equal to 1*10^5 ohm-cm, and equal to 1*10^12 ohm-cm.

[0111] The resistivity of the polycrystalline silicon carbide (SiC) substrate may be at least one of: between 1*10^5 ohm-cm and 1*10^9 ohm-cm, equal to 1*10^5 ohm-cm, and equal to 1*10^8 ohm-cm.

[0112] The first surface may have a thickness less than or equal to 5 angstroms. Roughness.

[0113] Most of a polycrystalline silicon carbide (SiC) substrate may be made of a 4H-SiC crystal structure.

[0114] Eighty percent (80%) of a polycrystalline silicon carbide (SiC) substrate may be made of a 4H-SiC crystal structure.

[0115] The grain size may be less than or equal to 5 millimeters (mm).

[0116] At least one embodiment of the method of the present disclosure is summarized as including: forming a polycrystalline silicon carbide (SiC) base substrate having a resistivity greater than 1*10^5 ohm-cm and a grain size equal to or greater than 0.5 millimeters (mm) on a supporting substrate; and removing the polycrystalline silicon carbide (SiC) base substrate from the supporting substrate.

[0117] Forming a polycrystalline silicon carbide (SiC) base substrate may include: raising the temperature within a chamber of an HTCVD (high temperature chemical vapor deposition) furnace containing a support substrate to at least one of: between 2000 and 2500 degrees Celsius (°C), equal to 2000 degrees Celsius (°C), and equal to 2500 degrees Celsius (°C); and introducing a silane source gas and an ethylene source gas into a chamber where the polycrystalline silicon carbide (SiC) base substrate is grown on the support substrate.

[0118] Forming a polycrystalline silicon carbide (SiC) base substrate may include: raising the temperature within a chamber of a CVD (chemical vapor deposition) furnace containing a support substrate to at least one of: between 1250 and 1350 degrees Celsius (°C), equal to 1250 degrees Celsius (°C), and equal to 1350 degrees Celsius (°C); and introducing a silane source gas and an ethylene source gas into a chamber where the polycrystalline silicon carbide (SiC) base substrate is grown on the support substrate.

[0119] The various embodiments described above can be combined to provide further embodiments.Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.

[0120] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which the claims are entitled. Therefore, the claims are not limited by the present disclosure.

Claims

1. A device comprising: Polycrystalline silicon carbide (SiC) base substrate, including: a first surface; a second surface opposite to the first surface; A resistivity greater than or equal to 1*10^5 ohm-cm; and A grain size equal to or greater than 0.5 millimeters (mm); and A single crystal silicon carbide (SiC) substrate is directly coupled to the first surface of the polycrystalline silicon carbide (SiC) base substrate. 2 . The device of claim 1 , wherein the single crystal silicon carbide (SiC) substrate has a thickness of at least one of: less than 1 micrometer (μm) and equal to 1 micrometer (μm). 3 . The device of claim 2 , wherein the polycrystalline silicon carbide (SiC) base substrate has a thickness greater than or equal to 300 micrometers (μm).

4. The device of claim 3, wherein the polycrystalline silicon carbide (SiC) base substrate has a thickness of at least one of: between 300 and 500 micrometers (μm), equal to 300 micrometers (μm), and equal to 500 micrometers (μm).

5. The device of claim 1, wherein the resistivity of the polycrystalline silicon carbide (SiC) base substrate is at least one of: between 1*10^5 ohm-cm and 1*10^12 ohm-cm, equal to 1*10^5 ohm-cm, and equal to 1*10^12 ohm-cm.

6. The device of claim 1, wherein the resistivity of the polycrystalline silicon carbide (SiC) base substrate is at least one of: between 1*10^5 ohm-cm and 1*10^9 ohm-cm, equal to 1*10^5 ohm-cm, and equal to 1*10^8 ohm-cm.

7. The device of claim 1, wherein the first surface has a thickness less than or equal to Roughness.

8. The device of claim 1, wherein the grain size is less than or equal to 5 millimeters (mm).

9. A device comprising: Polycrystalline silicon carbide (SiC) substrates, including: a first surface; a second surface opposite to the first surface; A resistivity greater than or equal to 1*10^5 ohm-cm; and A grain size equal to or greater than 0.5 millimeters (mm).

10. The device of claim 9, wherein the polycrystalline silicon carbide (SiC) substrate has a thickness greater than or equal to 300 micrometers (μm).

11. The device of claim 10, wherein the polycrystalline silicon carbide (SiC) substrate has a thickness of at least one of: between 300 and 500 micrometers (μm), equal to 300 micrometers (μm), and equal to 500 micrometers (μm).

12. The device of claim 9, wherein the resistivity of the polycrystalline silicon carbide (SiC) substrate is at least one of: between 1*10^5 ohm-cm and 1*10^12 ohm-cm, equal to 1*10^5 ohm-cm, and equal to 1*10^12 ohm-cm.

13. The device of claim 9, wherein the resistivity of the polycrystalline silicon carbide (SiC) substrate is at least one of: between 1*10^5 ohm-cm and 1*10^9 ohm-cm, equal to 1*10^5 ohm-cm, and equal to 1*10^8 ohm-cm.

14. The device of claim 9, wherein the first surface has a thickness less than or equal to Roughness.

15. The device of claim 9, wherein a majority of the polycrystalline silicon carbide (SiC) substrate is made of a 4H-SiC crystal structure.

16. The device of claim 15, wherein 80% of the polycrystalline silicon carbide (SiC) substrate is made of a 4H-SiC crystal structure.

17. The device of claim 9, wherein the grain size is less than or equal to 5 millimeters (mm).

18. A method comprising: forming a polycrystalline silicon carbide (SiC) base substrate having a resistivity greater than 1*10^5 ohm-cm and a grain size equal to or greater than 0.5 millimeters (mm) on a surface of a support substrate, the support substrate being a polycrystalline material and having a roughness less than or equal to 5 nanometers (nm); as well as The polycrystalline silicon carbide (SiC) base substrate is removed from a support substrate.

19. The method of claim 18, wherein forming the polycrystalline silicon carbide (SiC) base substrate comprises: Raising the temperature within a chamber of a high temperature chemical vapor deposition (HTCVD) furnace containing the support substrate to at least one of: between 2000 and 2500 degrees Celsius (°C), equal to 2000 degrees Celsius (°C), and equal to 2500 degrees Celsius (°C); and A silane source gas and an ethylene source gas are introduced into a chamber where the polycrystalline silicon carbide (SiC) base substrate is grown on a support substrate.

20. The method of claim 18, wherein forming the polycrystalline silicon carbide (SiC) base substrate comprises: raising the temperature within a chamber of a chemical vapor deposition (CVD) furnace containing the support substrate to at least one of: between 1250 and 1350 degrees Celsius (°C), equal to 1250 degrees Celsius (°C), and equal to 1350 degrees Celsius (°C); and A silane source gas and an ethylene source gas are introduced into a chamber where a polycrystalline silicon carbide (SiC) base substrate is grown on a support substrate.

21. The device of claim 1, wherein the polycrystalline silicon carbide (SiC) base substrate has a resistivity greater than or equal to 1*10^7 ohm-cm.

22. The device of claim 1, wherein the polycrystalline silicon carbide (SiC) base substrate has a resistivity greater than or equal to 1*10^8 ohm-cm.

23. The device of claim 1, wherein the polycrystalline silicon carbide (SiC) base substrate has a purity greater than or equal to 98%.

24. The device of claim 1, wherein the polycrystalline silicon carbide (SiC) base substrate has a density ranging from 3.14 grams / cm^3 (g / cm^3) to 3.21 grams / cm^3 (g / cm^3) or equal to the upper and lower ends of the range.

25. The device of claim 1, wherein the polycrystalline silicon carbide (SiC) base substrate has a density greater than or equal to 3.19 grams / cm^3 (g / cm^3).

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