Phase change material, phase change storage chip, storage device and electronic device

Abstract

The invention discloses a phase change material, a phase change storage chip, storage equipment and electronic equipment, and belongs to the technical field of semiconductor storage. The phase change material comprises a Ge-Sb-Te phase change base material, and a first doping element and a second doping element which are doped in the Ge-Sb-Te phase change base material. The first doping element comprises an Hf element, and the atomic percent of the first doping element is 1.5%-6.5%; the second doping element comprises at least one of an N element, a C element, an In element and a Ga element, and the atomic percent of the second doping element is 1.0%-5%. The phase-change material has high adhesive force, and enables a phase-change device to have the properties of large read window, long service life and the like.

Description

[0001] This application claims priority to Chinese patent application No. 202311290353.5 filed on September 28, 2023, with invention name “A Phase Change Memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of semiconductor storage technology, and in particular to phase change materials, phase change storage chips, storage devices and electronic devices. Background Art

[0003] Phase change memory (PCM) has the advantages of low latency and high fatigue life. It uses phase change materials as storage media. Phase change materials exhibit low resistivity in the crystalline state and high resistivity in the amorphous state. Phase change memory realizes data storage and erasure based on the resistance difference between the phase change materials in the crystalline and amorphous states.

[0004] In the related art, a phase change memory includes a plurality of phase change memory cells, each of which includes a phase change material layer and a barrier layer located on both sides of the phase change material layer. The sandwich structure composed of the phase change material layer and the barrier layer is subjected to large stress during processes such as annealing and etching, which may cause interface peeling between the phase change material layer and other functional layers such as the barrier layer. This will not only cause the phase change memory cell to be unable to be used normally, but also the material particles dropped due to the peeling will have an adverse effect on the equipment, etc.

[0005] It can be seen that it is necessary to improve the interface adhesion between the phase change material layer and other functional layers in the phase change memory.

[0006] Public Content

[0007] On the one hand, a phase change material is provided, which includes a Ge-Sb-Te phase change substrate, a first doping element and a second doping element doped in the Ge-Sb-Te phase change substrate; the first doping element includes an Hf element, and the atomic percentage of the first doping element in the phase change material is 1.5%-6.5%; the second doping element includes at least one of an N element, a C element, an In element, and a Ga element, and the atomic percentage of the second doping element in the phase change material is 1.0%-5%.

[0008] The phase change material provided by the embodiments of the present disclosure can enhance the adhesion force of the phase change material layer by further doping at least one of N element, C element, In element, and Ga element into the Ge-Sb-Te phase change substrate doped with Hf element, realize the tight combination between the phase change material layer and other adjacent functional layers, reduce the probability of interface peeling, increase the product yield of the phase change memory chip, and avoid pollution and interference to the production line and production equipment. In particular, by making the doping amount of Hf element be 1.5%-6.5%, and the doping amount of at least one of N element, C element, In element, and Ga element be 1.0%-5.0%, while realizing the improvement of the adhesion force of the phase change material layer, it is also beneficial to make the phase change device have a large read window and high lifetime.

[0009] In some possible implementation manners, the phase change material further includes: a third doping element, and the third doping element includes at least one of O element, Si element, B element, Sn element, Bi element, Cd element, Pb element, Zr element, Zn element, Cr element, Al element, Sc element, Y element, Ta element, Ti element, Er element, Lu element, Ho element, Tm element, Dy element, Tb element, Ca element, Nd element, Pr element, Yb element, Ca element, Ce element. By further introducing a specific content of the third doping element into the phase change material, the purpose of optimizing the comprehensive performance of the phase change memory device can also be achieved.

[0010] In some possible implementation manners, the chemical general formula of the Ge-Sb-Te phase change substrate is as follows: (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , where x is the atomic percentage and 0 < x < 1, a and b are parameters related to the atomic number ratio, 0 < a ≤ 1, 0 < b ≤ 3, and a = 1 and b = 3 do not exist simultaneously; or, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where x is the atomic percentage and 0 < x < 1, y, c, and d are parameters related to the atomic number ratio, y ≥ 2, 0 < c ≤ 1, 0 < d ≤ 1, and c = 1 and d = 1 do not exist simultaneously.

[0011] By making the chemical general formula of the Ge-Sb-Te phase change substrate as described above, the purpose is to ensure that the adhesion force of the phase change material layer is stronger than that of the phase change material layer corresponding to the Ge-Sb-Te phase change substrate.

[0012] On the other hand, a phase change material is provided. The phase change material includes a Ge-Sb-Te phase change substrate, a first doping element and a second doping element doped in the Ge-Sb-Te phase change substrate; the first doping element includes Hf element, and the atomic percentage of the first doping element in the phase change material is 1.5%-7%; the second doping element includes at least one of N element, C element, In element, and Ga element, and the atomic percentage of the second doping element in the phase change material is 1.0%-7%; the sum of the atomic percentages of the first doping element and the second doping element is greater than 4% and less than 10%.

[0013] For the phase change materials provided in the embodiments of the present disclosure, by further doping at least one of N element, C element, In element, and Ga element into the Ge-Sb-Te phase change substrate doped with Hf element, the adhesion of the phase change material layer can be enhanced, the tight combination between the phase change material layer and other adjacent functional layers can be realized, the interface peeling probability can be reduced, the product yield of the phase change memory chip can be increased, and the pollution and interference to the production line and production equipment can be avoided. In particular, by making the doping amount of Hf element be 1.5%-7%, and making the doping amount of at least one of N element, C element, In element, and Ga element be 1.0%-7%, and the sum of the atomic percentages of the two doping elements is greater than 4% and less than 10%, while improving the adhesion of the phase change material layer, it is also beneficial to make the phase change device have a large read window, high life, and cycle stability.

[0014] In some possible implementation manners, the phase change material further includes: a third doping element, and the third doping element includes at least one of O element, Si element, B element, Sn element, Bi element, Cd element, Pb element, Zr element, Zn element, Cr element, Al element, Sc element, Y element, Ta element, Ti element, Er element, Lu element, Ho element, Tm element, Dy element, Tb element, Ca element, Nd element, Pr element, Yb element, Ca element, Ce element. By further introducing a specific content of the third doping element into the phase change material, the purpose of optimizing the comprehensive performance of the phase change memory device can also be achieved.

[0015] In some possible implementation manners, the chemical general formula of the Ge-Sb-Te phase change substrate is as follows: (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , where x is the atomic percentage and 0 < x < 1, a and b are parameters related to the atomic number ratio, 0 < a ≤ 1, 0 < b ≤ 3, and a = 1 and b = 3 do not exist simultaneously; or, (GeTe 1-c ) x (Sby Te 1-d ) 1-x , where x is the atomic percentage and 0 < x < 1, and y, c, and d are parameters related to the ratio of the number of atoms, y ≥ 2, 0 < c ≤ 1, 0 < d ≤ 1, and c = 1 and d = 1 do not exist simultaneously.

[0016] By making the chemical general formula of the Ge-Sb-Te phase change substrate as described above, the purpose is to ensure that the adhesion force of the phase change material layer is stronger than that of the phase change material layer corresponding to the Ge-Sb-Te phase change substrate.

[0017] Furthermore, the chemical general formula of the Ge-Sb-Te phase change substrate is as follows: (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , and 0.2 < x ≤ 0.4, or, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , and 0.2 < x ≤ 0.4.

[0018] By further defining the chemical general formula of the Ge-Sb-Te phase change substrate as shown above, the embodiments of the present disclosure facilitate making the phase change device have both low latency and high lifespan, and ensure that the phase change material layer has high adhesion.

[0019] On the other hand, a phase change memory chip is provided. The phase change memory chip includes: a plurality of phase change memory cells, and the phase change memory cells include a phase change material layer, and the phase change material layer is prepared from the phase change material described in any of the above.

[0020] For the phase change memory chip provided by the embodiments of the present disclosure, since its phase change material layer is prepared from the phase change material provided by the embodiments of the present disclosure, the phase change memory chip has all the advantages of the phase change material provided by the embodiments of the present disclosure.

[0021] In some possible implementation manners, the phase change memory cell further includes an adhesion layer, the adhesion layer is stacked on at least one surface of the phase change material layer, and the adhesion layer is used to increase the adhesion force between the phase change material layer and an adjacent functional layer.

[0022] For the phase change memory chip provided by the embodiments of the present disclosure, not only is the phase change material itself improved, but also the structure of the phase change memory chip is improved by adding an adhesion layer to further enhance the adhesion force between the phase change material layer and an adjacent functional layer, significantly reducing the probability of interface peeling, thereby increasing the product yield of the phase change memory cell, and also avoiding pollution and interference to the production line.

[0023] In some possible implementations, the adhesion layer raw material used for the adhesion layer includes at least one of a nitride of a target element and a carbide of a target element;

[0024] The target element is selected from at least one of W element, Ti element, Ge element, Ta element, Hf element, In element, Ga element, Al element, Cu element, Co element, and Mo element.

[0025] In some possible implementations, the adhesion layer raw material used for the adhesion layer includes a Ge-Sb-Te phase change material doped with a fourth doping element, and the adhesion layer raw material is different from the phase change material;

[0026] The fourth doping element is selected from at least one of Hf, N, C, In and Ga, and the atomic percentage of the fourth doping element in the raw material of the adhesion layer is 0.01%-20%.

[0027] In some possible implementations, the phase-change memory unit further includes a barrier layer, and the adhesion layer is located between the phase-change material layer and the barrier layer to increase adhesion between the phase-change material layer and the barrier layer.

[0028] In some possible implementations, the barrier layer material used for the barrier layer includes at least one of a single substance, a nitride, and a carbide of W element, Ti element, Ge element, Ta element, Hf element, In element, Ga element, Al element, Cu element, Co element, and Mo element.

[0029] In some possible implementations, the phase change memory unit further includes an electrode layer, and the adhesion layer is located between the phase change material layer and the electrode layer to increase adhesion between the phase change material layer and the electrode layer.

[0030] In some possible implementations, the phase-change memory chip further includes: a plurality of gate tube units, wherein the gate tube units are arranged in series with the phase-change memory units.

[0031] In some possible implementations, the gate tube unit includes a gate layer, and the gate tube material used in the gate layer includes at least one of an S-series gate tube material, a Se-series gate tube material, and a Te-series gate tube material.

[0032] In some possible implementations, the gate tube material also includes a fifth doping element, and the fifth doping element is selected from at least one of B element, Al element, Ga element, In element, C element, Si element, Ge element, Sn element, N element, P element, As element, Sb element, Bi element, O element, Au element, Hf element, Pd element, Cu element, Co element, Ag element, Pt element, Sc element, Ti element, and Ta element.

[0033] On the other hand, an embodiment of the present disclosure provides a storage device, which includes a controller and at least one phase-change memory chip as described above, wherein the controller is used to store data in the phase-change memory chip.

[0034] The storage device (also referred to as a memory) may be configured to store various types of data, which may be contact data, phone book data, messages, pictures, videos, etc., or may be instructional data.

[0035] On the other hand, an embodiment of the present disclosure provides an electronic device, which includes a processor and the above-mentioned storage device, and the processor is used to store data generated by the electronic device in the storage device.

[0036] The electronic devices include but are not limited to: computers, mobile phones, music playing devices, digital broadcasting devices, message sending and receiving devices, game control devices, medical devices, fitness equipment, personal digital assistants, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a schematic diagram of the interface peeling process between the phase change material layer and the barrier layer in the related art;

[0038] Figure 2 is the mean square displacement diagram of Hf element in Ge-Sb-Te phase change matrix;

[0039] Figure 3 is the mean square displacement diagram of In element in Ge-Sb-Te phase change substrate;

[0040] Figure 4 is the mean square displacement diagram of Ga element in Ge-Sb-Te phase change matrix;

[0041] Figure 5 A schematic diagram of the structure of an exemplary phase change memory unit provided in an embodiment of the present disclosure;

[0042] Figure 6 A schematic structural diagram of another exemplary phase change memory unit provided by an embodiment of the present disclosure;

[0043] Figure 7A schematic structural diagram of another exemplary phase change memory unit provided in an embodiment of the present disclosure;

[0044] Figure 8 A schematic structural diagram of another exemplary phase change memory unit provided in an embodiment of the present disclosure;

[0045] Fig. 9 A schematic diagram of the structure of an exemplary phase change memory chip provided in an embodiment of the present disclosure;

[0046] Fig.10 A schematic structural diagram of another exemplary phase-change memory chip provided in an embodiment of the present disclosure;

[0047] Fig.11 A schematic structural diagram of another exemplary phase change memory chip provided in an embodiment of the present disclosure;

[0048] Fig.12 A schematic structural diagram of another exemplary phase-change memory chip provided in an embodiment of the present disclosure;

[0049] Fig.13 An array diagram of an exemplary phase change memory chip provided by an embodiment of the present disclosure;

[0050] Fig.14 A schematic diagram of the first preparation step of the phase change memory chip provided in Example 1;

[0051] Fig.15 A schematic diagram of the second preparation step of the phase change memory chip provided in Example 1;

[0052] Fig.16 A schematic diagram of the third preparation step of the phase change memory chip provided in Example 1;

[0053] Fig.17 A schematic diagram of the fourth preparation step of the phase change memory chip provided in Example 1;

[0054] Fig.18 A schematic diagram of the fifth preparation step of the phase change memory chip provided in Example 1;

[0055] Fig.19 A schematic diagram of the sixth preparation step of the phase change memory chip provided in Example 1;

[0056] Fig. 20 A schematic diagram of the seventh preparation step of the phase change memory chip provided in Example 1;

[0057] Fig.21 A schematic diagram of the eighth preparation step of the phase change memory chip provided in Example 1;

[0058] Fig. 22A schematic diagram of the ninth preparation step of the phase change memory chip provided in Example 1;

[0059] Fig.23 A schematic diagram of the tenth preparation step of the phase change memory chip provided in Example 1;

[0060] Fig.24 A schematic diagram of the relationship between the lifespan and SET state resistance of the phase change memory chip provided in an embodiment of the present disclosure.

[0061] The reference numerals represent:

[0062] 001, storage subunit; 002, word line; 003, bit line; 004, substrate; 005, mask layer; 100, phase change material layer; 200, adhesion layer; 300, barrier layer; 400, insulating layer; 401, first insulating layer; 402, second insulating layer; 403, third insulating layer; 404, fourth insulating layer; 501, top electrode; 502, bottom electrode; 503, middle electrode; 600, selection layer; 701, first trench; 702, second trench; 703, third trench. DETAILED DESCRIPTION

[0063] In the description of the embodiments of the present disclosure, the terms "vertical direction", "horizontal direction", "top", "bottom", "upper", "lower" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the embodiments of the present disclosure and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the embodiments of the present disclosure. When the product is placed in different postures, the orientation may change, for example, "top" and "bottom" may be interchangeable.

[0064] Phase change memory (PCM), also known as phase change memory chip, is a solid-state semiconductor non-volatile memory that uses phase change material as a storage medium. The phase change material can undergo reversible transformation between crystalline and amorphous states. By utilizing the difference in high resistivity and low resistivity of the phase change material in the amorphous and crystalline states, the phase change memory can store data "0" and "1".

[0065] The working process of phase change memory includes: erase operation (SET) process and write operation (RESET) process. The SET process refers to: applying a wide and weak electric pulse to heat the phase change material, so that the temperature of the phase change material rises to between the crystallization temperature and the melting temperature, the phase change material crystallizes into an ordered state, and forms a crystalline state with low resistivity to achieve the storage of data "0". The RESET process refers to applying a narrow and strong electric pulse to heat the phase change material, so that the temperature of the phase change material rises above the melting temperature and melts into a disordered state, and then undergoes a rapid cooling quenching process, the phase change material directly enters the amorphous state with higher resistivity from the molten state to achieve the storage of data "1".

[0066] In the related art, a phase change memory includes a plurality of phase change memory units, such as the attached Figure 1 As shown, the phase change memory unit includes a phase change material layer 100 and a barrier layer 300 located on both sides of the phase change material layer 100. The sandwich structure formed by the phase change material layer 100 and the barrier layer 300 undergoes many processes such as annealing, patterning, etching, and protective layer covering during the preparation of the phase change memory, which causes it to be subjected to large stress, which may cause peeling between the interface of the phase change material layer 100 and other functional layers such as the barrier layer 300 (see Figure 1 ), which will not only cause the phase change memory unit in the peeling area to be unable to be used normally (for example, the interface between the phase change material layer and the barrier layer peels off, making it impossible to combine). In addition, the granular materials that fall due to peeling will also have an adverse effect on production equipment, etc. (for example, polluting the production line, interfering with the normal operation of the equipment, etc.). It can be seen that it is necessary to improve the interface adhesion between the phase change material layer and other functional layers.

[0067] The first embodiment of the present disclosure provides a phase change material, which includes a Ge-Sb-Te phase change substrate and a first doping element and a second doping element doped in the Ge-Sb-Te phase change substrate. The first doping element includes an Hf element, and the first doping element accounts for 1.5%-6.5% of the atomic percentage of the phase change material; the second doping element includes at least one of an N element, a C element, an In element, and a Ga element, and the second doping element accounts for 1.0%-5.0% of the atomic percentage of the phase change material.

[0068] Exemplarily, some examples of the atomic percentage of the first doping element Hf in the phase change material include but are not limited to: 1.5%, 1.6%, 1.7%, 1.8%, 1.9%, 2%, 2.1%, 2.2%, 2.3%, 2.4%, 2.5%, 2.6%, 2.7%, 2.8%, 2.9%, 3%, 3.1%, 3.2%, 3.3%, 3.4%, 3.5%, 3.6%, 3.7%, 3.8%, 3.9%, 4%, 4.1%, 4.2%, 4.3%, 4.4%, 4.5%, 4.6%, 4.7%,

[0069] 4.8%, 4.9%, 5%, 5.1%, 5.2%, 5.3%, 5.4%, 5.5%, 5.6%, 5.7%, 5.8%, 5.9%, 6%, 6.1%, 6.2%, 6.3%, 6.4%, 6.5%, etc.

[0070] For example, some examples of the atomic percentage of the second doping element in the phase change material include, but are not limited to: 1%, 1.1%, 1.2%, 1.3%, 1.4%, 1.5%, 1.6%, 1.7%, 1.8%, 1.9%, 2%, 2.1%, 2.2%, 2.3%, 2.4%, 2.5%, 2.6%, 2.7%,

[0071] 2.8%, 2.9%, 3%, 3.1%, 3.2%, 3.3%, 3.4%, 3.5%, 3.6%, 3.7%, 3.8%, 3.9%, 4%, 4.1%, 4.2%, 4.3%, 4.4%, 4.5%, 4.6%, 4.7%, 4.8%, 4.9%, 5%, etc.

[0072] The second doping element can be one of N element, C element, In element, and Ga element. For example, the second doping element is N element, C element, In element, or Ga element. Alternatively, the second doping element can also be a combination of any two elements among N element, C element, In element, and Ga element, a combination of any three elements, or include these four elements simultaneously.

[0073] The phase change material provided in the embodiment of the present disclosure can enhance the adhesion between the phase change material layer and other functional layers by doping Hf element and at least one of N element, C element, In element and Ga element into the Ge-Sb-Te phase change substrate. The adhesion enhancement principles are described below.

[0074] (1) When the second doping element is N or C, N or C can form a bond with Hf, thereby introducing HfN or HfC into the phase change material. The introduced HfN or HfC does not match the lattice constant of the Ge-Sb-Te phase change substrate (for example, the lattice constant of the HfN compound is 0.452 nm, and the lattice constant of the HfC compound is 0.463 nm). They do not match the lattice constant of the Ge-Sb-Te phase change substrate (for example, the lattice constant of Ge1Sb4Te6 is 0.612 nm). Thus, additional grain boundaries are introduced, the grain size of the phase change material is reduced, the roughness of the phase change material is reduced, and the contact area and bonding force between the phase change material layer and other functional layers are increased, thereby achieving the effect of increasing the adhesion of the phase change material layer.

[0075] Further research found that when the atomic percentage of N element or C element is 1.0%-5.0%, it can further ensure that the phase change device has a large read window. The relevant principle is as follows: for the operation of 1S1R type phase change memory chip, the threshold voltage of opening the gate tube unit + crystalline phase change memory unit is VtS, and the threshold voltage of opening the gate tube unit + amorphous phase change memory unit is VtR. The read window is VtR-VtS. It can be seen that the size of the read window is proportional to the difference between the high resistance and the low resistance of the phase change material layer.

[0076] On the one hand, HfN compounds and HfC compounds can improve the high resistance of phase change materials, which is beneficial to increase the read window of phase change devices. On the other hand, if Hf is doped into the Ge-Sb-Te phase change substrate alone, Hf will come into contact with O or other substances with oxidizing properties during the process preparation, making it easy to be oxidized to form HfOx. The resistivity of HfOx is greater than that of the phase change material, which will cause the low resistance of the phase change material to increase to a certain extent, thereby reducing the read window of the phase change device. However, the melting points of HfN compounds and HfC compounds are 3310℃ and 3900℃, respectively. They have high chemical stability and are not easy to react with other elements such as O, which reduces the oxidation probability of the Hf element, thereby ensuring that the phase change device has a large read window.

[0077] However, the influence of N element or C element on the read window of the phase change device is related to the doping amount thereof in the phase change material. The embodiments disclosed in the present invention have confirmed through relevant experiments that when the atomic percentage of Hf element is greater than 6.5% (not within the specified range of 1.5% to 6.5%) and the atomic percentage of N element or C element is greater than 5.0% (not within the specified range of 1% to 5%), the read window of the phase change device will deteriorate.

[0078] For example, the above-mentioned “related experiments” are as follows:

[0079] The disclosed embodiment provides a phase change material, wherein the Hf element and the N element are doped in the Ge-Sb-Te phase change substrate, wherein the atomic percentage ratio of each element in the chemical formula of the Ge-Sb-Te phase change substrate satisfies Ge:Sb:Te=1:4:6 (which can be abbreviated as Ge1Sb4Te6, GeSbTe146 or GST146). When other parameters remain quantitative, by changing the doping amount of the Hf element and the N element, the low resistance corresponding to the crystalline state and the high resistance corresponding to the amorphous state of the phase change material layer are tested respectively. For relevant test parameters and test results, please refer to Table 1.

[0080] Table 1

[0081]

[0082] Combining the phase change material 1 and the phase change material 3 in Table 1, it can be known that by further doping the Ge-Sb-Te phase change substrate doped with the Hf element with the N element, the high resistance of the phase change material layer can be increased, thereby facilitating an increase in the read window size.

[0083] Combined with the phase change material 2 in Table 1, it can be seen that when the doping concentration of the Hf element is 6.5% and the doping concentration of the N element is 5%, its crystallization temperature is increased by 35°C compared with the phase change material 1 (undoped N) in Table 1, and its low resistance is increased by more than 100 times compared with the solution of the phase change material 4 (Hf2% + N2%) in Table 1, and its low resistance is increased by more than 5 times compared with the phase change material 3 (Hf4% + N4%) in Table 1, which to a certain extent causes the phenomenon of read window degradation. It can be seen that when the atomic percentage of the Hf element is greater than 6.5%, and the atomic percentage of the N element or the C element is greater than 5.0%, the crystallization temperature will be further increased. In this way, under certain post-process device process heat treatment conditions, the low resistance of the phase change material layer will increase, thereby causing the read window of the phase change device to decrease. It can be seen that the embodiment of the present disclosure has an important significance for ensuring that the phase change device has a large read window by making the atomic percentage of the Hf element 1.5% to 6.5% and the atomic percentage of the N element or the C element greater than 1% to 5%.

[0084] In addition, as mentioned above, the melting points of HfN compounds and HfC compounds are 3310°C and 3900°C respectively, and they have high chemical stability.

[0085] It can be seen that the high melting points of HfN and HfC compounds enable them to remain stably during the melting process (about 600°C) of the phase change material RESET.

[0086] Moreover, the stable HfN compound and HfC compound clusters hinder the element segregation and phase separation in the GeSbTe phase change substrate, which is beneficial to the phase change device to have a long lifespan.

[0087] (2) When the second doping element is In or Ga, In and Ga easily form metal-metal bonds with metal elements such as Hf, thereby enhancing the bonding force between the phase change material layer and other functional layers. This is because In and Ga have a low melting point (<200°C) relative to other solid metal elements at room temperature, which gives them strong diffusion capabilities. As a result, In and Ga are conducive to forming metal-metal bonds with metal elements in other functional layers, and then forming alloys, thereby enhancing the adhesion between the phase change material and other functional layers containing metal elements. For example, the "other functional layers" referred to here may be the barrier layer or adhesion layer involved in the phase change memory chip described below.

[0088] The present disclosure calculates the mean square displacement of Hf, In and Ga in the Ge-Sb-Te phase change matrix based on the first principle. Figure 2 -Attached Figure 4 As shown, the mean square displacement of In and Ga elements in the Ge-Sb-Te phase change substrate system is large, which indicates that under ambient temperature conditions, In and Ga elements are more likely to diffuse, making it easier for them to form alloys with metal elements in other functional layers.

[0089] For example, when other functional layers contain metal elements such as W, Ti, Ge, Ta, Hf, In, Ga, Al, Cu, Co, and Mo, In and Ga elements can easily combine with these metal elements to form alloys, forming metal-metal bonds, thereby improving the adhesion between the phase change material and other functional layers, thereby increasing the adhesion of the phase change material layer.

[0090] The embodiments of the present disclosure also conducted relevant tests on the adhesion between the phase change material layer and the W electrode corresponding to some phase change materials doped with In element and those not doped with In element, see Table 2, these phase change materials are: (a) phase change material Hf-GeSbTe, which refers to a single Hf element doped in a Ge1Sb4Te6 phase change substrate, and the atomic percentage of Hf is 5%; (b) phase change material In-GeSbTe, which refers to a single In element doped in a Ge1Sb4Te6 phase change substrate, and the atomic percentage of In is 3%; (c) phase change material InHf-GeSbTe, which refers to a Ge1Sb4Te6 phase change substrate doped with both Hf element and In element, and the atomic percentages of Hf and In are 3% and 2%, respectively.

[0091] Table 2

[0092] Test subjects Adhesion (au) Hf-GeSbTe / W electrode 1 InHf-GeSbTe / W electrode 1.32 In-GeSbTe / W electrode 1.2

[0093] It can be seen from Table 2 that, on the basis that the atomic percentage of the In element satisfies the specified range of 1% to 5%, compared with the Hf-GeSbTe phase change material layer doped with only Hf and the In-GeSbTe phase change material layer doped with only In, the InHf-GeSbTe phase change material layer doped with both Hf and In elements has a higher adhesion to the W electrode, thereby achieving an improvement in the interface adhesion, thereby achieving the effect of increasing the adhesion of the phase change material layer.

[0094] Further research found that when In or Ga and Hf are co-doped into the GeSbTe phase change substrate, the phase change device can also be ensured to have a high lifespan. To support this conclusion, the embodiments of the present disclosure also tested the bonding strength of Hf, In, Ga, Ge, Sb, and Te, as well as their own bonding strength, where the unit of bonding strength is kJ / mol. See Table 3 for the test results.

[0095] Table 3

[0096]

[0097] As shown in Table 3, Hf, In and Ga can form covalent bonds with themselves, and each of them with Ge, Sb and Te with similar strength. Therefore, if In or Ga is doped into Ge-Sb-Te phase change substrate alone, In or Ga and Ge-Sb-Te phase change substrate easily form solid solution, and after electrical operation, it is impossible to prevent the element segregation of Ge, Sb and Te, resulting in a low life span of phase change device. The phase change material provided by the embodiment of the present disclosure introduces In and / or Ga elements into Ge-Sb-Te phase change substrate, and also introduces Hf element. The formed HfIn alloy or HfGa alloy has a high melting point, and HfIn alloy or HfGa alloy can be stably retained in the melting process (about 600°C) of phase change material RESET, and the above-mentioned stable HfIn and HfGa alloy clusters also hinder the element segregation and phase separation of Ge-Sb-Te phase change substrate, which is conducive to making the phase change device have a high life span characteristic. Of course, as mentioned above, when other functional layers adjacent to the phase change material layer contain Hf elements, HfIn alloy or HfGa alloy is also very beneficial for enhancing the adhesion of the phase change material layer.

[0098] In summary, the phase change material provided by the embodiments of the present disclosure can enhance the adhesion of the phase change material layer by further doping at least one of N element, C element, In element, and Ga element into the Ge-Sb-Te phase change base material doped with Hf element, realize the tight combination between the phase change material layer and other adjacent functional layers, reduce the probability of interface peeling, increase the product yield of the phase change memory chip, and avoid pollution and interference to the production line and production equipment. In particular, by making the doping amount of Hf element be 1.5%-6.5%, and making the doping amount of at least one of N element, C element, In element, and Ga element be 1.0%-5.0%, while realizing the improvement of the adhesion of the phase change material layer, it is also beneficial to make the phase change device have a large read window and high lifespan.

[0099] In some implementation manners, the phase change material provided by the embodiments of the present disclosure further includes: a third doping element, and the third doping element includes: at least one of O element, Si element, B element, Sn element, Bi element, Cd element, Pb element, Zr element, Zn element, Cr element, Al element, Sc element, Y element, Ta element, Ti element, Er element, Lu element, Ho element, Tm element, Dy element, Tb element, Ca element, Nd element, Pr element, Yb element, Ca element, Ce element. By further introducing a specific content of the third doping element into the phase change material, the purpose of optimizing the comprehensive performance of the phase change memory device can also be achieved. Among them, the atomic percentage of the third doping element in the phase change material is 0.01%-10%.

[0100] For the Ge-Sb-Te phase change base material, the chemical general formula of its Ge-Sb-Te compound can be shown as any of the following chemical general formulas:

[0101] Chemical general formula one, (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , where x is the atomic percentage and 0 < x < 1, a and b are parameters related to the atomic number ratio, 0 < a ≤ 1, 0 < b ≤ 3, and a = 1 and b = 3 do not exist simultaneously. For example, for the compound GeTe 1-a , it means that the atomic number ratio of Ge element to Te element is 1:1 - a, and for Sb2Te 3-b , it means that the atomic number ratio of Sb element to Te element is 2:3 - b. Of course, it is not excluded that in the compound GeTe 1-a , the atomic numbers of Ge element and Te element are 1 and 1 - a respectively, and in the compound Sb2Te 3-b , the atomic numbers of Sb element and Te element are 2 and 3 - b respectively.

[0102] Chemical formula II, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where x is the atomic percentage and 0 < x < 1, y, c, and d are parameters related to the atomic number ratio, y ≥ 2, 0 < c ≤ 1, 0 < d ≤ 1, and c = 1 and d = 1 do not exist simultaneously. For example, for the compound GeTe 1-c , it means that the atomic number ratio of Ge element to Te element is 1:1 - c. For Sb y Te 1-d , it means that the atomic number ratio of Sb element to Te element is y:1 - d. Of course, it is not excluded that in the compound GeTe 1-c , the atomic numbers of Ge element and Te element are 1 and 1 - c respectively, and in the compound Sb y Te 1-d , the atomic numbers of Sb element and Te element are y and 1 - d respectively.

[0103] Exemplarily, the values of a include but are not limited to: 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1, etc.

[0104] The values of b include but are not limited to: 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.9, 3, etc.

[0105] The values of y include but are not limited to: 2, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.9, 3, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6, 3.7, 3.8, 3.9, 4, 4.1, 4.2, 4.3, 4.4, 4.5, 4.6, 4.7, 4.8, 4.9, 5, 6, 7, 8, 9, 10, etc.

[0106] The values of c include but are not limited to: 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1, etc.

[0107] The values of d include, but are not limited to: 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1, etc.

[0108] In the embodiments of the present disclosure, by making the chemical general formula of the Ge-Sb-Te phase change substrate as described above, the purpose is to ensure that the adhesion force of the phase change material layer obtained based on the Ge-Sb-Te phase change substrate of the embodiments of the present disclosure is stronger than that of the phase change material layers obtained from other Ge-Sb-Te phase change substrates. This is because GeTe, Sb2Te3, and Sb y Te (y≥2) are all stable compounds with stable chemical component ratios. Considering that Te single crystal is a typical two-dimensional material, after Te-Te bonding, a layered structure is formed, and the interlayer is bonded by van der Waals forces, resulting in poor adhesion. At the same time, the melting point of Sb2Te3 (620°C) is higher than that of Te single crystal (450°C). At the high temperature during the phase change process, Te is more likely to precipitate to form Te single crystal two-dimensional material, resulting in poor adhesion. In the embodiments of the present disclosure, making a, b, c, and d all greater than 0 can make the Ge-Sb-Te phase change substrate in a state of lacking Te compared with the above-mentioned stable compounds. By appropriately reducing the content of Te element, it is ensured that the adhesion force of the phase change material layer is stronger than that of the phase change material layer corresponding to the Ge-Sb-Te phase change substrate.

[0109] To support the above conclusion, the embodiments of the present disclosure conducted relevant adhesion tests. The test results show that the adhesion force between the Te-deficient Ge-Sb-Te phase change substrate and the W electrode is 1.14 a.u., and the adhesion force between the non-Te-deficient Ge-Sb-Te phase change substrate and the W electrode is 1 a.u. It can be seen that the Te-deficient Ge-Sb-Te phase change substrate has stronger adhesion force than the non-Te-deficient Ge-Sb-Te phase change substrate.

[0110] In some examples, for the first chemical general formula of the Ge-Sb-Te phase change substrate, (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , where 0.2 < x ≤ 0.4. For the second chemical general formula of the Ge-Sb-Te phase change substrate, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where 0.2 < x ≤ 0.4.

[0111] Exemplarily, the value of x includes, but is not limited to, 0.22, 0.23, 0.24, 0.25, 0.26, 0.27, 0.28, 0.29, 0.3, 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, 0.37, 0.38, 0.39, 0.4, etc.

[0112] By making the chemical formula of the Ge-Sb-Te phase change substrate as shown above, on the basis of ensuring that the adhesion of the phase change material layer is strong enough, it is also beneficial to accelerate the delay of the phase change device and improve the life of the phase change device.

[0113] The phase change material provided in the embodiments of the present disclosure exists in the form of, but is not limited to, alloy, compound, combination of a single substance and a compound, combination of a single substance and an alloy, etc. The phase change material layer is prepared according to the various forms of the phase change material.

[0114] For example, one form of phase change material is a combination of Ge-Sb-Te ternary compound / alloy, a single substance or compound corresponding to the Hf element, and a single substance or compound corresponding to at least one of the N element, the C element, the In element, and the Ga element. In this case, according to the atomic percentage of each element in the phase change material, a corresponding amount of each of the above-mentioned single substances or compounds is provided according to the ratio. The three types of materials, Ge-Sb-Te ternary compound / alloy, Hf element single substance or compound, and at least one of the N element, the C element, the In element, and the Ga element, do not need to be mixed, so that they are independent of each other for standby use. Alternatively, these three types of materials can also be mixed and formed into a phase change material in the form of a compound or alloy by smelting.

[0115] Of course, it is not excluded that the phase change material can also exist in the following forms: a combination of Ge element, Sb element, Te element, Hf element and at least one corresponding element among N element, C element, In element and Ga element. According to the atomic percentage of each element in the phase change material, the corresponding amount of each element is provided according to the ratio. These specific amounts of elements do not need to be mixed and can be independent of each other. Alternatively, these specific amounts of elements can also be mixed and formed into a phase change material in the form of a compound or alloy by smelting.

[0116] The second embodiment of the present disclosure also provides a phase change material, which includes a Ge-Sb-Te phase change substrate and a first doping element and a second doping element doped in the Ge-Sb-Te phase change substrate. The first doping element includes an Hf element, and the first doping element accounts for 1.5%-7% of the atomic percentage of the phase change material; the second doping element includes at least one of an N element, a C element, an In element, and a Ga element, and the second doping element accounts for 1.0%-7% of the atomic percentage of the phase change material; and the sum of the atomic percentages of the first doping element and the second doping element is greater than 4% and less than 10%.

[0117] Exemplarily, some examples of the atomic percentage of the first doping element Hf in the phase change material include, but are not limited to: 1.5%, 1.6%, 1.7%, 1.8%, 1.9%, 2%, 2.1%, 2.2%, 2.3%, 2.4%, 2.5%, 2.6%, 2.7%, 2.8%, 2.9%, 3%, 3.1%, 3.2%, 3.3%, 3.4%, 3.5%, 3.6%, 3.7%, 3.8%. , 3.9%, 4%, 4.1%, 4.2%, 4.3%, 4.4%, 4.5%, 4.6%, 4.7%, 4.8%, 4.9%, 5%, 5.1%, 5.2%, 5.3%, 5.4%, 5.5%, 5.6%, 5.7%, 5.8%, 5.9%, 6%, 6.1%, 6.2%, 6.3%, 6.4%, 6.5%, 6.6%, 6.7%, 6.8%, 6.9%, etc.

[0119] Illustratively, some examples of the atomic percentage of the second doping element in the phase change material include, but are not limited to: 1%, 1.1%, 1.2%, 1.3%, 1.4%, 1.5%, 1.6%, 1.7%, 1.8%, 1.9%, 2%, 2.1%, 2.2%, 2.3%, 2.4%, 2.5%, 2.6%, 2.7%, 2.8%, 2.9%, 3%, 3.1%, 3.2%, 3.3%, 3.4%, 3.5%, 3.6%, 3.7%, 3.8%, 3.9%, 4.1%, 4.2%, 4.3%, 4.4%, 4.5%, 4.6%, 4.7%, 4.8%, 4.9%, 5.1%, 5.2%, 5.3%, 5.4%, 5.5%, 5.6%, 5.7%, 5.8%, 5.9%, 6.1%, 6.2%, 6.3%, 6.4%, 6.5%, 6.6%, 6.7%, 6.8%, 6.9%, 7. %, 3.7%, 3.8%, 3.9%, 4%, 4.1%, 4.2%, 4.3%, 4.4%, 4.5%, 4.6%, 4.7%, 4.8%, 4.9%, 5%, 5.1%, 5.2%, 5.3%, 5.4%, 5.5%, 5.6%, 5.7%, 5.8%, 5.9%, 6%, 6.1%, 6.2%, 6.3%, 6.4%, 6.5%, 6.6%, 6.7%, 6.8%, 6.9%, etc.

[0123] The sum of the atomic percentages of the first doping element and the second doping element may be 4.5%, 5%, 5.5%, 6%, 6.5%, 7%, 7.5%, 8%, 8.5%, 9%, 9.5%, etc.

[0124] The second doping element can be one of N element, C element, In element, and Ga element. For example, the second doping element is N element, C element, In element, or Ga element. Alternatively, the second doping element can also be a combination of any two elements among N element, C element, In element, and Ga element, a combination of any three elements, or include these four elements simultaneously.

[0125] Regarding the relevant principle of the second doping element being N, C, In or Ga to enhance the adhesion of the phase change material layer, reference may be made to the relevant principle description of the phase change material involved in the first embodiment above, which will not be repeated here.

[0126] Compared with the phase change material involved in the first embodiment, the atomic percentage of N element, C element, In element or Ga element in the phase change material involved in the second embodiment is increased (atomic percentage is 1.0%-7%).

[0127] In this type of phase change material layer, the doping concentration of the first doping element and the second doping element each needs to be controlled within 7%, so as to ensure that the phase change material layer has strong adhesion while also ensuring that the phase change device has a high and stable high resistance, thereby improving the read window and cycle stability of the phase change device, and ensuring that the phase change device has a high and stable low resistance, thereby improving the life and cycle stability of the phase change device.

[0128] The reasons are as follows:

[0129] Research has found that when the atomic percentages of the first doping element and the second doping element are each greater than 7%, side effects will occur, resulting in degradation of the read window, lifespan and other performance of the phase change device.

[0130] Taking the second doping element as N element as an example and combining the data in Table 5 in Example 5, it can be seen that when the atomic percentage of Hf element is too high (greater than 7%), the high resistance of the phase change device becomes low, resulting in a smaller read window, and the high resistance is unstable during the cycle, and segregation is prone to occur, and then the phase change device is prone to fatigue failure. When the atomic percentage of N element is too high (greater than 7%), the low resistance of the phase change device increases abnormally and is unstable during the cycle, and keeps decreasing during the fatigue process, which may be related to the fact that thermoelectric accumulation is more likely to occur during operation, leading to segregation.

[0131] As shown in Table 5, when the atomic percentage of the Hf element is 8% (exceeding the upper limit of 7%), the high resistance of the phase change memory chip will become low and unstable during the cycle. When the atomic percentage of the N element is 8% (exceeding the upper limit of 7%), the low resistance of the phase change memory chip will become high, but it will be unstable during the cycle. Therefore, the embodiment of the present disclosure makes the atomic percentages of the Hf element and the N element less than or equal to 7% respectively, thereby ensuring that the phase change device has a higher and stable high resistance, and ensuring that the phase change device has a higher and stable low resistance.

[0132] In addition, in this type of phase change material, the sum of the atomic percentages of the first doping element and the second doping element also needs to be greater than 4% and less than 10%. In this way, while ensuring that the phase change material layer has strong adhesion, the phase change device can also have a long life and cycle stability.

[0133] Here are the reasons:

[0134] The study found that for this type of phase change material, the life of the phase change device is more related to the doping concentration of Hf and the second doping element. In the performance analysis of the phase change device, it was found that the low resistance of the phase change device is proportional to its ultimate fatigue life, such as Fig.24 As shown in the figure, within a certain range, the higher the low resistance of the phase change device, the better the fatigue characteristics of the phase change device. The low resistance of the phase change device is mainly determined by the low resistance and crystallization temperature of the phase change material layer. Fig.24 The values ​​of the horizontal and vertical coordinates are obtained by normalizing and taking logarithms.

[0135] Taking N as the second doping element as an example and combining the data in Table 1, it can be seen that when the doping concentrations of Hf and N elements increase, the low resistance and crystallization temperature of the phase change material layer will increase accordingly (see phase change material 3 and phase change material 4 in Table 1). As a result, the low resistance of the phase change device will also increase, thereby obtaining a longer lifespan of the phase change device.

[0136] Therefore, in order to ensure a longer life of the phase change device, it is necessary to make the low resistance of the phase change material layer as high as possible while maintaining a certain read window. The phase change material 4 in Table 1 has an atomic percentage of 2% of the Hf element and an atomic percentage of 2% of the N element, and the phase change material 1 in Table 1 has an atomic percentage of 4% of the Hf element and an atomic percentage of 0% of the N element. The low resistance of the phase change material layer corresponding to both is about 400 ohms, which is much less than 1k ohms, and the sum of the atomic percentages of the Hf element and the N element in both is 4%. Therefore, the embodiment of the present disclosure limits the sum of the atomic percentages of the Hf element and the N element to be greater than 4%, that is, the sum of the atomic percentages of the first doping element and the second doping element is greater than 4%, which is very necessary for giving the phase change device a high life characteristic.

[0137] The sum of the doping concentrations of the first doping element and the second doping element is not the higher the better. Studies have shown that when the sum of the doping concentrations of the first doping element and the second doping element is greater than 10%, side effects will occur, resulting in instability in the cycle process of the phase change device, including: making the low resistance of the phase change device abnormally high and unstable during the cycle, specifically, continuously decreasing during the cycle, which may be due to the fact that the phase change material layer is more susceptible to thermoelectric accumulation and segregation during operation. Still taking the second doping element as N element as an example and combining the data in Table 5 in Example 5, it can be seen that when the atomic percentage of the Hf element is 6.5% and the atomic percentage of the N element is 5%, since the sum of the atomic percentages of the two is greater than 10%, the low resistance increases abnormally and is unstable during the cycle. Therefore, it is expected that the sum of the atomic percentages of the Hf element and the N element is less than 10%.

[0138] In summary, the phase change material provided in the embodiment of the present disclosure can enhance the adhesion of the phase change material layer by further doping at least one of the N element, C element, In element, and Ga element into the Ge-Sb-Te phase change substrate doped with the Hf element, thereby achieving close bonding between the phase change material layer and other adjacent functional layers, reducing the probability of interface peeling, increasing the product yield of the phase change memory chip, and avoiding pollution and interference to the production line and production equipment. In particular, by making the doping amount of the Hf element 1.5%-7%, and making the doping amount of at least one of the N element, C element, In element, and Ga element 1.0%-7%, and the sum of the atomic percentages of the two doping elements greater than 4% and less than 10%, while achieving the improvement of the adhesion of the phase change material layer, it is also beneficial for the phase change device to have a large read window, a high lifespan, and cycle stability.

[0139] In some implementations, the phase change material provided by the embodiments of the present disclosure further includes: a third doping element, and the third doping element includes: at least one of O element, Si element, B element, Sn element, Bi element, Cd element, Pb element, Zr element, Zn element, Cr element, Al element, Sc element, Y element, Ta element, Ti element, Er element, Lu element, Ho element, Tm element, Dy element, Tb element, Ca element, Nd element, Pr element, Yb element, Ca element, and Ce element. By further introducing a specific content of the third doping element into the phase change material, the purpose of optimizing the comprehensive performance of the phase change memory device can also be achieved. Among them, the third doping element accounts for 0.01%-10% of the atomic percentage of the phase change material.

[0140] For the Ge-Sb-Te phase change substrate, the chemical formula of the Ge-Sb-Te compound can be shown as any of the following chemical formulas:

[0141] Chemical formula 1, (GeTe 1-a )x (Sb2Te 3-b ) 1-x , where x is the atomic percentage and 0 < x < 1, a and b are parameters related to the atomic number ratio, 0 < a ≤ 1, 0 < b ≤ 3, and a = 1 and b = 3 do not exist simultaneously.

[0142] Chemical general formula two, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where x is the atomic percentage and 0 < x < 1, y, c, and d are parameters related to the atomic number ratio, y ≥ 2, 0 < c ≤ 1, 0 < d ≤ 1, and c = 1 and d = 1 do not exist simultaneously.

[0143] Regarding the chemical general formula one and chemical general formula two of the Ge - Sb - Te phase change substrate involved above, for the exemplary values of each parameter and the related explanations, reference can be made to the relevant descriptions in the phase change material involved in the above first embodiment, and details will not be repeated here.

[0144] In the embodiments of the present disclosure, by making the chemical general formula of the Ge - Sb - Te phase change substrate as described above, the purpose is to ensure that the adhesion force of the phase change material layer obtained based on the Ge - Sb - Te phase change substrate of the embodiments of the present disclosure is stronger than that of the phase change material layers obtained from other Ge - Sb - Te phase change substrates. This is because GeTe, Sb2Te3, Sb y Te (y ≥ 2) are all stable compounds with stable chemical component ratios. Considering that Te single crystal is a typical two - dimensional material, after Te - Te bonding, a layered structure is formed, and the interlayer is bonded by van der Waals forces, resulting in poor adhesion. At the same time, the melting point of Sb2Te3 (620 °C) is higher than that of Te single crystal (450 °C). At the high temperature during the phase change process, Te is more likely to precipitate to form Te single crystal two - dimensional material, leading to poor adhesion. In the embodiments of the present disclosure, making a, b, c, and d all greater than 0 can make the Ge - Sb - Te phase change substrate in a state of lacking Te compared with the above - mentioned stable compounds. By appropriately reducing the content of Te element, it is ensured that the adhesion force of the phase change material layer is strong enough.

[0145] In addition, regarding the relevant adhesion force test of the above Ge - Sb - Te phase change substrate, reference can still be made to the relevant descriptions in the phase change material involved in the above first embodiment, and details will not be repeated here.

[0146] In some examples, for the chemical general formula one of the Ge - Sb - Te phase change substrate, (GeTe 1-a ) x (Sb2Te 3-b ) 1-x, where 0.2 < x ≤ 0.4, for the second general chemical formula of the Ge-Sb-Te phase change substrate, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where 0.2 < x ≤ 0.4.

[0147] Exemplarily, the values of x include but are not limited to: 0.22, 0.23, 0.24, 0.25, 0.26, 0.27, 0.28, 0.29, 0.3, 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, 0.37, 0.38, 0.39, 0.4, etc.

[0148] For the first or second general chemical formula of the Ge-Sb-Te phase change substrate corresponding to 0.2 < x ≤ 0.4, another expression of the corresponding general chemical formula can also be as follows: Ge x Sb y Te 1-x-y , where both x and y represent the atomic percentages of the corresponding elements, and 6% < x < 15%, 35% < y < 45% (alternatively, Ge x Sb y Te 100-x-y , where both x and y are the mass fractions of the corresponding atoms, 6 < x < 15, 35 < y < 45).

[0149] For example, on the basis of satisfying the above general chemical formula, in the Ge-Sb-Te phase change substrate, the ratio of the atomic percentages of Ge element, Sb element and Te element includes but is not limited to: 1:4:5, 1:4:6, 1:4:7, etc., and the corresponding GeSbTe compounds are respectively abbreviated as GeSbTe145 (or Ge1Sb4Te5, GST145), GeSbTe146 (or Ge1Sb4Te6, GST146), GeSbTe147 (or Ge1Sb4Te7, GST147).

[0150] By making the general chemical formula of the Ge-Sb-Te phase change substrate as shown above, not only is the adhesion force of the phase change material layer ensured to be strong enough, but also it is beneficial to reduce the time delay of the phase change device and improve the lifespan of the phase change device.

[0151] The disclosed embodiments have conducted relevant tests on the effects of the contents of Ge and Sb in the Ge-Sb-Te phase change substrate on adhesion, time delay and lifespan. The test results show that the atomic percentage of the Sb element is an important factor in determining the speed of the phase change device. The crystallization temperature of the Sb element is low and the growth rate is fast. Therefore, the atomic percentage of the Sb element is positively correlated with the SET performance of the phase change device. In theory, the higher the atomic percentage of the Sb element, the shorter the time delay of the phase change device.

[0152] Experiments have shown that when the atomic percentage of Sb in the Ge-Sb-Te phase change substrate is greater than 35% (corresponding to x≤0.4 in the above stoichiometric ratio), the delay of the phase change device can reach less than 100ns due to the low crystallization temperature and fast growth rate of Sb single substance. However, the higher the atomic percentage of Sb, the better. When the atomic percentage of Sb in the Ge-Sb-Te phase change substrate exceeds 45% (corresponding to x>0.2 in the above stoichiometric ratio), the amount of Sb and Te forming a stable compound is relatively reduced, and the Sb single substance is relatively excessive and has poor stability, resulting in a certain reduction in the life of the phase change device. It can be seen that by limiting the atomic percentage of Sb to greater than 35% and less than 45%, it is beneficial for the phase change device to have both low delay and high life.

[0153] For the Ge element, experiments have confirmed that when the atomic percentage of the Ge element is greater than 15%, its concentration is too high, which will cause the delay of the phase change device to slow down to a certain extent. When the atomic percentage of Ge is less than 6% (corresponding to satisfying x>0.2 in the above stoichiometric ratio), its concentration is too low, which will reduce the adhesion of the phase change material layer, resulting in excessive difficulty in mass production process tuning. It can be seen that by limiting the atomic percentage of Ge to greater than 6% and less than 15%, it is beneficial to ensure that the phase change material layer has high adhesion and the phase change device has low delay.

[0154] In addition, for the existence form of the phase change material provided in the second embodiment, reference can still be made to the relevant description of the phase change material involved in the first embodiment, and no further details will be given here.

[0155] It can be seen that the embodiments of the present disclosure achieve balanced optimization of the performance of the phase change memory chip by identifying the corresponding coupling relationship between different elements in the phase change material and key device performance (speed, life, window, adhesion), and adjusting the stoichiometric ratio of each element, thereby ensuring that the overall performance of the phase change memory chip is more excellent.

[0156] The embodiment of the present disclosure further provides a phase change memory chip, which includes a plurality of phase change memory units. The phase change memory unit includes a phase change material layer 100. The phase change material layer 100 is prepared from any of the above-mentioned phase change materials.

[0157] The phase change memory chip can also be called a phase change memory. The phase change memory chip provided in the embodiment of the present disclosure is based on the fact that its phase change material layer 100 is prepared from the phase change material provided in the embodiment of the present disclosure, so that the phase change memory chip has all the advantages of the phase change material provided in the embodiment of the present disclosure.

[0158] The phase change memory unit is disposed on the substrate 004. In some examples, such as the attached Figure 5 As shown, the phase change memory unit includes, in addition to the above-mentioned phase change material layer 100, a top electrode 501, a bottom electrode 502, and an insulating layer 400. From bottom to top, the substrate 004, the bottom electrode 502, the phase change material layer 100, and the top electrode 501 are stacked in sequence, and the insulating layer 400 at least covers the outer side of the phase change material layer 100.

[0159] In some other examples, the phase change memory unit includes, in addition to the above-mentioned phase change material layer 100, as shown in the attached Figure 6 As shown, it also includes a top electrode 501, a bottom electrode 502, an insulating layer 400, and a barrier layer 300. From bottom to top, the substrate 004, the bottom electrode 502, the barrier layer 300, the phase change material layer 100, the barrier layer 300, and the top electrode 501 are sequentially stacked, and the insulating layer 400 at least covers the outer sides of the phase change material layer 100 and the barrier layer 300.

[0160] Exemplarily, the barrier layer material used for the barrier layer 300 includes: single substances of W element, Ti element, Ge element, Ta element, Hf element, In element, Ga element, Al element, Cu element, Co element, Mo element, nitrides of the above elements, and at least one of carbides of the above elements.

[0161] Taking the second doping element in the phase change material layer 100 as N element or C element as an example, the N element or C element can form a bond with the above-mentioned metal element in the barrier layer 300 to form a non-metal-metal ion bond, thereby enhancing the bonding force between the adhesion layer 200 and the barrier layer 300 and reducing the probability of interface peeling between the two during the process.

[0162] Furthermore, as attached Figure 7 and attached Figure 8 As shown, the phase change memory unit provided by the embodiment of the present disclosure further includes an adhesion layer 200, which is stacked on at least one surface of the phase change material layer 100, and the adhesion layer 200 is used to increase the adhesion between the phase change material layer 100 and the adjacent functional layer.

[0163] For example, the adhesion layer 200 may be disposed on the surface of the phase change material layer 100 facing the top electrode 501, or on the surface of the phase change material layer 100 facing the bottom electrode 502, or respectively on the two opposite surfaces of the phase change material layer 100.

[0164] By adding the adhesion layer 200 on at least one surface of the phase change material layer 100 , the adhesion between the phase change material layer 100 and the adjacent functional layer is increased, wherein the adjacent functional layer may be the barrier layer 300 or the electrode layer.

[0165] It can be seen that the phase change memory chip provided in the embodiment of the present disclosure not only improves the phase change material itself, but also improves the structure of the phase change memory chip to add an adhesion layer 200, so as to further enhance the adhesion between the phase change material layer 100 and the adjacent functional layer, significantly reduce the probability of interface peeling, thereby increasing the product yield of the phase change memory unit, and also avoiding pollution and interference to the production line.

[0166] The adhesion layer 200 is prepared using an adhesion layer raw material. In some implementations, the adhesion layer raw material includes at least one of a nitride of a target element and a carbide of a target element; wherein the target element is selected from at least one of W, Ti, Ge, Ta, Hf, In, Ga, Al, Cu, Co, and Mo. For example, when the target element is W, the adhesion layer raw material may be tungsten nitride or tungsten carbide.

[0167] When the second doping element in the phase change material layer 100 is N element or C element, N element or C element can form a non-metal-metal ion bond with the target element in the adhesion layer 200, thereby improving the bonding force between the adhesion layer 200 and the phase change material layer 100, enhancing the interface adhesion, and reducing the probability of interface peeling between the two during the process.

[0168] When the second doping element in the phase change material layer 100 is In element or Ga element, In element or Ga element can combine with the target element in the adhesion layer 200 to form an alloy, forming a metal-metal bond, thereby improving the bonding force between the adhesion layer 200 and the phase change material layer 100, enhancing the interface adhesion, and reducing the probability of interface peeling between the two during the process.

[0169] It can be seen that by using the above-mentioned adhesion layer raw materials, the interface bonding ability and bonding force between the phase change material layer and the adhesion layer can be achieved, preventing the phase change material layer from falling off from the interface of the barrier layer and causing a decrease in device yield.

[0170] In order to verify that the interface adhesion of the phase change memory chip with the adhesion layer is stronger, the embodiments of the present disclosure provide the following types of phase change materials for related adhesion test experiments, and these phase change materials are as follows: (d) phase change material HfGST, which refers to the single doping of Hf element in Ge1Sb4Te6 phase change substrate, and the atomic percentage of Hf is 3%; (e) phase change material NHfGST, which refers to the simultaneous doping of Hf element and N element in Ge1Sb4Te6 phase change substrate, and the atomic percentages of Hf and N are 3% and 2% respectively. The adhesion between the phase change material layer corresponding to these phase change materials and the W electrode was tested, and the test results are shown in Table 2.

[0171] The adhesion between the phase change material layers corresponding to these phase change materials and the adhesion layer of the W electrode and the W2N material was tested respectively. The test results are shown in Table 4.

[0172] Table 4

[0173] Test subjects Adhesion force limit (N) Median adhesion force (N) NHfGST / W electrode 2118 1408 HfGST / W electrode 1847 1272 <![CDATA[NHfGST / Adhesion layer W2N]]> 2234 1435

[0174] It can be seen from Table 4 that, on the basis that the atomic percentages of the Hf element and the N element satisfy the respective specified atomic percentage ranges, it can be seen that, compared with the phase change material layer doped with a simple single Hf element, the adhesion between the phase change material layer doped with both the Hf element and the N element and the W electrode in the present application is significantly greater than the adhesion between the phase change material layer not doped with the N element and the W electrode, while the adhesion between the phase change material layer doped with both the Hf element and the N element and the W electrode is slightly smaller than the adhesion between the phase change material layer doped with both the Hf element and the N element and the adhesion layer W2N. It can be seen that by further adding an adhesion layer, the interfacial adhesion of the phase change material layer can be further improved.

[0175] In other implementations, the adhesion layer raw material includes: a Ge-Sb-Te phase change material doped with a fourth doping element, and the adhesion layer raw material is different from the phase change material used in the phase change material layer. The fourth doping element is selected from at least one of Hf, N, C, In, and Ga, and the fourth doping element accounts for 0.01%-20% of the adhesion layer raw material by atomic percentage, and can further be 0.01%-10%.

[0176] The chemical formula of the Ge-Sb-Te phase change material involved can be shown as follows: (GeTe 1-a ) x (Sb2Te 3-b ) 1-x, where \(0 \lt x \lt 1\), \(0 \lt a \leq 1\), \(0 \lt b \leq 3\), and \(a = 1\) and \(b = 3\) do not exist simultaneously (here, \(x\), \(a\), and \(b\) are parameters representing atomic percentages). Alternatively, the chemical general formula of the Ge-Sb-Te phase change material can also be shown as follows: (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where \(0 \lt x \lt 1\), \(y \geq 2\), \(0 \lt c \leq 1\), \(0 \lt d \leq 1\), and \(c = 1\) and \(d = 1\) do not exist simultaneously (here, \(x\), \(y\), \(c\), and \(d\) are parameters representing atomic percentages).

[0177] For example, the simplified formulas of some applicable adhesion layer raw materials can be shown as follows: NHfGeSbTe, CHfGeSbTe, InHfGeSbTe, GaHfGeSbTe, HfGeSbTe, NGeSbTe, CGeSbTe, InGeSbTe, GaGeSbTe, etc.

[0178] The doping amount of the fourth doping element in the Ge-Sb-Te phase change material is within the above range, so that the Ge-Sb-Te phase change material doped with the fourth doping element is different from the phase change material in the phase change material layer 100, mainly playing an interface adhesion role.

[0179] As described above, the adhesion layer 200 is located between the phase change material layer 100 and the adjacent functional layer, where the adjacent functional layer can be the barrier layer 300 or an electrode layer (including at least one of the top electrode 501 and the bottom electrode 502).

[0180] In one scheme, the phase change memory cell includes a barrier layer 300, and the adhesion layer 200 is located between the phase change material layer 100 and the barrier layer 300, for increasing the adhesion force between the phase change material layer 100 and the barrier layer 300.

[0181] The barrier layer 300 plays a role in preventing the elements in the phase change material layer 100 from diffusing to the electrode layer. The adhesion layer 200 is located between the phase change material layer 100 and the barrier layer 300, effectively preventing peeling between the phase change material layer 100 and the barrier layer 300.

[0182] In some examples, as shown Figure 7 , the number of the barrier layers 300 is two, and the two barrier layers 300 are respectively located on the opposite sides of the phase change material layer 100. In this case, the number of the adhesion layers 200 can also be two, where one adhesion layer 200 is located between the first surface of the phase change material layer 100 and one barrier layer 300, and the other adhesion layer 200 is located between the second surface of the phase change material layer 100 and the other barrier layer 300.

[0183] Exemplarily, the barrier layer material used for the barrier layer 300 includes at least one of W, Ti, Ge, Ta, Hf, In, Ga, Al, Cu, Co, and Mo, nitrides of the above elements, and carbides of the above elements. Of course, the barrier layer material is different from the adhesion layer material.

[0184] When the second doping element in the phase change material layer 100 is N element or C element, N element or C element can form a non-metal-metal ion bond with the metal element in the barrier layer 300, thereby improving the bonding force between the barrier layer 300 and the phase change material layer 100, enhancing the interface adhesion, and reducing the probability of interface peeling between the two during the process.

[0185] When the second doping element in the phase change material layer 100 is In element or Ga element, In element or Ga element can combine with the metal element in the barrier layer 300 to form an alloy, forming a metal-metal bond, thereby improving the bonding force between the barrier layer 300 and the phase change material layer 100, enhancing the interface adhesion, and reducing the probability of interface peeling between the two during the process.

[0186] In view of the above solution, the phase change memory cell may further include a top electrode 501, a bottom electrode 502, and an insulating layer 400 in addition to the above phase change material layer 100, the adhesion layer 200, and the barrier layer 300. Figure 7 As shown, along the bottom-up direction, the substrate 004, the bottom electrode 502, the barrier layer 300, the adhesion layer 200, the phase change material layer 100, the adhesion layer 200, the barrier layer 300, and the top electrode 501 are stacked in sequence, and the insulating layer 400 at least covers the outer sides of the phase change material layer 100, the adhesion layer 200 and the barrier layer 300.

[0187] In some examples, the thickness of the blocking layer 300 and the adhesion layer 200 are independently 1nm to 8nm, including but not limited to: 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, etc. For example, the thickness of the blocking layer 300 and the adhesion layer 200 can both be 2nm.

[0188] Another solution is that the phase change memory unit includes an electrode layer, and the adhesion layer 200 is located between the phase change material layer 100 and the electrode layer to increase the adhesion between the phase change material layer 100 and the electrode layer. The adhesion layer 200 is located between the phase change material layer 100 and the corresponding electrode layer to effectively prevent peeling between the phase change material layer 100 and the electrode layer.

[0189] According to the above solution, the phase change memory unit may include a top electrode 501, a bottom electrode 502, and an insulating layer 400 in addition to the above phase change material layer 100 and the adhesion layer 200. Figure 8 As shown, along the bottom-up direction, the substrate 004 , the bottom electrode 502 , the adhesion layer 200 , the phase change material layer 100 , the adhesion layer 200 , and the top electrode 501 are stacked in sequence, and the insulating layer 400 at least covers the outer sides of the phase change material layer 100 and the adhesion layer 200 .

[0190] For the phase-change memory cell involved above, the structure of the phase-change memory cell includes but is not limited to the following: a confined structure, a T-shaped structure, a U-shaped groove structure, an L-shaped structure, and the like.

[0191] In some implementations, the phase change memory chip provided by the embodiment of the present disclosure further includes: a plurality of gate tube units, which are arranged in series with the phase change memory unit. The gate tube units are used as switching devices of the phase change memory unit, thereby effectively suppressing the leakage current generated during the operation of the phase change memory chip.

[0192] See also Fig. 9 The gate tube unit includes a gate layer 600, and the gate tube material used in the gate layer 600 includes at least one of an S-series gate tube material, a Se-series gate tube material, and a Te-series gate tube material. The above-mentioned S-series gate tube material, Se-series gate tube material, and Te-series gate tube material can all be some gate materials currently known or on sale, and examples are not given here one by one. The above-mentioned gate tube material can be a binary compound, a ternary compound, or other multi-component compound containing more elements.

[0193] Further, the gate tube material further includes a fifth doping element, and the fifth doping element is selected from at least one of B element, Al element, Ga element, In element, C element, Si element, Ge element, Sn element, N element, P element, As element, Sb element, Bi element, O element, Au element, Hf element, Pd element, Cu element, Co element, Ag element, Pt element, Sc element, Ti element, and Ta element. The atomic percentage of the fifth doping element in the gate tube material may be 0.01%-20%, and further may be 0.01%-10%.

[0194] In some examples, the fifth doping element includes at least one of B element, Al element, Ga element, In element, C element, Si element, Ge element, Sn element, N element, P element, As element, Sb element, Bi element, and O element, and also includes at least one of Au element, Hf element, Pd element, Cu element, Co element, Ag element, Pt element, Sc element, Ti element, and Ta element.

[0195] By doping the fifth doping element into the gate tube material, the gate layer 600 can have the advantages of low leakage current, strong thermal stability, long cycle life, etc.

[0196] The thickness of the gating layer 600 may be 10 nm to 50 nm, for example, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, etc. The thickness of the gating layer 600 may be determined according to the electrical properties of the phase change memory unit connected in series therewith to ensure that the gating tube unit maintains the desired switching characteristics.

[0197] In some examples, such as the attached Fig. 9 -Attached Fig.12 As shown, the gate tube unit may only include the gate layer 600 , and the gate layer 600 is integrated into the phase change memory unit, and the gate layer 600 and the phase change material layer 100 in the phase change memory unit are connected in series via the intermediate electrode 503 .

[0198] In some examples, the gate tube unit and the corresponding phase change memory unit are independent of each other (not shown in the figure). For this example, the gate tube unit may include a substrate, a bottom electrode, a gate layer and a top electrode stacked from bottom to top, and the outer side of the gate layer is also covered with an insulating layer. The electrode layer of the gate tube unit and the electrode layer of the corresponding phase change memory unit can be connected in series by means of a wire (such as a copper interconnection line).

[0199] The phase change memory chip provided in the embodiments of the present disclosure can be prepared by thin film deposition process, photolithography process, etching process, etc., wherein multiple functional layers in the phase change memory chip, such as the phase change material layer 100, the adhesion layer 200, the barrier layer 300, the gating layer 600, etc., can all be prepared by thin film deposition process.

[0200] Exemplarily, some applicable thin film deposition processes include, but are not limited to: atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), etc. For further example, the above-mentioned functional layers can be prepared by using plasma enhanced chemical vapor deposition (PECVD) process, magnetron sputtering process, electron beam evaporation process, etc.

[0201] Magnetron sputtering is a type of physical vapor deposition process, which has the advantages of easy control, large coating area, strong adhesion, and a wide range of preparation objects. Exemplarily, the embodiments of the present disclosure may use a magnetron sputtering process to form each functional layer. The sputtering gas used in the magnetron sputtering process includes, but is not limited to, at least one of argon Ar, krypton Kr, xenon Xe, neon Ne, and nitrogen N2.

[0202] The substrate 004 involved in the above-mentioned phase change memory unit and some gate tube units includes, but is not limited to: silicon dioxide substrate, silicon carbide substrate, silicon wafer substrate, sapphire substrate, diamond substrate, etc.

[0203] The electrodes (top electrode 501, bottom electrode 502 and middle electrode 503) involved in the above-mentioned phase change memory unit and some gate tube units, their electrode materials include but are not limited to: titanium tungsten TiW (such as Ti3W7), tungsten W, aluminum Al, titanium nitride TiN, titanium Ti, tantalum Ta, silver Ag, platinum Pt, carbon C, copper Cu, ruthenium Ru, gold Au, cobalt Co, chromium Cr, nickel Ni, iridium Ir, palladium Pd, rhodium Rh, etc.

[0204] The electrode materials mentioned above may be deposited into corresponding electrode layers by using a physical vapor deposition (PVD) process (eg magnetron sputtering).

[0205] The insulating layer 400 involved in the above-mentioned phase change memory unit and some gate tube units is used to provide insulation and thermal isolation, and the insulating and heat-insulating materials used include but are not limited to: silicon nitride Si3N4, silicon carbide SiC, silicon dioxide SiO2, etc. The above-mentioned insulating and heat-insulating materials can be deposited into the insulating layer 400 by a chemical vapor deposition (CVD) process, such as a plasma enhanced chemical vapor deposition (PECVD) process.

[0206] In some examples, such as the attached Fig. 9 -Attached Fig.12 As shown, the insulating layer 400 includes a first insulating layer 401 and a second insulating layer 402. The first insulating layer 401 at least covers the outer surface of the phase change material layer 100, and further, can also cover the outer surfaces of the barrier layer 300, the adhesion layer 200, and the top electrode 501. The second insulating layer 402 covers the outer surface of the first insulating layer 401.

[0207] For example, the first insulating layer 401 is silicon nitride Si3N4, silicon carbide SiC, etc., and its thickness is greater than 1nm, for example, 2nm to 3nm. The second insulating layer 402 is a compound formed by Si element and at least one of N element, C element, and O element, for example, at least one of silicon nitride Si3N4, silicon carbide SiC, and silicon dioxide SiO2, and its thickness is greater than 1nm, for example, 2nm to 3nm.

[0208] By arranging the first insulating layer 401 and the second insulating layer 402 from the inside to the outside of the phase change material layer 100 , the purpose of optimizing insulation isolation and thermal isolation is achieved.

[0209] In some examples, such as the attached Fig. 9 -Attached Fig.12 As shown, the insulating layer includes a third insulating layer 403 and a fourth insulating layer 404. The third insulating layer 403 at least covers the outer surface of the gate layer 600, and further, can also cover the outer surfaces of the middle electrode 503 and the bottom electrode 502. The fourth insulating layer 404 covers the outer surface of the third insulating layer 403.

[0210] For example, the third insulating layer 403 is silicon nitride Si3N4, silicon carbide SiC, etc., and its thickness is greater than 1nm, for example, 2nm to 3nm. The fourth insulating layer 404 is a compound formed by Si element and at least one of N element, C element, and O element, for example, at least one of silicon nitride Si3N4, silicon carbide SiC, and silicon dioxide SiO2, and its thickness is greater than 1nm.

[0211] For example, for the fourth insulating layer 404 of the single-layer structure, its thickness can be 2nm to 3nm. In some examples, the fourth insulating layer 404 can also be set as a two-layer structure that is sequentially covered from the inside to the outside, and the two layers of the structure are made of different materials. For the fourth insulating layer 404 of the double-layer structure, its thickness can be 2nm to 15nm.

[0212] By disposing the third insulating layer 403 and the fourth insulating layer 404 from the inside to the outside of the gating layer 600, the purpose of optimizing insulation isolation and thermal isolation is achieved.

[0213] The structural forms of the phase change memory chip provided by the embodiments of the present disclosure include but are not limited to: 1S1R (One Selector One Resistor) structure, 1SnR (One Selector n Resistor) structure, etc. For the phase change memory chip with 1S1R structure, one gate tube unit controls one phase change memory unit, and for the phase change memory chip with 1SNR structure, one gate tube unit controls N phase change memory units simultaneously.

[0214] In some examples, the structure of the phase change memory chip involved in the embodiments of the present disclosure may be a 1S1R structure, and each group of series-connected gate tube units and phase change memory units is defined as a storage subunit 001, as shown in the attached Fig.13 As shown, the 1S1R phase-change memory chip includes a plurality of memory sub-units 001, a plurality of word lines 002, and a plurality of bit lines 003. Of course, the phase-change memory chip also includes a peripheral control circuit.

[0215] A plurality of storage sub-units 001 constitute a phase change storage array, wherein the plurality of storage sub-units 001 are arranged in an array, a plurality of word lines 002 are distributed in parallel and spaced apart, and each word line 002 can extend inwardly along a first direction, a plurality of bit lines 003 are distributed in parallel and spaced apart, and each bit line 003 can extend inwardly along a second direction, and an angle is formed between the first direction and the second direction, and the angle is greater than 0° and less than or equal to 90°.

[0216] For example, the angle between the first direction and the second direction is equal to 90°, so that the multiple word lines 002 are arranged in rows, the multiple bit lines 003 are arranged in columns, and the multiple rows of word lines 002 and the multiple rows of bit lines 003 cooperate to form an array compatible with the multiple storage sub-units 001. Each storage sub-unit 001 is located in a matrix sub-unit composed of word lines 002 and bit lines 003 (that is, located in the overlapping area of ​​word lines 002 and bit lines 003), each storage sub-unit 001 is connected to the bit line 003 of the corresponding column through its top electrode 501, and each storage sub-unit 001 is connected to the word line 002 of the corresponding row through its bottom electrode 502.

[0217] When used, multiple word lines 002 arranged in rows are connected to row selection circuit A1, which can be driven by row voltage control circuit B1; multiple bit lines 003 arranged in columns are connected to column selection circuit A2, which can be driven by column voltage control circuit B2. The read / write circuit C receives the command of the processor and is connected to the row voltage control circuit B1 or the column voltage control circuit B2 respectively. In this way, the read / write circuit C receives the command of the processor and controls the row selection circuit A1 or the column selection circuit A2 through the row voltage control circuit B1 or the column voltage control circuit B2, thereby performing read / write operations on the phase change memory cell in the selected memory sub-unit 001.

[0218] In the process of reading and writing phase change memory cells, the gate transistor unit is used as a switch device. When the storage sub-unit 001 is not selected by the row selection circuit A1 and the column selection circuit A2 at the same time, its corresponding gate transistor unit is in a closed state to avoid the influence of leakage current on other units.

[0219] The phase change memory chip provided by the embodiment of the present disclosure can be three-dimensionally stacked to form an N-layer structure (N≥1) in the vertical direction, so that the storage density of the three-dimensional stacked memory reaches 4F. 2 *N, where F is the semiconductor process feature size.

[0220] In the following, the structures of some phase change memory chips provided by the embodiments of the present disclosure are exemplarily described in combination with a solution in which the phase change memory chip includes a gating layer 600 and the gating layer 600 is integrated into a phase change memory unit.

[0221] As an example, see the attached Fig. 9 , which illustrates a 1S1R type phase change memory chip, which is arranged on a substrate 004. The 1S1R type phase change memory chip includes multiple storage sub-units 001, multiple word lines 002 and multiple bit lines 003. The multiple storage sub-units 001 are arranged in an array, the multiple word lines 002 are arranged in rows, and the multiple bit lines 003 are arranged in columns. Each storage sub-unit 001 is connected to the bit line 003 of the corresponding column through its top electrode 501, and is connected to the word line 002 of the corresponding row through its bottom electrode 502.

[0222] Each storage sub-unit 001 includes a bottom electrode 502, a gating layer 600, an intermediate electrode 503, a blocking layer 300, a phase change material layer 100, a blocking layer 300 and a top electrode 501 which are stacked in sequence from bottom to top, and adjacent storage sub-units 001 are isolated by an insulating layer. Specifically, for each storage sub-unit 001, the outer surfaces of the blocking layer 300, the phase change material layer 100, the blocking layer 300 and the top electrode 501 are sequentially coated with a first insulating layer 401 and a second insulating layer 402 from the inside to the outside, and the outer surfaces of the bottom electrode 502, the gating layer 600 and the intermediate electrode 503 are sequentially coated with a third insulating layer 403 and a fourth insulating layer 404 from the inside to the outside.

[0223] In the phase-change memory chip provided in Example 1, the phase-change material layer 100 adopts the improved phase-change material provided in the above embodiment of the present disclosure, which can effectively improve the adhesion between the phase-change material layer 100 and the barrier layer 300.

[0224] As Example 2, see Attachment Fig.10 , which illustrates a 1S1R type phase change memory chip, which is arranged on a substrate 004. The 1S1R type phase change memory chip includes multiple storage sub-units 001, multiple word lines 002 and multiple bit lines 003. The multiple storage sub-units 001 are arranged in an array, the multiple word lines 002 are arranged in rows, and the multiple bit lines 003 are arranged in columns. Each storage sub-unit 001 is connected to the bit line 003 of the corresponding column through its top electrode 501, and is connected to the word line 002 of the corresponding row through its bottom electrode 502.

[0225] Each storage sub-unit 001 includes a bottom electrode 502, a selection layer 600, an intermediate electrode 503, a blocking layer 300, an adhesion layer 200, a phase change material layer 100, an adhesion layer 200, a blocking layer 300 and a top electrode 501 which are stacked in sequence from bottom to top, and adjacent storage sub-units 001 are isolated by an insulating layer. Specifically, for each storage sub-unit 001, the outer surfaces of the blocking layer 300, the adhesion layer 200, the phase change material layer 100, the adhesion layer 200, the blocking layer 300 and the top electrode 501 are sequentially coated with a first insulating layer 401 and a second insulating layer 402 from the inside to the outside, and the outer surfaces of the bottom electrode 502, the selection layer 600 and the intermediate electrode 503 are sequentially coated with a third insulating layer 403 and a fourth insulating layer 404 from the inside to the outside.

[0226] The phase change memory chip provided in Example 2, on the one hand, has a phase change material layer 100 using the improved phase change material provided in the above embodiment of the present disclosure, and on the other hand, an adhesion layer 200 is added between the phase change material layer 100 and the barrier layer 300, which can further enhance the adhesion between the phase change material layer 100 and the barrier layer 300.

[0227] As Example 3, see Attachment Fig.11 , which illustrates a 1S1R type phase change memory chip, which is arranged on a substrate 004. The 1S1R type phase change memory chip includes multiple storage sub-units 001, multiple word lines 002 and multiple bit lines 003. The multiple storage sub-units 001 are arranged in an array, the multiple word lines 002 are arranged in rows, and the multiple bit lines 003 are arranged in columns. Each storage sub-unit 001 is connected to the bit line 003 of the corresponding column through its top electrode 501, and is connected to the word line 002 of the corresponding row through its bottom electrode 502.

[0228] Each storage sub-unit 001 includes a bottom electrode 502, a selection layer 600, an intermediate electrode 503, a blocking layer 300, a phase change material layer 100, an adhesion layer 200, a blocking layer 300 and a top electrode 501 which are stacked in sequence from bottom to top, and adjacent storage sub-units 001 are isolated by an insulating layer. Specifically, for each storage sub-unit 001, the outer surfaces of the blocking layer 300, the phase change material layer 100, the adhesion layer 200, the blocking layer 300 and the top electrode 501 are sequentially coated with a first insulating layer 401 and a second insulating layer 402 from the inside to the outside, and the outer surfaces of the bottom electrode 502, the selection layer 600 and the intermediate electrode 503 are sequentially coated with a third insulating layer 403 and a fourth insulating layer 404 from the inside to the outside.

[0229] The phase change memory chip provided in Example 3, on the one hand, has a phase change material layer 100 using the improved phase change material provided in the above embodiment of the present disclosure, and on the other hand, an adhesion layer 200 is added to the side of the phase change material layer 100 close to the top electrode 501, which can further enhance the adhesion between the phase change material layer 100 and the barrier layer 300.

[0230] Of course, the phase change memory chip provided in Example 3 may also add an adhesion layer 200 on the side of the phase change material layer 100 close to the gating layer 600 to increase the bonding force between the phase change material layer 100 and the barrier layer 300 close to the gating layer 600 .

[0231] As Example 4, see Attachment Fig.12 , which illustrates a 1S1R type phase change memory chip, which is arranged on a substrate 004. The 1S1R type phase change memory chip includes multiple storage sub-units 001, multiple word lines 002 and multiple bit lines 003. The multiple storage sub-units 001 are arranged in an array, the multiple word lines 002 are arranged in rows, and the multiple bit lines 003 are arranged in columns. Each storage sub-unit 001 is connected to the bit line 003 of the corresponding column through its top electrode 501, and is connected to the word line 002 of the corresponding row through its bottom electrode 502.

[0232] Each storage sub-unit 001 includes a bottom electrode 502, a selection layer 600, an intermediate electrode 503, an adhesion layer 200, a phase change material layer 100, an adhesion layer 200 and a top electrode 501 which are stacked in sequence from bottom to top, and adjacent storage sub-units 001 are isolated by an insulating layer. Specifically, for each storage sub-unit 001, the outer surfaces of its adhesion layer 200, the phase change material layer 100, the adhesion layer 200 and the top electrode 501 are sequentially coated with a first insulating layer 401 and a second insulating layer 402 from the inside to the outside, and the outer surfaces of its bottom electrode 502, the selection layer 600 and the intermediate electrode 503 are sequentially coated with a third insulating layer 403 and a fourth insulating layer 404 from the inside to the outside.

[0233] The phase change memory chip provided in Example 4, on the one hand, has a phase change material layer 100 using the improved phase change material provided in the above embodiment of the present disclosure, and on the other hand, an adhesion layer 200 is added between the phase change material layer 100 and the electrode layer, which can further enhance the adhesion between the phase change material layer 100 and the electrode layer.

[0234] The embodiments of the present disclosure are combined with any of the above-mentioned phase change materials to exemplify the structural arrangement and preparation process of some 1S1R phase change memory chips.

[0235] As example (1), a 1S1R type phase change memory chip is provided, which is arranged on a silicon oxide substrate 004. The 1S1R type phase change memory chip includes a plurality of storage subunits 001, a plurality of word lines 002 and a plurality of bit lines 003, as shown in the attached Fig. 9 As shown, each storage sub-unit 001 includes a bottom electrode 502, a gating layer 600, an intermediate electrode 503, a barrier layer 300, a phase change material layer 100, a barrier layer 300 and a top electrode 501 stacked sequentially from bottom to top, and adjacent storage sub-units 001 are isolated by an insulating layer. A plurality of storage sub-units 001 are arranged in an array, a plurality of word lines 002 are arranged sequentially in rows, and a plurality of bit lines 003 are arranged sequentially in columns. Each storage sub-unit 001 is connected to the bit line 003 of the corresponding column through its top electrode 501, and is connected to the word line 002 of the corresponding row through its bottom electrode 502.

[0236] For example, the word line 002 and the bit line 003 are made of metal tungsten W, the top electrode 501, the bottom electrode 502 and the middle electrode 503 are made of carbon C, and the barrier layer 300 is made of metal tungsten W. The gate tube material used in the gate layer 600 is the currently available SiGeAsSe gate material. The phase change material of the phase change material layer 100 can be the phase change material involved in the first embodiment.

[0237] The preparation process of the 1S1R phase change memory chip is as follows:

[0238] As attached Fig.14 As shown, a thin film precursor of a phase change memory chip is provided, and the thin film precursor includes: a substrate 004, a word line 002 layer, a bottom electrode 502, a gate layer 600, an intermediate electrode 503, a barrier layer 300, a phase change material layer 100, a barrier layer 300, a top electrode 501 and a mask layer 005 which are sequentially stacked from bottom to top. The mask layer 005 is mainly used to protect the material layers below it and prevent the etching process from affecting the material layers below it.

[0239] As attached Fig.15 As shown, the thin film precursor is subjected to a first patterning process to form a first groove 701. The first patterning process includes a photolithography process and an etching process. Fig.15 In the first horizontal direction (i.e., the middle Z-axis direction), the first groove 701 sequentially penetrates the mask layer 005, the top electrode 501, the barrier layer 300, the phase change material layer 100 and the barrier layer 300 from top to bottom to expose the middle electrode 503. Fig.15 In the X-axis direction), the first trenches 701 are arranged in a plurality of intervals to form a plurality of first memory cell precursors.

[0240] As attached Fig.16As shown, an insulating material is filled into the first trench 701 to form an insulating layer. This includes: the first insulating material and the second insulating material are sequentially filled into the first trench 701, the first insulating material forms a first insulating layer 401 and covers the surface of the corresponding first memory cell precursor, and the second insulating material forms a second insulating layer 402 and covers the surface of the first insulating layer 401. The material of the first insulating layer 401 is silicon nitride, and the material of the second insulating layer 402 is silicon dioxide, both of which can prevent the phase change material layer 100 from being affected by the subsequent etching process.

[0241] As attached Fig.17 As shown, the second patterning process is continued, so that the first trench 701 extends downward in the vertical direction to form a second trench 702. The second patterning process includes photolithography and etching.

[0242] In the vertical direction, the second trench 702 sequentially penetrates the mask layer 005, the top electrode 501, the barrier layer 300, the phase change material layer 100, the barrier layer 300, the middle electrode 503, the gating layer 600, the bottom electrode 502, and the word line 002 from top to bottom. In the first horizontal direction, the second trench 702 is arranged in multiple intervals to form multiple second memory cell precursors.

[0243] As attached Fig.18 As shown, the second trench 702 is filled with an insulating material to form an insulating layer, which includes: the third insulating material and the fourth insulating material are sequentially filled into the second trench 702, the third insulating material forms a third insulating layer 403 and covers the surface of the corresponding second memory cell precursor, and the fourth insulating material forms a fourth insulating layer 404 and covers the surface of the third insulating layer 403, so as to obtain an integrated third memory cell precursor. The third insulating layer 403 is made of silicon nitride, and the fourth insulating layer 404 is made of silicon dioxide, and the two perform insulation isolation between different second memory cell precursors and can also provide mechanical support for them.

[0244] As attached Fig.19 As shown in FIG. 1 , the third memory cell precursor is polished to remove the mask layer 005 and expose the top electrode 501. Then, a bit line 003 and a new mask layer 005 are sequentially formed on the surface of the top electrode 501 to obtain an integrated fourth memory cell precursor. The structure of the cross section of the fourth memory cell precursor along the second horizontal direction is shown in FIG. Fig. 20 The cross section along the second horizontal direction is also shown in FIG. Fig.19 The second horizontal direction is the cross section shown by the dotted line AB. Fig. 20 The Y-axis direction is perpendicular to the aforementioned X-axis direction.

[0245] As attached Fig.21As shown, the third patterning process is performed on the fourth memory cell precursor to form a third trench 703. The third patterning process includes a photolithography process and an etching process. In the vertical direction, the third trench 703 sequentially penetrates the mask layer 005, the bit line 003 layer, the top electrode 501, the barrier layer 300, the phase change material layer 100, and the barrier layer 300 from top to bottom to expose the middle electrode 503. In the second horizontal direction, the third trench 703 is arranged in multiple intervals to form multiple fifth memory cell precursors.

[0246] As attached Fig. 22 As shown, an insulating material is filled into the third trench 703 to form an insulating layer, which includes: sequentially filling the third trench 703 with a first insulating material and a second insulating material, the first insulating material forming a first insulating layer 401 and coating the corresponding surface of the fifth memory cell precursor, the second insulating material forming a second insulating layer 402 and coating the surface of the first insulating layer 401, to obtain an integrated sixth memory cell precursor.

[0247] Further as attached Fig. 22 As shown, the sixth memory cell precursor is further subjected to the fourth patterning process, so that the third groove 703 extends downward in the vertical direction to form a fourth groove. The fourth patterning process includes a photolithography process and an etching process. In the vertical direction, the fourth groove sequentially penetrates the mask layer 005, the bit line 003 layer, the top electrode 501, the barrier layer 300, the phase change material layer 100, the barrier layer 300, the intermediate electrode 503, the gating layer 600, and the bottom electrode 502 from top to bottom to expose the word line 002. In the second horizontal direction, the fourth grooves are arranged in a plurality along the intervals, thereby forming a plurality of seventh memory cell precursors.

[0248] As attached Fig. 22 As shown, an insulating material is filled into the fourth trench to form an insulating layer, which includes: filling the third insulating material and the fourth insulating material into the fourth trench in sequence, the third insulating material forms a third insulating layer 403 and covers the corresponding surface of the seventh memory cell precursor, the fourth insulating material forms a fourth insulating layer 404 and covers the surface of the third insulating layer 403, and obtains an integrated eighth memory cell precursor.

[0249] As attached Fig.23 As shown, the eighth memory cell precursor is polished to remove the mask layer 005 and the third insulating layer 403 and the fourth insulating layer 404 above the bit line 003 to expose the bit line 003, thereby preparing the phase change memory chip provided in Example 1.

[0250] The phase change memory chip provided in Example 1 effectively improves the bonding force between the phase change material layer 100 and the barrier layer 300 by improving the phase change material, preventing delamination, peeling, etc. between layers, which may lead to a decrease in the yield of the phase change memory chip. At the same time, the improved phase change material still helps the phase change memory chip to have advantages such as a large read window, low latency, and high endurance characteristics.

[0251] For the phase change memory chips involved in this type of example, the bonding force between the phase change material layer 100 and the barrier layer 300 is effectively improved by improving the phase change material, preventing delamination, peeling, etc. between layers, which may lead to a decrease in the yield of the phase change memory chip. At the same time, the improved phase change material still helps the phase change memory chip to have advantages such as a large read window and high endurance characteristics.

[0252] As Example (2), a type of 1S1R phase change memory chip is provided. The 1S1R phase change memory chip involved in this type of example includes a plurality of memory sub-units 001, a plurality of word lines 002, and a plurality of bit lines 003. As shown in the appendix Fig.10 Each memory sub-unit 001 includes a bottom electrode 502, a select layer 600, an intermediate electrode 503, a barrier layer 300, an adhesion layer 200, a phase change material layer 100, an adhesion layer 200, a barrier layer 300, and a top electrode 501, which are stacked in sequence from bottom to top. Adjacent memory sub-units 001 are isolated by an insulating layer. Compared with Example (1), an adhesion layer 200 is added to the memory sub-unit 001, and the arrangement of other layers is the same. Exemplarily, the thickness of the adhesion layer 200 can be 2 nm, and the material of the adhesion layer 200 can be WN or InGeSbTe. Among them, WN can be W2N, WN, WN2, or any component that satisfies the following general formula: W x N 1-x , where x is the atomic percentage, and 0 < x < 1. The InGeSbTe compound can be, for example, In3%-Ge2Sb2Te5, that is, the atomic percentage of In is 3%, and in the GeSbTe phase change substrate, the ratio of the atomic percentages of Ge, Sb, and Te is 2:2:5.

[0253] The manufacturing process of the phase change memory chip involved in this type of Example (2) can refer to the above Example (1), except that when forming the memory sub-unit 001, the adhesion layer 200 is formed at a specific position.

[0254] The phase change memory chip involved in this type of example (2) improves the phase change material on the one hand, and on the other hand, effectively improves the bonding force between the phase change material layer 100 and the barrier layer 300 by adding an adhesion layer 200 between the phase change material layer 100 and the barrier layer 300. In addition, since the total thickness of the two adhesion layers 200 can be 4 nm, which is only one tenth of the thickness of the phase change material layer 100, the performance of the phase change material layer 100 is less affected.

[0255] As example (3), a 1S1R type phase change memory chip is provided. Its structure and preparation process can be referred to in example (1). The difference between the 1S1R type phase change memory chip and the phase change memory chip of example (1) is as follows: Fig.12 The barrier layer 300 in Example 1 is directly replaced by the adhesion layer 200 , that is, an adhesion layer 200 is directly disposed between the phase change material layer 100 and the top electrode 501 , and between the phase change material layer 100 and the middle electrode 503 .

[0256] The phase change memory chip involved in this type of example (3) improves the phase change material on the one hand, and on the other hand, increases the bonding force between the phase change material layer 100 and the electrode layer by adding an adhesion layer 200 between the phase change material layer 100 and the electrode layer.

[0257] As example (4), a 1S1R type phase change memory chip is provided, the structure and preparation process of which can be referred to example (1). The difference from the phase change memory chip of example (1) is that the doping elements in the phase change material used in the phase change material layer 100 are limited to Hf element and In element.

[0258] As example (5), a 1S1R type phase change memory chip is provided, and its structure and preparation process can be referred to example (1). The difference between the 1S1R type phase change memory chip and the phase change memory chip of example (1) is that the phase change material of the phase change material layer 100 can be the phase change material involved in the second embodiment mentioned above.

[0259] For the 1S1R type phase change memory chip involved in Example (5), the delay, life, high and low resistance characteristics, etc. of those phase change memory chips in which the atomic percentage ratio of each atom in the Ge-Sb-Te phase change matrix is: Ge:Sb:Te=1:4:7 (referred to as GST147) were tested. The test results are shown in Table 5, where NA involved in Table 5 means that the data has no meaning.

[0260] Table 5

[0261]

[0262] Experiments have confirmed that when the atomic percentage of Sb in the Ge-Sb-Te phase-change substrate is greater than 35% and less than 45%, the delay of the phase-change memory chip can reach less than 100ns. When the atomic percentage of Sb in the Ge-Sb-Te phase-change substrate exceeds 45%, the life of the phase-change memory chip is reduced to a certain extent. When the atomic percentage of Ge is greater than 15%, the delay of the phase-change memory chip is slowed down to a certain extent. When the atomic percentage of Ge is less than 6%, the adhesion of the phase-change material layer is reduced.

[0263] As shown in Table 5, the sum of the atomic percentages of the Hf element and the N element is greater than 4%, which is very necessary to give the phase change memory chip a high life characteristic. When the atomic percentage of the Hf element is 6.5% and the atomic percentage of the N element is 5%, since the sum of the atomic percentages of the two is greater than 10%, the low resistance rises abnormally and is unstable during the cycle.

[0264] As shown in Table 5, when the atomic percentage of Hf element is 8%, the high resistance of the phase change memory chip will become lower and unstable during the cycle. When the atomic percentage of N element is 8%, the low resistance of the phase change memory chip will become higher, but it will be unstable during the cycle.

[0265] The phase change memory chip provided in the embodiments of the present disclosure has the potential to replace the solid state drive (SSD) due to its high speed, high density and non-volatile characteristics. If the operating speed is further improved, it has the potential to be applied to universal memory, combining the functions of internal memory and external memory.

[0266] On the other hand, an embodiment of the present disclosure further provides a storage device, which includes a controller and any one of the above-mentioned phase change memory chips, wherein the controller is used to store data in the phase change memory chip, wherein the controller reads and writes data stored in the storage device and interacts with an external interface.

[0267] The storage device (also referred to as a memory) may be configured to store various types of data, which may be contact data, phone book data, messages, pictures, videos, etc., or may be instructional data.

[0268] The storage devices involved in the embodiments of the present disclosure may be configured into various types, for example, including but not limited to: memory, hard disk, magnetic disk, optical disk, etc.

[0269] An embodiment of the present disclosure further provides an electronic device, which includes a processor and the above-mentioned storage device, and the processor is used to store data generated by the electronic device in the storage device.

[0270] In some examples, the electronic device includes, but is not limited to, a computer, a mobile phone, a music player, a digital broadcast device, a messaging device, a game control device, a medical device, a fitness device, a personal digital assistant, and the like.

[0271] The above description is only for the purpose of facilitating those skilled in the art to understand the technical solution of the present disclosure and is not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A phase change material, characterized in that: The phase change material includes a Ge-Sb-Te phase change substrate, a first doping element and a second doping element doped in the Ge-Sb-Te phase change substrate; The first doping element includes Hf element, and the atomic percentage of the first doping element in the phase change material is 1.5%-6.5%; The second doping element includes at least one of N, C, In and Ga, and the atomic percentage of the second doping element in the phase change material is 1.0%-5%.

2. The phase change material according to claim 1, characterized in that: The phase change material also includes: a third doping element, and the third doping element includes at least one of O element, Si element, B element, Sn element, Bi element, Cd element, Pb element, Zr element, Zn element, Cr element, Al element, Sc element, Y element, Ta element, Ti element, Er element, Lu element, Ho element, Tm element, Dy element, Tb element, Ca element, Nd element, Pr element, Yb element, Ca element, and Ce element.

3. The phase change material according to any one of claims 1 to 2, characterized in that: The chemical general formula of the Ge-Sb-Te phase change substrate is as follows: (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , where x is the atomic percentage and 0 < x < 1, a and b are parameters related to the atomic number ratio, 0 < a ≤ 1, 0 < b ≤ 3, and a = 1 and b = 3 do not exist simultaneously; Alternatively, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where x is the atomic percentage and 0 < x < 1, y, c, and d are parameters related to the atomic number ratio, y ≥ 2, 0 < c ≤ 1, 0 < d ≤ 1, and c = 1 and d = 1 do not exist simultaneously.

4. A phase change material, characterized in that: The phase change material includes a Ge-Sb-Te phase change substrate, a first doping element and a second doping element doped in the Ge-Sb-Te phase change substrate; The first doping element includes Hf element, and the atomic percentage of the first doping element in the phase change material is 1.5%-7%; The second doping element includes at least one of N, C, In and Ga, and the atomic percentage of the second doping element in the phase change material is 1.0%-7%; The sum of the atomic percentages of the first doping element and the second doping element is greater than 4% and less than 10%.

5. The phase change material according to claim 4, characterized in that: The phase change material also includes: a third doping element, and the third doping element includes at least one of O element, Si element, B element, Sn element, Bi element, Cd element, Pb element, Zr element, Zn element, Cr element, Al element, Sc element, Y element, Ta element, Ti element, Er element, Lu element, Ho element, Tm element, Dy element, Tb element, Ca element, Nd element, Pr element, Yb element, Ca element, and Ce element.

6. The phase change material according to any one of claims 4 to 5, characterized in that: The chemical general formula of the Ge-Sb-Te phase change substrate is as follows: (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , where x is the atomic percentage and 0 < x < 1, a and b are parameters related to the atomic number ratio, 0 < a ≤ 1, 0 < b ≤ 3, and a = 1 and b = 3 do not exist simultaneously; Alternatively, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where x is the atomic percentage and 0 < x < 1, y, c, and d are parameters related to the atomic number ratio, y ≥ 2, 0 < c ≤ 1, 0 < d ≤ 1, and c = 1 and d = 1 do not exist simultaneously.

7. The phase change material according to claim 6, characterized in that: The chemical general formula of the Ge-Sb-Te phase change substrate is as follows: (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , and 0.2 < x ≤ 0.4, or, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , and 0.2 < x ≤ 0.

4.

8. A phase change memory chip, characterized in that: The phase change memory chip comprises: a plurality of phase change memory units, wherein the phase change memory unit comprises a phase change material layer, wherein the phase change material layer is prepared from the phase change material according to any one of claims 1 to 3, or the phase change material layer is prepared from the phase change material according to any one of claims 4 to 7.

9. The phase change memory chip according to claim 8, characterized in that: The phase-change memory unit further includes an adhesion layer, which is stacked on at least one surface of the phase-change material layer and is used to increase adhesion between the phase-change material layer and an adjacent functional layer.

10. The phase change memory chip according to claim 9, characterized in that: The adhesion layer raw material used in the adhesion layer includes at least one of a nitride of a target element and a carbide of a target element; The target element is selected from at least one of W element, Ti element, Ge element, Ta element, Hf element, In element, Ga element, Al element, Cu element, Co element, and Mo element.

11. The phase change memory chip according to claim 9, characterized in that: The adhesion layer raw material used in the adhesion layer includes a Ge-Sb-Te phase change material doped with a fourth doping element, and the adhesion layer raw material is different from the phase change material; The fourth doping element is selected from at least one of Hf, N, C, In and Ga, and the atomic percentage of the fourth doping element in the raw material of the adhesion layer is 0.01%-20%.

12. The phase change memory chip according to any one of claims 9 to 11, characterized in that: The phase-change memory unit further includes a barrier layer. The adhesion layer is located between the phase-change material layer and the barrier layer, and is used to increase adhesion between the phase-change material layer and the barrier layer.

13. The phase change memory chip according to claim 12, characterized in that: The barrier layer material used in the barrier layer includes at least one of the simple substances, nitrides and carbides of W, Ti, Ge, Ta, Hf, In, Ga, Al, Cu, Co and Mo.

14. The phase change memory chip according to any one of claims 9 to 11, characterized in that: The phase change memory unit further includes an electrode layer. The adhesion layer is located between the phase change material layer and the electrode layer and is used to increase the adhesion between the phase change material layer and the electrode layer.

15. The phase change memory chip according to any one of claims 8 to 14, characterized in that: The phase-change memory chip further comprises: a plurality of gate tube units, wherein the gate tube units are arranged in series with the phase-change memory units; The gate tube unit includes a gate layer, and the gate tube material used in the gate layer includes at least one of an S series gate tube material, a Se series gate tube material, and a Te series gate tube material.

16. The phase change memory chip according to claim 15, characterized in that: The gate tube material also includes a fifth doping element, and the fifth doping element is selected from at least one of B element, Al element, Ga element, In element, C element, Si element, Ge element, Sn element, N element, P element, As element, Sb element, Bi element, O element, Au element, Hf element, Pd element, Cu element, Co element, Ag element, Pt element, Sc element, Ti element, and Ta element.

17. A storage device, characterized in that: The storage device comprises a controller and at least one phase-change memory chip as claimed in any one of claims 8 to 16, wherein the controller is used to store data in the phase-change memory chip.

18. An electronic device, characterized in that: The electronic device comprises a processor and the storage device according to claim 17, wherein the processor is used to store data generated by the electronic device in the storage device.

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