Integrated CMOS source-drain formation with advanced control

Abstract

A finFET device includes a doped source and / or drain extension disposed between a gate spacer of the finFET and a bulk semiconductor portion of a semiconductor substrate on which an n-doped or p-doped source or drain extension is disposed. A doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate to the gate spacer. After forming the cavity, advanced process control (APC) (i.e., integrated metrology) is used to determine the recess distance without exposing the substrate to an oxidizing environment. The isotropic etch process, metrology, and selective epitaxial growth may be performed in the same stage.

Description

[0001] This application is a divisional application of the invention patent application with application date of July 5, 2019, application number 201980044705.4, and invention name “Integrated CMOS source and drain formation using advanced control”. Technical Field

[0002] Embodiments of the present disclosure relate generally to the fabrication of integrated circuits, and more particularly, to apparatus and methods for forming source-drain extensions in finFETs using selective epitaxial growth (SEG). Background Art

[0003] Transistors are key components of most integrated circuits. Since the drive current of a transistor, and thus the speed of the transistor, is proportional to the gate width of the transistor, faster transistors generally require larger gate widths. Therefore, there is a tradeoff between transistor size and speed, and "fin" field effect transistors (finFETs) have been developed to address the conflicting goals of transistors with maximum drive current and minimum size. FinFETs are characterized by a fin-shaped channel region that greatly increases the size of the transistor without significantly increasing the area occupied by the transistor, and finFETs are currently used in many integrated circuits. However, finFETs have their own drawbacks.

[0004] Forming horizontal source / drain extensions is becoming increasingly difficult for narrow and tall finFETs because the fin-shaped channel region can be easily amorphized or otherwise damaged by conventional ion implantation techniques (such as beamline ion implantation). Specifically, in some finFET architectures (e.g., horizontal gate-all-around, h-GAA), ion implantation can result in severe intermixing between the silicon channel and the adjacent sacrificial silicon germanium (SiGe) layer. Such intermixing is highly undesirable because the ability to selectively remove the sacrificial SiGe layer is subsequently reduced. Furthermore, repairing such implant damage via thermal annealing increases the thermal budget of the finFET device.

[0005] Furthermore, precise placement of desired dopants in the horizontal source / drain extension regions of a finFET is difficult at best, as the source / drain extensions in a finFET may be covered by other structures. For example, (internal) sidewall spacers on a sacrificial SiGe superlattice (SL) layer typically cover the source / drain extension regions when doping is performed. Therefore, conventional line-of-sight ion implantation techniques cannot uniformly deposit dopants directly into the finFET source / drain extension regions.

[0006] Additionally, the time that the substrate is exposed to the atmosphere (also known as the Q-time) can have a significant impact on the defectivity of the epitaxial film. Thus, there is a need for processing equipment and techniques for precisely doping the source / drain regions in finFET devices currently available or under development. Summary of the invention

[0007] One or more embodiments of the present disclosure relate to a method of forming a semiconductor device. An anisotropic etching process is performed on a semiconductor material on a semiconductor substrate to expose a surface in the semiconductor material. The surface is disposed between an existing structure of the semiconductor device and a main semiconductor portion of the semiconductor substrate on which the semiconductor material is formed. An isotropic etching process is performed on the exposed sidewall to recess the semiconductor material disposed between the existing structure and the main semiconductor portion of the semiconductor substrate by a distance to form a cavity. A deposited material layer is formed on the cavity surface via a selective epitaxial growth (SEG) process. Between forming the cavity and SEG, the substrate does not undergo a pre-cleaning process.

[0008] Additional embodiments of the present disclosure relate to methods of forming a semiconductor device. A semiconductor substrate is positioned within a semiconductor material thereon in a first processing chamber. An anisotropic etching process is performed on the semiconductor material to expose a surface in the semiconductor material. The surface is disposed between an existing structure of the semiconductor device and a main semiconductor portion of the semiconductor substrate on which the semiconductor material is formed. An isotropic etching process is performed on the exposed sidewalls to recess the semiconductor material disposed between the existing structure and the main semiconductor portion of the semiconductor substrate by a distance to form a cavity. The semiconductor substrate is moved from the first processing chamber to a second processing chamber without exposing the semiconductor substrate to oxidizing conditions. A distance that the semiconductor material has been recessed after the isotropic etching is determined. A layer of deposited material is formed on the surface of the cavity using a selective epitaxial growth (SEG) process in the second processing chamber. Between forming the cavity and the SEG, the semiconductor substrate does not undergo a pre-cleaning process. The SEG process takes into account the distance that the semiconductor material has been recessed after the isotropic etching.

[0009] Another embodiment of the present disclosure relates to a processing tool for forming a semiconductor device. A central transfer station has a plurality of processing chambers arranged around the central transfer station. A robot is within the central transfer station and is configured to move a substrate between the plurality of processing chambers. A first processing chamber is connected to the central transfer station. The first processing chamber is configured to perform an isotropic etching process. A metrology station is within the processing tool and accessible to the robot. The metrology station is configured to determine a recess distance of semiconductor material on a substrate from an isotropic etching process. A second processing chamber is connected to the central transfer station. The second processing chamber is configured to perform a selective epitaxial growth (SEG) process. A controller is connected to one or more of the central transfer station, the robot, the first processing chamber, the metrology station, or the second processing chamber. The controller has one or more configurations selected from: a first configuration for moving a substrate on a robot between multiple processing chambers and a metrology station; a second configuration for performing an isotropic etching process on the substrate in a first processing chamber; a third configuration for performing an analysis to determine recess of a semiconductor material in the metrology station; or a fourth configuration for performing a selective epitaxial growth process in a second processing chamber, the selective epitaxial growth process being adjusted with respect to recess of the semiconductor material. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are used, a more particular description of the present disclosure briefly summarized above may be made with reference to the embodiments, some of which are shown in the accompanying drawings. It will be noted, however, that the accompanying drawings illustrate only typical embodiments of the present disclosure and are not to be considered limiting of its scope, as the present disclosure may admit to other equally effective embodiments.

[0011] Figure 1 is a perspective view of a fin field effect transistor (finFET) according to one or more embodiments of the present disclosure;

[0012] Figure 2 According to one or more embodiments of the present disclosure Figure 1 A cross-sectional view of a finFET;

[0013] Figure 3 is a flow chart of a manufacturing process for forming a finFET according to one or more embodiments of the present disclosure;

[0014] FIG. 4A to FIG. 4E The diagram shows a schematic diagram of one or more embodiments of the present disclosure. Figure 3 Schematic cross-sectional views of semiconductor devices at various stages of a process;

[0015] Figure 5 According to one or more embodiments of the present disclosure, after forming the cavity Figure 1A schematic cross-sectional view of a finFET;

[0016] Figure 6 is a flow chart of a fabrication process for forming a nanowire structure according to one or more embodiments of the present disclosure;

[0017] FIG. 7A to FIG. 7G According to one or more embodiments of the present disclosure, Figure 6 Schematic cross-sectional views of the nanowire / nanosheet structure of FIG. 7 at various stages of the process;

[0018] Figure 8 is a flow chart of a manufacturing process for forming a semiconductor device according to one or more embodiments of the present disclosure; and

[0019] Fig. 9 A schematic diagram of a processing system for performing the method of any embodiment of the present disclosure is illustrated. DETAILED DESCRIPTION

[0020] Before describing several exemplary embodiments of the present disclosure, it will be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and can be practiced or carried out in various ways.

[0021] As used in this specification and the appended claims, the term "substrate" refers to a surface, or a portion of a surface, on which a process acts. It will also be understood by those skilled in the art that, unless the context clearly indicates otherwise, reference to a substrate may also refer to only a portion of a substrate. In addition, reference to depositing on a substrate may refer to both a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0022] As used herein, "substrate" refers to any substrate or a surface of a material formed on a substrate on which film processing is performed during a manufacturing process. For example, depending on the application, the substrate surface on which processing can be performed includes materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material, such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. The substrate may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure, and / or bake the substrate surface. In addition to performing film processing directly on the substrate surface itself, in the present disclosure, as disclosed in more detail below, any film processing step disclosed may also be performed on an underlying layer formed on the substrate, and the term "substrate surface" is intended to include such an underlying layer as indicated by the context. Thus, for example, where a film / layer or portion of a film / layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0023] Embodiments of the present disclosure relate to semiconductor devices, processing tools, and processing methods that include doped semiconductor materials that are formed in a region disposed between an existing structure of the semiconductor device and a bulk semiconductor portion of a semiconductor substrate. In one or more embodiments, the semiconductor device comprises a finFET device. In such an embodiment, an n-doped silicon-containing material forms an n-doped source or drain extension disposed between a gate spacer of the finFET and a bulk semiconductor portion of a semiconductor substrate on which the n-doped source or drain extension is disposed. Although embodiments of the present disclosure are described with respect to forming nMOS (n-type metal oxide semiconductor) and n-doped films, a skilled person will recognize that p-doped films may also be formed by similar processes. References to "nMOS" or "n-doped" throughout the present disclosure are only for ease of description, and the present disclosure should not be considered limited to nMOS or n-doped structures. In some embodiments, the method relates to forming pMOS (p-type metal oxide semiconductor) or p-doped films. Some embodiments of the present disclosure relate to processes for forming a PMOS device, wherein the source / drain (SD) comprises multiple layers of SiGe and boron. In one or more embodiments, the SD material provides compressive stress that increases hole mobility for PMOS devices.Controlling the amount of lateral push in conjunction with epitaxial SD layer formation can affect overall performance.

[0024] Figure 11 is a perspective view of a fin field effect transistor (finFET) 100 according to an embodiment of the present disclosure. The finFET 100 includes a semiconductor substrate 101, an insulating region 102 formed on a surface of the semiconductor substrate 101, a fin structure 120 formed on the surface of the semiconductor substrate 101, and a gate electrode structure 130 formed on the insulating region 102 and on the fin structure 120. A top portion of the fin structure 120 is exposed and electrically coupled to a source contact (not shown) of the finFET 100, another top portion of the fin structure 120 is exposed and electrically coupled to a drain contact (not shown) of the finFET 100, and a central portion of the semiconductor fin 121 includes a channel region of the finFET 100. The gate electrode structure 130 serves as a gate of the finFET 100.

[0025] The semiconductor substrate 101 may be a bulk silicon (Si) substrate, a bulk germanium (Ge) substrate, a bulk silicon germanium (SiGe) substrate, or the like. The insulating region 102 (or referred to as shallow trench isolation (STI)) may include one or more dielectric materials, such as silicon dioxide (SiO2), silicon nitride (Si3N4), or multiple layers thereof. The insulating region 102 may be formed by high-density plasma (HDP), flowable chemical vapor deposition (FCVD), or the like.

[0026] The fin structure 120 includes a semiconductor fin 121 and a fin spacer (not shown for clarity) formed on the sidewall of the semiconductor fin 121. The semiconductor fin 121 may be formed from the semiconductor substrate 101 or from a different semiconductor material deposited on the semiconductor substrate 101. In the latter case, the different semiconductor material may include silicon germanium, a III-V compound semiconductor material, or the like.

[0027] The gate electrode structure 130 includes a gate electrode layer 131, a gate dielectric layer 132, a gate spacer 133, and a mask layer 136. In some embodiments, the gate electrode layer 131 includes a polysilicon layer or a metal layer covered with a polysilicon layer. In other embodiments, the gate electrode layer 131 includes a material selected from the following: metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), and molybdenum nitride (MoN x )), metal carbides (such as tantalum carbide (TaC) and hafnium carbide (HfC)), metal-nitride-carbides (such as TaCN), metal oxides (such as molybdenum oxide (MoO x )), metal oxynitrides (such as molybdenum oxynitride (MoO x Ny )), metal silicide (such as nickel silicide), and combinations of the above materials. The gate electrode layer 131 can also be a metal layer covered with a polysilicon layer.

[0028] The gate dielectric layer 132 may include silicon oxide (SiO x ), the silicon oxide may be formed by thermal oxidation of the semiconductor fin 121. In other embodiments, the gate dielectric layer 132 is formed by a deposition process. Suitable materials for forming the gate dielectric layer 132 include silicon oxide, silicon nitride, oxynitride, metal oxides (such as HfO2, HfZrO x 、HfSiO x 、HfTiO x 、HfAlO x ), and combinations and multilayers of the above materials. Gate spacers 133 are formed on the sidewalls of gate electrode layer 131, and each may include a nitride portion 134 and / or an oxide portion 135, as shown. In some embodiments, mask layer 136 may be formed on gate electrode layer 131 as shown, and may include silicon nitride.

[0029] Figure 2 is a cross-sectional view of a finFET 100 according to one embodiment of the present disclosure. Figure 2 The cross-sectional view shown in Figure 1 As shown, the finFET 100 includes a semiconductor fin 121 having a heavily doped region 201, a doped extension region 202, and a channel region 205. Although the embodiments herein are described with respect to the formation of nMOS, the skilled person will recognize that the heavily doped region 201 and the doped extension region 202 may be p-doped regions.

[0030] Heavily doped region 201 forms the source and drain regions of finFET 100 and includes a relatively high concentration of an n-dopant (e.g., phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), lithium (Li)) or a p-dopant (e.g., boron (B), aluminum (Al), gallium (Ga), or indium (In)). Although region 201 may be referred to as heavily n-doped, skilled artisans will recognize that this region may be a p-doped region and may include a relatively high concentration of a p-dopant, such as boron (B). For example, in some embodiments, the dopant concentration in heavily doped region 201 may be as high as 5×10 21 Atom / cm 3 In some embodiments, the heavily doped region 201 has a doping area of ​​about 1×10 20 Atom / cm 3 About 1x10 22 Atom / cm 3The heavily doped regions 201 may be produced by any suitable doping technique. Because the heavily doped regions 201 are generally not covered by intervening structures of the finFET 100 when doped, a line-of-sight doping technique, such as beamline ion implantation, may be used. Alternatively, because a substantial portion of each heavily doped region 201 is generally exposed when doped, a conformal doping technique, such as plasma doping (PLAD), may be used to form the heavily doped regions 201.

[0031] The doped extension regions 202 form the source and drain extensions of the finFET 100 and include one or more n-dopants. A skilled person will recognize that the extension regions may be p-doped regions. According to an embodiment of the present disclosure, the doped extension regions 202 include one or more n-dopants that act as a diffusion barrier for n-dopants located in the heavily doped regions 201. Thus, because the doped extension regions 202 are disposed between the channel region 205 and the heavily doped regions 201, n-dopants (such as phosphorus) located in the heavily doped regions 201 cannot diffuse into the channel region 205. With the small geometries associated with modern finFET devices, the width 133A of the gate spacer 133 (which is also close to the distance between the heavily doped regions 201) may be only a few nanometers. Thus, such n-dopant diffusion may be a severe challenge in nMOS devices such as the finFET 100. In some embodiments, the doped extension region 202 includes one or more heavier mass atoms (eg, Ge, Sn, etc.) that increase compressive stress in the channel region 205 .

[0032] In some embodiments, the n-dopant located in the heavily doped region 201 may include phosphorus. In such an embodiment, the n-dopant included in the doped extension region 202 may include arsenic (As), which may serve as a primary diffusion barrier to phosphorus diffusion or simply as a spatial (geometric) offset. Alternatively or additionally, in such an embodiment, the n-dopant included in the doped extension region 202 may include antimony (Sb), which may also serve as a partial barrier to phosphorus diffusion. In some embodiments, the p-dopants included in the region 201 and the region 202 may independently include one or more of boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0033] In some embodiments, the doped extension region 202 is formed to have a thickness 202A that is less than the width 133A of the gate spacer 133. For example, in such an embodiment, the thickness 202A of the doped extension region 202 can be about 1 nanometer less than the width 133A. Therefore, in such an embodiment, the doped extension region 202 does not extend into the channel region 205.

[0034] Furthermore, according to an embodiment of the present disclosure, the doped extension region 202 is formed via a (SEG) process. Specifically, a cavity is formed in a portion of the semiconductor fin 121 that is disposed between the gate spacer 133 and the bulk semiconductor portion of the semiconductor substrate 101. The cavity is then filled with an n- or p-doped semiconductor material, such as a silicon material doped with arsenic (As) (e.g., also referred to herein as Si:As) or a silicon material doped with boron (B) (e.g., also referred to herein as Si:B). Thus, source-drain extensions for the finFET 100 are formed in a region of the semiconductor fin 121 that is between the existing structure of the semiconductor fin 121 and the bulk semiconductor portion of the semiconductor substrate 101. Additionally, the n-dopant included in the doped extension region 202 may be selected to serve as a diffusion barrier for the n-dopant located in the heavily doped region 201. Note that due to the presence of the gate spacer 133, the doped extension region 202 cannot be formed by beamline ion implantation or PLAD. As described below in conjunction with Figure 3 as well as FIG. 4A to FIG. 4E Various embodiments in which doped extension region 202 may be formed in finFET 100 are described.

[0035] Figure 3 is a flow chart of a fabrication process 300 for forming an nMOS finFET according to various embodiments of the present disclosure. A skilled artisan will recognize that a pMOS finFET may be formed by a similar fabrication process. FIG. 4A to FIG. 4E are semiconductor devices (such as Figure 1 Although process 300 is shown as being used to form a doped extension region, process 300 may also be used to form other structures on a substrate.

[0036] Process 300 begins at operation 301, such as Figure 4A As shown, in operation 301, a gate electrode structure 130 and a gate spacer 133 are formed on the semiconductor fin 121. Figure 4A In the embodiment shown in FIG. 1 , the semiconductor fin 121 is formed by a portion of the semiconductor substrate 101 .

[0037] In operation 302, an anisotropic etching process is performed on a portion of the semiconductor fin 121 that is disposed between the gate spacer 133 and a bulk semiconductor portion of the semiconductor substrate 101. Figure 4B1 , one or more sidewall surfaces 401 are exposed in the semiconductor material of the semiconductor fin 121. As shown, the sidewall surfaces 401 are disposed between the existing structure of the finFET 100 and the bulk semiconductor portion of the semiconductor substrate 101. That is, the sidewall surfaces 401 are disposed between the gate spacer 133 and the semiconductor substrate 101. Therefore, the sidewall surfaces 401 are in areas of the semiconductor fin 121 that are not accessible by conventional, normal surface line-of-sight ion implantation techniques.

[0038] The anisotropic etching process of operation 302 can be selected to remove sufficient material from the semiconductor fin 121 so that the sidewall surface 401 has any suitable target length 401A. For example, in some embodiments, the anisotropic etching process of operation 302 is performed so that the sidewall surface 401 has a target length 401A of about 5 nm to about 10 nm. In other embodiments, the sidewall surface 401 can have a target length 401A greater than 10 nm or less than 5 nm, depending on the geometry of the gate spacer 133, the concentration of n-dopants in the heavily doped region 201, the size of the channel region 205, and other factors. The anisotropic etching process of operation 302 can be, for example, a deep reactive-ion etch (DRIE) process during which the gate spacer 133 and other portions of the finFET 100 are masked.

[0039] In operation 303, Figure 4C 1 , an isotropic etching process is performed on sidewall surface 401 to form one or more cavities 402 in the material of semiconductor fin 121. As shown, each cavity 402 has a surface 403. In addition, each cavity 402 is disposed between an existing structure of finFET 100 (i.e., one of gate spacers 133) and a bulk semiconductor portion of semiconductor substrate 101. Thus, portions of cavities 402 are each in areas of semiconductor fin 121 that are not accessible to line-of-sight ion implantation techniques.

[0040] The isotropic etching process of operation 303 can be selected to remove sufficient material from the semiconductor fin 121 so that the cavity 402 has any suitable target width 402A. For example, in some embodiments, the isotropic etching process of operation 303 is performed so that the cavity 402 has a target width 402A of about 2 nm to about 10 nm. In other embodiments, depending on the geometry of the gate spacer 133, the concentration of n-dopants or p-dopants in the heavily doped region 201, and other factors, the sidewall surface 401 can have a target width 402A greater than 10 nm or less than 2 nm. For example, in some embodiments, the target width 402A can be selected so that the cavity 402 has a target width 402A that is no more than about 1 nm less than the width 133A of the gate spacer 133.

[0041] The isotropic etching process of operation 303 may include any suitable etching process that is selective to the semiconductor material of the semiconductor fin 121. For example, when the semiconductor fin 121 includes silicon (Si), the isotropic etching process of operation 303 may include one or more of a HCl-based chemical vapor etch (CVE) process, a HCl and GeH4-based CVE process, and / or a Cl2-based CVE process. In some embodiments, the isotropic etching process of operation 303 includes one or more of a wet etching process or a dry etching process. In some embodiments, the isotropic etching process of operation 303 includes a dry etching process.

[0042] In some embodiments, an optional operation 304 is performed in which a pre-deposition cleaning process or other surface preparation process is performed on the surface 403 of the cavity 402. The surface preparation process can be performed to remove native oxide on the surface 403 and otherwise prepare the surface 403 before the (SEG) process performed in operation 305. The surface preparation process can include a dry etching process, a wet etching process, or a combination of both.

[0043] In such an embodiment, the dry etching process may include conventional plasma etching, or a remote plasma assisted dry etching process, such as SiCoNi etch, available from Applied Materials, Inc., Santa Clara, California. TM Etching process. TM During the etching process, the surface 403 is exposed to H2, NF3 and / or NH3 plasma species, such as plasma excited hydrogen and fluorine species. For example, in some embodiments, the surface 403 may be exposed to H2, NF3 and NH3 plasma simultaneously. TM The etch process can be performed in a SiCoNi pre-clean chamber that can be integrated into one of a variety of multi-processing platforms, including the Centura TM 、Dual ACP、Producer TM GT and Endura platforms. The wet etching process may include a hydrofluoric (HF) acid post process, i.e., a so-called "HF post" process, in which an HF etch of the surface 403 is performed to hydrogen terminate the surface 403. Alternatively, any other liquid-based pre-epitaxial pre-cleaning process may be employed in operation 304. In some embodiments, the process includes a sublimation etch for native oxide removal. The etching process may be plasma-based or thermal. The plasma process may be any suitable plasma (e.g., conductively coupled plasma, inductively coupled plasma, microwave plasma).

[0044] In some embodiments, the apparatus or processing tool is configured to maintain the substrate under vacuum conditions to prevent the formation of an oxide layer and does not use a pre-epitaxial pre-cleaning process. In such embodiments, the processing tool is configured to move the substrate from the etch process chamber to the epitaxial chamber without exposing the substrate to atmospheric conditions.

[0045] In operation 305, as Figure 4D 4, a selective epitaxial growth (SEG) process is performed on surface 403 to grow a layer of deposition material 406, thereby forming doped extension region 202. In particular, the deposition material includes a semiconductor material such as silicon and an n-type dopant. For example, in some embodiments, deposition material 406 includes Si:As, where the arsenic concentration in deposition material 406 is selected based on the electrical needs of finFET 100. Note that Si:As can be deposited via (SEG) with an electrically active dopant concentration of arsenic up to about 5x10 21 Atom / cm 3 However, such high arsenic concentration present in the doped extension region 202 may result in increased resistivity due to the formation of undesirable As V (arsenic-vacancy) complexes and arsenic diffusion into the channel region 205. In addition, AsP V (arsenic-phosphorus-vacancy) complexes may form in the doped extension region 202, resulting in increased phosphorus diffusion into the channel region 205. Therefore, in some embodiments, the deposited material 406 includes no more than about 5×10 20 Atom / cm 3 The concentration of arsenic electrically active dopant is

[0046] In some embodiments, deposited material 406 may have a deposition thickness 406A of about 2 nm to about 10 nm. In other embodiments, for certain configurations of finFET 100, deposited material 406 may have a deposition thickness 406A that is thicker than 10 nm. Figure 4D As shown, deposition thickness 406A is selected such that deposition material 406 completely fills cavity 402 . In other embodiments, deposition thickness 406A is selected such that deposition material 406 partially fills cavity 402 and covers exposed surfaces of semiconductor fins 121 forming cavity 402 .

[0047] A suitable SEG process in operation 305 may include a specific process temperature and pressure, process gas, and gas flow selected to promote selective growth of a specific n-doped or p-doped semiconductor material. In an embodiment where the specific n-doped semiconductor material includes Si:As, the doping gas used in the SEG process of operation 305 may include AsH3, As(SiH3)3, AsCl3, or tertiarybutylarsine (TBA). Other gases used in the SEG process may include dichlorosilane (DCS), HCl, SiH4, Si2H6, and / or Si4H 10 . In such an embodiment, the SEG process of operation 305 can be performed in an atmospheric pressure or a high sub-atmospheric pressure chamber with a low H2 carrier gas flow. For example, in such an embodiment, the process pressure in the processing chamber performing the SEG process can be on the order of about 20-700F. In such an embodiment, the high reactor pressure and low dilution (due to the low carrier gas flow) can produce high arsenic and high dichlorosilane (H2SiCl2 or DCS) partial pressures, thereby facilitating the removal of chlorine (Cl) and excess arsenic from the surface 403 during the SEG process. Therefore, a high film growth rate and an associated high arsenic incorporation rate are achieved, and good crystal quality can be obtained. In some embodiments, the doping gas used provides a p-doped semiconductor material. In some embodiments, the p-doped semiconductor material includes one or more of boron (B), aluminum (Al), gallium (Ga), or indium (In). In some embodiments, the doping precursor includes one or more of borane, diborane, or a plasma thereof.

[0048] The SEG process of operation 305 may be performed in any suitable processing chamber, such as a processing chamber integrated into one of a variety of multi-processing platforms, including the Producer TM GT, Centura TM AP and Endura platforms. In this embodiment, the SiCoNi of operation 304 TM The etching process may be performed in another chamber of the same multi-processing platform.

[0049] In operation 306, if Figure 4E, a second SEG process is performed, wherein a heavily doped region 201 is formed. The heavily doped region 201 is formed on the doped extension region 202. The heavily doped region 201 may be formed of any suitable semiconductor material, including doped silicon, doped silicon germanium, doped silicon carbon, or the like. The one or more dopants may include any suitable n-dopant, such as phosphorus. For example, in some embodiments, the heavily doped region 201 may include phosphorus-doped silicon (Si:P). Any suitable SEG process may be used to form the heavily doped region 201. The thickness and other film properties of the heavily doped region 201 may be selected based on the electrical requirements of the finFET 100, the size of the finFET 100, and other factors.

[0050] In some embodiments, the second SEG process is performed in the same processing chamber as the SEG process of operation 305. Thus, the doped extension region 202 can be formed in a preliminary deposition step during the actual formation of the heavily doped region 201. Thus, in such an embodiment, a dedicated processing chamber is not required to form the doped extension region 202, and additional time for transferring the substrate from the first processing chamber (for performing SEG of the doped extension region 202) to the second processing chamber (for performing SEG of the heavily doped region 201) is avoided. Furthermore, in such an embodiment, the deposited material 406 is not exposed to air. Alternatively, in some embodiments, the second SEG process is performed in a different processing chamber from the SEG process of operation 305, thereby reducing the number of processing chambers exposed to harmful dopants (such as arsenic). In such an embodiment, both chambers can be integrated into the same multi-processing platform, thereby avoiding vacuum break and exposure of the deposited material 406 to air.

[0051] After operation 306 , the remaining components of finFET 100 may be completed using conventional manufacturing techniques.

[0052] The implementation of process 300 enables the formation of doped extension regions 202 in precisely defined locations (i.e., in regions of the semiconductor fin 121 that are difficult to reach with conventional ion implantation techniques). Furthermore, the process of forming doped extension regions 202 can be integrated into existing selective epitaxial growth steps already employed in the manufacture of finFETs, thereby minimizing or eliminating disruptions to the process flow for forming finFETs. Additionally, implant damage (i.e., defects from heavy mass ion implantation, such as silicon gaps or even silicon amorphization) is avoided, as well as any deleterious interactions between such crystal defects and high concentrations of arsenic and / or phosphorus. Thus, no post-implantation annealing or associated additional thermal budget affecting the process is required. Furthermore, when the SEG process of operation 305 is performed in the same processing chamber as the SEG process of operation 306 or in a different processing chamber on the same multi-processing platform, material losses associated with additional pre-cleaning are also avoided because no vacuum break occurs between the deposition of doped extension regions 202 and heavily doped regions 201.

[0053] As is well known in the art, introducing tensile strain into the channel region of an nMOS finFET can increase charge mobility in the nMOS finFET. Additionally, as described herein, forming an epitaxially grown Si:As material adjacent to the channel region 205 of the semiconductor fin 121 can introduce significant tensile strain in the channel region 205. For example, according to some embodiments of the present disclosure, the n-doped extension region can be deposited to have an arsenic concentration sufficient to produce a targeted tensile strain within the doped extension region 202. Thus, in embodiments where the deposited material 406 includes epitaxially grown Si:As, an additional benefit of forming the doped extension region 202 in the finFET 100 is that the channel region 205 can have improved charge mobility due to the tensile strain introduced into the channel region 205 by forming the n-doped extension region. In some embodiments, for example, germanium (Ge), antimony (Sb), and / or tin (Sn) are doped into the p-doped extension region to provide compressive stress to the channel.

[0054] In some embodiments, an optional carbon-containing layer is formed in the cavity 402. In such an embodiment, the carbon-containing layer can be a liner between the doped extension region 202 and the heavily n-doped region 201. Figure 5 One such implementation is shown in .

[0055] Figure 54 is a schematic cross-sectional view of finFET 100 after forming cavity 402 according to various embodiments of the present disclosure. As shown, carbon-containing layer 501 is deposited on surface 407 of deposited material 406. The presence of carbon (C) can enhance arsenic diffusion while reducing phosphorus diffusion. Therefore, in some embodiments, carbon-containing layer 501 includes between about 0.5% and about 1.0% carbon. In such embodiments, carbon-containing layer 501 can further include phosphorus, for example, at about 1x10 20 Atom / cm 3 With about 5x10 20 Atom / cm 3 Such a carbon-containing layer can be grown in an atmospheric or near-atmospheric SEG chamber at a process temperature of about 650°C ± 50°C. Therefore, in an embodiment where the carbon-containing layer 501 includes Si:C:P, a three-layer structure including Si:P (heavy n-doped region 201), Si:C:P (carbon-containing layer 501) and Si:As (doped extension region 202) is formed. Such a three-layer structure can cause arsenic to diffuse away from the channel region 205 and toward the heavily n-doped region 201.

[0056] In some embodiments, n-doped semiconductor materials can be formed as part of a nanowire structure in regions of the nanowire structure that are not accessible via conventional ion implantation techniques. Figure 6 as well as 7A to 7E The formation of one such embodiment is described.

[0057] Figure 6 is a flow chart of a fabrication process 600 for forming a nanowire structure 700 according to various embodiments of the present disclosure. 7A to 7E is a schematic cross-sectional view of a nanowire structure 700 corresponding to various stages of process 600 according to an embodiment of the present disclosure. Although process 600 is depicted as being used to form an n-doped region in a nanowire structure, process 600 may also be used to form other structures on a substrate.

[0058] Process 600 begins at operation 601, such as Fig. 7A , wherein alternating silicon layers 710 and silicon germanium (SiGe) layers are formed on a bulk semiconductor substrate 701. The bulk semiconductor substrate 701 may be formed of silicon, silicon germanium, or any other suitable bulk crystalline semiconductor material. The silicon layers 710 and silicon germanium layers 720 may each be formed via a SEG process and typically include crystalline semiconductor materials.

[0059] In operation 602, as Figure 7BAs shown in FIG. 6 , the silicon layer 710 and the silicon germanium layer 720 are patterned and etched to expose vertical sidewalls 711 on the silicon layer 710 and vertical sidewalls 721 on the silicon germanium layer 720. In some embodiments, operation 602 includes a DRIE process.

[0060] In operation 603, as Figure 7C 706, the silicon germanium layer 720 is selectively etched inward from the vertical sidewalls 721 to form the cavity 706. In some embodiments, a chemical vapor etching (CVE) process is used to selectively remove the silicon germanium layer 720 relative to the silicon layer 710. For example, selective etching of SiGe relative to Si in a reduced pressure chemical vapor deposition reactor has been demonstrated in gaseous hydrochloric acid. Alternatively, an ex situ HF dip followed by an in situ GeH4 enhanced Si etch may be performed in operation 603 in an epitaxy reactor.

[0061] In operation 604, as Fig.7D As shown in FIG. 7 , a low dielectric constant material 704 is then conformally deposited on the main semiconductor substrate 701 . The low dielectric constant material 704 fills at least a portion of the cavity 706 .

[0062] In operation 605, as Fig. 7E , the low dielectric constant material 704 is patterned and etched to expose vertical sidewalls 711 on the silicon layer 710 and the filled cavity 706 on the silicon germanium layer 720. In some embodiments, operation 605 includes a DRIE process. The filled cavity 706 forms a spacer 702, wherein each spacer 702 is formed at an edge region 705 of the silicon germanium layer 720.

[0063] In operation 606, as Figure 7F 7 , a portion of the silicon layer 710 is selectively removed from the edge region 705 to form a cavity 706. The silicon may be removed from the edge region 705 via a CVE process, such as a CVE process that is selective to silicon relative to the spacer 702. In some embodiments, the CVE process may include one or more of a HCl-based CVE process, a HCl and GeH4-based CVE process, and / or a Cl2-based CVE process.

[0064] In operation 607, Figure 7G , n-doped silicon material 718 is grown via a SEG process in cavity 706. In some embodiments, the n-dopant is arsenic, and the n-doped silicon material includes Si:As. In such embodiments, the SEG process of operation 605 may be substantially similar to the SEG process of operation 305 in process 300 described above.

[0065] In an alternative embodiment, the spacers 702 may be formed by selectively oxidizing portions of the silicon germanium layer 720 rather than selectively etching portions of the silicon germanium layer 720 that are subsequently filled with the low dielectric constant material 704 .

[0066] Implementation of process 600 enables formation of a nanowire structure 700 that includes a doped region, namely, a cavity 706 filled with an n-doped silicon material 708. Note that the doped region described above is not accessible by line-of-sight ion implantation techniques, since cavity 706 is disposed between the existing structure of nanowire structure 700 and the bulk semiconductor portion of semiconductor substrate 701. Therefore, such a doped region cannot be formed via conventional techniques.

[0067] Figure 8 Another embodiment of the present disclosure is shown. The skilled person will recognize that Figure 8 The method 800 shown in FIG. 8 can be combined with the process 300 or the process 600. Figure 8 as well as FIG. 4A to FIG. 4E , method 800 begins at 801, where a semiconductor substrate is provided for processing. The semiconductor substrate has semiconductor material thereon. As used in this specification and the appended claims, the term "providing" means placing a substrate into a position for processing. For example, the substrate can be placed in a first processing chamber for processing.

[0068] At operation 802, an anisotropic etching process is performed on the semiconductor material on the semiconductor substrate. The anisotropic etching process exposes a surface in the semiconductor material. In some embodiments, operation 802 is not performed. The exposed surface of some embodiments is disposed between an existing structure of the semiconductor device and a bulk semiconductor portion of the semiconductor substrate on which the semiconductor material is formed.

[0069] At operation 803, an isotropic etching process is performed on the exposed sidewalls to recess the semiconductor material disposed between the existing structure and the bulk semiconductor portion of the substrate. The sidewalls are recessed a distance to form a cavity. The amount of sidewall recessing may vary based on, for example, isotropic etching conditions.

[0070] At operation 804, a distance that the semiconductor material has been recessed by the isotropic etching process is determined. The recess distance may be measured by any suitable technique known to a skilled artisan. In some embodiments, the recess distance is determined by refractometry.

[0071] At operation 805, a layer of deposited material is formed on the cavity surface via a selective epitaxial growth (SEG) process. Between forming the cavity and SEG, the substrate of some embodiments does not undergo a pre-cleaning process. In some embodiments, between forming the cavity and SEG, the substrate is not exposed to atmospheric conditions or oxidizing conditions.

[0072] The SEG process of some embodiments is adjusted based on the recess distance from a predetermined method. For example, if the predetermined method is configured for The actual measured depth of the depression is The SEG conditions can then be changed to grow enough film to compensate for the difference. In some embodiments, the SEG process is adjusted to perform more than one type of growth. For example, if the recess depth is greater than a predetermined limit, the SEG process can begin by depositing silicon before forming the doped deposited material.

[0073] In one or more embodiments, operations 803, 804, and 805 are integrated by using advanced process control (APC). As used herein, the term "integrated" means that lateral push and epitaxial growth are performed in the same platform (under vacuum processing). At operation 804, integrated metrology can be used to determine the amount of recess distance. In some embodiments, the integrated metrology is performed in situ. Once the recess distance has been determined by the integrated metrology, the measurement results are fed to the epitaxial tool so that compensation can be performed (e.g., the thickness / composition of the first epitaxial layer can be adjusted accordingly). In some embodiments, the advanced process control includes one or more of scatterometry (i.e., optical critical dimension (OCD) metrology), refractometry, ellipsometry, or electron beam.

[0074] refer to Fig. 9 , additional embodiments of the present disclosure are directed to a processing tool 900 for performing the methods described herein. Fig. 9 A system 900 is shown that can be used to process substrates according to one or more embodiments of the present disclosure. The system 900 can be referred to as a cluster tool. The system 900 includes a central transfer station 910 having a robot 912 therein. The robot 912 is shown as a single leaf robot; however, one skilled in the art will recognize that other robot 912 configurations are within the scope of the present disclosure. The robot 912 is configured to move one or more substrates between chambers connected to the central transfer station 910.

[0075] At least one pre-clean / buffer chamber 920 is connected to the central transfer station 910. The pre-clean / buffer chamber 920 may include one or more of a heater, a radical source, or a plasma source. The pre-clean / buffer chamber 920 may be used as a holding area for a single semiconductor substrate or for a cassette of wafers for processing. The pre-clean / buffer chamber 920 may perform a pre-cleaning process or may preheat a substrate for processing or may simply be a staging area for a process sequence. In some embodiments, there are two pre-clean / buffer chambers 920 connected to the central transfer station 910.

[0076] exist Fig. 9 In the illustrated embodiment, the pre-clean chamber 920 can be used as a pass-through chamber between the factory interface 905 and the central transfer station 910. The factory interface 905 can include one or more robots 906 for moving substrates from the cassette to the pre-clean / buffer chamber 920. The robot 912 can then move the substrates from the pre-clean / buffer chamber 920 to other chambers within the system 900.

[0077] The first processing chamber 930 may be connected to the central transfer station 910. The first processing chamber 930 may be configured as an anisotropic etch chamber and may be in fluid communication with one or more reactive gas sources to provide one or more flows of reactive gas to the first processing chamber 930. The substrate may be moved to and from the deposition chamber 930 by the robot 912 passing through the isolation valve 914.

[0078] The processing chamber 940 can also be connected to the central transfer station 910. In some embodiments, the processing chamber 940 comprises an isotropic etching chamber and is in fluid communication with one or more reactive gas sources to provide reactive gas flow to the processing chamber 940 to perform an isotropic etching process. The substrate can be moved to and from the deposition chamber 940 by the robot 912 through the isolation valve 914.

[0079] Processing chamber 945 may also be connected to central transfer station 910. In some embodiments, processing chamber 945 is of the same type as processing chamber 940 and is configured to perform the same process as processing chamber 940. This arrangement may be useful in situations where the process occurring in processing chamber 940 takes significantly longer than the process in processing chamber 930.

[0080] In some embodiments, the processing chamber 960 is connected to the central transfer station 910 and is configured to function as a selective epitaxial growth chamber. The processing chamber 960 can be configured to perform one or more different epitaxial growth processes.

[0081] In some embodiments, the anisotropic etching process occurs in the same processing chamber as the isotropic etching process. In such embodiments, processing chambers 930 and 960 can be configured to perform etching processes on two substrates simultaneously, and processing chambers 940 and 945 can be configured to perform a selective epitaxial growth process.

[0082] In some embodiments, each of the process chambers 930, 940, 945, and 960 is configured to perform a different portion of a process recipe. For example, process chamber 930 may be configured to perform an anisotropic etch process, process chamber 940 may be configured to perform an isotropic etch process, process chamber 945 may be configured as a metrology station or to perform a first selective epitaxial growth process, and process chamber 960 may be configured to perform a second selective epitaxial growth process. The skilled artisan will recognize that the number and arrangement of the various process chambers on a tool may vary, and Fig. 9 The embodiment shown in FIG. 1 represents only one possible configuration.

[0083] In some embodiments, the processing system 900 includes one or more metrology stations. For example, the metrology station can be located within the pre-clean / buffer chamber 920, within the central transfer station 910, or within any of the various processing chambers. The metrology station can be located anywhere within the system 900 that allows the recess distance to be measured without exposing the substrate to an oxidizing environment.

[0084] At least one controller 950 is coupled to one or more of the central transfer station 910, pre-clean / buffer chamber 920, process chambers 930, 940, 945, or 960. In some embodiments, there is more than one controller 950 connected to each chamber or station, and a main control processor is coupled to each of the individual processors to control the system 900. The controller 950 can be one of any form of general purpose computer processor, microcontroller, microprocessor, etc., which can be used in an industrial environment to control the various chambers and sub-processors.

[0085] At least one controller 950 may have a processor 952, a memory 954 coupled to the processor 952, an input / output device 956 coupled to the processor 952, and support circuits 958 for communication between different electronic components. The memory 954 may include one or more of a temporary memory (e.g., random access memory) and a non-temporary memory (e.g., storage).

[0086] The processor's memory 954 or computer readable medium may be one or more of readily available memories such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. The memory 954 may store instruction sets that are operable by the processor 952 to control parameters and components of the system 900. Support circuits 958 are coupled to the processor 952 for supporting the processor in a conventional manner. For example, the circuits may include cache memory, power supplies, clock circuits, input / output circuits, subsystems, and the like.

[0087] The process may be typically stored in a memory as a software program that, when executed by a processor, causes the processing chamber to perform the process of the present disclosure. The software program may also be stored and / or executed by a second processor (not shown) that is remote from the hardware controlled by the processor. Some or all of the methods of the present disclosure may also be performed in hardware. Thus, the process may be implemented in software and executed using a computer system, implemented in hardware as, for example, an application specific integrated circuit or other type of hardware implementation, or implemented as a combination of software and hardware. When executed by a processor, the software program converts a general purpose computer into a special purpose computer (controller) that controls the chamber operations so that the process is performed.

[0088] In some embodiments, the controller 950 has one or more configurations for performing various processes or sub-processes to perform the method. The controller 950 can be connected to the intermediate component and configured to operate the intermediate component to perform the functions of the method. For example, the controller 950 can be connected to one or more of a gas valve, an actuator, a motor, a slit valve, a vacuum control, etc. and configured to control one or more of the gas valve, the actuator, the motor, the slit valve, the vacuum control, etc.

[0089] The controller 950 of some embodiments has one or more configurations selected from the following: a configuration for moving a substrate on a robot between multiple processing chambers and a metrology station; a configuration for performing an anisotropic etching process on a substrate; a configuration for performing an isotropic etching process on a substrate in a processing chamber; a configuration for performing analysis to determine recesses in a semiconductor material in a metrology station; a configuration for performing a selective epitaxial growth process in an epitaxial chamber; a configuration for adjusting a selective epitaxial growth process plan to account for recesses in a semiconductor material; a configuration for performing a bulk selective epitaxial growth process; and a configuration for loading and / or unloading a substrate from a system.

[0090] In summary, one or more embodiments of the present disclosure provide systems and techniques for forming a region of doped semiconductor material disposed between an existing structure of a semiconductor device and a bulk semiconductor portion of a semiconductor substrate on which a doped silicon-containing material is formed. In embodiments where the semiconductor device comprises a finFET device, the doped semiconductor material forms a doped source and / or drain extension disposed between a gate spacer of the finFET and a bulk semiconductor portion of a semiconductor substrate on which the doped source or drain extension is disposed.

[0091] References throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearance of phrases such as "in one or more embodiments," "in certain embodiments," "in an embodiment," or "in an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Additionally, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0092] Although the disclosure herein has been described with reference to specific embodiments, it will be understood by those skilled in the art that the described embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations may be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Therefore, the disclosure may include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method for forming a semiconductor device, the method comprising: performing an anisotropic etching process on a semiconductor material on a semiconductor substrate to expose a surface of the semiconductor material, the surface being disposed between an existing structure of the semiconductor device and a bulk semiconductor portion of the semiconductor substrate on which the semiconductor material is formed, the semiconductor substrate being located in a first processing chamber; performing an isotropic etching process on the exposed sidewalls to recess the semiconductor material disposed between the existing structure and the bulk semiconductor portion of the semiconductor substrate by a distance to form a cavity; moving the semiconductor substrate from the first processing chamber to a second processing chamber without exposing the semiconductor substrate to oxidizing conditions; measuring in situ the distance the semiconductor material has been recessed after the isotropic etch; as well as forming a layer of deposition material on a surface of the cavity using a selective epitaxial growth (SEG) process in the second processing chamber, the semiconductor substrate not undergoing a pre-cleaning process between forming the cavity and SEG, the SEG process taking into account the distance that the semiconductor material has been recessed after the isotropic etch, The isotropic etching process, the SEG process and the in-situ measurement are performed in a single platform under vacuum processing.

2. The method of claim 1 further comprising adjusting the SEG process based on the distance that the semiconductor material has been recessed.

3. The method of claim 2, further comprising forming a doped region on the layer of the deposited material via a selective epitaxial growth (SEG) process, wherein the doped region comprises one or more of phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), lithium (Li), boron (B), aluminum (Al), gallium (Ga), and indium (In), and the doped region has a relative humidity of about 1 x 10 20 Atom / cm 3 About 1x 10 22 Atom / cm 3 The dopant concentration is within the range of .

4. The method of claim 1, wherein the isotropic etching occurs in a first processing chamber, and further comprising moving the substrate from the first processing chamber to a second processing chamber for the SEG process.

5. The method of claim 1, further comprising epitaxially growing a portion of the semiconductor material prior to forming the layer of deposited material.

6. The method of claim 1 wherein the distance that the semiconductor material has been recessed is measured by refractometry.

7. The method of claim 1, wherein the isotropic etching process comprises an etching process that is selective to the semiconductor material.

8. The method of claim 7, wherein the isotropic etching process comprises a chemical vapor etching process, the chemical vapor etching process comprising exposing the exposed sidewalls to at least one of HCl, GeH4, or / and Cl2.

9. The method of claim 1, wherein forming the layer of the deposition material comprises filling the cavity with the deposition material.

10. The method of claim 1, further comprising, before forming the layer of deposition material, depositing a carbon-containing material on the surface of the cavity, wherein the carbon-containing material comprises a silicon carbon phosphorus (SiCP) material.

11. The method of claim 10, wherein the SiCP material comprises carbon in the range of about 0.1 to 2.0 atomic percent and 20 Atom / cm 3 Up to 1x10 21 Atom / cm 3 Phosphorus in the range.

12. The method of claim 1, wherein performing the isotropic etching process on the exposed sidewalls to form the cavity in the semiconductor material comprises removing semiconductor material until a portion of the semiconductor material comprising phosphorus-doped bulk semiconductor material is exposed.

13. The method of claim 1 , wherein the deposited material comprises an n-type dopant, the n-type dopant comprises arsenic (As), and the selective epitaxial growth (SEG) process comprises exposing the surface of the cavity to at least one of AsCl 3 , TBA or AsH 3 and dichlorosilane (DCS), HCl, SiH 4 , Si 2 H 6 or Si 4 H 10 at least one of.

14. The method of claim 13, wherein forming the layer of deposited material comprises filling the cavity with an arsenic-doped material having an arsenic concentration sufficient to produce a targeted tensile strain in the deposited material.

15. The method of claim 1, wherein the deposited material comprises a p-type dopant, the p-type dopant comprises boron (B), and the selective epitaxial growth (SEG) process comprises exposing the surface of the cavity to one or more of borane, diborane, a plasma of borane, or a plasma of diborane. 16 . The method of claim 1 , wherein the layer of additional deposition material is formed without exposing the layer of deposition material formed on the surface of the cavity to air.

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