Method and device for improving alignment precision of metal bonding in three directions

Abstract

The invention relates to the technical field of integrated circuit manufacturing, and particularly discloses a method and device for improving alignment precision of metal bonding in three directions, and the method comprises the steps: manufacturing an anisotropically etched groove and a first metal bonding bump on a first wafer; manufacturing passivation layer bumps corresponding to the grooves and second metal bonding bumps corresponding to the first metal bonding bumps on a second wafer; and positioning through the grooves and the passivation layer bumps, and bonding the first wafer and the second wafer together by using the first metal bonding bumps and the second metal bonding bumps to form a bonding device. According to the method, photoetching interlayer alignment and the alignment precision of a bonding alignment machine in the wafer production process are considered, the alignment deviation after bonding can be smaller than 5 microns, the available area of a device structure is increased, the size of a designed chip can be smaller, cost is saved, product competitiveness is improved, meanwhile, the amount of compression of bonding can be controlled, and production efficiency is improved. Therefore, the in-chip consistency of the product is improved, and the wafer yield is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a method and a device for improving the alignment accuracy of metal bonding in three directions. Background Art

[0002] Metal bonding is a process that connects two or more wafers together through metal, and is widely used in the manufacture of semiconductor devices and micro-electromechanical devices. The key to this technology is to ensure that the two wafers are accurately aligned during the bonding process to ensure the reliability of the electrical connection and the performance of the device. However, due to the extremely small size and thickness of the wafers, as well as the physical and chemical effects during the metal bonding process, accurate alignment becomes very difficult.

[0003] The existing technical solutions related to metal bonding are mainly to achieve precise alignment of wafers through precision positioning equipment and specific bonding processes; and to control process processing conditions through a very narrow process window to improve and reduce changes in bonding shift positions and compression caused by bonding.

[0004] Although existing solutions have improved the alignment accuracy of metal bonding to a certain extent, there are still some problems and limitations. First, these methods usually require complex equipment and precise operations, which increases manufacturing costs and difficulty. Second, these methods have high requirements on environmental conditions and operators, and any slight error may lead to reduced alignment accuracy. Finally, these methods have limited effect on preventing wafers from sliding during the bonding process, which may affect the quality of bonding and the performance of the device.

[0005] Currently, the metal eutectic bonding slip causes the maximum alignment deviation after metal bonding to reach 10um, and the size within this deviation range leads to waste. Furthermore, the spacing between the device layer and the COMS wafer is one of the key parameters of product performance and directly affects product performance. Currently, due to the uncontrollability of the metal bonding degree, the uniformity of the spacing within the wafer is poor, and even some areas are over-bonded, resulting in product performance failure and scrap.

[0006] Based on this technical background, the present invention proposes a method and a device for improving the alignment accuracy of metal bonding in three directions. Summary of the invention

[0007] In view of the shortcomings of the prior art, the present invention proposes a method and device for improving the alignment accuracy of metal bonding in three directions. The method takes into account the inter-layer alignment of the lithography and the alignment accuracy of the bonding alignment machine during the wafer production process, and can make the alignment deviation after bonding less than 5um, so that the available area of ​​the device structure is increased, the chip size can be designed to be smaller, cost is saved, and product competitiveness is increased. At the same time, metal bonding can not only control the alignment deviation, but also control the bonding compression amount, so as to improve the consistency of the product within the chip and improve the wafer yield.

[0008] In order to achieve the above object, the first aspect of the present invention provides a method for improving the alignment accuracy of metal bonding in three directions, comprising:

[0009] Forming anisotropically etched grooves and first metal bonding bumps on a first wafer;

[0010] Fabricating, on a second wafer, a passivation layer bump corresponding to the groove and a second metal bonding bump corresponding to the first metal bonding bump;

[0011] The first wafer and the second wafer are bonded together by positioning through the groove and the passivation layer bump, using the first metal bonding bump and the second metal bonding bump to form a bonding device.

[0012] The second aspect of the present invention provides a device for improving the alignment accuracy of metal bonding in three directions, which is manufactured by the above method, and is characterized by comprising:

[0013] A first wafer is provided with anisotropically etched grooves and first metal bonding bumps;

[0014] A second wafer is provided with a passivation layer bump corresponding to the groove, and a second metal bonding bump;

[0015] The first wafer and the second wafer are positioned by the groove and the passivation layer bump, and are bonded together by using the first metal bonding bump and the second metal bonding bump to form a bonding device.

[0016] The technical effects of the present invention include:

[0017] (1) The method proposed in the present invention for improving the alignment accuracy of metal bonding in three directions takes into account the inter-layer alignment of the photolithography and the alignment accuracy of the bonding alignment machine during the wafer production process, and can make the alignment deviation after bonding less than 5um, thereby increasing the available area of ​​the device structure and making the chip size smaller, saving costs and increasing product competitiveness. At the same time, metal bonding can not only control the alignment deviation, but also control the bonding compression amount, thereby improving the consistency within the product chip and improving the wafer yield.

[0018] (2) The method for improving the alignment accuracy of metal bonding in three directions proposed in the present invention proposes technical issues such as how to improve the alignment accuracy of metal bonding without relying on complex equipment and high-precision operations, how to increase the process window to reduce process difficulty, and how to effectively prevent the wafer from sliding during the bonding process to improve bonding quality and device performance.

[0019] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, wherein like reference numerals generally represent like components throughout the exemplary embodiments of the present invention.

[0021] Figure 1 The present invention is a flow chart of a method for improving the alignment accuracy of metal bonding in three directions.

[0022] Figure 2 A schematic diagram of the process of making anisotropically etched grooves and first metal bonding bumps on a first wafer in the method for improving the alignment accuracy of metal bonding in three directions proposed by the present invention.

[0023] Figure 3 A schematic diagram of the process of making passivation layer bumps and second metal bonding bumps on a second wafer in the method for improving the alignment accuracy of metal bonding in three directions proposed by the present invention.

[0024] Figure 4 The present invention is a schematic structural diagram of a specific implementation of a device for improving the alignment accuracy of metal bonding in three directions.

[0025] Description of reference numerals:

[0026] 100 - second wafer, 110 - second metal bonding bump, 120 - passivation layer bump;

[0027] 200 - a first wafer, 210 - an integrated MEMS chip, 220 - a first metal bonding bump, 230 - a groove, 240 - a largest mass block. DETAILED DESCRIPTION

[0028] The preferred embodiments of the present invention will be described in more detail below. Although the preferred embodiments of the present invention are described below, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0029] In the present invention, unless otherwise specified, the directional words used, such as "upper and lower", generally refer to the upper and lower parts of the device in normal use, and "inside and outside" refer to the outline of the device. In addition, the terms "first, second, third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first, second, third" may explicitly or implicitly include one or more of the features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0030] The present invention provides a method for improving the alignment accuracy of metal bonding in three directions, such as Figure 1 As shown, including:

[0031] Anisotropically etched grooves 230 and first metal bonding bumps 220 are fabricated on the first wafer 200;

[0032] Manufacturing a passivation layer bump 120 corresponding to the groove 230 and a second metal bonding bump 110 corresponding to the first metal bonding bump 220 on the second wafer 100;

[0033] The first wafer 200 and the second wafer 100 are bonded together by positioning the grooves 230 and the passivation layer bumps 120 using the first metal bonding bumps 220 and the second metal bonding bumps 110 to form a bonded device.

[0034] The method of the present invention takes into account the inter-layer alignment of the lithography and the alignment accuracy of the bonding alignment machine during the wafer production process, and can make the alignment deviation after bonding less than 5um, so that the available area of ​​the device structure is increased, the chip size can be designed to be smaller, cost is saved, and product competitiveness is increased. At the same time, metal bonding can not only control the alignment deviation, but also control the bonding compression amount, so as to improve the consistency within the product chip and improve the wafer yield.

[0035] According to the present invention, forming anisotropically etched grooves 230 and first metal bonding bumps 220 on a first wafer 200 includes:

[0036] By using anisotropic etching technology, a groove 230 is etched on the surface of the first wafer 200;

[0037] A metal layer is deposited on the surface of the first wafer 200 , and the metal layer is fabricated into first metal bonding bumps 220 through photolithography and etching techniques.

[0038] According to the present invention, manufacturing the passivation layer bump 120 corresponding to the groove 230 and the second metal bonding bump 110 corresponding to the first metal bonding bump 220 on the second wafer 100 includes:

[0039] A passivation layer is deposited on the surface of the second wafer 100, and the passivation layer is made into a passivation layer bump 120 corresponding to the groove 230 by photolithography and etching technology;

[0040] A metal layer is deposited on the surface of the second wafer 100 , and the metal layer is fabricated into second metal bonding bumps 110 corresponding to the first metal bonding bumps 220 through photolithography and etching techniques.

[0041] According to the present invention, the anisotropic etching is dry etching or wet chemical etching.

[0042] According to the present invention, the materials of the first metal bonding bump 220 and the second metal bonding bump 110 include at least one of titanium, aluminum, germanium, gold, copper and tin;

[0043] The material of the passivation layer bump 120 is silicon oxide, silicon nitride, aluminum or titanium.

[0044] Preferably, the design and layout of the groove 230 are determined according to the position of the passivation layer bump 120 on the second wafer 100, so as to ensure that the passivation layer bump 120 is accurately stuck in the groove 230 during bonding alignment;

[0045] The depth of the groove 230 depends on the capacitance between the two wafer surfaces required by the design;

[0046] The height of the passivation layer depends on the tolerance value of the photolithography exposure alignment accuracy of the entire process and the overall size of the bumps on the second wafer 100;

[0047] The expression of the capacitance between the two wafer surfaces is:

[0048] C = εS / 4πke;

[0049] Where C is the capacitance, which is determined by the product design, ε is the dielectric constant, S is the plate area of ​​the two wafer surfaces that form the effective capacitance, e is the distance between the two wafer surfaces, and k is the electrostatic force constant;

[0050] The calculation formula for the groove depth is:

[0051] a=be;

[0052] Wherein, a is the depth of the groove, and b is the height of the passivation layer.

[0053] In the present invention, if the first wafer 200 is integrated with a MEMS chip, it includes a plurality of mass blocks, such as Figure 4 As shown, at this time, the area of ​​the plates that form the effective capacitor between the two wafer surfaces can be represented by the area of ​​the largest mass block 240 .

[0054] According to the present invention, the expression of the maximum alignment deviation after bonding is:

[0055] (xy) / 2;

[0056] Wherein, x is the bottom width of the groove 230 , and y is the width of the passivation layer bump 120 .

[0057] In the present invention, the value of x is generally greater than the value of y, and both are set before the groove 230 and the passivation layer bump 120 are formed.

[0058] In the present invention, the groove 230 is formed by forming a photoresist on the first wafer 200, and after exposure and development, it is formed by wet etching; the passivation layer bump 120 is formed by first forming a passivation material layer on the second wafer 100, and then forming a photoresist on the passivation material layer, and after exposure and development, it is formed by dry etching.

[0059] According to the present invention, the calculation formula for the amount of metal compression after bonding is:

[0060] (c+d)-(ba);

[0061] Wherein, c is the thickness of the first metal bonding bump 220 , and d is the thickness of the second metal bonding bump 110 .

[0062] The method of the present invention proposes technical issues such as how to improve the alignment accuracy of metal bonding without relying on complex equipment and high-precision operations, how to increase the process window to reduce process difficulty, and how to effectively prevent wafer sliding during the bonding process to improve bonding quality and device performance.

[0063] The present invention also provides a device manufactured by the above method for improving the alignment accuracy of metal bonding in three directions, such as Figure 4 As shown, including:

[0064] A first wafer 200 is provided with anisotropically etched grooves 230 and first metal bonding bumps 220;

[0065] The second wafer 100 is provided with a passivation layer bump 120 corresponding to the groove 230 and a second metal bonding bump 110;

[0066] The first wafer 200 and the second wafer 100 are positioned through the grooves 230 and the passivation layer bumps 120 , and are bonded together using the first metal bonding bumps 220 and the second metal bonding bumps 110 to form a bonded device.

[0067] According to the present invention, the first wafer 200 is integrated with a MEMS chip;

[0068] The second wafer 100 is integrated with a CMOS chip.

[0069] The present invention will be described in more detail below through specific embodiments.

[0070] Example 1

[0071] like Figure 1 As shown, this embodiment provides a method for improving the alignment accuracy of metal bonding in three directions, which specifically includes the following steps:

[0072] 1) Anisotropically etched grooves 230 and first metal bonding bumps 220 are fabricated on a first wafer 200 (with a MEMS chip integrated therein), such as Figure 2 As shown:

[0073] First, a first wafer 200 suitable for the device layer is selected, and then a groove 230 with a certain depth and width is made on the surface of the first wafer 200 by etching technology including but not limited to dry etching, wet chemical etching and other process technologies, wherein the depth is a and the bottom width is x, wherein the value of a depends on the size of the inter-surface capacitance required by the design, and the value of b depends on the tolerance value of the alignment accuracy of the whole process lithography exposure and the size of the bump of the second wafer 100; the design and layout of the groove 230 should be determined according to the position of the passivation layer bump 120 on the second wafer 100, so as to ensure that the passivation layer bump 120 can be accurately stuck in the groove during bonding alignment;

[0074] Secondly, a first metal bonding bump 220 with a thickness of c is formed on the first wafer 200: a layer of metal is deposited, including but not limited to titanium, aluminum, germanium, gold, copper, tin and the like, and the metal layer is formed into a desired shape and size by photolithography and etching techniques;

[0075] 2) The second wafer 100 (with integrated CMOS chip) uses the passivation layer to make passivation layer bumps 120 (whose height is b and width is y) and second metal bonding bumps 110, such as Figure 3 As shown:

[0076] First, a second wafer 100 is selected, and a passivation layer bump 120 corresponding to 230 on the first wafer 200 is made on its surface. The passivation layer bump 120 is formed by depositing a layer of other materials, including but not limited to silicon oxide, silicon nitride, aluminum, titanium and the like, on the surface of the second wafer 100, and then the passivation layer is made into a desired shape and size by photolithography and etching techniques;

[0077] Secondly, a second metal bonding bump 110 is made on the second COMS wafer 100, and its height is d: a layer of metal is deposited, including but not limited to titanium, aluminum, germanium, gold, copper, tin and other metals that can be used for bonding, and the metal layer is made into a desired shape and size through photolithography and etching technology;

[0078] 3) Metal bonding is performed on the first wafer 200 and the second wafer 100:

[0079] During bonding alignment, after the bonding alignment machine equipment is optically aligned, the actual alignment accuracy is less than 2um. The first wafer 200 integrated with the MEMS chip and the second wafer 100 integrated with the COMS chip are aligned through the alignment mark. At this time, the passivation layer bump 120 is aligned with the groove 230: during metal bonding, the two aligned wafers are pressed together so that the passivation layer bump 120 falls into the groove 230; when the two wafers are shifted during the metal bonding process, the structure of the passivation layer bump 120 and the groove 230 can limit the wafer shifting phenomenon, and the maximum alignment deviation after bonding also depends on the values ​​of x and y, and the maximum alignment deviation is (xy) / 2;

[0080] In the vertical direction, the metal bonding is mutually soluble. The amount of metal compression after bonding can be controlled according to a and x as well as the metal heights b and y on both sides. The value of the metal eutectic bonding compression is calculated as (c+d)-(ba).

[0081] In this embodiment, 1) the height b of the passivation layer bump 120 and the depth a of the groove 230 determine that after the MEMS device is bonded, the maximum height of the gap between the device layer structure and the COMS wafer is ba, and the gap will not be reduced due to (overbonding), so that the uniformity of the device key dimension out-of-plane gap in the wafer is improved; 2) the width y of the passivation layer bump 120 and the bottom width x of the groove 230, the two sizes determine that the maximum alignment offset after bonding is (xy) / 2, so that the offset of the metal eutectic bonding is reduced. Small and controllable; 3) The second metal bonding bump 110 of the second wafer 100 of the integrated COMS chip has a height d, the passivation layer bump 120 has a height b, the first metal bonding bump 220 of the first wafer 200 of the integrated MEMS chip has a thickness c, and the groove structure 230 has a depth a. After the second metal bonding bump 110 and the first metal bonding bump 220 are bonded, the value of the metal eutectic bonding compression amount is (c+d)-(ba), so that the metal bonding degree (metal compression amount) can be controlled and the process window is increased.

[0082] In this embodiment, a device for improving the alignment accuracy of metal bonding in three directions is manufactured using the method of the present invention, such as Figure 4 As shown, through the technical means of this embodiment, under the condition of normal parameters of the metal bonding process, the alignment accuracy after metal bonding can be greatly improved, the metal bonding parameter window can be increased, the sliding of the wafer during the bonding process can be effectively prevented, the bonding quality can be improved, and the uniformity of key parameters in the MEMS device production process can be improved, the design size of the MEMS device can be smaller, and the cost can be reduced.

[0083] The method for improving the alignment accuracy of metal bonding in three directions proposed in the embodiment of the present invention takes into account the inter-layer alignment of the lithography and the alignment accuracy of the bonding alignment machine during the wafer production process. The alignment deviation after bonding can be less than 5um, so that the available area of ​​the device structure is increased, the chip size can be designed to be smaller, cost is saved, and product competitiveness is increased. At the same time, metal bonding can not only control the alignment deviation, but also control the bonding compression amount, thereby improving the consistency within the product chip and improving the wafer yield.

[0084] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A method for improving the alignment accuracy of metal bonding in three directions, characterized in that: include: Forming anisotropically etched grooves and first metal bonding bumps on a first wafer; Fabricating, on a second wafer, a passivation layer bump corresponding to the groove and a second metal bonding bump corresponding to the first metal bonding bump; The first wafer and the second wafer are bonded together by positioning through the groove and the passivation layer bump, using the first metal bonding bump and the second metal bonding bump to form a bonding device.

2. The method according to claim 1, characterized in that Producing anisotropically etched grooves and first metal bonding bumps on a first wafer includes: Etching the groove on the surface of the first wafer by anisotropic etching technology; A metal layer is deposited on the surface of the first wafer, and the metal layer is made into first metal bonding bumps through photolithography and etching techniques.

3. The method according to claim 1, characterized in that The method of manufacturing a passivation layer bump corresponding to the groove and a second metal bonding bump corresponding to the first metal bonding bump on the second wafer includes: Depositing a passivation layer on the surface of the second wafer, and manufacturing the passivation layer into passivation layer bumps corresponding to the grooves by photolithography and etching techniques; A metal layer is deposited on the surface of the second wafer, and the metal layer is made into second metal bonding bumps corresponding to the first metal bonding bumps through photolithography and etching techniques.

4. The method according to claim 1, characterized in that: The anisotropic etching is dry etching or wet chemical etching.

5. The method according to claim 1, characterized in that The materials of the first metal bonding bump and the second metal bonding bump include at least one of titanium, aluminum, germanium, gold, copper and tin; The material of the passivation layer bumps is silicon oxide, silicon nitride, aluminum or titanium.

6. The method according to claim 1, characterized in that The design and layout of the groove are determined according to the position of the passivation layer bump on the second wafer, so as to ensure that the passivation layer bump is accurately stuck in the groove during bonding alignment; The depth of the groove depends on the capacitance between the two wafer surfaces required by the design; The height of the passivation layer depends on the tolerance value of the alignment accuracy of the whole set of process lithography exposure and the overall size of the bumps on the second wafer; The expression of the capacitance between the two wafer surfaces is: C = εS / 4πke; Among them, C is the capacitance, which is determined by the product design, ε is the dielectric constant, S is the plate area of ​​the two wafer surfaces facing each other to form an effective capacitor, e is the distance between the two wafer surfaces, and k is the electrostatic force constant. The calculation formula for the depth of the groove is: a=be; Wherein, a is the depth of the groove, and b is the height of the passivation layer.

7. The method according to claim 1, characterized in that The expression of the maximum alignment deviation after bonding is: (xy) / 2; Wherein, x is the bottom width of the groove, and y is the width of the passivation layer bump.

8. The method according to claim 6, characterized in that The calculation formula for the metal compression after bonding is: (c+d)-(ba); Wherein, c is the thickness of the first metal bonding bump, and d is the thickness of the second metal bonding bump.

9. A device for improving the alignment accuracy of metal bonding in three directions manufactured by the method according to any one of claims 1 to 8, characterized in that: include: A first wafer is provided with anisotropically etched grooves and first metal bonding bumps; A second wafer is provided with a passivation layer bump corresponding to the groove, and a second metal bonding bump; The first wafer and the second wafer are positioned by the groove and the passivation layer bump, and are bonded together by using the first metal bonding bump and the second metal bonding bump to form a bonding device.

10. The device according to claim 9, characterized in that The first wafer is integrated with a MEMS chip; The second wafer is integrated with a CMOS chip.

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