Real-time phase error detection in quadrature demodulators

Abstract

An apparatus for detecting real-time phase and offset errors of a Q demodulator includes: an RF signal path configured to receive an RF signal from an RF component; a first chopper for chopping the RF signal at a first frequency to generate a chopped RF signal; an LO signal path configured to receive an LO signal; a second chopper for chopping the LO signal at a second frequency to generate a chopped LO signal; and a summing mechanism for combining the chopped LO signal and the chopped RF signal into a combined signal. The apparatus further comprises a Q demodulator and at least two filters, the Q demodulator comprising: a phase shifter configured to shift a phase of the combined signal and a phase of the LO signal; and a mixer configured to multiply the shifted combined signal with the shifted LO signal to generate a baseband signal, and the at least two filters configured to extract different signals included in the baseband signal for analysis.

Description

Technical Field

[0001] The present disclosure relates to an apparatus and method for detecting real-time phase and offset errors in a quadrature demodulator (Q-demodulator). Specifically, the present disclosure discloses a circuit comprising: two choppers for RF signals and LO signals before the Q-demodulator for generating a baseband signal; and several filters for extracting different signals from the baseband signal for analysis and compensation. Background Art

[0002] Modulators and demodulators are used to transmit data over different frequency bands in various RF communication circuits. In circuits using quadrature modulators and / or demodulators, it is necessary to have both in-phase and quadrature versions of the RF signal. In order to extract the quadrature components of the signal, the demodulator's radio frequency (RF) and local oscillator (LO) input signals are offset 90 degrees from each other.

[0003] If there is any error in the 90 degree phase shift, the output of the demodulator will also contain errors. Therefore, a technique for detecting phase shift errors in a quadrature demodulator is needed. Summary of the invention

[0004] In one aspect, an apparatus for detecting phase error includes: an RF signal path configured to receive an RF signal from an RF component; a first chopper including a chopping switch for chopping the RF signal at a first frequency to generate a chopped RF signal; an LO signal path configured to receive an LO signal; a second chopper including a chopping switch for chopping the LO signal at a second frequency to generate a chopped LO signal; a summing mechanism (e.g., an adder) disposed on the RF path and configured to combine the chopped LO signal with the chopped RF signal into a combined signal. The apparatus also includes an orthogonal demodulator (Q demodulator) including: a phase shifter configured to shift the phase of the combined signal to generate a shifted combined signal, and configured to shift the phase of the LO signal to generate a shifted LO signal, so that the phase difference between the combined signal and the LO signal is set to 90 degrees; a mixer configured to multiply the shifted combined signal with the shifted LO signal to generate a baseband signal; and at least one filter configured to extract a signal contained in the baseband signal.

[0005] In one embodiment, the phase shifter includes a high pass filter configured to shift the phase of the combined signal; and a low pass filter configured to shift the phase of the LO signal.

[0006] Specifically, the phase shifter includes: a first amplifier configured to amplify the combined signal and provide the amplified combined signal to a high pass filter; and a second amplifier configured to amplify the LO signal and provide the amplified LO signal to a low pass filter. The first amplifier and the second amplifier can act as buffers. The first amplifier and the second amplifier are not required and can be omitted in some embodiments.

[0007] In another embodiment, the apparatus further comprises an amplifier configured to amplify the baseband signal output from the Q demodulator at a specific gain. The amplifier is not required and may be omitted in some embodiments.

[0008] In an embodiment, the apparatus further comprises an analog-to-digital converter (ADC) configured to digitize the baseband signal.

[0009] Furthermore, the apparatus may further comprise a digital signal processor (DSP) configured to extract the different signals to be analyzed.

[0010] Furthermore, the DSP includes a low pass filter (LPF) configured to output a circuit offset indicating a DC offset generated in the Q demodulator.

[0011] Furthermore, the apparatus includes an offset cancellation loop configured to feed back the circuit offset to the Q-demodulator to adjust the offset of the Q-demodulator so as to remove the offset error.

[0012] In addition, the DSP includes a band pass filter configured to pass the baseband signal of the first chopping frequency to output a desired signal indicating a result of the operation of the RF component.

[0013] In yet another embodiment, the RF component is a gyroscopic sensor, and the desired signal is indicative of an angular velocity measured by the gyroscopic sensor.

[0014] Furthermore, the DSP includes a bandpass filter configured to pass the RF signal of the second chopping frequency to extract an error signal indicating an amount of phase error generated in the Q-demodulator.

[0015] Furthermore, the apparatus includes a phase error cancellation loop configured to feed back an error signal to the Q-demodulator to adjust the phase of the Q-demodulator so as to remove the phase error.

[0016] The apparatus may further include an attenuator configured to reduce the amplitude of the chopped LO signal. Thus, the reduced amplitude of the chopped LO signal may be greater than, less than, or equal to the amplitude of the RF signal in the RF path.

[0017] In yet another embodiment, the apparatus includes: a low pass filter (LPF) configured to output a circuit offset indicating a DC offset generated in a Q-demodulator; and an offset cancellation loop configured to feed back the circuit offset to the Q-demodulator to adjust the offset of the Q-demodulator so as to remove the offset error.

[0018] Furthermore, the apparatus may include a bandpass filter configured to pass the RF signal of the first chopping frequency to output a desired signal indicating a result of the operation of the RF component.

[0019] The apparatus may further include: a bandpass filter configured to pass the RF signal of the second chopping frequency to extract an error signal indicating an amount of phase error generated in the Q-demodulator; and a phase error cancellation loop configured to feed back the error signal to the Q-demodulator to adjust the phase of the Q-demodulator so as to remove the phase error.

[0020] In another aspect, a method for detecting a phase error includes receiving an RF signal from an RF component into an RF signal path; chopping the RF signal at a first frequency to generate a chopped RF signal; receiving an LO signal from a local oscillator into the LO signal path; chopping the LO signal at a second frequency to generate a chopped LO signal; combining the chopped LO signal with the chopped RF signal into a combined signal; shifting the phase of the combined signal by a phase shifter in an orthogonal demodulator to generate a shifted combined signal, and shifting the phase of the LO signal to generate a shifted LO signal, so that a phase difference between the combined signal and the LO signal is set to 90 degrees; multiplying the shifted combined signal by a quadrature demodulator (Q-demodulator) with the shifted LO signal to generate a baseband signal; and extracting a signal contained in the baseband signal by at least one filter.

[0021] In one embodiment, the method further includes: filtering the baseband signal by a low pass filter to extract a circuit offset, the circuit offset representing a DC offset generated in the Q demodulator; and feeding back the circuit offset to the Q demodulator to adjust the offset of the Q demodulator so as to remove the offset error.

[0022] In another embodiment, the method further includes filtering the baseband signal by a bandpass filter having a center frequency equal to the first chopping frequency to output a desired signal, the desired signal indicating a result of the operation of the RF component.

[0023] In yet another embodiment, the method further includes: filtering the baseband signal by a bandpass filter having a center frequency equal to the second chopping frequency to extract an error signal indicating an amount of phase error generated in the Q demodulator; and feeding back the error signal to the Q demodulator to adjust the phase of the Q demodulator so as to remove the phase error.

[0024] Other aspects, advantages and salient features of the present disclosure will become more apparent to those skilled in the art from the following detailed description, which, taken in conjunction with the accompanying drawings, discloses exemplary embodiments of the present disclosure.

[0025] Before proceeding to the detailed description below, it may be helpful to set forth definitions of certain words and phrases used throughout this patent document: the terms "include" and "comprising" and their derivatives mean including but not limiting; the term "or" is inclusive, meaning "and / or"; the phrases "associated with" and "associated with" and their derivatives may mean including, (being) included in, interconnected with, containing, (being) contained in, connected to or connected with, coupled to or coupled with, communicable with, cooperating with, intertwined, side by side, adjacent to, (being) bound to or bound with, having, having the property of, etc.; and the term "controller" means any device, system, or part thereof that controls at least one operation, which device may be implemented in hardware, firmware, or software, or some combination of at least two thereof. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions of certain words and phrases are provided in this patent document, and it should be understood by those skilled in the art that in many, if not most instances, these definitions apply to prior and future uses of such defined words and phrases. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] For a more complete understanding of the present disclosure and its advantages, reference will now be made to the following description taken in conjunction with the accompanying drawings, wherein like reference numerals represent like parts:

[0027] [ Figure 1 ] Figure 1 An example of a circuit for detecting phase error in a Q-demodulator according to one embodiment of the present disclosure is shown.

[0028] [ Figure 2 ] Figure 2 Another example of a circuit for detecting a phase error in a Q-demodulator according to an embodiment of the present disclosure is shown.

[0029] [ Figure 3 ] Figure 3 An embodiment according to the present disclosure is shown. Figure 1 The circuit shown along with the offset cancellation loop and the phase error cancellation loop.

[0030] [ Figure 4 ] Figure 4 An embodiment according to the present disclosure is shown. Figure 2 The circuit shown along with the offset cancellation loop and the phase error cancellation loop.

[0031] [ Figure 5 ] Figure 5 An example of a method for detecting a phase error according to an embodiment of the present disclosure is shown.

[0032] Throughout the drawings, it should be noted that like reference numbers are used to depict the same or similar elements, features, and structures. DETAILED DESCRIPTION

[0033] The following discussion Figures 1 to 5 And the various embodiments used to describe the principles of the present disclosure in this patent document are for illustration only and should not be interpreted as limiting the scope of the present disclosure in any way. Those skilled in the art will understand that the principles of the present disclosure can be implemented in any appropriately arranged system and method. The following description with reference to the accompanying drawings is provided to help fully understand the various embodiments of the present disclosure as defined by the claims and their equivalents. The following description includes various specific details to help understanding, but these specific details should be regarded as examples only. Therefore, those of ordinary skill in the art will recognize that various changes and modifications may be made to the various embodiments described herein without departing from the scope and spirit of the present disclosure. In addition, for the sake of clarity and brevity, the description of known functions and structures may be omitted.

[0034] It should be apparent to those skilled in the art that the following description of various embodiments of the present disclosure is provided for illustration purpose only and not for the purpose of limiting the present disclosure as defined by the appended claims and their equivalents.

[0035] Although ordinal numbers such as "first," "second," and the like are used to describe various components, those components are not limited herein. Such terms are only used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component without departing from the teachings of the present inventive concept.

[0036] The terms used herein are only for describing various embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms used herein are also intended to include the plural forms. It will be further understood that when used in this specification, the terms "including" and / or "having" represent the presence of the features, quantities, steps, operations, components, elements, or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, steps, operations, components, elements, or combinations thereof.

[0037] Figure 1 An example of a circuit 100 for detecting phase and offset errors in a Q-demodulator is shown according to one embodiment of the present disclosure.

[0038] The circuit 100 includes: an RF path 3 for receiving an RF signal; a first chopper 2 disposed on the RF path 3; a second chopper 5a and an attenuator 5b coupled to the LO signal path 7; a Q demodulator 10 including a phase shifter 11 and a mixer 12; an amplifier 16; an ADC 17; and a DSP 20.

[0039] Initially, the RF path 3 receives RF signals from various RF devices, such as a gyro sensor (not shown). The received RF signals are then coupled to a first chopper 2, which includes a set of chopping switches for generating a chopped version of the RF signal at a first chopping frequency f_chp1.

[0040] A local oscillator signal (LO signal) having an LO frequency is generated from an oscillator (not shown) and coupled to a chopper 5a, which includes a set of chopping switches for generating a chopped version of the LO signal at a second chopping frequency f_chp2. An attenuator 5b also includes a set of resistors for reducing the amplitude of the chopped LO signal to an appropriate value for summing with the chopped RF signal and then processing by the Q demodulator 10.

[0041] The combined chopped signal and LO signal are phase shifted and mixed within the Q-demodulator 10 to generate a baseband signal.

[0042] The adder 4 combines the attenuated and chopped LO signal with the chopped RF signal, and then feeds the combined signal to the high-pass filter 14 of the phase shifter 11 via amplifiers (or buffers) 13a, 13b. In addition, another LO signal is directly provided to the low-pass filter 15 of the phase shifter 11 via amplifiers (or buffers) 13c, 13d.

[0043] The high pass filter 14 and low pass filter 15 of the phase shifter 11 can be implemented in any number of known designs using resistors, inductors and / or capacitors. The phase shifter 11 shifts the phase of the combined signal and the LO signal so that the phase difference between the combined signal and the LO signal is set to 90 degrees.

[0044] Then, the phase-shifted combined signal and the phase-shifted LO signal are supplied to the mixer 12, which multiplies the phase-shifted combined signal and the phase-shifted LO signal to generate a baseband signal.

[0045] The baseband signal output from the Q-demodulator 10 is provided to an amplifier 16 which then amplifies the baseband signal to provide sufficient gain to facilitate phase error detection.

[0046] The amplified baseband signal is supplied to an analog-to-digital converter (ADC) 17 which samples the amplified baseband signal for digitization. The ADC 17 may be implemented in a known analog-to-digital converter circuit which generates a digitized version of the baseband signal sampled at a particular sampling frequency.

[0047] After digitization by ADC 17, the digitized baseband signal is supplied to a digital signal processor (DSP) 20 to extract different signals to be analyzed. In this embodiment, DSP 20 may include three filters: a low pass filter (LPF) 21, a band pass filter (BPF) 22, and a BPF 23 connected in parallel to each other.

[0048] The LPF 21 is configured to pass a direct current (DC) signal in the digitized baseband signal to extract an offset signal indicating a DC offset generated in the Q demodulator 10 .

[0049] The BPF 22 is configured to pass the baseband signal of the first chopping frequency f_chp1 to output a desired signal indicating the result of the operation of various RF devices. As an example, in the case where the circuit initially receives an RF signal from a gyro sensor, the desired signal may be a signal indicating the angular velocity measured by the gyro sensor. In addition, the BPF 22 may further include a root mean square (RMS) circuit for obtaining an RMS value of the baseband signal of f_chp1.

[0050] The BPF 23 is configured to pass the baseband signal of the second chopping frequency f_chp2 to extract an error signal indicating the amount of phase error generated in the Q demodulator 10. When there is no phase error generated in the Q demodulator 10, the phase-shifted chopping LO signal will be offset with another phase-shifted LO signal during the multiplication operation at the mixer 12, and therefore, the BPF 23 does not generate an error signal of the second chopping frequency f_chp2. In addition, the BPF 23 may further include an RMS circuit for obtaining an RMS value of the baseband signal of f_chp2.

[0051] Figure 2 Another example of a circuit 200 for detecting phase and offset errors in a Q-demodulator according to one embodiment of the present disclosure is shown.

[0052] Circuit 200 is similar to Figure 1 The circuit 100 is shown except that analog processing is used to extract different analog signals. Therefore, repeated description of the same components will be omitted.

[0053] The circuit 200 includes: a first chopper 2 disposed in an RF path 3; a chopper 5a and an attenuator 5b coupled to an LO signal path 7; a Q demodulator 10 including a phase shifter 11 and a mixer 12; an amplifier 16; and an analog filter 30.

[0054] The RF signal is chopped at a first chopping frequency f_chp1 at a first chopper 2. The LO signal is also chopped at a second chopper 5a at a second chopping frequency f_chp2 and attenuated at an attenuator 5b, which may include a resistor for reducing the amplitude of the chopped LO signal to a suitable value for summing with the chopped RF signal and then processing by the Q-demodulator 10. The combined chopped signal and LO signal are phase shifted in the Q-demodulator 10 and then mixed to generate a baseband signal.

[0055] The baseband signal is amplified with sufficient gain in the amplifier 16. In this embodiment, the amplified baseband signal is not digitized but supplied to three parallel analog filters LPF 31, BPF 32 and BPF 33. Contrary to the filter of the DSP 20 extracting a digitized signal from the digitized baseband signal output from the ADC 17, these three analog filters extract different analog signals to be analyzed.

[0056] The LPF 31 is configured to extract an offset signal indicating an offset generated in the Q demodulator 10. The BPF 32 is configured to pass a signal of a first chopping frequency f_chp1 to output a desired signal. The BPF 33 is configured to pass a signal of a second chopping frequency f_chp2 to extract an error signal indicating an amount of phase error generated in the Q demodulator 10.

[0057] Figure 3 An embodiment according to the present disclosure is shown. Figure 1 The circuit shown along with the offset cancellation loop and the phase error cancellation loop.

[0058] Circuit 300 is similar to Figure 1 The circuit 100 is shown except that an offset cancellation loop 35 and a phase error cancellation loop 36 are added. Therefore, repeated description of the same components will be omitted.

[0059] The circuit 300 includes: a first chopper 2 coupled to the RF signal input 1; a chopper 5a and an attenuator 5b coupled to the LO signal path 7; a Q demodulator 10 including a phase shifter 11 and a mixer 12; an amplifier 16; an ADC 17; and a DSP 20. Figure 1 Similar to the illustrated embodiment, the DSP 20 includes: an LPF 21 configured to output an offset signal; a BPF 22 configured to output a desired signal; and a BPF 23 configured to output an error signal.

[0060] The circuit 300 includes an offset cancellation loop 35 that feeds back an offset signal from the output of the LPF 21 to the Q-demodulator 10 to adjust the offset of the Q-demodulator 10 so as to remove the offset error.

[0061] The circuit 300 further includes a phase error cancellation loop 36 which feeds back an error signal from the output of the BPF 23 to the Q-demodulator 10 to adjust the phase of the Q-demodulator 10 so as to remove the phase error.

[0062] Figure 4 An embodiment according to the present disclosure is shown. Figure 2 The circuit 400 is similar to the circuit shown in FIG. Figure 2 The circuit 200 is shown except that an offset cancellation loop 45 and a phase error cancellation loop 46 are added. Therefore, repeated description of the same components will be omitted.

[0063] The circuit 400 includes an offset cancellation loop 45 that feeds back an offset signal from the output of the LPF 31 to the Q-demodulator 10 to adjust the offset of the Q-demodulator 10 so as to remove the offset error.

[0064] The circuit 400 further includes a phase error cancellation loop 46 which feeds back an error signal from the output of the BPF 33 to the Q-demodulator 10 to adjust the phase of the Q-demodulator 10 so as to remove the phase error.

[0065] Figure 5 An example of a method 500 for detecting phase error according to one embodiment of the present disclosure is shown.

[0066] The method begins by receiving an RF signal from one of the various RF components into the RF signal path in step S11 .

[0067] Subsequently, in step 12 , the chopper 2 chops the received RF signal at a first chopping frequency f_chp1 to generate a chopped version of the RF signal.

[0068] In step S13, the LO signal is received from the oscillator, and in step S14, the chopper 5a chops the LO signal at a second chopping frequency f_chp2 to generate a chopped version of the LO signal. In one embodiment, the LO signal may be further attenuated by an attenuator before or after being chopped.

[0069] In step S15 , the phase shifter 11 shifts the phases of the combined signal and the LO signal so that the phase difference between the combined signal and the LO signal is set to 90 degrees.

[0070] In step S16 , the mixer 12 multiplies the phase-shifted combined signal and the phase-shifted LO signal to generate a baseband signal.

[0071] In step S17, the LPF extracts an offset signal from the baseband signal, the BPF whose center frequency is equal to the first chopping frequency extracts a desired signal from the baseband signal, and the BPF whose center frequency is equal to the second chopping frequency extracts an error signal from the baseband signal. There is an interval between the first chopping frequency and the second chopping frequency so that the desired signal does not interfere with the error signal. For example, the first chopping frequency can be 20KHz, and the second chopping frequency can be 50KHz.

[0072] In step S18, the offset cancellation loop feeds back the offset signal from the output of the LPF to the Q demodulator 10 to adjust the offset of the Q demodulator 10 so as to remove the offset error. In addition, the phase error cancellation loop feeds back the error signal from the output of the LPF to the Q demodulator 10 to adjust the phase of the Q demodulator 10 so as to remove the phase error.

[0073] Although the present disclosure has been described using example embodiments, various changes and modifications may be apparent to those skilled in the art. The present disclosure is intended to encompass such changes and modifications as fall within the scope of the appended claims.

Claims

1. A device for detecting phase and offset errors, the device comprising: an RF signal path configured to receive an RF signal from the RF component; a first chopper including a chopping switch for chopping the RF signal at a first frequency to generate a chopped RF signal; an LO signal path configured to receive an LO signal; a second chopper including a chopping switch for chopping the LO signal at a second frequency to generate a chopped LO signal; a summing mechanism disposed on the RF path and configured to combine the chopped LO signal and the chopped RF signal to generate a combined signal; Q-demodulator, including: a phase shifter configured to shift the phase of the combined signal to generate a shifted combined signal, and configured to shift the phase of the LO signal to generate a shifted LO signal, such that a phase difference between the combined signal and the LO signal is set to 90 degrees; a mixer configured to multiply the shifted combined signal with the shifted LO signal to generate a baseband signal; and At least one filter is configured to extract a signal contained in the baseband signal.

2. The device according to claim 1, wherein: The phase shifter comprises: a high pass filter configured to shift the phase of the combined signal; and A low pass filter is configured to shift the phase of the LO signal.

3. The device according to claim 1, wherein: The phase shifter comprises: a first amplifier or a first buffer configured to amplify the combined signal and provide the amplified combined signal to a high pass filter; and The second amplifier or the second buffer is configured to amplify the LO signal and provide the amplified LO signal to the low pass filter.

4. The apparatus according to claim 1, further comprising: An amplifier is configured to amplify the baseband signal output from the Q demodulator with a specific gain.

5. The apparatus according to claim 1, further comprising: The analog-to-digital converter ADC is configured to digitize the baseband signal.

6. The apparatus according to claim 5, further comprising: The digital signal processor DSP is configured to extract the different signals to be analyzed.

7. The device according to claim 6, wherein: The DSP includes: The low pass filter LPF is configured to output a circuit offset, wherein the circuit offset indicates a DC offset generated in the Q demodulator.

8. The apparatus according to claim 7, further comprising: The offset cancellation loop is configured to feed back the circuit offset to the Q-demodulator to adjust the offset of the Q-demodulator so as to remove the offset error.

9. The device according to claim 5, wherein: The DSP includes: The bandpass filter is configured to pass the baseband signal of the first chopping frequency to output a desired signal, wherein the desired signal indicates a result of the operation of the RF component.

10. The device according to claim 9, wherein: The RF component is a gyro sensor, and The expected signal indicates an angular velocity measured by the gyro sensor.

11. The device according to claim 5, wherein: The DSP includes: A bandpass filter is configured to pass the baseband signal of the second chopping frequency to extract an error signal indicating an amount of phase error generated in the Q demodulator.

12. The apparatus according to claim 1, further comprising: The phase error cancellation loop is configured to feed back the error signal to the Q-demodulator to adjust the phase of the Q-demodulator so as to remove the phase error.

13. The apparatus according to claim 1, further comprising: An attenuator is configured to reduce the amplitude of the chopped LO signal to be summed with the RF signal in the RF path.

14. The apparatus according to claim 1, further comprising: a low pass filter LPF configured to output a circuit offset, wherein the circuit offset indicates a DC offset generated in the Q demodulator; as well as The offset cancellation loop is configured to feed back the circuit offset to the Q-demodulator to adjust the offset of the Q-demodulator so as to remove the offset error.

15. The apparatus according to claim 1, further comprising: The bandpass filter is configured to pass the baseband signal of the first chopping frequency to output a desired signal, wherein the desired signal indicates a result of the operation of the RF component.

16. The apparatus according to claim 1, further comprising: a bandpass filter configured to pass the baseband signal of the second chopping frequency to extract an error signal indicating an amount of phase error generated in the Q demodulator, and The phase error cancellation loop is configured to feed back the error signal to the Q-demodulator to adjust the phase of the Q-demodulator so as to remove the phase error.

17. A method for detecting phase and offset errors, the method comprising: receiving RF signals from RF components into an RF signal path; chopping the RF signal at a first frequency to generate a chopped RF signal; receiving an LO signal from a local oscillator into an LO signal path; chopping the LO signal at a second frequency to generate a chopped LO signal; combining the chopped LO signal with the chopped RF signal into a combined signal; shifting the phase of the combined signal by a quadrature demodulator to generate a shifted combined signal, and shifting the phase of the LO signal to generate a shifted LO signal, so that a phase difference between the combined signal and the LO signal is set to 90 degrees; multiplying the shifted combined signal by the shifted LO signal to generate a baseband signal by the quadrature demodulator; and A signal contained in the baseband signal is extracted by at least one filter.

18. The method according to claim 17, further comprising: filtering the baseband signal by a low pass filter to extract a circuit offset, the circuit offset being indicative of a DC offset produced in a Q demodulator; as well as The circuit offset is fed back to the Q-demodulator to adjust the offset of the Q-demodulator so as to remove the offset error.

19. The method according to claim 17, further comprising: The baseband signal is filtered by a bandpass filter having a center frequency equal to a first chopping frequency to output a desired signal indicating a result of the operation of the RF component.

20. The method of claim 17, further comprising: filtering the baseband signal by a bandpass filter having a center frequency equal to a second chopping frequency to extract an error signal indicating an amount of phase error produced in the Q demodulator; as well as The error signal is fed back to the Q-demodulator to adjust the phase of the Q-demodulator so as to remove the phase error.

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