Medium laser accelerator micro-nano acceleration structure and preparation method

Abstract

The invention provides a preparation method of a micro-nano acceleration structure of a medium laser accelerator, and the method comprises the steps: machining the side wall of a wafer through an FIB, bombarding an edge with the length of 5mm through an ion beam, and cutting through the edge with the thickness of 0.2 mm, and because the ion beam is parallel to a thickness surface, a smooth and flat plane can be obtained, and the problem of low efficiency is solved; the etching depth of the inductively coupled plasma deep silicon is greater than 40 microns, the back surface of the ultraviolet lithography is aligned with the patterned grating hollow area, the etching depth of the inductively coupled plasma deep silicon is greater than 160 microns, the grating hollow area is subjected to ultraviolet lithography and positioning, and the whole thickness is etched through through double-sided deep silicon etching; and a smooth and flat grating plane to be processed is obtained. The micro-nano acceleration structure of the medium laser accelerator is prepared at a high platform of a square hole obtained by etching the side surface and the back surface, so that electrons are prevented from being shielded in an electron acceleration experiment process, a small-size side micro-nano structure in which a TEM pole shoe is placed can be obtained in the whole processing flow, and the experiment requirement is met.

Description

Technical Field

[0001] The present invention relates to the field of electronic information technology, and in particular to a medium laser accelerator micro-nano acceleration structure and a preparation method thereof. Background Art

[0002] Particle accelerators are one of the important tools for human beings to explore the microscopic world and are widely used in industries such as industry, agriculture, medicine and scientific research. Dielectric laser accelerators are one of the most promising accelerator miniaturization technologies recognized by the world. The use of micro-nanoscale dielectric structures to control the laser-driven light field can achieve small sizes. At the same time, dielectric materials have a higher breakdown threshold than metal materials and can produce higher acceleration gradients. One of the core technologies of dielectric laser accelerators is the preparation of micro-nano acceleration structures. The practicality of acceleration structures obtained by different preparation methods is different. Therefore, it is necessary to select a suitable micro-nano acceleration structure preparation method based on the premise of conducting electron acceleration experiments under TEM equipment.

[0003] like Figure 1 As shown, the preparation method of the dielectric laser accelerator disclosed in patent CN202111125969.8 is: the acceleration zone is formed by bonding two chips, and gratings are formed on both chips, wherein the preparation of the acceleration zone includes the following steps: growing a first chip by vapor phase epitaxial deposition technology, which includes a first restriction layer and a top reflector; performing photoresist coating on the first restriction layer, and then performing photolithography to obtain a preset mask to expose a position corresponding to the width and length of the acceleration channel; performing wet etching or dry etching to form an etching groove, the etching depth of which is 0.35λ±0.05λ, λ The wavelength of the incident light is then removed, and a positioning mark is made on the first confinement layer; a second chip is grown using vapor phase epitaxial deposition technology, which includes a bottom reflector and an active area; a second confinement layer is grown on the upper layer of the active area, and a second grating with a depth of L is etched on the second confinement layer, and then a positioning mark is made on the second confinement layer, where L = 2 (n-1) ± 0.1λ = 0.5λ ± 0.1λ, λ is the wavelength of the incident light, and n is the refractive index of the confinement layer; the first chip and the second chip are bonded according to the positioning mark to obtain an acceleration zone containing the acceleration channel, and the acceleration channel is provided with a grating only on one side. Existing technical solution 2 (Stanford doctoral thesis), such as Figure 2As shown, the accelerator device was fabricated at the Stanford Nanofabrication Facility (SNF) and the Stanford Nanofabrication Shared Facility (SNSF) on a 500 nm device layer, 3 μm buried oxide layer silicon-on-insulator wafer purchased from Soitec. The accelerator, waveguide, and grating coupler structures were patterned with 330 nm thick ZEP-520A electron beam resist using a JEOL JBC-6300FS electron beam lithography tool. Electron beam writing was performed by soaking in dimethicone for 40 seconds, followed by a 30 second soak in a methyl isobutyl ketone (25%) / 2-propanol (75%) solution, and finally a 30 second soak in a 2-propanol bath. The samples were reactively etched using a C2F6 breakthrough step, and a BCl3 / Cl2 / O2 chemistry for the main etch. The resist was removed by soaking in 1165 overnight, followed by a piranha solution (a 4:1 ratio of sulfuric acid and 30% hydrogen peroxide).

[0004] The defects of the preparation methods in the prior art are: the existing micro-nano lithography technology is a planar processing technology, which is usually carried out on the wafer plane by etching, deposition, growth and other processing methods. The area of ​​the wafer is usually on the order of 10 cm or larger. Whether the scheme of first scribing and then lithography or first lithography and then scribing is adopted, since the process steps such as coating photoresist and cutting need to be clamped or fixed, the plane size of the chip where the micro-nano acceleration structure is located will basically not be less than 2 mm. Taking the grating as an example of the micro-nano acceleration structure, in the TEM electron acceleration experiment scheme, electrons need to pass through the grating surface by glancing. Considering the aggregation, positioning and measurement stability of electrons, the length of the plane where the grating surface is located should be less than 0.3 mm. The existing preparation technology method does not meet this requirement. If the thinning methods such as mechanical grinding and chemical polishing commonly used in transmission electron microscopy sample preparation are selected, it is easy to damage the grating structure. Therefore, a preparation method that directly prepares it to meet the TEM sample size is required during micro-nano processing.

[0005] The size of the sample stage used in the electron acceleration experiment is about 4mm*5.5mm (such as Figure 3 As shown in blue, the white part is hollow to allow electrons to pass through), and green is a schematic diagram of the small piece. The 5mm length can ensure that both sides of the small piece are fixed and will not exceed the size, and the 2mm width is to leave a gap for electrons to pass through. Summary of the invention

[0006] In view of this, the present invention provides a medium laser accelerator micro-nano acceleration structure and a preparation method thereof.

[0007] A method for preparing a dielectric laser accelerator micro-nano acceleration structure, comprising:

[0008] a. Cut the 0.2mm thick silicon wafer into a 0.2mm high rectangular silicon wafer;

[0009] b. Coating a 2 μm thick silicon oxide film on one side of a rectangular silicon wafer;

[0010] c. defining the side of the rectangular silicon wafer that is not coated with silicon oxide film as the front side, and the other side as the back side; performing ultraviolet lithography on the front side of the rectangular silicon wafer, thereby forming a scribe line 6 with a width of 3 μm on the midline in the longitudinal direction;

[0011] d. Etch the scribe line 6 to a depth of >40 μm;

[0012] e. A square countersunk hole with a side length of 40 μm is formed at the center of one side of the rectangular silicon wafer coated with silicon oxide film by ultraviolet lithography, and a scribe line 7 is formed on the midline in the length direction, and the etching depth is greater than 160 μm;

[0013] f. Splitting the rectangular silicon wafer along the scribing line 6 and the scribing line 7 of the center line to form a structure with two smooth and flat surfaces;

[0014] g. After the rectangular silicon wafer is cracked along the scribe line, at the position of the square countersunk hole, there is a countersunk hole on one edge and the other edge is raised relative to the countersunk hole, thus forming a step. On this step, a focused ion beam dual-beam etching system is used for grating direct writing to obtain a micro-nano acceleration structure.

[0015] Preferably, the depth of the square countersunk hole is 20 μm.

[0016] Preferably, an inductively coupled plasma deep silicon etching device is used.

[0017] Preferably, two small grooves are made on both sides of the etched grating position as positioning marks 5; when the experiment is carried out, the grating is between these two positioning marks 5.

[0018] The present invention has the following beneficial effects:

[0019] The present invention provides a method for preparing a micro-nano acceleration structure of a dielectric laser accelerator. The side wall of a wafer is processed by FIB, and an ion beam is used to bombard an edge of 5 mm in length and to carve through a thickness of 0.2 mm. Since the ion beam is parallel to the thickness surface, a smooth and flat plane can be obtained, thereby solving the problem of low efficiency. The ultraviolet lithography patterning has a scribe line with a width of 3 μm, and the inductively coupled plasma deep silicon etching depth is greater than 40 μm. The back of the ultraviolet lithography is aligned with the patterned grating hollow area, and the inductively coupled plasma deep silicon etching depth is greater than 160 μm. The grating hollow area is etched and positioned by ultraviolet lithography, and the entire thickness is etched through by double-sided deep silicon etching to obtain a smooth and flat grating to be processed plane. The micro-nano acceleration structure of a dielectric laser accelerator is prepared at the high platform of the square hole obtained by etching the side and back to avoid shielding of electrons during the electron acceleration experiment. The entire processing flow can obtain a small-sized side micro-nano structure placed in a TEM pole shoe, thereby meeting the experimental requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is the medium laser accelerator structure disclosed in patent CN202111125969.8;

[0021] Figure 2 A dielectric laser accelerator structure etching process from Stanford University;

[0022] Figure 3 A schematic diagram of placing the micro-nano acceleration structure of the dielectric laser accelerator of the present invention on the sample stage of the electron acceleration experiment;

[0023] Figure 4 This is a schematic diagram of the final structure of the medium laser accelerator micro-nano acceleration structure of the present invention;

[0024] FIG5 is the front and back etching patterns of the silicon wafer in step ce;

[0025] Figure 6 It is a front view of the half of the silicon wafer after being separated in FIG5;

[0026] Figure 7 A perspective view of the side of the half of the silicon wafer in FIG. 5 after being separated, facing upward;

[0027] Figure 8 A smooth surface formed by ion polishing and two deposited markers.

[0028] Among them, 1-electron acceleration experiment sample stage, 2-micro-nano acceleration structure, 3-square countersunk hole, 4-grating etching area, 5-positioning mark, 6-scribing line on the front side of the silicon wafer, 7-scribing line on the back side of the silicon wafer, 8-mark formed by deposition. DETAILED DESCRIPTION

[0029] like Figure 4 As shown, the present invention utilizes a relatively thin silicon wafer sidewall (about 0.2 mm) for structural etching processing, and the back hollowing area is a method of further thinning. When the front side is deeply etched (>40 microns), the plane of the accelerating structure etching area will be tilted, and only a 40-micron portion will be etched, and it is necessary to ensure that after the side etching of the accelerating structure, the etching area is still a protruding part, so a part of the back side must be hollowed out from bottom to top; the entire structure has a step structure when viewed from the side, and the surface above the step is the accelerating structure etching area; the positioning mark is two vertical lines etched through the two sides of the accelerating structure etching area, the purpose of which is to quickly locate the accelerating structure etching area under projection electron microscope observation.

[0030] The specific implementation scheme of the method for preparing a medium laser accelerator micro-nano acceleration structure of the present invention is as follows:

[0031] a. As shown in Figure 5(a), a 0.2 mm thick silicon wafer is cut into a 0.2 mm high rectangular silicon wafer; the subsequent grating structure is processed at this thickness so that it can be directly placed on the TEM sample stage in the electron acceleration scheme (not too thick).

[0032] b. Coating a 2 μm thick silicon oxide film on the upper or lower surface of the rectangular silicon wafer;

[0033] c. As shown in FIG. 5( a ), the side of the rectangular silicon wafer that is not coated with the silicon oxide film is defined as the front side, and the other side is defined as the back side; UV lithography is performed on the front side to form a scribe line 6 with a width of 3 μm on the midline in the longitudinal direction;

[0034] d. The scribe line 6 is etched to a depth of >40 μm by using an inductively coupled plasma deep silicon etching device;

[0035] e. As shown in FIG5(b), a square countersunk hole with a side length of 40 μm and a depth of about 20 μm is formed at the exact center of the back side of the silicon oxide film by ultraviolet lithography, and a scribe line 7 is formed on the midline in the length direction, and an inductively coupled plasma deep silicon etching device is used to etch it to a depth of >160 μm; thus, the total depth of the scribe line 6 and the scribe line 7 exceeds the height of the rectangular silicon wafer by 0.2 mm, which is beneficial to the cutting of the silicon wafer. Now a dividing line with a depth of 40 μm is etched on the front side, and then a dividing line and a square hole with a depth of 160 μm are etched on the back side to penetrate the silicon wafer. The present invention is divided into the above two steps to etch a thickness of 200 μm. The reason why it is not directly etched through is that the processing will cause a break during direct etching, thereby avoiding damage to the smooth surface. Among them, the selection of the side length of 40 μm of the square countersunk hole is related to the length of the grating to be processed. In the electron acceleration experiment, the position of the grating can be located through this countersunk hole.

[0036] f. Split the rectangular silicon wafer along the center line of the scribe line 6, 7 to form a structure with two smooth and flat surfaces, such as Figure 6 and Figure 7 As shown;

[0037] g. Figure 7 As shown, after the rectangular silicon wafer is cracked along the scribe line, due to the square countersunk holes etched on the back, one edge of the fracture surface of the silicon wafer has a countersunk hole, and the other edge is raised relative to the countersunk hole, thus forming a step with a height of 40μm. On this step, a focused ion beam dual-beam etching system is used for grating direct writing.

[0038] It should be noted that the width of the scribing line 6 on the front side of the rectangular silicon wafer is larger than the width of the scribing line 7 on the back side, so the remaining part after etching on the front side can be seen from the front side; in addition to thinning the silicon wafer to form a boss, the square countersunk hole can also provide a positioning function for the accelerating grating during the electron acceleration experiment. The side length of the square countersunk hole is consistent with the width of the grating, and the width of the scribing line on the front side is larger than that on the back side. Figure 6 As shown, there is a groove when viewed from the front, and this groove is the position of the accelerating grating. If the size of the square countersink is too large (for example, the side is directly polished with an ion polisher to make this square hole) or the width of the grating to be etched later is smaller than the side length of the square hole, the square countersink will not have a positioning effect, and two additional 1μm wide small grooves need to be made on both sides of the etched grating position as positioning marks 5. When the experiment is carried out, the grating is between these two positioning marks 5. The silicon wafer itself is not conductive. After the conductive glue is applied, it is placed in the sample chamber of the FIB equipment. The sample is observed through the electron beam to find the position of the positioning mark 5, and the grating is processed according to the layout, starting from the edge (the best position for electron bunching in electron acceleration experiments is at the edge).

[0039] The area of ​​UV lithography can be as large as 10cm, and multiple groups of samples can be made at the same time. The size of each group is about 4mm*5mm. A group of samples is shown in Figure 5 and can be separated into two pieces.

[0040] The present invention also provides a method for preparing a smooth surface by an ion polishing apparatus:

[0041] a. Get a small piece of 2mm*5mm*0.2mm;

[0042] b. Polish the 5mm thick surface of the 2mm*5mm small piece with an ion polisher to obtain a polished surface with an area of ​​0.5mm*0.2mm and a depth of 1μm;

[0043] c. Find the polished surface through electron beam observation and use ion beam to etch the grating near one edge;

[0044] d. Deposit two small dots with a diameter of 1 μm on both sides of the grating as the position mark of the grating 8. Figure 8 As shown:

[0045] The minimum size of the ion polisher is large, and the polished plane with an area of ​​0.5mm*0.2mm is beyond the field of view of the TEM. It is necessary to deposit growth positioning and alignment markers, which are easily obscured by the roughness or dirt on the sample edge.

[0046] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a dielectric laser accelerator micro-nano acceleration structure, characterized in that: include: a. Cut the 0.2mm thick silicon wafer into a 0.2mm high rectangular silicon wafer; b. Coating a 2 μm thick silicon oxide film on one side of a rectangular silicon wafer; c. defining the side of the rectangular silicon wafer that is not coated with the silicon oxide film as the front side, and the other side as the back side; performing ultraviolet lithography on the front side of the rectangular silicon wafer, thereby forming a scribe line (6) with a width of 3 μm on the center line in the longitudinal direction; d. Etching the scribe line (6) to a depth of >40 μm; e. A square countersunk hole with a side length of 40 μm is formed at the center of one side of the rectangular silicon wafer coated with the silicon oxide film by ultraviolet lithography, and a scribe line (7) is formed on the midline in the length direction, and the etching depth is greater than 160 μm; f. splitting the rectangular silicon wafer along the scribing line (6) and the scribing line (7) of the center line to form a structure having two smooth and flat surfaces; g. After the rectangular silicon wafer is cracked along the scribe line, at the position of the square countersunk hole, there is a countersunk hole on one edge and the other edge is raised relative to the countersunk hole, thus forming a step. On this step, a focused ion beam dual-beam etching system is used for grating direct writing to obtain a micro-nano acceleration structure.

2. The method for preparing a medium laser accelerator micro-nano acceleration structure according to claim 1, characterized in that: The depth of the square countersunk hole is 20 μm.

3. The method for preparing a medium laser accelerator micro-nano acceleration structure according to claim 1, characterized in that: Using inductively coupled plasma deep silicon etching equipment.

4. The method for preparing a medium laser accelerator micro-nano acceleration structure according to claim 1, characterized in that: Two small grooves are made on both sides of the etched grating position as positioning marks (5); when the experiment is carried out, the grating is between these two positioning marks (5).

Images