Transmission electron microscope sample preparation method for in-situ measurement of reliability of three-terminal device

Abstract

The invention discloses a transmission electron microscope sample preparation method for in-situ measurement of reliability of a three-terminal device, and mainly solves the problems of difficult electrode connection and heavy ion beam damage in the prior art. According to the implementation scheme, a to-be-tested device is placed in a focused ion beam scanning electron microscope; adjusting the image to determine a sampling position; beveling the to-be-tested device by using an ion beam to expose an electrode section; depositing a Pt layer between the source electrode and the grid electrode of the device, and leading out the grid electrode; the SiO2 layer is deposited on the Pt layer, so that the damage of ion beams to a sample is reduced; transferring the sample sheet from the device to a micro electro mechanical system chip; depositing a Pt layer at the contact part of the sample sheet and the micro electro mechanical system chip again, and connecting the sample sheet with the chip; carrying out selective etching on the sample sheet and the chip so as to enable three-terminal electrodes of the sample sheet to be disconnected mutually; the sample sheet is thinned to be electronically transparent by ions. The method has the characteristics of high efficiency and visualization, is low in cost and high in timeliness, and can be used for observing the microstructure change in real time when the three-terminal device of the transistor degenerates and fails.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic component reliability analysis, and particularly relates to a transmission electron microscope sample preparation method, which can be used to observe in real time the microscopic structural changes of a transistor three-terminal device during degradation and failure. Background Art

[0002] Reliability analysis is a key link in device design and practical application. Understanding and analyzing the internal physical and chemical properties of the device and its degradation and failure mechanism during application can help improve device design, manufacturing and application. In order to study reliability issues, it is urgent to adopt advanced high spatial resolution failure analysis technology and develop corresponding sample preparation methods to accurately discover degradation and failure mechanisms.

[0003] At present, the mainstream idea of ​​studying device reliability issues is to apply single excitation and multi-physical field combined excitation to the device to make it degrade or completely fail. Then, by comparing the degradation or failure conditions under different excitations, different technical means, different processes, etc., the mechanism and location of device failure can be inferred. This kind of forensic autopsy-style examination after device failure is often laborious and cumbersome. Although some researchers have begun to use scanning electron microscopes (SEM) and transmission electron microscopes (TEM) to conduct experiments, most of them are limited to the study of two-terminal devices, and in-situ transmission electron microscope research on transistor three-terminal devices is very limited.

[0004] In-situ transmission electron microscopy has great potential in device reliability research. This technology allows researchers to directly observe the microstructural changes of samples under single excitation and multi-physical field combined excitation in real time from the atomic level, which helps to explore the mechanism of device degradation and failure. The difficulty of this technology lies in how to prepare electron transparent samples that meet the observation conditions. For example, a three-terminal device of a transistor contains a source, a drain and a gate. It is a major technical challenge to disconnect the three terminals from each other and connect them to the electrodes of a micro-electromechanical system MEMS chip, especially the connection between the gate and the MEMS chip electrode is more difficult to achieve. During the thinning process in the focused ion beam scanning electron microscope FIB-SEM chamber, the ion beam may damage the sample surface, and how to protect the sample is also a major difficulty. Therefore, there is an urgent need for a transmission electron microscope sample preparation method for in-situ measurement of the reliability of three-terminal devices to provide help for targeted improvement of device reliability.

[0005] The patent document with application number CN201320631538.3 discloses a "transmission electron microscope sample stage for in-situ measurement of nano devices", which includes a metal nanoprobe, an insulating plug and a sample support platform, wherein the front and back surfaces of the insulating plug are respectively provided with a plurality of metal electrodes, and the corresponding metal electrodes are conductively connected through metallized through holes; one end of the sample support platform is connected to the insulating plug, and the other end is provided with a sampling area and a test area, wherein the test area is a metal electrode provided on the surface of the sample support platform and suspended in the air, and the metal electrode of the sample support platform is conductively connected to the metal electrode of the insulating plug; the metal nanoprobe, the metal electrode of the test area and the sample to be measured constitute a three-terminal field effect transistor. Although this structure can observe the sample at the atomic scale resolution and perform electrical measurements in real time, it can reveal the electrical properties and nanostructure changes of the unit to be measured in situ. However, since the metal nanoprobe adds additional mechanical stress, it may cause damage to the sample; at the same time, since the sample stage is fixed, it is not conducive to real-time observation of the microstructure of the sample from multiple angles; in addition, the cost of making a transmission electron microscope sample stage for in-situ measurement of nano devices is relatively high.

[0006] Wang et al. proposed a MEMS chip with mechanical drive, heating and electrical bias characteristics in the article "Grainsize-induced thermo-mechanical coupling in zirconium thin films" published in the Journal of Thermal Analysis and Calorimetry. The MEMS chip has three pairs of electrical contact pads: AA', BB' and CC', which can be mounted on the bracket of a customized transmission electron microscope in-situ sample rod for real-time observation. However, this use of MEMS chips to assist in the observation of samples requires custom MEMS chips for transistor three-terminal device samples of different sizes to achieve three-terminal connection, which will lead to longer experimental cycles and higher costs.

[0007] The patent document with application number CN202110471682.4 discloses a "transmission electron microscope sample preparation method for in-situ observation of integrated circuit structure and its evolution". Its implementation scheme includes: placing an in-situ powered chip with at least three electrodes and an integrated circuit sample to be detected into a dual-beam device at the same time, and the in-situ powered chip contains at least one hollow through-hole area. This method connects the three-pole structure to the in-situ powered chip electrode respectively, and then connects it to an external control power supply to truly simulate the changes of the device during operation, and prevents the sample matrix from interfering with the loading signal through the insulating layer on the surface of the integrated circuit sample. The hollow design of the in-situ powered chip loading area facilitates the penetration of the electron beam, avoids the high design cost and effort to transform the function of the transmission electron microscope itself, and enables the transmission electron microscope to characterize the structure and evolution of the integrated circuit sample under normal working conditions in real time. Since this method does not give a detailed relationship between the connection between the three-pole structure and the in-situ powered chip electrode and the connection between the gate covered with a passivation layer and the in-situ MEMS chip electrode, it is difficult to complete the transmission electron microscope sample preparation more effectively according to its technical solution. Summary of the invention

[0008] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and to propose a transmission electron microscope sampling method for in-situ measurement of the reliability of three-terminal devices, so as to reduce the transmission electron microscope sampling cycle, reduce the sampling cost, and realize efficient and visualized in-situ transmission electron microscope sampling of transistor three-terminal devices.

[0009] The technical idea for achieving the purpose of the present invention is: by depositing conductive materials, the source, gate and drain electrodes of the three-terminal transistor device are connected in an orderly manner with the two-terminal MEMS chip electrodes, so as to reduce the sample preparation cost without having to spend a long period of time to customize the expensive three-terminal MEMS chip electrodes, and by selective disconnection, the problem of easy short circuit between the source, gate and drain electrodes is avoided. Through the FIB-SEM stack protection design, the damage to the sample by the ion beam during the processing is reduced to ensure the quality of the sample preparation.

[0010] According to the above ideas, the technical solution of the present invention includes the following steps:

[0011] (1) inserting a nail stage with a three-terminal device such as a transistor to be tested and a micro-electromechanical system (MEMS) chip into a sample stage of a focused ion beam scanning electron microscope (FIB-SEM) chamber and extracting air to obtain a vacuum environment;

[0012] (2) In the electron beam window of the FIB-SEM, adjust the focal length until the image in the electron microscope field of view is clear, place the gate of the transistor in the center of the electron microscope field of view, and make the source and drain electrodes symmetrically distributed on both sides of the gate;

[0013] (3) In the ion beam window of the FIB-SEM, adjust the focus until the image is clear, then rotate the sample stage and use the ion beam to cut out an oblique cross section of the transistor;

[0014] (4) depositing a Pt layer on the source and gate tops and oblique cross-sections of the transistor, and temporarily short-circuiting the source and gate electrodes;

[0015] (5) Deposit a SiO2 protective layer on the Pt layer of the transistor source, gate top and oblique cross section and the drain of the transistor to reduce ion beam damage;

[0016] (6) Cutting a sample slice from the transistor by means of single-side grooving and U-shaped cutting, and transferring the sample slice to an in-situ transmission electron microscope MEMS chip by means of robot extraction;

[0017] (7) depositing a Pt layer at the contact points between the source, gate and drain electrodes of the sample sheet and the electrodes of the MEMS chip, and connecting the source, gate and drain electrodes of the sample sheet to the corresponding electrodes of the MEMS chip respectively;

[0018] (8) Using FIB-SEM ion beam to etch a part of the MEMS chip, the source, gate and drain electrodes of the sample slice are disconnected from each other;

[0019] (9) The ion beam of FIB-SEM is used to perform ion thinning on one side of the sample slice on the MEMS chip until the electron beam can easily penetrate, and finally the electron transparent sample is prepared.

[0020] Compared with the prior art, the present invention has the following advantages:

[0021] First, the present invention uses FIB-SEM to realize the connection between the transistor three-terminal device and the in-situ transmission electron microscope MEMS chip, and can observe the degradation and failure behavior of the electron transparent device sample under the condition of thermoelectric coupling in real time;

[0022] Second, the present invention adopts a FIB-SEM stacked protection design, by depositing a Pt layer and a SiO2 protective layer on the top and oblique cross section of the device, which can reduce the damage of the ion beam to the sample during sample preparation and achieve the effect of protecting the device;

[0023] Thirdly, the present invention completes the sample preparation of the three-terminal device on the universal two-terminal MEMS chip electrode without customizing the dedicated three-terminal MEMS chip electrode, thus saving the sample preparation time and sample preparation cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a flow chart for realizing the present invention;

[0025] Figure 2 It is a schematic diagram of the structure of a transistor three-terminal device in the present invention;

[0026] Figure 3 It is a schematic diagram of an oblique cross section of a target position in the present invention;

[0027] Figure 4 This is a schematic diagram of the first deposition of a Pt layer in the present invention;

[0028] Figure 5 It is a schematic diagram of depositing a SiO2 protective layer in the present invention;

[0029] Figure 6 This is a schematic diagram of a U-shaped cut three-dimensional structure in the present invention;

[0030] Figure 7 This is a schematic diagram of the second deposition of the Pt layer in the present invention;

[0031] Figure 8 It is a schematic diagram of single-side ion thinning in the present invention;

[0032] Fig. 9 This is a schematic diagram showing the completion of sample preparation of the electron transparent sample of the present invention; DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0034] The transistor three-terminal device used in this example is an AlGaN / GaN heterojunction, which includes a source 1, a gate 2, a drain 3, a passivation layer 4 and a heterojunction 5, such as Figure 2 shown.

[0035] The focused ion beam scanning electron microscope FIB-SEM used in this example is equipped with control software for controlling the entire sample preparation and its corresponding function keys. Among them, the Pump key is used to extract the gas in the FIB-SEM chamber, the Beam key is used to control the electron beam and ion beam, the Focus key is used to adjust the focal length of the electron microscope, the StageZ up / down key is used to adjust the height of the sample stage, and the Easylift needle of the manipulator is used to extract the sample.

[0036] Reference Figure 1 , the implementation steps of this example are as follows:

[0037] Step 1: Sample injection.

[0038] 1.1) After the focused ion beam scanning electron microscope FIB-SEM is deflated, turn off the electron beam source and ion beam source of the FIB-SEM;

[0039] 1.2) Slowly pull open the hatch of the FIB-SEM horizontally, place the nail table with the AlGaN / GaN device and MEMS chip to be tested into the in-situ sample rod holder, then insert the in-situ sample rod holder into the sample table of the FIB-SEM chamber to fix it, and close the hatch;

[0040] 1.3) Click the Pump button in the FIB-SEM control software to pump out the gas in the chamber and reduce the chamber pressure to 5x10 -3 Pa or less, and a vacuum environment is obtained.

[0041] Step 2: Determine the sampling location.

[0042] 2.1) Turn on the electron beam and ion beam Beam buttons in the FIB-SEM control software, adjust the working distance, that is, place the area where the transistor needs to be sampled in the center of the electron microscope field of view, and adjust the Focus button at a low magnification of less than 5000 times, and then adjust the sample stage height several times to a working distance of 4mm from the ion beam source;

[0043] 2.2) Adjust the sample stage to 0°, and adjust the sampling position to the center of the electron beam window, then tilt the sample stage to 15°, use the StageZ up / down key to adjust the sampling position to the center of the electron beam window, then tilt the sample stage to 52°, and further adjust the sampling position to the center of the electron beam window. A total of three adjustments are performed to complete the concentric height adjustment;

[0044] 2.3) Move the FIB-SEM sample stage and place the gate of the three-terminal transistor in the center of the electron microscope field of view. The source and drain are symmetrically distributed on both sides. The area near the gate is the sampling position, such as Figure 2 shown.

[0045] Step 3: Bevel cut the device sample.

[0046] 3.1) Enlarge the transistor three-terminal device in the electron beam window of FIB-SEM, that is, adjust the focus in the ion beam window at a high magnification of 5000 to 15000 times until the image is clear. Since electron beam or ion beam scanning is required multiple times during the adjustment process, this will cause damage to the surface of the device sample, and the damage intensity of electron beam scanning to the device is smaller than that of ion beam scanning. Therefore, this example adopts the method of first performing electron beam scanning and then performing ion beam scanning to effectively reduce the damage to the device sample;

[0047] 3.2) Rotate the FIB-SEM sample stage and use the ion beam to cut an oblique cross section with an angle θ of 20° to 50° with the vertical plane at the sampling position of the transistor to expose the source, gate and drain electrodes, which is convenient for the subsequent deposition of the Pt layer, such as Figure 3 shown.

[0048] Step 4: Deposit a Pt layer for the first time between the source and gate of the AlGaN / GaN device to be tested.

[0049] like Figure 4As shown, a Pt layer 6 is first deposited on the top and oblique cross section of the AlGaN / GaN device between the source and the gate of the AlGaN / GaN device using a Pt deposition source in FIB-SEM, and the thickness of the Pt layer is 1um to 2um, so that the Pt layer is connected to the upper half of the gate. In the process of depositing Pt, it is necessary to avoid the influence of the complete disconnection of the source and the gate caused by the complete coverage of the gate in the subsequent process. The deposition of the Pt layer can reduce the damage of the ion beam to the sample slice during the FIB-SEM processing.

[0050] A gate is drawn out from the deposited Pt layer and connected to the electrode of the MEMS chip. The source and gate of the AlGaN / GaN device to be tested are then temporarily short-circuited so that the two electrodes can be disconnected later by selective disconnection.

[0051] Step 5: Deposit SiO2 protective layer.

[0052] like Figure 5 As shown, a SiO2 protective layer 7 with a thickness of 0.1um to 1um is deposited on the top and oblique cross-section Pt layer of the AlGaN / GaN device using a SiO2 deposition source in FIB-SEM, so as to protect the sample and reduce the damage to the sample caused by the ion beam during FIB-SEM processing; on the other hand, the insulating properties of SiO2 are used to ensure that the current only flows through the two ends of the first deposited Pt layer.

[0053] Step 6: Cut and transfer the sample slices.

[0054] 6.1) Single-side groove digging: Adjust the ion beam perpendicular to the transistor surface, and dig a groove at the transistor sampling position with the ion beam flow. The voltage used is 30kV, and the current is 20nA-30nA. The value is adjusted according to the size of the device. Then rotate the vertical axis of the sample stage to 54°, and trim the side of the transistor. The voltage used is 30kV, and the current is 9.1nA-15nA. The value is adjusted according to the size of the device.

[0055] 6.2) U-shaped cutting: Use the FIB-SEM ion beam to cut off the left and bottom of the sample slice, leaving the right side connected to the transistor, and lower the FIB-SEM manipulator Easylift needle to connect it to the cut side of the sample slice; then use the FIB-SEM ion beam to cut off the remaining support part on the right side. At this time, the sample slice is only connected to the Easylift needle, as shown in Figure 6. Figure 6 The Easylift needle 8 is shown;

[0056] 6.3) Sample transfer: Use the Easylift needle to remove the sample slice from the transistor substrate, and lift the Easylift needle to transfer the removed sample slice to the substrate of the MEMS chip; then cut off the connection between the Easylift needle and the sample slice, and remove the Easylift needle.

[0057] Step 7: Deposition of the Pt layer for the second time.

[0058] Pt layers are deposited at the contact points between the source, gate and drain electrodes of the sample sheet and the first electrode, second electrode and third electrode of the MEMS chip, respectively, so that the sample sheet and the MEMS chip are connected as one. Figure 7 As shown, 9 is a substrate, 10 is a first electrode, 11 is a second electrode, 12 is a third electrode, 13 is a gate Pt layer, 15 is a drain Pt layer, 16 is a source Pt layer, and 18 is a hollow area.

[0059] Step 8: Select the area to disconnect.

[0060] 8.1) Using FIB-SEM ion beam etching, the area on the MEMS chip substrate includes a portion of the area between the first electrode 10 and the second electrode 11, such as Figure 7 Middle first area 14;

[0061] 8.2) The sample slice and the area below it are etched by ion beam of FIB-SEM, the area including part of the source electrode of the sample slice, part of the second electrode below the source electrode and part of the substrate below the second electrode, such as Figure 7 The second area 17.

[0062] Step 9: Use the ion beam of FIB-SEM to perform ion thinning on one side of the sample slice until it becomes electron transparent.

[0063] 9.1) Rotate the vertical axis of the FIB-SEM sample stage by ±0.3°, set the voltage to 30 kV and the current to 0.44-0.26 nA, and use ion beam etching to perform a primary thinning of the upper portion of the sample slice to a depth of 3-6 μm in the electron beam window of the electron microscope;

[0064] 9.2) Rotate the vertical axis of the FIB-SEM sample stage by ±0.3°, set the voltage to 30 kV and the current to 46-90 pA, and use ion beam etching to perform secondary thinning of the upper portion of the sample slice to a depth of 3-6 μm in the electron beam window of the electron microscope;

[0065] 9.3) Rotate the vertical axis of the FIB-SEM sample stage by ±3°, set the voltage to 5kV and the current to 63pA, and use ion beam etching to perform three fine thinnings of 30 to 50s on the upper part of the sample slice in the electron beam window of the electron microscope. If the sample slice is significantly bent during the thinning process, correct it to facilitate subsequent processing;

[0066] 9.4) Rotate the vertical axis of the FIB-SEM sample stage by ±5°, set the voltage to 2kV and the current to 44pA, and use the ion beam to etch the upper part of the sample slice in the electron beam window of the electron microscope for four times of 30 to 50s to obtain the thinned sample slice, such as Figure 8 shown. Figure 8 In the figure, 19 is the thinned sample slice, and 20 is the etched part;

[0067] 9.5) Adjust the parameters used according to the needs of the actual sample, and repeat the fine thinning operation several times to make the thickness of the sample slice 10nm ~ 100nm. The passivation layer on the electrode of the sample slice will be removed during the thinning process, so that the gate is connected to the first deposited Pt layer, and finally an electron transparent sample slice is formed, and the sample preparation is completed. Fig. 9 shown.

[0068] The effect of the present invention can be further illustrated by the following experimental results:

[0069] 1. Experimental process

[0070] The process of this experiment is as follows:

[0071] The transistor device to be sampled is AlGaN / GaN HEMT, which is placed in FIB-SEM; the transistor device is beveled to form an oblique section at the target position; a sample is taken from the oblique section of the transistor to obtain a sample slice, which is extracted and placed on the substrate of the MEMS chip; the electron beam image on the MEMS chip in FIB-SEM is enlarged; a Pt layer is deposited on the source and gate of the transistor for the first time to lead out the gate; a SiO2 protective layer is deposited on the Pt layer to protect the device. The FIB-SEM ion beam is used to etch a part of the MEMS chip substrate for selective disconnection; finally, the FIB-SEM ion beam is used to perform single-side ion thinning on the sample slice to prepare an electron transparent sample.

[0072] 2. Experimental content and results analysis

[0073] The electron transparent sample of AlGaN / GaN device prepared by FIB-SEM was mounted on the MEMS chip of the in-situ sample holder, and the in-situ sample holder was inserted into the transmission electron microscope TEM chamber. The electrical characteristics and failure process of the electron transparent sample were observed in real time under the application of gate bias and drain bias. The results are as follows:

[0074] When a -4V gate voltage was applied to the electron transparent sample, part of the gate metal melted and disappeared immediately, indicating that the three-terminal connection of the electron transparent sample was normal and there was no leakage. Although Pt particles of different sizes appeared in the Pt protective layer, the electron transparent sample was not damaged, indicating that the FIB-SEM sample preparation stacking protection design successfully played a protective role.

[0075] Under drain bias, due to the enhanced piezoelectric effect, the drain current density can be higher than the current density on the electron transparent sample, resulting in heat accumulation, so that the electron transparent sample can exhibit an effect similar to "spring stretching".

[0076] When the drain bias voltage is increased to the point where the material layer exceeds the thermal expansion limit, the electron-transparent sample eventually ruptures and fails through the so-called "spring-break" failure behavior, and this phenomenon under extreme conditions can also be successfully observed.

[0077] The above experiments show that the present invention can complete the three-terminal device sample preparation process on a two-terminal universal MEMS chip without the need to customize a dedicated three-terminal MEMS chip. The prepared electron transparent samples can also meet the needs of electron microscopy observation and save R&D time and cost.

[0078] The above description is only a specific example of the present invention and does not constitute any limitation to the present invention. It is obvious that after understanding the content and principle of the present invention, professionals in the field may make various modifications and changes in form and details without departing from the principle and structure of the present invention. For example, the present invention shows a method of connecting the sample sheet with the MEMS chip by depositing a conductive material, and a mirror or other deformed connection method can also be performed on this basis. These modifications and changes based on the idea of ​​the present invention are still within the scope of protection of the claims of the present invention.

[0079] It should be noted that the step numbers in the specification and claims of the present invention are only for a clear description of the implementation scheme of the present invention to facilitate understanding, and the order of the numbers is not limited.

Claims

1. A transmission electron microscope sample preparation method for in-situ measurement of three-terminal device reliability, characterized in that: The steps include: (1) inserting a nail stage with a three-terminal device such as a transistor to be tested and a micro-electromechanical system (MEMS) chip into a sample stage of a focused ion beam scanning electron microscope (FIB-SEM) chamber and extracting air to obtain a vacuum environment; (2) In the electron beam window of the FIB-SEM, adjust the focal length until the image in the electron microscope field of view is clear, place the gate of the transistor in the center of the electron microscope field of view, and make the source and drain electrodes symmetrically distributed on both sides of the gate; (3) In the ion beam window of the FIB-SEM, adjust the focus until the image is clear, then rotate the sample stage and use the ion beam to cut out an oblique cross section of the transistor; (4) depositing a Pt layer on the source and gate tops and oblique cross-sections of the transistor, and temporarily short-circuiting the source and gate electrodes; (5) Deposit a SiO2 protective layer on the Pt layer of the transistor source, gate top and oblique cross section and the drain of the transistor to reduce ion beam damage; (6) Cutting a sample slice from the transistor by means of single-side grooving and U-shaped cutting, and transferring the sample slice to the MEMS chip by means of robot extraction; (7) depositing a Pt layer at the contact points between the source, gate and drain electrodes of the sample sheet and the electrodes of the MEMS chip, and connecting the source, gate and drain electrodes of the sample sheet to the corresponding electrodes of the MEMS chip respectively; (8) Using FIB-SEM ion beam to etch a part of the MEMS chip, the source, gate and drain electrodes of the sample slice are disconnected from each other; (9) The ion beam of FIB-SEM is used to perform ion thinning on one side of the sample slice on the MEMS chip until the electron beam can easily penetrate, and finally the electron transparent sample is prepared.

2. The method according to claim 1, characterized in that In the step (3), an oblique cross section of the transistor is cut out by an ion beam, and the cutting is performed on the surface of the transistor at an angle θ between the oblique cross section and the vertical plane of 20° to 50°, exposing the three electrodes of source, gate and drain for deposition of Pt.

3. The method according to claim 1, characterized in that In the step (4), a Pt layer with a thickness of 1 um to 2 um is deposited on the source and gate top and the oblique cross section of the transistor, so as to lead the gate located in the middle of the transistor to the side so as to connect the gate to the electrode of the MEMS chip and reduce the damage caused by the ion beam during FIB-SEM processing.

4. The method according to claim 1, characterized in that: The SiO2 protective layer deposited on the Pt layer of the transistor source, gate top and oblique cross section and the drain of the transistor in the step (5) has a thickness of 0.1um to 1um to reduce the damage caused by the ion beam during FIB-SEM processing and allow the current to flow only from the two ends of the first deposited Pt layer.

5. The method according to claim 1, characterized in that In the step (6), a sample slice is cut out from the transistor by means of single-side grooving and U-shaped cutting, which is implemented as follows: (6a) adjusting the ion beam of the FIB-SEM to be perpendicular to the upper surface of the electrode of the cut transistor, digging a groove at the position to be sampled with the ion beam, and then tilting the sample stage to perform fine trimming on one side of the portion to be sampled in the groove; (6b) Use the ion beam of FIB-SEM to cut off one side of the sampled part from the transistor and the bottom from the transistor, keep the other side connected to the transistor as a support, insert the Pt deposition source, and then extend the Easylift needle of the robot to connect it to the cut-off side of the sampled part, and then use the ion beam of FIB-SEM to cut off the remaining support part on the other side, and cut a sample slice from the transistor.

6. The method according to claim 1, characterized in that In the step (6), the sample slice is transferred to the in-situ transmission electron microscope MEMS chip by means of extraction by a robot. The sample slice is first removed from the transistor substrate by the Easylift needle of the robot. Then, the Easylift needle is lifted and the Pt deposition source is withdrawn. The removed sample slice is then transferred and bonded to the pre-prepared MEMS chip by the Easylift needle, and the Pt deposition source is used to weld it to the electrode of the MEMS chip, and then the Easylift needle and the Pt deposition source are withdrawn.

7. The method according to claim 1, characterized in that In the step (7), a Pt layer is deposited at the contact points between the source, gate and drain electrodes of the sample slice and the electrodes of the MEMS chip, and the Pt layer is deposited at the contact points between the source electrode of the sample slice and the first electrode of the MEMS chip, the contact points between the gate electrode of the sample slice and the second electrode of the MEMS chip, and the contact points between the drain electrode of the sample slice and the third electrode of the MEMS chip, respectively, so as to fix the sample slice on the MEMS chip.

8. The method according to claim 1, characterized in that In the step (8), the ion beam of FIB-SEM is used to etch a partial area on the MEMS chip, which is to first etch a partial area between the first electrode and the second electrode of the MEMS chip using the ion beam of FIB-SEM; and then etch a partial source electrode of the sample slice and a partial second electrode and substrate area of ​​the MEMS chip thereunder.

9. The method according to claim 1, characterized in that: In step (9), the ion beam of FIB-SEM is used to perform ion thinning on one side of the sample slice on the MEMS chip, which is achieved as follows: (9a) The vertical axis of the FIB-SEM sample stage is rotated, the voltage is set to 30 kV, the current is set to 0.44-0.26 nA, and the upper part of the sample slice is etched with an ion beam at the electron beam window of the electron microscope to perform a primary rough thinning with a depth of 3-6 μm; (9b) The vertical axis of the FIB-SEM sample stage is rotated, the voltage is set to 30 kV, the current is set to 46-90 pA, and the upper part of the sample slice is etched with an ion beam in the electron beam window of the electron microscope to perform secondary thinning with a depth of 3-6 μm; (9c) Rotate the vertical axis of the FIB-SEM sample stage, set the voltage to 5 kV and the current to 63 pA, and use ion beam etching to perform three fine thinnings of 30 to 50 s on the upper part of the sample slice in the electron beam window of the electron microscope. If the sample slice is significantly bent during the thinning process, correct it to facilitate subsequent processing; (9d) The vertical axis of the FIB-SEM sample stage is rotated, the voltage is set to 2 kV, the current is set to 44 pA, and the upper part of the sample slice is finely thinned four times for 30 to 50 s using an ion beam in the electron beam window of the electron microscope; (9e) All the values ​​in the above steps are adjusted according to the needs of the actual sample, so that the thickness of the electron transparent sample is 10nm~100nm, and the passivation layer on the electrode of the sample slice is removed, so that the gate is connected to the first deposited Pt layer to facilitate the penetration of the electron beam.

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