Display Panel and its Manufacturing Method

Abstract

This application relates to a display panel and a method for manufacturing the same. The display panel includes an array substrate and a color filter substrate disposed opposite to the array substrate. The array substrate includes a substrate, an active layer, a first metal layer, a second metal layer, a common electrode layer, and a third metal layer sequentially disposed along its thickness direction. The first metal layer includes a gate electrode. The second metal layer includes a source electrode and a drain electrode. The common electrode layer includes at least two common electrodes and at least one first electrode connection line. The third metal layer includes at least two common electrode lines and at least one second electrode connection line. The first electrode connection line connects two adjacent common electrodes, and the second electrode connection line is connected to the common electrode lines. The second electrode connection line is located on the side of the first electrode connection line away from the second metal layer and is in contact with the first electrode connection line. This application can effectively improve the transmittance of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and a method for manufacturing the same. Background Technology

[0002] High transmission fringe field switching (HFS) type displays drive liquid crystal deflection through a horizontal electric field between the common electrode (COM-ITO) and pixel electrode (Pixel-ITO) on the array substrate side, thereby enabling normal display. The voltage on the COM-ITO is provided by the common electrode line (Acom). In traditional common electrode connection designs, to avoid short circuits between the COM-ITOs of two pixels and the gate line when they are connected, vias and bridging metal between the two vias are typically used to connect the COM-ITOs of adjacent pixels. However, because light cannot pass through the vias and the shielding layer (BM) used to block the vias, the aperture ratio decreases significantly, thereby reducing the transmittance of the display panel. Summary of the Invention

[0003] This application provides a display panel and a method for manufacturing the same, which can effectively improve the transmittance of the display panel.

[0004] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, the display panel comprising an array substrate and a color filter substrate disposed opposite to the array substrate; the array substrate comprising:

[0005] Substrate;

[0006] A first metal layer is disposed above the substrate, and the first metal layer includes a gate.

[0007] An active layer is disposed on the side of the first metal layer away from the substrate;

[0008] A second metal layer is disposed on the side of the active layer away from the substrate, and the second metal layer includes a source and a drain.

[0009] A common electrode layer is disposed on the side of the second metal layer away from the active layer, the common electrode layer including at least two common electrodes and at least one first electrode connection line; and

[0010] A third metal layer is disposed on the side of the common electrode layer away from the second metal layer, and the third metal layer includes at least two common electrode lines and at least one second electrode connection line.

[0011] The first electrode connection line connects two adjacent common electrodes, the second electrode connection line is connected to the common electrode line, the second electrode connection line is located on the side of the first electrode connection line away from the second metal layer, and is in contact with the first electrode connection line.

[0012] In some embodiments, the first metal layer further includes a plurality of gate lines extending along a first direction, and the second metal layer further includes a plurality of data lines extending along a second direction. The first direction intersects with the second direction, and the plurality of data lines and the plurality of gate lines are intersected to define a plurality of pixel regions. The common electrode corresponds one-to-one with the pixel region.

[0013] Both the first electrode connecting line and the second electrode connecting line extend along the second direction, and in the second direction, the length of the second electrode connecting line is greater than or equal to the length of the first electrode connecting line.

[0014] In some embodiments, the common electrode line is located on the side of the common electrode away from the second metal layer and is in contact with the common electrode;

[0015] The common electrode line extends along the first direction and is located at the edge of the common electrode. One end of the second electrode connecting line is connected to the common electrode line, and the other end extends toward the adjacent common electrode.

[0016] In some embodiments, the third metal layer further includes a second electrode connection line extension, the second electrode connection line extension being located at one end of the second electrode connection line away from the common electrode line, the orthographic projection of the second electrode connection line extension on the substrate being within the orthographic projection range of the common electrode on the substrate, and the width of the second electrode connection line extension in the first direction being greater than the width of the second electrode connection line in the first direction.

[0017] In some embodiments, the material of the first electrode connecting wire is the same as the material of the common electrode, and the material of the second electrode connecting wire is the same as the material of the common electrode wire.

[0018] In some embodiments, the material of the common electrode is a metal oxide, and the material of the common electrode wire is a metal.

[0019] In some embodiments, the display panel further includes:

[0020] Multiple spacer pillars are disposed between the array substrate and the color filter substrate, and the spacer pillars are located between two adjacent common electrodes;

[0021] The orthographic projections of the first electrode connection line and the second electrode connection line on the substrate are both located between the orthographic projections of the adjacent spacer pillars on the substrate.

[0022] In some embodiments, the array substrate further includes:

[0023] A gate insulating layer is disposed between the first metal layer and the active layer;

[0024] A passivation layer is disposed between the second metal layer and the common electrode layer;

[0025] A planarization layer is disposed on the side of the third metal layer away from the common electrode layer; and

[0026] A pixel electrode layer is disposed on the side of the planarization layer away from the third metal layer;

[0027] The pixel electrode layer is connected to the second metal layer through a first via penetrating the planarization layer and the passivation layer.

[0028] According to a second aspect of this application, a method for manufacturing a display panel is provided, comprising:

[0029] Provide a substrate;

[0030] A first metal layer is formed on the substrate, the first metal layer including a gate;

[0031] An active layer is formed on top of the first metal layer;

[0032] A second metal layer is formed on the active layer, the second metal layer including a source and a drain.

[0033] A common electrode layer is formed on the second metal layer. The common electrode layer includes at least two common electrodes and at least one first electrode connection line. The common electrodes correspond one-to-one with the pixel area. The first electrode connection line connects two adjacent common electrodes.

[0034] A third metal layer is formed on the common electrode layer. The third metal layer includes at least two common electrode lines and at least one second electrode connection line. The second electrode connection line is connected to the common electrode lines and is located on the side of the first electrode connection line away from the second metal layer, and is in contact with the first electrode connection line.

[0035] In some embodiments, the common electrode layer and the third metal layer are formed using a halftone photomask process.

[0036] This application provides a display panel and its manufacturing method. In this application, adjacent common electrodes on the array substrate side of the display panel are connected via a first electrode connection line, and a second electrode connection line is disposed on the first electrode connection line. The second electrode connection line contacts the first electrode connection line and is connected to the common electrode line. Therefore, the common electrode line can transmit a common signal to the two adjacent common electrodes connected by the first electrode connection line through the second electrode connection line. In this application, the first metal layer, the common electrode layer, and the third metal layer are located in different film layers, and there is no short circuit at the overlap. Furthermore, this application directly provides the first electrode connection line on the same layer as the common electrode to bridge the two adjacent common electrodes, enabling signal conduction between adjacent common electrodes and stabilizing the common electrode signal. Simultaneously, the second electrode connection line is stacked with and directly contacts the first electrode connection line to transmit the common signal, enhancing signal conductivity. This application achieves signal connection between adjacent common electrodes without the need for vias and bridging metals connecting the vias, and therefore also eliminates the need for BMs (blocking metals) to obstruct the vias. This improves the pixel aperture ratio, thereby enhancing the transmittance of the display panel. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0039] Figure 1 This is a top view of a display panel provided by existing technology;

[0040] Figure 2 yes Figure 1 Sectional view at point 1-1;

[0041] Figure 3 yes Figure 1 Sectional view at point 2-2 in the middle;

[0042] Figure 4 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0043] Figure 5 This is a top view of a display panel provided in an embodiment of this application;

[0044] Figure 6 yes Figure 5 Sectional view at point 3-3 in the middle;

[0045] Figure 7 yes Figure 5 Sectional view at point 4-4 in the middle;

[0046] Figure 8 yes Figure 5 Sectional view at point 5-5 in the middle;

[0047] Figure 9 This is a top view of the first metal layer of a display panel provided in an embodiment of this application;

[0048] Figure 10 This is a top view of the first and second metal layers of a display panel provided in an embodiment of this application;

[0049] Figure 11 This is a top view of a display panel comprising a first metal layer, a second metal layer, a common electrode layer, and a third metal layer, provided in an embodiment of this application.

[0050] Explanation of reference numerals in the attached figures:

[0051] 10. Display panel; 100. Array substrate; 110. Substrate; 111. Gate insulating layer; 112. Active layer; 1121. Semiconductor structure; 113. Passivation layer; 114. Planarization layer; 115. First contact hole; 116. Second contact hole; 117. Bridging metal; 120. First metal layer; 121. Gate line; 122. Gate; 123. First barrier portion; 130. Second metal layer; 131. Data line; 132. Source; 133. Drain; 134. Second barrier portion; 140, Common electrode layer; 141, Common electrode; 1411, First common electrode; 1412, Second common electrode; 142, First electrode connection line; 143, Third blocking portion; 150, Third metal layer; 151, Common electrode line; 152, Second electrode connection line; 153, Fourth blocking portion; 154, Extension of second electrode connection line; 160, Pixel electrode layer; 170, Limiting barrier; 180, Spacer post; 190, First via; 200, Color filter substrate; 300, Liquid crystal layer. Detailed Implementation

[0052] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0053] Please see Figures 1-3 , Figure 1This is a top view of a display panel provided by the prior art. The display panel includes an array substrate 100 and a color filter substrate 200, and a liquid crystal layer 300 located between the array substrate 100 and the color filter substrate 200.

[0054] Please see Figure 2 The display panel is in HFS display mode, meaning that both the common electrode 141 (COM-ITO) and the pixel electrode (Pixel-ITO) are located on the array substrate 100 side. The liquid crystal deflection is driven by the horizontal electric field between the common electrode 141 and the pixel electrode on the array substrate 100 side. Specifically, the array substrate 100 includes a substrate 110, a common electrode layer 140, a first metal layer 120, a gate insulating layer 111, an active layer 112, a second metal layer 130, a passivation layer 113, and a pixel electrode layer 160, sequentially disposed along its thickness direction. The common electrode layer 140 includes a plurality of common electrodes 141 arranged in an array. The first metal layer 120 includes multiple gate lines 121, which extend along a first direction and are arranged along a second direction. The second metal layer 130 includes multiple data lines 131, which extend along the second direction and are arranged along the first direction. The multiple data lines 131 and the multiple gate lines 121 are intersected to define multiple pixel regions. The common electrode 141 is provided in a one-to-one correspondence with each pixel region.

[0055] Please see Figure 1 and Figure 3 The second metal layer 130 further includes a bridging metal 117. Along the second direction, adjacent pixel regions are respectively provided with a first contact hole 115 and a second contact hole 116. The first contact hole 115 exposes the common electrode 141 of one of the pixel regions, and the second contact hole 116 exposes the common electrode 141 of the other pixel region. Both the first contact hole 115 and the second contact hole 116 are filled with electrode material. The bridging metal 117 contacts the electrode material in the first contact hole 115 and the electrode material in the second contact hole 116 to achieve electrical connection between the common electrodes 141 of the two adjacent pixel regions. However, a shielding layer is usually required above the contact hole. The area shielded above the contact hole cannot transmit light. Therefore, the via design reduces the aperture ratio, thereby reducing the transmittance of the display panel.

[0056] To resolve the above issues, please refer to [link / reference]. Figures 4-11This application provides a display panel 10, which includes an array substrate 100 and a color filter substrate 200 disposed opposite to the array substrate 100. The array substrate 100 includes a substrate 110, an active layer 112, a first metal layer 120, a second metal layer 130, a common electrode layer 140, and a third metal layer 150. The first metal layer 120 is disposed above the substrate 110 and includes a gate electrode 122. The active layer 112 is disposed on the side of the first metal layer 120 away from the substrate 110. The second metal layer 130 is disposed on the side of the first metal layer 120 away from the active layer 112 and includes a source electrode 132 and a drain electrode 133. The common electrode layer 140 is disposed on the side of the second metal layer 130 away from the active layer 112 and includes at least two common electrodes 141 and at least one first electrode. Electrode connection line 142; the third metal layer 150 is disposed on the side of the common electrode layer 140 away from the second metal layer 130, the third metal layer 150 includes at least two common electrode lines 151 and at least one second electrode connection line 152; wherein, the first electrode connection line 142 connects two adjacent common electrodes 141, the second electrode connection line 152 is connected to the common electrode lines 151, the second electrode connection line 152 is located on the side of the first electrode connection line 142 away from the second metal layer 130, and is in contact with the first electrode connection line 142.

[0057] In this application, the array substrate 100 directly provides the first electrode connection line 142 on the same layer as the common electrode 141. Adjacent common electrodes 141 are bridged through the first electrode connection line 142 to achieve signal conduction between adjacent common electrodes 141, thereby stabilizing the signal of the common electrode 141. Therefore, this application does not require vias to connect adjacent common electrodes 141, nor does it require a shielding layer to block vias, effectively improving the aperture ratio. Furthermore, the array substrate 100 of this application provides a second electrode connection line 152 on the first electrode connection line 142. The second electrode connection line 152 contacts the first electrode connection line 142 and connects to the common electrode line 151. The common electrode line 151 can transmit the common signal to the two adjacent common electrodes 141 connected by the corresponding first electrode connection line 142 through the second electrode connection line 152. The second electrode connection line 152 is stacked with the first electrode connection line 142 and in direct contact, which enhances signal conduction and ensures the signal stability of the common electrode 141. Furthermore, the first metal layer 120, the common electrode layer 140, and the third metal layer 150 of this application are located in different film layers, and there will be no short circuit at the overlapping point.

[0058] For further details, please refer to Figures 5-7 The array substrate 100 further includes a gate insulating layer 111, a passivation layer 113, a planarization layer 114, and a pixel electrode layer 160. The gate insulating layer 111 is disposed between the first metal layer 120 and the active layer 112; the passivation layer 113 is disposed between the second metal layer 130 and the common electrode layer 140; the planarization layer 114 is disposed on the side of the third metal layer 150 away from the common electrode layer 140; and the pixel electrode layer 160 is disposed on the side of the planarization layer 114 away from the third metal layer 150.

[0059] In one embodiment, please refer to Figure 5-Figure 11 The array substrate 100 includes a substrate 110, a first metal layer 120, a gate insulating layer 111, an active layer 112, a second metal layer 130, a passivation layer 113, a common electrode layer 140, a third metal layer 150, a planarization layer 114, and a pixel electrode layer 160.

[0060] The substrate 110 may be a flexible substrate, such as polyimide (PI), or a rigid substrate, such as glass, but is not limited thereto.

[0061] The first metal layer 120 is disposed on one side of the substrate 110. (See also...) Figure 5 and Figure 9 The first metal layer 120 includes a gate 122 and a plurality of gate lines 121. The gate 122 is connected to the gate lines 121 and is a part of the gate lines 121. The gate lines 121 extend along a first direction, and the plurality of gate lines 121 are arranged along a second direction. The material of the first metal layer 120 is a metal, such as one or more combinations of Mo, Al, and Cu, but is not limited thereto. In this application, the first direction refers to the X direction in the figure, and the second direction refers to the Y direction in the figure.

[0062] The gate insulating layer 111 is disposed on the side of the first metal layer 120 away from the substrate 110, so that the first metal layer 120 is insulated from the active layer 112 and the second metal layer 130. The material of the gate insulating layer 111 is an inorganic material, such as silicon nitride (SiNx), silicon oxide (SiOx), etc., but is not limited thereto.

[0063] The active layer 112 is disposed on the side of the gate insulating layer 111 away from the first metal layer 120, and includes a semiconductor structure 1121. The semiconductor structure 1121 is disposed on the side of the gate insulating layer 111 away from the gate 122, and serves as part of a thin-film transistor. The material of the active layer 112 may be amorphous silicon (a-Si) or doped amorphous silicon, but is not limited thereto.

[0064] The second metal layer 130 is disposed on the side of the active layer 112 away from the gate insulating layer 111. (See also...) Figure 5 and Figure 10 The second metal layer 130 includes a source 132, a drain 133, and multiple data lines 131. (See also...) Figure 6 The source electrode 132 and the drain electrode 133 are connected to the active layer 112. The source electrode 132, the drain electrode 133, the semiconductor structure 1121, and the gate electrode 122 constitute a thin-film transistor. The data line 131 extends along the second direction, and multiple data lines 131 are arranged along the first direction. The multiple data lines 131 and multiple gate lines 121 are intersected to define multiple pixel regions. Each pixel region corresponds to a pixel unit, and each pixel unit includes one thin-film transistor. For example, the first direction and the second direction can be perpendicular, and the multiple pixel regions can be arranged in an array, that is, arranged in an array along the first direction and the second direction. Correspondingly, the pixel unit and the thin-film transistor are also arranged in an array. The material of the second metal layer 130 is a metal, such as one or more combinations of Mo, Al, and Cu, but is not limited thereto.

[0065] The passivation layer 113 is disposed on the side of the second metal layer 130 away from the active layer 112, and covers the source electrode 132, the drain electrode 133, and the data line 131 to protect the second metal layer 130. The material of the passivation layer 113 is an inorganic material, such as silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0066] The common electrode layer 140 is disposed on the side of the passivation layer 113 away from the second metal layer 130. (See also...) Figure 5 and Figure 11The common electrode layer 140 includes multiple common electrodes 141 and multiple first electrode connection lines 142. Each common electrode 141 corresponds one-to-one with a pixel region, meaning one common electrode 141 is disposed within each pixel region. The common electrodes 141 are block electrodes, and the multiple common electrodes 141 are arranged in an array along the first direction and the second direction. Along the second direction, the multiple common electrodes 141 are spaced apart. The first electrode connection lines 142 are located between adjacent common electrodes 141 and connect adjacent common electrodes 141. The first electrode connection lines 142 enable signal connection between adjacent common electrodes 141 to stabilize the common (COM) signal on the common electrode 141. The material of the common electrode 141 can be a metal oxide, such as indium tin oxide (ITO), but is not limited to this.

[0067] For details, please refer to Figure 5 Taking a first common electrode 1411 and a second common electrode 1412 adjacent in the second direction as an example, the first electrode connecting line 142 extends along the second direction, one end of the first electrode connecting line 142 is connected to the first common electrode 1411, and the other end of the first electrode connecting line 142 is connected to the second common electrode 1412. The material of the first electrode connecting line 142 can be the same as the material of the common electrode 141, so that the first electrode connecting line 142 and the common electrode 141 can be set in the same layer, that is, patterned using the same process, to simplify the process.

[0068] The third metal layer 150 is disposed on the side of the common electrode layer 140 away from the passivation layer 113. (See also...) Figure 5 and Figure 11 The third metal layer 150 includes multiple common electrode lines 151 and multiple second electrode connection lines 152. The multiple common electrode lines 151 are arranged along the second direction and extend along the first direction. The common electrode lines 151 are used to provide a common signal to the common electrode 141. Please refer to [link / reference]. Figure 5 and Figure 7The second electrode connection line 152 is connected to the common electrode line 151. The second electrode connection line 152 is located on the side of the first electrode connection line 142 away from the second metal layer 130 and is in contact with the first electrode connection line 142. Therefore, the common signal of the common electrode line 151 can be transmitted to the two adjacent common electrodes 141 connected to the corresponding first electrode connection line 142 through the second electrode connection line 152 connected to it. The second electrode connection line 152 and the first electrode connection line 142 are stacked and in contact, together forming a signal connection line between adjacent common electrodes 141, which can increase the overall conductivity of the signal connection line between two adjacent common electrodes 141, thereby further improving the signal stability of the common electrode 141.

[0069] In this application, the material of the second electrode connection line 152 is the same as the material of the common electrode line 151, so that the second electrode connection line 152 and the common electrode line 151 are disposed in the same layer, that is, patterned using the same process, to simplify the process. The material of the third metal layer 150 is metal, that is, the material of the second electrode connection line 152 and the material of the common electrode line 151 are metals, such as one or more combinations of Mo, Al, and Cu, but not limited to these.

[0070] For details, please refer to Figure 5 Both the first electrode connection line 142 and the second electrode connection line 152 extend along the second direction. In the second direction, the length of the second electrode connection line 152 is greater than or equal to the length of the first electrode connection line 142. That is, one end of the second electrode connection line 152 extends to the first common electrode 1411, and the other end of the second electrode connection line 152 extends to the second common electrode 1412. This is beneficial for the common electrode 141 that is far away from the common electrode line 151 among two adjacent common electrodes 141 to maintain signal stability.

[0071] In this application, one common electrode line 151 can be correspondingly provided for each pixel area. The common electrode line 151 can be disposed on the edge of the common electrode 141, located on the side of the common electrode 141 away from the second metal layer 130, and in contact with the common electrode 141 to facilitate signal transmission to the common electrode 141 and connection with the second electrode connection line 152, while reducing the impact on the pixel opening area. One end of the second electrode connection line 152 is connected to the common electrode line 151, and the other end extends toward the adjacent common electrode 141. For details, please refer to [link to relevant documentation]. Figure 5The common electrode line 151 can be located at the edge of the second common electrode 1412 near the first common electrode 1411. One end of the second electrode connecting line 152 is connected to the common electrode line 151, and the other end extends into the range of the second common electrode 1412.

[0072] In some embodiments, please refer to Figure 5 and Figure 11 The third metal layer 150 further includes a second electrode connection line extension 154, which is located at the end of the second electrode connection line 152 away from the common electrode line 151. The orthographic projection of the second electrode connection line extension 154 on the substrate 110 lies within the orthographic projection range of the common electrode 141 on the substrate 110. The length of the second electrode connection line 152 in the second direction is equal to the length of the first electrode connection line 142 in the second direction. Figure 11 The second electrode connection line 152 covers the first electrode connection line 142, and the width of the extension portion 154 of the second electrode connection line in the first direction is greater than the width of the second electrode connection line 152 in the first direction. This can increase the contact area between the second electrode connection line 152 and the common electrode 141 on the side away from the common electrode line 151, further enhancing the signal conductivity between two adjacent common electrodes 141, so as to ensure the signal stability of the common electrode 141.

[0073] The planarization layer 114 is disposed on the side of the third metal layer 150 away from the common electrode layer 140, and is used to planarize the third metal layer 150. The material of the planarization layer 114 is an organic material, such as soluble polytetrafluoroethylene (PFA), but not limited thereto.

[0074] The pixel electrode layer 160 is disposed on the side of the planarization layer 114 away from the third metal layer 150. The pixel electrode layer 160 is a strip electrode or a comb electrode. A first via 190 penetrating the passivation layer 113 and the planarization layer 114 is also disposed on the array substrate 100. The first via 190 exposes the drain 133 located in the second metal layer 130. The pixel electrode layer 160 is electrically connected to the drain 133 of the thin-film transistor through the first via 190. The drain 133 is connected to the source 132 through the semiconductor structure 1121. The source 132 is connected to the data line 131, thus realizing signal transmission between the data line 131 and the pixel electrode layer 160. The material of the pixel electrode layer 160 can be a metal oxide, such as indium tin oxide (ITO), but is not limited thereto.

[0075] In this application, the array substrate 100 provides a data signal to the pixel electrode layer 160 through the data line 131, and the common electrode 141 provides a common signal through the common electrode line 151. The liquid crystal is deflected under the action of the data signal and the common signal, thereby realizing the display of the screen on the display panel 10, i.e., HFS display mode. The deflection of the liquid crystal is driven by the horizontal electric field between the common electrode 141 and the pixel electrode layer 160 on the array substrate 100 side.

[0076] In this application, please refer to Figure 4 The display panel 10 also includes a liquid crystal layer 300 and a plurality of spacer pillars 180.

[0077] The liquid crystal layer 300 is disposed between the array substrate 100 and the color filter substrate 200, and the display panel 10 displays images by deflecting the liquid crystal molecules.

[0078] The spacer post 180 is disposed between the array substrate 100 and the color filter substrate 200, serving a supporting function. For details, please refer to [link to relevant documentation]. Figure 5 The orthographic projection of the spacer post 180 on the substrate 110 is located in the non-display area between the orthographic projections of two adjacent common electrodes 141 on the substrate 110, thereby reducing the impact on the pixel aperture ratio. The spacer post 180 is located on one side of the thin-film transistor in the first direction to make reasonable use of the non-display area between two adjacent common electrodes 141 and improve the pixel aperture ratio.

[0079] In this application, the orthographic projections of the first electrode connection line 142 and the second electrode connection line 152 on the substrate 110 are both located between the orthographic projections of the adjacent spacer pillars 180 on the substrate 110. This makes reasonable use of space and reduces the risk of interference between the first electrode connection line 142, the second electrode connection line 152 and the metal lines such as the thin film transistor and the data line 131 due to excessively close distance.

[0080] In some embodiments, the display panel 10 further includes a limiting barrier 170 located on the array substrate 100, the limiting barrier 170 being located on at least one side of the spacer post 180. For details, please refer to... Figure 5 and Figure 8The orthographic projection of the limiting barrier 170 on the substrate 110 lies between the orthographic projection of the common electrode 141 on the substrate 110 and the orthographic projection of the spacer post 180 on the substrate 110. The limiting barrier 170 includes a first blocking portion 123, a second blocking portion 134, a third blocking portion 143, and a fourth blocking portion 153 sequentially arranged along the thickness direction of the substrate 110. The first blocking portion 123 is located in the first metal layer 120 and is made of the same material as the first metal layer 120; the second blocking portion 134 is located in the second metal layer 130 and is made of the same material as the second metal layer 130; the third blocking portion 143 is located in the common electrode layer 140 and is made of the same material as the common electrode layer 140; and the fourth blocking portion 153 is located in the third metal layer 150 and is made of the same material as the third metal layer 150. By simultaneously forming the first blocking portion 123, the second blocking portion 134, the third blocking portion 143, and the fourth blocking portion 153 during the fabrication of the first metal layer 120, the second metal layer 130, the common electrode layer 140, and the third metal layer 150, respectively, each of these portions is an independent protruding structure. These portions are stacked in the thickness direction of the substrate 110 to form a protruding structure, constituting the limiting barrier 170. This prevents the spacer pillar 180 from sliding during the alignment of the array substrate 100 and the color filter substrate 200, thus limiting the spacer pillar 180. The limiting barrier 170 can be disposed on one side or opposite sides of the spacer pillar 180 in the second direction; no specific limitation is imposed here.

[0081] This application also provides a method for manufacturing a display panel 10, the method comprising:

[0082] Provide a substrate 110;

[0083] A first metal layer 120 is formed on the substrate 110, and the first metal layer 120 includes a gate 122;

[0084] A gate insulating layer 111 is formed on the first metal layer 120;

[0085] An active layer 112 is formed on the gate insulating layer 111;

[0086] A second metal layer 130 is formed on the active layer 112, the second metal layer 130 including a source 132 and a drain 133;

[0087] A passivation layer 113 is formed on the second metal layer 130;

[0088] A common electrode layer 140 is formed on the passivation layer 113. The common electrode layer 140 includes at least two common electrodes 141 and at least one first electrode connection line 142, wherein the first electrode connection line 142 connects two adjacent common electrodes 141.

[0089] A third metal layer 150 is formed on the common electrode layer 140. The third metal layer 150 includes at least two common electrode lines 151 and at least one second electrode connection line 152. The second electrode connection line 152 is connected to the common electrode lines 151. The second electrode connection line 152 is located on the side of the first electrode connection line 142 away from the second metal layer 130 and is in contact with the first electrode connection line 142.

[0090] A planarization layer 114 is formed on the third metal layer 150; and

[0091] A pixel electrode layer 160 is formed on the planarization layer 114 to form the array substrate 100.

[0092] Furthermore, the method for manufacturing the display panel 10 also includes:

[0093] Spacer pillars 180 are formed on the array substrate 100;

[0094] A color filter substrate 200 is provided, and the color filter substrate 200 is paired with the array substrate 100, wherein one end of the spacer post 180 is connected to the array substrate 100 and the other end is connected to the color filter substrate 200.

[0095] Liquid crystal is injected between the array substrate 100 and the color filter substrate 200 to form the display panel 10.

[0096] In some embodiments, during the fabrication of the array substrate 100, the common electrode layer 140 and the third metal layer 150 can be formed using a single halftone photomask process. Forming the patterns of the common electrode layer 140 and the third metal layer 150 using a single photomask process saves on fabrication steps, simplifies the process, and reduces costs. Since the common electrode layer 140 and the third metal layer 150 are made of different materials and are located on different layers, the photomasks for the common electrode layer 140 and the third metal layer 150 can be implemented using a halftone process.

[0097] Specifically, taking the HFS display panel 10 with a 6-mask process as an example, the fabrication method of the array substrate 100 includes:

[0098] S1. A substrate 110 is provided. The substrate 110 may be a flexible substrate, such as polyimide (PI), or a rigid substrate, such as glass.

[0099] S2. A first metal material layer is deposited on the substrate 110. The first metal material layer is patterned using a first photomask process to form the pattern of the first metal layer 120. (See also...) Figure 9 The first metal layer 120 includes multiple gate lines 121, gates 122, and a first blocking portion 123. The material of the first metal layer 120 is a metal, such as one or more combinations of Mo, Al, and Cu.

[0100] S3. A gate insulating material layer is deposited on the first metal layer 120 to form the gate insulating layer 111. The gate insulating layer 111 is made of an inorganic material, such as silicon nitride (SiNx) or silicon oxide (SiOx).

[0101] S4. An active material layer is deposited on the gate insulating layer 111. The active layer 112 may be made of amorphous silicon (a-Si) or doped amorphous silicon.

[0102] S5. A second metal material layer is deposited on the active film layer. A second photomask process is then used to pattern the active material layer and the second metal material layer, forming the patterns of the active layer 112 and the second metal layer 130. The active layer 112 includes a semiconductor structure 1121. (See also...) Figure 10 The second metal layer 130 includes multiple data lines 131, a source electrode 132, a drain electrode 133, and a second blocking portion 134. By forming the patterns of the active layer 112 and the second metal layer 130 in a single photomask process, the number of photomask operations can be reduced, the process simplified, and costs lowered. The material of the second metal layer 130 is a metal, such as one or more combinations of Mo, Al, and Cu.

[0103] S6. A passivation material layer is deposited on the second metal layer 130. The passivation material layer is patterned using a third photomask process to form the passivation layer 113. The passivation layer 113 includes a second via, which exposes the drain electrode 133. The material of the passivation layer 113 is an inorganic material, such as silicon nitride (SiNx) or silicon oxide (SiOx).

[0104] S7. A common electrode material layer is deposited on the passivation layer 113. The material of the common electrode 141 may be indium tin oxide (ITO).

[0105] S8. A third metal material layer is deposited on the common electrode material layer. A fourth photomask process is then used to pattern the common electrode material layer and the third metal material layer, forming the patterns of the common electrode layer 140 and the third metal layer 150. (See also...) Figure 11 The common electrode layer 140 includes a common electrode 141, a first electrode connecting line 142, and a third blocking portion 143. The first electrode connecting line 142 connects two adjacent common electrodes 141. The third metal layer 150 includes a common electrode line 151, a second electrode connecting line 152, a second electrode connecting line extension 154, and a fourth blocking portion 153. The second electrode connecting line 152 is connected to the common electrode line 151 and is located on the side of the first electrode connecting line 142 away from the second metal layer 130, and is in contact with the first electrode connecting line 142. The second electrode connecting line extension 154 is located at the end of the second electrode connecting line 152 away from the common electrode line 151. The material of the third metal layer 150 is a metal, such as one or more combinations of Mo, Al, and Cu.

[0106] S9. A planarization material layer is deposited on the third metal layer 150. The planarization material layer is patterned through a fifth photomask process to form the planarization layer 114. The planarization layer 114 includes a third via, which communicates with the second via to form the first via 190. The material of the planarization layer 114 may be PFA.

[0107] S10. A pixel electrode material layer is deposited on the planarization layer 114. The pixel electrode material layer is patterned by a sixth photomask process to form the pattern of the pixel electrode layer 160. The pixel electrode layer 160 is connected to the drain 133 through the first via 190 to form the array substrate 100.

[0108] In this application, the display panel 10 may be of the Fringe Field Switching (FFS) display type, the High Transmission Fringe Field Switching (HFS) display type, etc., but is not limited to these.

[0109] This application provides a display panel and its manufacturing method. In this application, adjacent common electrodes on the array substrate side of the display panel are connected via a first electrode connection line, and a second electrode connection line is disposed on the first electrode connection line. The second electrode connection line contacts the first electrode connection line and is connected to the common electrode line. Therefore, the common electrode line can transmit a common signal to the two adjacent common electrodes connected by the first electrode connection line through the second electrode connection line. In this application, the first metal layer, the common electrode layer, and the third metal layer are located in different film layers, and there is no short circuit at the overlap. Furthermore, this application directly provides the first electrode connection line on the same layer as the common electrode to bridge the two adjacent common electrodes, enabling signal conduction between adjacent common electrodes and stabilizing the common electrode signal. Simultaneously, the second electrode connection line is stacked with and directly contacts the first electrode connection line to transmit the common signal, enhancing signal conductivity. This application achieves signal connection between adjacent common electrodes without the need for vias and bridging metals connecting the vias, and therefore also eliminates the need for BMs (blocking metals) to obstruct the vias. This improves the pixel aperture ratio, thereby enhancing the transmittance of the display panel.

[0110] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0111] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0112] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0113] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, It includes an array substrate and a color filter substrate disposed opposite to the array substrate; the array substrate includes: Substrate; A first metal layer is disposed above the substrate, and the first metal layer includes a gate. An active layer is disposed on the side of the first metal layer away from the substrate; A second metal layer is disposed on the side of the active layer away from the substrate, and the second metal layer includes a source and a drain. A common electrode layer is disposed on the side of the second metal layer away from the active layer, the common electrode layer including at least two common electrodes and at least one first electrode connection line; and A third metal layer is disposed on the side of the common electrode layer away from the second metal layer, and the third metal layer includes at least two common electrode lines and at least one second electrode connection line. The first electrode connection line connects two adjacent common electrodes, the second electrode connection line is connected to the common electrode line, the second electrode connection line is located on the side of the first electrode connection line away from the second metal layer, and is in contact with the first electrode connection line.

2. The display panel according to claim 1, characterized in that, The first metal layer further includes multiple gate lines extending along a first direction, and the second metal layer further includes multiple data lines extending along a second direction. The first direction intersects with the second direction. The multiple data lines and the multiple gate lines are intersected to define multiple pixel regions, and the common electrode corresponds to each pixel region. Both the first electrode connecting line and the second electrode connecting line extend along the second direction, and in the second direction, the length of the second electrode connecting line is greater than or equal to the length of the first electrode connecting line.

3. The display panel according to claim 2, characterized in that, The common electrode line is located on the side of the common electrode away from the second metal layer and is in contact with the common electrode; The common electrode line extends along the first direction and is located at the edge of the common electrode. One end of the second electrode connecting line is connected to the common electrode line, and the other end extends toward the adjacent common electrode.

4. The display panel according to claim 3, characterized in that, The third metal layer further includes a second electrode connection line extension, which is located at the end of the second electrode connection line away from the common electrode line. The orthographic projection of the second electrode connection line extension on the substrate is within the orthographic projection range of the common electrode on the substrate, and the width of the second electrode connection line extension in the first direction is greater than the width of the second electrode connection line in the first direction.

5. The display panel according to claim 1, characterized in that, The material of the first electrode connecting wire is the same as the material of the common electrode, and the material of the second electrode connecting wire is the same as the material of the common electrode wire.

6. The display panel according to claim 5, characterized in that, The common electrode is made of metal oxide, and the common electrode wire is made of metal.

7. The display panel according to any one of claims 1 to 6, characterized in that, The display panel also includes: Multiple spacer pillars are disposed between the array substrate and the color filter substrate, and the orthographic projection of the spacer pillars on the substrate is located between the orthographic projections of two adjacent common electrodes on the substrate; The orthographic projections of the first electrode connection line and the second electrode connection line on the substrate are both located between the orthographic projections of the adjacent spacer pillars on the substrate.

8. The display panel according to any one of claims 1 to 6, characterized in that, The array substrate further includes: A gate insulating layer is disposed between the first metal layer and the active layer; A passivation layer is disposed between the second metal layer and the common electrode layer; A planarization layer is disposed on the side of the third metal layer away from the common electrode layer; and A pixel electrode layer is disposed on the side of the planarization layer away from the third metal layer; The pixel electrode layer is connected to the second metal layer through a first via penetrating the planarization layer and the passivation layer.

9. A method for manufacturing a display panel, characterized in that, include: Provide a substrate; A first metal layer is formed on the substrate, the first metal layer including a gate; An active layer is formed on top of the first metal layer; A second metal layer is formed on the active layer, the second metal layer including a source and a drain. A common electrode layer is formed on the second metal layer, the common electrode layer including at least two common electrodes and at least one first electrode connection line, the first electrode connection line connecting two adjacent common electrodes; A third metal layer is formed on the common electrode layer. The third metal layer includes at least two common electrode lines and at least one second electrode connection line. The second electrode connection line is connected to the common electrode lines and is located on the side of the first electrode connection line away from the second metal layer, and is in contact with the first electrode connection line.

10. The method for manufacturing a display panel according to claim 9, characterized in that, The common electrode layer and the third metal layer are formed using a single halftone photomask process.

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