Multistage cluster type three-dimensional network-on-chip system for neural network simulation

Abstract

The invention relates to a network-on-chip system, in particular to a multilevel cluster type three-dimensional network-on-chip system for neural network simulation. The multi-stage cluster type three-dimensional network-on-chip system for neural network simulation comprises a plurality of functional nodes, each functional node comprises a routing chip and a plurality of computing chips which are vertically stacked, and the routing chip is arranged at the bottom of the computing chips; the computing chip comprises a processing core, a first-level router, a second-level router and a higher-level router, the routing chip comprises the second-level router and the higher-level router, and the highest-level router of the computing chip and the highest-level router of the routing chip are the same in level. According to the invention, a multi-stage cluster type three-dimensional network-on-chip structure design is adopted, and the connection distance between chips is shortened through three-dimensional stacking in the functional nodes, so that the data transmission delay between chips is reduced, and the calculation efficiency of the system is improved.

Description

Technical Field

[0001] The present invention relates to a network-on-chip system, and in particular to a multi-level cluster type three-dimensional network-on-chip system for neural network simulation. Background Art

[0002] Neuromorphic systems used for on-chip neural network simulation are usually composed of multiple chips. The efficiency of on-chip and inter-chip communication is one of the main factors affecting system performance. On-chip network technology is often used to solve such communication problems. In neural network simulation, the processor core of the on-chip network can be regarded as a neuron model, and the routing node is similar to the synapse of the neuron. Through the interconnection between routing nodes, the application of on-chip network technology can complete the simulation of neural network calculation. However, the current two-dimensional on-chip neural network architecture is difficult to adapt to the needs of large-scale neural network simulation, and cannot simulate the local connection characteristics and global connection characteristics of the neural network at the same time, and the scalability needs to be improved. The existing single-level parallel design of the three-dimensional on-chip network structure will cause resource competition and link congestion when facing large-scale neural network calculations. The simple three-dimensional stacking structure is difficult to meet the real-time requirements of large-scale neural simulation. It is necessary to design an expandable neural network simulation chip network structure to reduce the delay of data transmission and increase the number of neurons that can be simulated. Summary of the invention

[0003] The technical problem to be solved by the present invention is to overcome the deficiencies in the prior art and provide a multi-level cluster type three-dimensional network-on-chip system for neural network simulation.

[0004] The present invention is achieved through the following technical solutions:

[0005] A multi-level clustered three-dimensional on-chip network system for neural network simulation, the on-chip network system comprising a plurality of functional nodes, the functional nodes comprising a routing chip and a plurality of computing chips arranged in a vertical stack, the routing chip being arranged at the bottom of the plurality of computing chips;

[0006] The computing chip includes a processing core, a first-level router, a second-level router and a higher-level router, the routing chip includes a second-level router and a higher-level router, and the highest-level router of the computing chip is of the same level as the highest-level router of the routing chip;

[0007] The first-level router is connected to the plurality of processing cores on the same computing chip, and two adjacent first-level routers on the same computing chip are connected;

[0008] The secondary router and higher-level routers on the computing chip are connected to multiple lower-level routers on the same computing chip, the secondary router and higher-level routers on the routing chip are connected to multiple same-level routers on the same routing chip, the secondary routers and higher-level routers on the routing chip are connected to multiple lower-level routers on the routing chip, and the secondary routers and higher-level routers are also connected to corresponding same-level routers on adjacent computing chips or corresponding same-level routers on adjacent routing chips.

[0009] Furthermore, the computing chip includes a plurality of neuron computing modules.

[0010] Furthermore, the neuron computing module includes:

[0011] A neuron model, which is used to calculate the firing data of neurons;

[0012] Block random access memory, which is used to store neuron and synapse parameters to achieve time division multiplexing;

[0013] Plastic synaptic model, which is used to calculate the connection strength between each neuron model.

[0014] Furthermore, the network-on-chip system includes three higher-level routers.

[0015] Further, the first-level router connects four adjacent processing cores on the same computing chip; and / or

[0016] The first-level router is connected to four adjacent first-level routers on the same computing chip; and / or

[0017] The secondary router on the computing chip is connected to four adjacent primary routers on the same computing chip; and / or

[0018] The secondary router is connected to the secondary router at the corresponding position on the adjacent computing chip or the corresponding secondary router on the adjacent routing chip; and / or

[0019] The third-level router on the computing chip is connected to four adjacent second-level routers on the same computing chip; and / or

[0020] The three-level router is connected to a corresponding three-level router on an adjacent computing chip or a corresponding three-level router on an adjacent routing chip; and / or

[0021] The third-level router on the routing chip is connected to four adjacent second-level routers on the same routing chip.

[0022] Furthermore, the network-on-chip system also includes a baseboard, and the plurality of functional nodes are deployed on the baseboard.

[0023] Furthermore, the base plate includes a communication interface, and the communication interface is used to connect a power supply, a digital-to-analog signal conversion module and a USB communication interface.

[0024] The beneficial effects of the present invention are as follows: the present invention designs a multi-level cluster-type three-dimensional network-on-chip structure in response to the needs of large-scale neural network hardware simulation, and forms an extensible system by stacking functional nodes including computing chips and routing chips. The main advantages are: first, the three-dimensional stacking structure inside the functional node shortens the connection distance between chips, thereby reducing the inter-chip data transmission delay inside the functional node; second, it enhances the scalability of the system, so that the system can continue to expand based on the grid topology structure with functional nodes as units; third, this architecture can be regarded as a two-level cluster design, with a first-level cluster inside the functional node, which has a lower inter-chip data transmission delay and can simulate the local connection characteristics of neurons in the neural network. Multiple first-level clusters can form a second-level cluster with a higher inter-chip data transmission delay, which can simulate the global connection characteristics of neurons in the neural network. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the connection structure of multiple functional nodes of the present invention.

[0026] Figure 2 It is a schematic diagram of the structure of the computing chip of the present invention.

[0027] Figure 3 It is a structural schematic diagram of the neuron computing module of the present invention.

[0028] Figure 4 It is a schematic diagram of the structure of the routing chip of the present invention.

[0029] Figure 5 It is a schematic diagram of the connection structure of multiple chips of the functional node of the present invention. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and the best embodiment. Based on the embodiments in the invention, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the invention.

[0031] In the description of the invention, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside" and "outside" etc. indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they cannot be understood as limitations on the invention.

[0032] In addition, it should be noted that in the description of the present invention, unless otherwise clearly specified and limited, the terms "installation", "setting", and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, an indirect connection through an intermediate medium, or the internal connection of two components. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0033] Reference Figure 1 The present invention provides a multi-level cluster three-dimensional network-on-chip system for neural network simulation. The system includes multiple functional nodes, each of which is similar to a hierarchical brain columnar cortex microcircuit. The functional node includes a routing chip and multiple computing chips arranged in a vertical stack, and the routing chip is arranged at the bottom of the multiple computing chips. The number of chips in the functional node can be increased or decreased according to actual needs. The network-on-chip of the functional node adopts a multi-level cluster three-dimensional mesh structure, which combines the advantages of cluster mesh routing and hierarchical routing, enhances the scalability of the system, and is conducive to large-scale implementation and application. When the number of functional nodes is small, a simple and efficient grid structure is selected to connect them. This architecture can be regarded as a two-level cluster design, in which the functional node is a first-level cluster with a low inter-chip data transmission delay, which can simulate the local connection characteristics of neurons in a neural network, and multiple first-level clusters can form a second-level cluster with a high inter-node data transmission delay, which can simulate the global connection characteristics of neurons in a neural network.

[0034] Reference Figure 2 , a plurality of processing cores P are arranged on the computing chip. In this embodiment, 64 processing cores P are arranged on one computing chip. A neuron computing module is arranged in the processing core P. Figure 3The neuron computing module includes a neuron model, a block random access memory, and a plastic synapse model. The neuron model is the main computing unit, which is used to calculate the discharge data of neurons. The English name of block random access memory is Block Random Access Memory, abbreviated as BRAM. BRAM is used to store neuron and synapse parameters to complete time division multiplexing. The plastic synapse model is used to calculate the connection strength between each neuron model. Since the neuron model computing unit and BRAM inside the chip are close to each other, it can simulate the "storage and computing in one" characteristics of the human brain to a certain extent.

[0035] The specific steps of the neuron computing module are as follows: when the neuron core receives a data packet containing pulse event information, it first decodes the data packet for synaptic current calculation, then updates the neuron state and weight, and performs time-division multiplexing calculations according to the configuration parameters. After the neuron state and synaptic weight are updated, the corresponding parameters are stored in the corresponding BRAM, and the neuron discharge data will also be output to the router for the next step.

[0036] Continue to refer to Figure 2 , a plurality of first-level routers R1 are also provided on the computing chip. In the present embodiment, 16 first-level routers R1 are provided on a computing chip. Each first-level router R1 is connected to four nearby processing cores P. The first-level router R1 is also connected to a nearby first-level router R1. In the present embodiment, a first-level router R1 is connected to a maximum of four first-level routers R1. The first-level router R1 can receive information input by the processing core P. When there is a large amount of incoming information, it is first input into the input cache module for cache before routing, and is used sequentially under the control of the cache controller after the first-in-first-out queue virtual channel. The data input from the processing core P needs to be packaged into one or more data packets by the data packet processor. The number of data packets and the destination address are determined by the neuron synapse routing table. The synapse routing table stores the numbers of all other nodes connected to the current node, which can be modified by the designer according to the connection relationship between neurons, thereby supporting the completion of the connection between any neurons.

[0037] The computing chip is also provided with a plurality of second-level routers R2. In this embodiment, one computing chip is provided with four second-level routers R2. Each second-level router R2 on the computing chip is connected to a nearby first-level router R1. In this embodiment, one second-level router R2 on the computing chip is connected to at most four first-level routers R1.

[0038] A third-level router R3 is also provided on the computing chip. In this embodiment, one third-level router R3 is provided on one computing chip. The third-level router R3 on the computing chip is connected to the second-level router R2. In this embodiment, one third-level router R3 on the computing chip is connected to four second-level routers R2.

[0039] The working principle of the second-level router R2 and the third-level router R3 on the computing chip are similar to that of the first-level router R1. In addition, the second-level router R2 is also connected to the second-level router R2 on other chips, and the third-level router R3 is also connected to the third-level router R3 on other chips.

[0040] Although in the present embodiment, the computing chip includes 64 processing cores P, 16 first-level routers R1, 4 second-level routers R2 and 1 third-level router R3, this arrangement is not a limitation of the present application. Without departing from the principle of the present invention, those skilled in the art may also adopt other arrangements in other embodiments, for example, other numbers of processing cores P and routers at all levels may also be arranged, the highest level of the router may also be adjusted, and the number of connections of each router may also be adjusted. These changes do not deviate from the basic principle of the present application, and therefore will fall within the protection scope of the present application.

[0041] Reference Figure 4 , a plurality of secondary routers R2 are arranged on the routing chip. In this embodiment, four secondary routers R2 are arranged on one routing chip. A secondary router R2 on a routing chip is connected to a nearby secondary router R2. In this embodiment, a secondary router R2 on a routing chip is connected to at most two secondary routers R2 on the same routing chip.

[0042] A third-level router R3 is also provided on the routing chip. In this embodiment, one third-level router R3 is provided on one routing chip. The third-level router R3 on the routing chip is connected to a nearby second-level router R2. In this embodiment, the third-level router R3 on the routing chip is connected to at most four second-level routers R2.

[0043] Reference Figure 5 The second-level router R2 is also connected to the second-level router R2 at the corresponding position on the adjacent computing chip, or to the second-level router R2 at the corresponding position on the adjacent routing chip. The third-level router R3 is also connected to the third-level router R3 at the corresponding position on the adjacent computing chip, or to the third-level router R3 at the corresponding position on the adjacent routing chip.

[0044] The working principle of the second-level router R2 and the third-level router R3 on the routing chip is similar to that of the second-level router R2 and the third-level router R3 on the computing chip. In addition, the second-level router R2 and the third-level router R3 on the routing chip are also connected to the same-level routers on the routing chip. This setting method can make the second-level router R2 and the third-level router R3 on the routing chip act as horizontal routers to relieve the pressure of routing communication when the load of the first-level router R1 is too high.

[0045] The traditional routing network structure is: the first-level router R1 is used as a horizontal router to connect routers on the same chip, and also as a vertical router to connect routers on adjacent chips. In the routing network structure of this application, the first-level router R1 is only used as a horizontal router, and a second-level router R2 and a third-level router R3 are added.

[0046] Furthermore, the on-chip network system also includes a baseboard, and the bottom routing chips of multiple functional nodes are all arranged on the baseboard. A communication interface is arranged on the baseboard. The communication interface is used to connect a power supply, a digital analog signal conversion module and a USB communication interface.

[0047] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A multi-level clustered three-dimensional network-on-chip system for neural network simulation, characterized in that: The method comprises a plurality of functional nodes, wherein the functional nodes comprise a routing chip and a plurality of computing chips which are vertically stacked, and the routing chip is arranged at the bottom of the plurality of computing chips; The computing chip includes a processing core, a first-level router, a second-level router and a higher-level router, the routing chip includes a second-level router and a higher-level router, and the highest-level router of the computing chip is of the same level as the highest-level router of the routing chip; The first-level router is connected to the plurality of processing cores on the same computing chip, and two adjacent first-level routers on the same computing chip are connected; The secondary router and higher-level routers on the computing chip are connected to multiple lower-level routers on the same computing chip, the secondary router and higher-level routers on the routing chip are connected to multiple same-level routers on the same routing chip, the secondary routers and higher-level routers on the routing chip are connected to multiple lower-level routers on the routing chip, and the secondary routers and higher-level routers are also connected to corresponding same-level routers on adjacent computing chips or corresponding same-level routers on adjacent routing chips.

2. The multi-level cluster type three-dimensional network-on-chip system for neural network simulation according to claim 1, characterized in that: The computing chip includes a plurality of neuron computing modules.

3. The multi-level cluster type three-dimensional network-on-chip system for neural network simulation according to claim 2, characterized in that: The neuron computing module comprises: A neuron model, which is used to calculate the firing data of neurons; Block random access memory, which is used to store neuron and synapse parameters to achieve time division multiplexing; Plastic synaptic model, which is used to calculate the connection strength between each neuron model.

4. The multi-level cluster type three-dimensional network-on-chip system for neural network simulation according to claim 1, characterized in that: The network-on-chip system includes three higher-level routers.

5. The multi-level cluster type three-dimensional network-on-chip system for neural network simulation according to claim 4, characterized in that: The first-level router connects four adjacent processing cores on the same computing chip; and / or The first-level router is connected to four adjacent first-level routers on the same computing chip; and / or The secondary router on the computing chip is connected to four adjacent primary routers on the same computing chip; and / or The secondary router is connected to the secondary router at the corresponding position on the adjacent computing chip or the corresponding secondary router on the adjacent routing chip; and / or The third-level router on the computing chip is connected to four adjacent second-level routers on the same computing chip; and / or The three-level router is connected to the corresponding three-level router on the adjacent computing chip or the corresponding three-level router on the adjacent routing chip; and / or The third-level router on the routing chip is connected to four adjacent second-level routers on the same routing chip.

6. The multi-level cluster type three-dimensional network-on-chip system for neural network simulation according to claim 1, characterized in that: The network-on-chip system further comprises a baseboard, and the plurality of functional nodes are deployed on the baseboard.

7. The multi-level cluster type three-dimensional network-on-chip system for neural network simulation according to claim 6, characterized in that: The base plate comprises a communication interface, and the communication interface is used to connect a power supply, a digital-to-analog signal conversion module and a USB communication interface.

Images