High-voltage capacitor-based level shift circuit adopting gallium nitride full-integration process

Abstract

The invention discloses a high-voltage capacitor-based level shift circuit adopting a gallium nitride full-integration process. The high-voltage capacitor-based level shift circuit comprises an anti-noise level conversion unit, a noise clamping unit, a high-speed latch unit and a reset unit, the anti-noise level conversion unit can realize conversion from a low-side input signal to a high-side output signal, and the symmetrical structure can effectively suppress common-mode noise; the noise clamping unit is used for effectively inhibiting the influence of dVS / dt noise on the circuit and clamping key node voltage to prevent breakdown; the high-speed latch unit is used for quickly restoring an input pulse signal into a level signal; the reset unit is used for generating a pulse signal to open a switch tube to help a key node to discharge charges; the whole circuit can better solve the problem of compromise between circuit power consumption and transmission delay of a traditional level shift circuit, and the problem that the delay of the level shift circuit changes along with VS and loses efficacy due to the influence of dVS / dt noise.

Description

Technical Field

[0001] The present invention relates to a power integrated circuit, and in particular to a level shift circuit based on a high-voltage capacitor using a gallium nitride full integration process, which can be applied to a gate drive circuit of a gallium nitride power tube. Background Art

[0002] Gallium nitride power devices made of third-generation semiconductor materials have excellent physical properties, such as wide bandgap, high electron mobility, high switching frequency, low on-resistance, high voltage resistance and high temperature resistance. They can significantly improve the switching speed, conversion efficiency and power density of the system when used in power conversion systems. With the increase of the operating frequency of the system, the discrete drive solution using silicon-based driver chips to drive gallium nitride devices will induce ringing, overshoot and other problems during the switching process due to its large parasitic inductance in the drive loop, which seriously affects the reliability of the system. In order to deal with this problem, leadless packaging technology can be used as a compromise solution, but this will greatly increase the cost of chip packaging. In order to fundamentally solve these problems, the gallium nitride process can be used to integrate the drive circuit and power devices on the same chip. This method can not only give full play to the high-frequency characteristics of gallium nitride devices, but also improve the reliability of the system, achieving the dual advantages of high-frequency application and stability.

[0003] Benefiting from the current mature N-type GaN fully integrated process, the half-bridge drive circuit and GaN power devices can be integrated on a bare chip to avoid the reliability issues faced by discrete solutions. Among them, the core part of the half-bridge drive circuit is the high-voltage level shift circuit, which converts low-voltage domain signals into high-voltage domain signals, thereby realizing the control of low-voltage signals over high-voltage circuit systems.

[0004] At present, the main problems faced by traditional integrated GaN process level shift circuits are as follows:

[0005] 1. When the low-side input signal is transmitted to the high-side circuit through the level shift circuit, there will be a large transmission delay between the low-side input signal and the high-side output signal. In order to reduce this delay, the on-current of the level conversion branch where the high-voltage GaN field-effect transistor is located in the level shift can be increased, thereby increasing the response speed of the high-side circuit. However, increasing the on-current will increase the power consumption of the circuit. Therefore, there is a severe trade-off between the power consumption and transmission delay of the traditional integrated GaN process level shift circuit.

[0006] 2. In the half-bridge circuit, the power driver tubes on the high and low sides will be turned on alternately, so that the output node VS of the half-bridge circuit will change back and forth between the bus voltage VBUS and the low-side ground GND. VS is the ground signal of the high-side circuit. Since the switching rate of the gallium nitride power tube is fast, the change rate of VS is very fast. The dVS / dt noise signal generated by the parasitic capacitance of the high-voltage power tube will be coupled to the high-side part of the level shift circuit, affecting the normal output signal of the circuit.

[0007] 3. When the half-bridge circuit is working normally, during the high-side and low-side output dead time, the high-side power tube will be turned off and the low-side power tube will not be turned on. In order to continue the current, the load inductor discharges the VS node. Since the GaN transistor has no parasitic body diode, its reverse conduction voltage drop is large, about 3 to 5V, so the VS node voltage will drop to a large negative voltage. This makes it more difficult for the high-side circuit to respond to the low-side input signal, or even not respond.

[0008] 4. In the half-bridge driving circuit, due to the existence of the level shift circuit, there is a difference in transmission delay between the low-side channel output signal and the high-side channel output signal. Although the high- and low-side channel output delays can be matched by adding a delay unit in the low-side circuit, the delay of the delay unit in the low-side circuit will change due to changes in the process-voltage-temperature environment, and the delay of the traditional level shift circuit in the high-side circuit will change with the change of VS. Therefore, traditional GaN half-bridge chips often have the problem of poor delay matching characteristics of the high- and low-side channel circuits.

[0009] 5. As the relevant technologies of existing P-type GaN devices are not yet mature, the carrier mobility of P-type devices is very low compared to N-type devices, and they have no practical value. Therefore, the existing commercial GaN process does not provide P-type devices, which makes it impossible to directly apply mature CMOS circuit structures to GaN circuits. Using only N-type devices will cause the circuit to lose its effective pull-up mechanism, resulting in increased delays in circuit modules such as latch circuits. Summary of the invention

[0010] The present invention provides a level shift circuit based on high-voltage capacitors using a gallium nitride fully integrated process, which can effectively improve the problems of high power consumption and poor delay matching of traditional gallium nitride level shift circuits, and can withstand the influence of dVS / dt noise and VS negative voltage, thereby ensuring the reliability and stability of the power integrated circuit system.

[0011] In order to achieve the purpose of the invention, the technical solution adopted by the present invention is as follows:

[0012] The present invention provides a level shift circuit based on high-voltage capacitors using a fully integrated gallium nitride process, which specifically includes an anti-noise level conversion unit, a high-speed latch unit, a noise clamp unit, and a reset unit. The anti-noise level conversion unit is used to realize the conversion of low-side input signals to high-side output signals, and its symmetrical structure can effectively suppress common-mode noise; the noise clamp unit is used to effectively suppress the influence of dVS / dt noise on the circuit and clamp the voltage of key nodes to prevent breakdown; the high-speed latch unit is used to quickly restore the input pulse signal to a level signal; the reset unit is used to generate a pulse signal to turn on the switch tube to help the key node discharge charge; the input signal V PWM Connect the input port of the anti-noise level conversion unit; the output port node of the anti-noise level conversion unit is V SET and V RESET Connect the two input ports of the high-speed latch unit respectively; the output port node of the high-speed latch unit is V HA and V HB The three output ports of the reset unit are connected to the V OP 、V OS 、V ON The node helps to improve the gate pull-down rate of the two GaN transistors in the symmetrical structure of the anti-noise level conversion unit and enhance the circuit's response to high-frequency input signals. The noise clamp unit is connected to the V OP 、V OS 、V ON node.

[0013] Further, the anti-noise level conversion unit includes a first enhancement transistor, a second enhancement transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first high-voltage capacitor, a second high-voltage capacitor, a third high-voltage capacitor, a first buffer, a second buffer, a third buffer and a first inverter;

[0014] The drain of the first enhancement transistor is connected to one end of the first resistor, and the other end of the first resistor is connected to the high-side power supply VB. The drain of the second enhancement transistor is connected to one end of the second resistor, and the other end of the second resistor is connected to the high-side power supply VB. The sources of the first enhancement transistor and the second enhancement transistor are connected and connected to one end of the second high-voltage capacitor. The gate of the first enhancement transistor is connected to one end of the first high-voltage capacitor, and the gate of the second enhancement transistor is connected to one end of the third high-voltage capacitor. One end of the third resistor is connected to one end of the first high-voltage capacitor, one end of the fourth resistor is connected to one end of the second high-voltage capacitor, one end of the fifth resistor is connected to one end of the third high-voltage capacitor, and the other ends of the third resistor, the fourth resistor, and the fifth resistor are connected to the high-side ground VS together; the power rails of the first buffer, the second buffer, the third buffer, and the first inverter are VDD-GND; the input signal V PWMThe input port of the first buffer is connected to the input port of the first inverter, the output port of the first buffer is connected to one end of the first high-voltage capacitor, the input port of the second buffer is connected to the low-side ground GND, the output port of the second buffer is connected to one end of the second high-voltage capacitor, the input port of the third buffer is connected to the output port of the first inverter, and the output port of the third buffer is connected to one end of the third high-voltage capacitor.

[0015] Further, the power rail of the high-speed latch unit is VB-VS; the high-speed latch unit includes a first diode, a second diode, a third diode, a fourth diode, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a third enhancement-mode transistor, a fourth enhancement-mode transistor, a fifth enhancement-mode transistor, a sixth enhancement-mode transistor, a first capacitor, a second capacitor, and an output-stage fourth buffer;

[0016] The gate of the third enhancement transistor is connected to the anode of the third diode and one end of the first capacitor, the drain of the third enhancement transistor is connected to one end of the sixth resistor, the source of the third enhancement transistor is connected to the other end of the first capacitor, the gate of the fifth enhancement transistor, the drain of the sixth enhancement transistor and one end of the eighth resistor, the gate of the fourth enhancement transistor is connected to the anode of the fourth diode and one end of the second capacitor, the drain of the fourth enhancement transistor is connected to one end of the seventh resistor, the source of the fourth enhancement transistor is connected to the other end of the second capacitor, the drain of the fifth enhancement transistor, the gate of the sixth enhancement transistor, one end of the ninth resistor and the input end of the fourth buffer, the anode of the first diode is connected to the cathode of the third diode, the cathode of the first diode is connected to the high-side power supply VB, the anode of the second diode is connected to the cathode of the fourth diode, the cathode of the second diode is connected to the high-side power supply VB, the other ends of the sixth resistor and the seventh resistor are connected to the high-side power supply VB, the sources of the fifth enhancement transistor and the sixth enhancement transistor and the other ends of the eighth resistor and the ninth resistor are connected to the high-side ground VS.

[0017] Further, the power rail of the noise clamp unit is VB-VS. The noise clamp unit includes a seventh enhancement transistor, an eighth enhancement transistor, a ninth enhancement transistor, a fifth diode, a sixth diode and a seventh diode; the drain of the seventh enhancement transistor is connected to the cathode of the fifth diode, the gate of the seventh enhancement transistor is connected to the gate of the ninth enhancement transistor, the gate and the drain of the eighth enhancement transistor, the drain of the eighth enhancement transistor is connected to the cathode of the sixth diode, the drain of the ninth enhancement transistor is connected to the cathode of the seventh diode, and the anodes of the fifth diode, the sixth diode and the seventh diode and the sources of the seventh enhancement transistor, the eighth enhancement transistor and the ninth enhancement transistor are connected to the high-side ground VS.

[0018] Furthermore, the power rail of the reset unit is VB-VS, and the reset unit includes a pulse generation module, a tenth enhancement mode transistor, an eleventh enhancement mode transistor, and a twelfth enhancement mode transistor; the input interface of the pulse generation module is connected to the V HA 、V HB The output port of the pulse generating module outputs the Vctrl signal and is connected to the gates of the tenth enhancement mode transistor, the eleventh enhancement mode transistor and the twelfth enhancement mode transistor. The sources of the tenth enhancement mode transistor, the eleventh enhancement mode transistor and the twelfth enhancement mode transistor are commonly connected to the high side ground VS. The drains of the tenth enhancement mode transistor, the eleventh enhancement mode transistor and the twelfth enhancement mode transistor are respectively connected to the V of the anti-noise level conversion unit. OP 、V OS 、V ON node.

[0019] Furthermore, the power rail of the pulse generating module is VB-VS, and the pulse generating module includes an OR gate, a first AND gate, a second AND gate, a second inverter, a third inverter, a first delay device and a second delay device; the output of the second delay device is connected to the input of the first delay device, the output of the first delay device and the input of the second inverter are simultaneously connected to the two input ports of the first AND gate, the output of the third inverter is connected to the input of the second delay device, the output of the second delay device and the input of the third inverter are simultaneously connected to the two input ports of the second AND gate, the outputs of the first AND gate and the second AND gate are connected to the two input ports of the OR gate, and the output port of the OR gate outputs the Vctrl signal.

[0020] Furthermore, the first buffer, the second buffer, the third buffer and the fourth buffer include a thirteenth enhancement-mode transistor, a fourteenth enhancement-mode transistor and a fourth inverter; the input port of the fourth inverter is connected to the gate of the fourteenth enhancement-mode transistor, the output port of the fourth inverter is connected to the gate of the thirteenth enhancement-mode transistor, and the source of the thirteenth enhancement-mode transistor is connected to the drain of the fourteenth enhancement-mode transistor.

[0021] Furthermore, the first buffer, the second buffer and the third buffer enhance the input signal V PWM The fourth buffer in the output stage of the high-speed latch unit converts the signal V HA The high-level voltage is increased to the high-side power supply voltage VB; the resistance values ​​of the first resistor and the second resistor are equal, the resistance values ​​of the third resistor and the fifth resistor are equal, and the resistance value of the fourth resistor is greater than the third resistor and the fifth resistor; the capacitance values ​​of the first high-voltage capacitor and the third high-voltage capacitor are equal, and the capacitance value of the second high-voltage capacitor is greater than the first high-voltage capacitor and the third high-voltage capacitor; the sizes of the first enhancement transistor and the second enhancement transistor are the same, and the size of the eighth enhancement transistor is smaller than the seventh enhancement transistor and the ninth enhancement transistor; the size of the sixth diode is larger than the fifth diode and the seventh diode.

[0022] Furthermore, enhancement mode transistors, resistors, capacitors and diodes are all devices based on GaN technology.

[0023] Furthermore, the enhancement mode transistor is an enhancement mode gallium nitride field effect N-type transistor, which is any one of an N-enhanced high electron mobility transistor or a metal-oxide-semiconductor field effect transistor; the resistor is any one of a polysilicon resistor, a metal film resistor or a gallium nitride body resistor; the capacitor is any one of a transistor capacitor or a metal-insulator-metal capacitor; and the diode is any one of a Schottky diode or a gallium nitride transistor diode connection.

[0024] The present invention provides a level shift circuit based on a high-voltage capacitor using a gallium nitride fully integrated process, which has the following advantages:

[0025] (1) By placing a high-voltage capacitor between the low-side circuit (a circuit using the low-side power supply VDD-low-side reference ground GND as the power supply rail) and the high-side circuit (a circuit using the high-side power supply VB-high-side reference ground VS as the power supply rail), the characteristics of the capacitor blocking DC and passing AC are utilized to avoid the formation of a DC path between VB and GND when the input signal is transmitted in the level shifting circuit, thereby preventing large losses. The effective signal is transmitted to the high-side circuit through the high-voltage capacitor in the form of current through the rapid change of the voltage on the lower plate of the capacitor. Although the current value between VB and GND is large at this moment, it only lasts for a short time, thus better alleviating the severe trade-off between the power consumption and transmission delay of the level shifting circuit. By adding a reset unit, the high-side node voltage V is pulled down at a specific moment. OP 、V ON and V OS , allowing the level shift circuit to respond to higher frequency signals.

[0026] (2) dVS / dt noise mainly appears in the form of common mode. The present invention eliminates the common mode noise through the symmetrical structure composed of the first enhancement transistor and the second enhancement transistor in the anti-noise level conversion unit and the noise clamping unit. Since the capacitance value of the second high-voltage capacitor is greater than the first high-voltage capacitor and the third high-voltage capacitor, and the resistance value of the fourth resistor is greater than the third resistor and the fifth resistor, when VS changes rapidly to a negative direction, V OS The voltage at the node is compared to V OP and V ON The node voltage changes more in the same time, so that the first enhancement transistor and the second enhancement transistor remain in the cut-off state, and the noise signal will not continue to be transmitted to the next stage, so that the output signal Vout is not affected by the noise. When VS changes rapidly in the positive direction, the noise clamp unit will clamp V OP 、V ON and V OSThe voltages of the three nodes are clamped at approximately the same voltage value, and the first enhancement-mode transistor and the second enhancement-mode transistor are also kept in the off state.

[0027] (3) The functions and characteristics of the level shift circuit based on high voltage capacitors of the present invention are not sensitive to the voltage value of VS. Figure 3 As shown, taking the left circuit of the anti-noise level conversion unit as an example, when the input signal V PWM When the voltage level changes rapidly from low to high, the maximum current output by the first buffer is approximately equal to the low-side power supply voltage VDD divided by the output impedance of the first buffer. This current value has nothing to do with VS. This current flows through the first high-voltage capacitor, generates a voltage drop on the third resistor, and charges the circuit node on the high side. Therefore, the low-side input signal V PWM After being converted into V by the circuit of the present invention out The transmission delay characteristics of VS have almost nothing to do with the voltage value of VS. And due to the bidirectional withstand voltage characteristics of high-voltage capacitors, the negative VS value that this circuit can allow can reach the reverse withstand voltage value of the high-voltage capacitor at the lowest, and this voltage value is almost the same as the forward withstand voltage value of the high-voltage capacitor. Figure 2 The traditional circuit structure shown can only tolerate a relatively high VS negative voltage value. Once the absolute value of the negative VS exceeds the trigger threshold of the RC filter circuit, the circuit cannot work normally.

[0028] (4) The delay of the level shift circuit based on high-voltage capacitors is almost independent of the voltage value of VS. In order to solve the problem of mismatched transmission delays between the high and low side channels, a completely symmetrical circuit structure can be used so that the amount of change of the high and low sides with other factors is the same, so as to ensure that the delays of the high and low channels are the same and achieve a better delay matching effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a typical application diagram of the present invention in a half-bridge driver chip and a power supply system based on gallium nitride technology;

[0030] Figure 2 It is a structural diagram of a traditional level shift circuit;

[0031] Figure 3 This is an example diagram of a level shift circuit based on high-voltage capacitors using a gallium nitride fully integrated process proposed by the present invention;

[0032] Figure 4 An example diagram of a pulse generating module of the present invention;

[0033] Figure 5 An example diagram of a buffer of the present invention;

[0034] Figure 6 It is a signal waveform diagram of the key nodes of the embodiment of the present invention;

[0035] Figure 7 It is a brief waveform diagram showing the circuit delay of the conventional circuit and the circuit of the present invention changing with the high-side ground VS. DETAILED DESCRIPTION

[0036] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0037] Figure 1 This is a typical application diagram of the present invention in the half-bridge driver chip and power supply system of the gallium nitride process. Except that the high-voltage level shift circuit adopts a fully integrated gallium nitride capacitive level shift circuit proposed by the present invention, the rest of the structure is the same as the prior art. The half-bridge driver circuit includes a high-voltage basin area and a low-voltage basin area, wherein the high-side control circuit and the high-side drive are located in the high-voltage basin area; the input logic processing circuit, the low-side control circuit and the low-side drive are located in the low-voltage basin area; the high-voltage level shift circuit is connected across the two basin areas and is responsible for signal transmission between the two areas. Gallium nitride power tube M H 、M L They are respectively used as the high-side power tube and low-side power tube of the half-bridge, and VBUS is the bus voltage of the half-bridge structure. The reference ground voltage of the low-voltage domain power rail is GND, and the power supply voltage is VDD; the floating reference ground voltage of the high-voltage domain power rail is VS, and the floating power supply voltage is VB. The voltage difference between VS and VB is usually the same as the voltage difference between VDD and GND.

[0038] The input signal of the driver chip is V PWM The signal is input into the logic processing circuit to generate two control signals, one for controlling M L The other is used to control M H Switch. V PWM Signal to M L The transmission path of the gate control signal is called the low-side transmission channel; V PWM Signal to M H The transmission path of the gate control signal is called the high-side transmission channel. H and M L Alternating switches, the voltage value of VS changes between GND and VBUS: When M L During the opening period, M H When the VS voltage is approximately equal to GND, the M H During the opening period, M L Off, the VS voltage is approximately equal to VBUS.

[0039] Since the power rails of the high basin circuit are different from the power rails of the low basin circuit, a level shifting circuit is required to transfer the control signal from the low basin to the high basin. Figure 2This is a structural diagram of a traditional level shift circuit, including a pulse generating module, a level conversion unit, an RC filtering unit, and an RS latch unit; the input signal VIN enters the pulse generating module, and the pulse generating module detects the rising edge and the falling edge of VIN to generate two narrow pulse signals, namely, a narrow pulse signal Pulse1 corresponding to the rising edge, and a narrow pulse signal Pulse2 corresponding to the falling edge.

[0040] The Pulse1 signal and the Pulse2 signal are connected to the gates of the first high-voltage tube 120 and the second high-voltage tube 121 of the level conversion unit, respectively. When the narrow pulse signal enters the level conversion unit, the corresponding first high-voltage tube 120 or the second high-voltage tube 121 is turned on, and the drain voltage of the turned-on tube will be pulled down. The eighth diode 127 and the ninth diode 128 are used to prevent the high-voltage tube from being broken down due to excessive voltage. The level conversion unit converts the original low-voltage domain signal VDD-GND into a high-voltage domain signal VB-VS. The RC filtering unit can enhance the circuit's ability to resist dVS / dt noise. Finally, the filtered signal restores and outputs the input signal through the RS latch unit to complete the level shifting process.

[0041] During signal transmission, a DC path is formed between the high voltage VB and GND in the traditional level shift circuit, resulting in large losses. The traditional level shift circuit uses an RC filter unit to filter out dVS / dt noise, which will cause a large transmission delay in the high-side transmission channel. The traditional level shift circuit can only tolerate a higher VS negative voltage value. Once the absolute value of the negative VS exceeds the trigger threshold of the RC filter circuit, the circuit cannot work properly. There is a difference in transmission delay between the low-side channel output signal and the high-side channel output signal. Although the high-side and low-side channel output delays can be made approximately equal by adding a delay unit to the low-side circuit, the delay of the delay unit of the low-side circuit will change due to changes in process-voltage-temperature in the environment, and the delay of the high-side circuit will change with the change of VS in the traditional structure of the level shift circuit, so the traditional GaN half-bridge chip often has the problem of poor delay matching characteristics of the high-side and low-side channel circuits.

[0042] Figure 3 This is a specific structural diagram of the level shift circuit based on high-voltage capacitors using a fully integrated gallium nitride process proposed in the present invention. The level conversion unit with similar functions in the traditional level shift circuit is retained, and a high-speed latch unit, a noise clamp unit and a reset unit are newly added.

[0043] The anti-noise level conversion unit includes a first enhancement mode transistor 100, a second enhancement mode transistor 101, a first resistor 102, a second resistor 103, a third resistor 104, a fourth resistor 105, a fifth resistor 106, a first high voltage capacitor 107, a second high voltage capacitor 108, a third high voltage capacitor 109, a first buffer 110, a second buffer 111, a third buffer 112 and a first inverter 113; the drain of the first enhancement mode transistor 100 is connected to one end of the first resistor 102, and the other end of the first resistor 102 is connected to a high side power supply VB, the drain of the second enhancement mode transistor 101 is connected to one end of the second resistor 103, and the other end of the second resistor 103 is connected to the high side power supply VB, the first enhancement mode transistor 100, the second enhancement mode transistor 101, the first resistor 102, the second resistor 103, the third resistor 104, the fourth resistor 105, the fifth resistor 106, the first high voltage capacitor 107, the second high voltage capacitor 108, the third high voltage capacitor 109, the first buffer 110, the second buffer 111, the third buffer 112 and the first inverter 113; The source of the enhanced transistor 101 is connected to one end of the second high-voltage capacitor 108, the gate of the first enhanced transistor 100 is connected to one end of the first high-voltage capacitor 107, the gate of the second enhanced transistor 101 is connected to one end of the third high-voltage capacitor 109, one end of the third resistor 104 is connected to one end of the first high-voltage capacitor 107, one end of the fourth resistor 105 is connected to one end of the second high-voltage capacitor 108, one end of the fifth resistor 106 is connected to one end of the third high-voltage capacitor 109, and the other ends of the third resistor 104, the fourth resistor 105, and the fifth resistor 106 are connected to the high-side ground VS; the power rails of the first buffer 110, the second buffer 111, the third buffer 112 and the first inverter 113 are VDD-GND; the input signal V PWM The input port of the first buffer 110 is connected to the input port of the first inverter 113, the output port of the first buffer 110 is connected to one end of the first high-voltage capacitor 107, the input port of the second buffer 111 is connected to the low-side ground GND, the output port of the second buffer 111 is connected to one end of the second high-voltage capacitor 108, the input port of the third buffer 112 is connected to the output port of the first inverter 113, and the output port of the third buffer 112 is connected to one end of the third high-voltage capacitor 109.

[0044] The high-speed latch unit includes a first diode 200, a second diode 201, a third diode 202, a fourth diode 203, a sixth resistor 204, a seventh resistor 205, an eighth resistor 212, a ninth resistor 213, a third enhancement mode transistor 206, a fourth enhancement mode transistor 207, a fifth enhancement mode transistor 210, a sixth enhancement mode transistor 211, a first capacitor 208, a second capacitor 209 and an output-stage fourth buffer 214; the gate of the third enhancement mode transistor 206 is connected to the anode of the third diode 202 and one end of the first capacitor 208, the drain of the third enhancement mode transistor 206 is connected to one end of the sixth resistor 204, the source of the third enhancement mode transistor 206 is connected to the other end of the first capacitor 208, the gate of the fifth enhancement mode transistor 210, the drain of the sixth enhancement mode transistor 211 and one end of the eighth resistor 212, the gate of the fourth enhancement mode transistor 207 is connected to the anode of the third diode 202 and one end of the first capacitor 208, the drain of the third enhancement mode transistor 206 is connected to one end of the sixth resistor 204, the source of the third enhancement mode transistor 206 is connected to the other end of the first capacitor 208, the gate of the fifth enhancement mode transistor 210, the drain of the sixth enhancement mode transistor 211 and one end of the eighth resistor 212, and the gate of the fourth enhancement mode transistor 207 is connected to the The anode of the fourth diode 203 is connected to one end of the second capacitor 209, the drain of the fourth enhancement mode transistor 207 is connected to one end of the seventh resistor 205, the source of the fourth enhancement mode transistor 207 is connected to the other end of the second capacitor 209, the drain of the fifth enhancement mode transistor 210, the gate of the sixth enhancement mode transistor 211, one end of the ninth resistor 213 and the input end of the fourth buffer 214, the anode of the first diode 200 is connected to the cathode of the third diode 202, the cathode of the first diode 200 is connected to the high-side power supply VB, the anode of the second diode 201 is connected to the cathode of the fourth diode 203, the cathode of the second diode 201 is connected to the high-side power supply VB, the other ends of the sixth resistor 204 and the seventh resistor 205 are connected to the high-side power supply VB, the sources of the fifth enhancement mode transistor 210 and the sixth enhancement mode transistor 211 and the other ends of the eighth resistor 212 and the ninth resistor 213 are connected to the high-side ground VS.

[0045] The noise clamp unit includes a seventh enhancement mode transistor 300, an eighth enhancement mode transistor 301, a ninth enhancement mode transistor 302, a fifth diode 303, a sixth diode 304 and a seventh diode 305; the drain of the seventh enhancement mode transistor 300 is connected to the cathode of the fifth diode 303, the gate of the seventh enhancement mode transistor 300 is connected to the gate of the ninth enhancement mode transistor 302, the gate and the drain of the eighth enhancement mode transistor 301, the drain of the eighth enhancement mode transistor 301 is connected to the cathode of the sixth diode 304, the drain of the ninth enhancement mode transistor 302 is connected to the cathode of the seventh diode 305, and the anodes of the fifth diode 303, the sixth diode 304 and the seventh diode 305 and the sources of the seventh enhancement mode transistor 300, the eighth enhancement mode transistor 301 and the ninth enhancement mode transistor 302 are commonly connected to the high side ground VS.

[0046] The reset unit includes a pulse generation module, a tenth enhancement mode transistor 407, an eleventh enhancement mode transistor 408 and a twelfth enhancement mode transistor 409; the input interface of the pulse generation module is connected to the V HA 、V HB The output port of the pulse generating module outputs the Vctrl signal and is connected to the gates of the tenth enhancement mode transistor 407, the eleventh enhancement mode transistor 408 and the twelfth enhancement mode transistor 409. The sources of the tenth enhancement mode transistor 407, the eleventh enhancement mode transistor 408 and the twelfth enhancement mode transistor 409 are commonly connected to the high side ground VS. The drains of the tenth enhancement mode transistor 407, the eleventh enhancement mode transistor 408 and the twelfth enhancement mode transistor 409 are respectively connected to the V OP 、V OS 、V ON Node. The pulse generating module includes an OR gate 400, a first AND gate 401, a second AND gate 402, a second inverter 405, a third inverter 406, a first delay 403 and a second delay 404; the output of the second delay 405 is connected to the input of the first delay 403, the output of the first delay 403 and the input of the second inverter 405 are simultaneously connected to two input ports of the first AND gate 401, the output of the third inverter 406 is connected to the input of the second delay 404, the output of the second delay 404 and the input of the third inverter 406 are simultaneously connected to two input ports of the second AND gate 402, the outputs of the first AND gate 401 and the second AND gate 402 are connected to the two input ports of the OR gate 400, and the output port of the OR gate 400 outputs a Vctrl signal.

[0047] like Figure 3 , Figure 4 and Figure 5 As shown, assuming that the initial state input signal V PWM is low level, the first buffer 110 outputs a signal V IP is low level, V IN The upper plate voltage V OP Due to the pull-down effect of the third resistor 104, it is equal to the high-side ground voltage VS; the upper plate voltage V ON Due to the pull-down effect of the fifth resistor 106, it is equal to the high-side ground voltage VS; the upper plate voltage V OS Due to the pull-down effect of the fourth resistor 105, the drain voltage V SET and V RESET The pull-up function of the first resistor 102 and the second resistor 103 maintains a high level.

[0048] When the input signal VPWM When the output voltage V of the first buffer 110 changes from a low level to a high level, IP The voltage at both ends of the capacitor cannot change suddenly from a low level to a high level. The output current of the first buffer 110 flows through the third resistor 104 and the first high-voltage capacitor 107, so that the upper plate voltage of the first high-voltage capacitor 107 rises rapidly in a short time relative to the high-side ground VS, that is, the gate voltage V OP With V IP The gate voltage V of the first enhancement mode transistor 100 is changed from low level to high level and rises relative to VS in a short time, so that the first enhancement mode transistor 100 is turned on. OP Since the input of the second buffer 111 is fixed to GND, V IS will not change, so the source voltage V OS remains unchanged. As the gate voltage V OP When the gate-source voltage of the first enhancement mode transistor 100 is greater than the threshold voltage, the first enhancement mode transistor 100 is turned on, and the drain voltage V SET Changes from high level to low level.

[0049] Due to the action of the first inverter 113, V IN Signal and V IP The signal is inverted, that is, at V IP When the voltage level changes from low to high quickly, V IN Similarly, the output current of the third buffer 112 flows through the fifth resistor 106 and the third high-voltage capacitor 109. Since the current flows from the upper plate to the lower plate of the third high-voltage capacitor 109, the voltage of the upper plate of the third high-voltage capacitor 109 drops rapidly in a short time relative to the high-side ground VS, that is, the gate voltage V ON With V IN The voltage V of the source of the second enhancement transistor 101 decreases relative to VS in a short time after the high level changes to the low level. OS remains unchanged, the second enhancement mode transistor 101 remains off, V RESET Remains unchanged and remains at a high level.

[0050] During the conduction period of the first enhancement mode transistor 100, the high-side power supply VB will increase the source voltage V of the first enhancement mode transistor 100 through the first resistor 102 and the first enhancement mode transistor 100. OS However, since the second high-voltage capacitor 108 and the first resistor 102 have large values ​​and the first enhancement mode transistor 100 is turned on for a short time, the source voltage V OSIt will only rise slightly, so it can be considered that V SET The voltage level remains low during the conduction period of the first enhancement mode transistor 100 .

[0051] Assume that the initial state input signal V PWM is low level, and the previous state has been latched by the high-speed latch unit, that is, V HB is high level, V HA is low level, the fifth enhancement mode transistor 210 is turned on, and the sixth enhancement mode transistor 211 is turned off. PWM When it changes from low level to high level, V SET is pulled low, V RESET Keep high, the third enhancement mode transistor 206 is turned off due to the reduction of gate voltage. Under the action of the pull-down current of the eighth resistor 212 and the coupling current of the first capacitor 208, V HB The voltage will decrease, and finally the fifth enhancement mode transistor 210 is turned off; and under the action of the pull-up current provided by the seventh resistor 205 and the fourth enhancement mode transistor 207, V HA will rise, eventually turning on the sixth enhancement mode transistor 211, changing and latching the output state of Vout.

[0052] For the initial state input signal V PWM For high level condition, when the input signal V PWM When the high level changes to the low level, due to the high symmetry of the circuit structure, its working process is the same as V PWM The situation is similar when changing from low level to high level.

[0053] In order to obtain a higher voltage and longer duration V during operation OP 、V ON and V OS , when designing, the third resistor 104, the fourth resistor 105 and the fifth resistor 106 with larger resistance are often selected, which will result in V IP and V IN After stopping changing, V OP 、V ON and V OS It takes a long time to return to the initial state equal to VS. When the circuit operates at a higher frequency, it may be due to V OP 、V ON and V OS Failure to restore to the initial state in time causes logic confusion. Therefore, when the circuit works under high frequency conditions, the assistance of the reset unit is required. The pulse generation module in the reset unit reads V HB and V HA When V HB and V HAWhen any of them has a rising edge, a short pulse signal will be output, and the pulse signal will control the tenth enhancement mode transistor 407, the eleventh enhancement mode transistor 408, and the twelfth enhancement mode transistor 409 to turn on, and the voltage V OP 、V ON and V OS Quickly pull down to VS.

[0054] During the operation of the half-bridge system, since the high-side circuit reference ground is connected to the half-bridge circuit switch node, the high-side reference ground signal VS will experience rapid voltage changes, which can be positive or negative. During the VS change, even if V IP 、V IN and V IS The voltage does not change. However, due to the change of VS, the voltage change across the high-voltage capacitor will also generate displacement current and produce voltage drops on the third resistor 104, the fourth resistor 105 and the fifth resistor 106, which may cause the ordinary capacitive level shift circuit to be triggered incorrectly. Figure 2 The same is true for the conventional circuit shown. The first high-voltage tube 120 and the second high-voltage tube 121 in the off state have a large drain-source parasitic capacitance, which will generate a voltage drop on the tenth resistor 125 and the eleventh resistor 126 due to the displacement current, causing the latch unit to enter an unstable state.

[0055] For the circuit of the present invention, when VS drops rapidly in a short period of time, a displacement current will be generated on the first high-voltage capacitor 107, the second high-voltage capacitor 108 and the third high-voltage capacitor 109, and the direction will flow from the lower plate to the upper plate. The displacement current will generate a voltage drop on the third resistor 104, the fourth resistor 105 and the fifth resistor 106, which will cause the gate voltage V of the first enhancement mode transistor 100 and the second enhancement mode transistor 101 to OP 、V ON and source voltage V OS By setting the capacitance of the isolation capacitor, the size of the enhancement transistor, and the resistance of the resistor, the capacitance of the second high-voltage capacitor 108 is greater than that of the first high-voltage capacitor 107 and the third high-voltage capacitor 109, the size of the eighth enhancement transistor 301 is smaller than that of the seventh enhancement transistor 300 and the ninth enhancement transistor 302, and the resistance of the fourth resistor 105 is greater than that of the third resistor 104 and the fifth resistor 106. Thus, the source voltage V OS The gate voltage V of the first enhancement mode transistor 100 and the second enhancement mode transistor 101 is OP and V ONThe gate-source voltage of the first enhancement mode transistor 100 and the second enhancement mode transistor 101 rises more in the same time, so the gate-source voltage of the first enhancement mode transistor 100 and the second enhancement mode transistor 101 remains below the transistor threshold voltage Vth, and the first enhancement mode transistor 100 and the second enhancement mode transistor 101 will not turn on. The design of the present invention can ensure that the first enhancement mode transistor 100 and the second enhancement mode transistor 101 remain in the off state, and can also prevent the V OP and V ON In addition, to prevent the voltage V OP 、V ON and V OS Unlimited rise leads to device breakdown, and the noise clamp unit will OS When it is too high, it turns on and clamps V OS voltage, and limits V by turning on the seventh enhancement mode transistor 300 and the ninth enhancement mode transistor 302 OP and V ON Voltage rise.

[0056] For the circuit of the present invention, when VS rises rapidly in a short time, a displacement current will be generated on the first high-voltage capacitor 107, the second high-voltage capacitor 108 and the third high-voltage capacitor 109, and the direction will flow from the upper plate to the lower plate. The displacement current will generate a voltage drop on the third resistor 104, the fourth resistor 105 and the fifth resistor 106, which will cause the gate voltage V of the first enhancement mode transistor 100 and the second enhancement mode transistor 101 to OP 、V ON and source voltage V OS decline.

[0057] When the high-voltage ground signal VS rises instantaneously, the gate voltages of the first enhancement mode transistor 100 and the second enhancement mode transistor 101 decrease relative to the high-voltage ground signal, and the fifth diode 303, the sixth diode 304, and the seventh diode 305 are forward-conducted, and V OP 、V ON and V OS The voltages of the three nodes are clamped at nearly the same voltage value to prevent transistor breakdown and ensure that the first enhancement mode transistor 100 and the second enhancement mode transistor 101 remain turned off. By setting the size of the sixth diode 304 to be larger than the fifth diode 303 and the seventh diode 305, it is ensured that even if the second high voltage capacitor 108 has a larger capacitance and a larger displacement current, V OS The voltage can still be maintained at V OP 、V ON Quite a level.

[0058] Figure 6 This is a working waveform diagram of a level shift circuit based on high-voltage capacitors using a gallium nitride fully integrated process proposed by the present invention. When the input signal V PWMWhen the low level changes to high level, V IN Drop, V IP Rising. V OP rises, while V ON However, it is clamped by the seventh diode 305 to be close to the VS voltage value. After the first enhancement mode transistor 100 is turned on, V OS Slightly increased, V SET The node voltage becomes low, so that the third enhancement mode transistor 206 is turned off. HB However, due to the bootstrap effect of the first capacitor 208, V HB The falling speed of V HB After falling, V HA The voltage at the point starts to rise. Due to the bootstrap effect of the second capacitor 209, the gate voltage of the fourth enhancement mode transistor 207 also rises accordingly, so that the on-resistance of the fourth enhancement mode transistor 207 will not be affected by V HA rises and decreases, so V HA The second diode 201 and the fourth diode 203 are used to prevent the gate voltage of the enhancement mode transistor 207 from being too high due to the bootstrap effect of the capacitor 209, resulting in device breakdown; the first diode 200 and the third diode 202 are used to prevent the gate voltage of the third enhancement mode transistor 206 from being too high due to the bootstrap effect of the first capacitor 208, resulting in device breakdown; if the device withstands enough voltage, these diodes can be removed.

[0059] V HA and V HB The signal enters the reset unit, generating a Vctrl signal, which turns on the tenth enhancement mode transistor 407, the eleventh enhancement mode transistor 408, and the twelfth enhancement mode transistor 409, and assists in pulling down V OP 、V ON and V OS The potential of a point. Figure 4 As shown, when there is a Vctrl signal, V OP 、V ON and V OS The fall-off is faster, allowing the circuit to respond to higher frequency input signals.

[0060] Figure 7 The figure is a brief relationship diagram of the circuit delay and VS voltage value of the conventional level shift circuit and the level shift circuit of the present invention. When VS is low, the first high-voltage tube 120 and the second high-voltage tube 121 of the conventional level shift circuit enter the linear region, and the generated pull-down current decreases, so the circuit delay is higher when VS is low. However, the circuit of the present invention is based on high-voltage capacitors, and the delay of the level shift circuit is largely independent of the voltage value of VS, and the delay is almost unaffected by the change of VS.

[0061] The enhancement-mode transistors, resistors, capacitors and diodes mentioned above are all devices based on gallium nitride technology. The enhancement-mode transistors mentioned above are enhancement-mode gallium nitride field effect N-type transistors, which can be N-enhanced high electron mobility transistors or metal-oxide-semiconductor field effect transistors; the resistors can be polysilicon resistors, metal film resistors, gallium nitride body resistors; the capacitors can be transistor capacitors, metal-insulator-metal capacitors; the diodes can be Schottky diodes or gallium nitride transistor diode connections.

Claims

1. A level shift circuit based on high-voltage capacitors using a fully integrated gallium nitride process, including an anti-noise level conversion unit, a noise clamping unit, a high-speed latch unit, and a reset unit; the anti-noise level conversion unit realizes the conversion of a low-side input signal to a high-side output signal, and its symmetrical structure can suppress common-mode noise; the noise clamping unit suppresses the influence of dVS / dt noise on the circuit and clamps the voltage of key nodes to prevent breakdown; the high-speed latch unit quickly restores the input pulse signal to a level signal; the reset unit generates a pulse signal to turn on the switch tube to help the key node discharge charge; the input signal V PWM Connect the input port of the anti-noise level conversion unit; the output port node of the anti-noise level conversion unit is V SET and V RESET Connect the two input ports of the high-speed latch unit respectively; the output port node of the high-speed latch unit is V HA and V HB The three output ports of the reset unit are connected to the V OP 、V OS 、V ON The node helps to improve the gate pull-down rate of the two GaN transistors in the symmetrical structure of the anti-noise level conversion unit and enhance the circuit's response to high-frequency input signals. The noise clamp unit is connected to the V OP 、V OS 、V ON node.

2. The level shift circuit based on high voltage capacitor using GaN full integration process according to claim 1, characterized in that: The anti-noise level conversion unit comprises a first enhancement-type transistor (100), a second enhancement-type transistor (101), a first resistor (102), a second resistor (103), a third resistor (104), a fourth resistor (105), a fifth resistor (106), a first high-voltage capacitor (107), a second high-voltage capacitor (108), a third high-voltage capacitor (109), a first buffer (110), a second buffer (111), a third buffer (112) and a first inverter (113); The drain of the first enhancement mode transistor (100) is connected to one end of the first resistor (102), the other end of the first resistor (102) is connected to a high-side power supply VB, the drain of the second enhancement mode transistor (101) is connected to one end of the second resistor (103), the other end of the second resistor (103) is connected to the high-side power supply VB, the sources of the first enhancement mode transistor (100) and the second enhancement mode transistor (101) are connected and connected to one end of the second high-voltage capacitor (108), the gate of the first enhancement mode transistor (100) is connected to one end of the first high-voltage capacitor (107), and the gate of the second enhancement mode transistor (101) is connected to one end of the first high-voltage capacitor (107). The first buffer (110), the second buffer (111), the third buffer (112) and the first inverter (113) are connected to one end of the high-voltage capacitor (109); one end of the third resistor (104) is connected to one end of the first high-voltage capacitor (107); one end of the fourth resistor (105) is connected to one end of the second high-voltage capacitor (108); one end of the fifth resistor (106) is connected to one end of the third high-voltage capacitor (109); the other ends of the third resistor (104), the fourth resistor (105) and the fifth resistor (106) are connected to the high-side ground VS; the power rails of the first buffer (110), the second buffer (111), the third buffer (112) and the first inverter (113) are VDD-GND; the input signal V PWM The input port of the first buffer (110) is connected to the input port of the first inverter (113), the output port of the first buffer (110) is connected to one end of the first high-voltage capacitor (107), the input port of the second buffer (111) is connected to the low-side ground GND, the output port of the second buffer (111) is connected to one end of the second high-voltage capacitor (108), the input port of the third buffer (112) is connected to the output port of the first inverter (113), and the output port of the third buffer (112) is connected to one end of the third high-voltage capacitor (109).

3. The level shift circuit based on high voltage capacitor using GaN full integration process according to claim 2, characterized in that: The power rail of the high-speed latch unit is VB-VS; the high-speed latch unit comprises a first diode (200), a second diode (201), a third diode (202), a fourth diode (203), a sixth resistor (204), a seventh resistor (205), an eighth resistor (212), a ninth resistor (213), a third enhancement-mode transistor (206), a fourth enhancement-mode transistor (207), a fifth enhancement-mode transistor (210), a sixth enhancement-mode transistor (211), a first capacitor (208), a second capacitor (209) and an output-stage fourth buffer (214); The gate of the third enhancement transistor (206) is connected to the anode of the third diode (202) and one end of the first capacitor (208); the drain of the third enhancement transistor (206) is connected to one end of the sixth resistor (204); the source of the third enhancement transistor (206) is connected to the other end of the first capacitor (208), the gate of the fifth enhancement transistor (210), the drain of the sixth enhancement transistor (211) and one end of the eighth resistor (212); the gate of the fourth enhancement transistor (207) is connected to the anode of the fourth diode (203) and one end of the second capacitor (209); the drain of the fourth enhancement transistor (207) is connected to one end of the seventh resistor (205); and the source of the fourth enhancement transistor (207) is connected to the other end of the second capacitor (209). The first and second enhancement mode transistors (210, 211) are connected to the high-side power supply VB, the drain of the fifth enhancement mode transistor (210), the gate of the sixth enhancement mode transistor (211), one end of the ninth resistor (213) and the input end of the fourth buffer (214); the anode of the first diode (200) is connected to the cathode of the third diode (202); the cathode of the first diode (200) is connected to the high-side power supply VB; the anode of the second diode (201) is connected to the cathode of the fourth diode (203); the cathode of the second diode (201) is connected to the high-side power supply VB; the other ends of the sixth resistor (204) and the seventh resistor (205) are connected to the high-side power supply VB; the sources of the fifth enhancement mode transistor (210), the sixth enhancement mode transistor (211) and the other ends of the eighth resistor (212) and the ninth resistor (213) are connected to the high-side ground VS.

4. The level shift circuit based on high voltage capacitor using GaN full integration process according to claim 3, characterized in that: The power rail of the noise clamp unit is VB-VS, and the unit comprises a seventh enhancement-mode transistor (300), an eighth enhancement-mode transistor (301), a ninth enhancement-mode transistor (302), a fifth diode (303), a sixth diode (304) and a seventh diode (305); the drain of the seventh enhancement-mode transistor (300) is connected to the cathode of the fifth diode (303), the gate of the seventh enhancement-mode transistor (300) is connected to the gate of the ninth enhancement-mode transistor (302), the gate and the drain of the eighth enhancement-mode transistor (301), the drain of the eighth enhancement-mode transistor (301) is connected to the cathode of the sixth diode (304), the drain of the ninth enhancement-mode transistor (302) is connected to the cathode of the seventh diode (305), and the anodes of the fifth diode (303), the sixth diode (304) and the seventh diode (305) and the sources of the seventh enhancement-mode transistor (300), the eighth enhancement-mode transistor (301) and the ninth enhancement-mode transistor (302) are commonly connected to the high-side ground VS.

5. The level shift circuit based on high voltage capacitor using GaN full integration process according to claim 4, characterized in that: The reset unit has a power rail of VB-VS and includes a pulse generation module, a tenth enhancement-type transistor (407), an eleventh enhancement-type transistor (408) and a twelfth enhancement-type transistor (409); the input interface of the pulse generation module is connected to the V HA 、V HB The output port of the pulse generating module outputs a Vctrl signal and is connected to the gates of the tenth enhancement mode transistor (407), the eleventh enhancement mode transistor (408) and the twelfth enhancement mode transistor (409); the sources of the tenth enhancement mode transistor (407), the eleventh enhancement mode transistor (408) and the twelfth enhancement mode transistor (409) are commonly connected to the high side ground VS; the drains of the tenth enhancement mode transistor (407), the eleventh enhancement mode transistor (408) and the twelfth enhancement mode transistor (409) are respectively connected to the V of the anti-noise level conversion unit. OP 、V OS 、V ON node.

6. The level shift circuit based on high voltage capacitor using GaN full integration process according to claim 5, characterized in that: The power rail of the pulse generating module is VB-VS, and the module comprises an OR gate (400), a first AND gate (401), a second AND gate (402), a second inverter (405), a third inverter (406), a first delay device (403) and a second delay device (404); the output of the second delay device (405) is connected to the input of the first delay device (403), the output of the first delay device (403) and the input of the second inverter (405) are simultaneously connected to two input ports of the first AND gate (401), the output of the third inverter (406) is connected to the input of the second delay device (404), the output of the second delay device (404) and the input of the third inverter (406) are simultaneously connected to two input ports of the second AND gate (402), the outputs of the first AND gate (401) and the second AND gate (402) are connected to two input ports of the OR gate (400), and the output port of the OR gate (400) outputs a Vctrl signal.

7. The level shift circuit based on high voltage capacitor using GaN full integration process according to claim 6, characterized in that: The first buffer (110), the second buffer (111), the third buffer (112) and the fourth buffer (214) comprise a thirteenth enhancement-mode transistor (115), a fourteenth enhancement-mode transistor (116) and a fourth inverter (114); an input port of the fourth inverter (114) is connected to the gate of the fourteenth enhancement-mode transistor (116), an output port of the fourth inverter (114) is connected to the gate of the thirteenth enhancement-mode transistor (115), and a source of the thirteenth enhancement-mode transistor (115) is connected to the drain of the fourteenth enhancement-mode transistor (116).

8. The level shift circuit based on high voltage capacitor using GaN full integration process according to claim 4, characterized in that: The first buffer (110), the second buffer (111) and the third buffer (112) enhance the input signal V PWM The fourth buffer (214) of the output stage in the high-speed latch unit converts the signal V HA The high-level voltage of the first enhancement mode transistor (100) and the second enhancement mode transistor (101) are increased to the high-side power supply voltage VB; the resistance values ​​of the first resistor (102) and the second resistor (103) are equal, the resistance values ​​of the third resistor (104) and the fifth resistor (106) are equal, and the resistance value of the fourth resistor (105) is greater than the third resistor (104) and the fifth resistor (106); the capacitance values ​​of the first high-voltage capacitor (107) and the third high-voltage capacitor (109) are equal, and the capacitance value of the second high-voltage capacitor (108) is greater than the first high-voltage capacitor (107) and the third high-voltage capacitor (109); the sizes of the first enhancement mode transistor (100) and the second enhancement mode transistor (101) are the same, and the size of the eighth enhancement mode transistor (301) is smaller than the seventh enhancement mode transistor (300) and the ninth enhancement mode transistor (302); and the size of the sixth diode (304) is greater than the fifth diode (303) and the seventh diode (305).

9. The level shift circuit based on high voltage capacitors using gallium nitride fully integrated technology according to claim 7, characterized in that: Enhancement mode transistors, resistors, capacitors and diodes are all devices based on GaN technology.

10. The level shift circuit based on high voltage capacitor using GaN full integration process according to claim 9, characterized in that: The enhancement mode transistor is an enhancement mode gallium nitride field effect N-type transistor, which is any one of an N-enhanced high electron mobility transistor and a metal-oxide-semiconductor field effect transistor; the resistor is any one of a polysilicon resistor, a metal film resistor and a gallium nitride body resistor; the capacitor is any one of a transistor capacitor and a metal-insulator-metal capacitor; and the diode is any one of a Schottky diode and a gallium nitride transistor diode connection.

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