Level conversion circuit, level converter and control method

Abstract

The present invention discloses a level conversion circuit, a level converter and a control method, wherein the level conversion circuit comprises a timing control circuit, a pulse fast pull circuit, a differential pair control circuit, a first pull-up circuit, a first clamp pull-down circuit, a first switch pull-down circuit, a second pull-up circuit, a second clamp pull-down circuit, a constant current pull-down circuit, a second switch pull-down circuit and a seventh PMOS tube, wherein the pulse fast pull circuit is connected to the differential pair control circuit, the differential pair control circuit and the first switch pull-down circuit are both connected to the gate of the seventh PMOS tube, the first clamp pull-down circuit is connected to the first pull-up circuit, the second pull-up circuit is connected to the drain of the seventh PMOS tube, and the second clamp pull-down circuit, the constant current pull-down circuit and the second switch pull-down circuit are all connected to the output signal VOUT pin. The input level can be adjusted to an output level higher than the withstand voltage of the process device, so as to adapt to the application scenario of the high withstand voltage circuit, reduce the risk of circuit damage and reduce the chip manufacturing cost.

Description

Technical Field

[0001] The present invention relates to the technical field of analog circuits, and in particular to a level conversion circuit, a level converter and a control method. Background Art

[0002] In electronic chip design, the conversion of signals from one power domain to another power domain is usually designed. When the voltage difference between the two power domains is large, the power domain level conversion processing is required, especially when converting from a low voltage to a high voltage, a specific conversion circuit is required for processing.

[0003] The level conversion circuit is usually within the process voltage range. For example, if the voltage is 3.3V, the input or output operating voltage is less than or equal to 3.3V. However, in some high-voltage control circuit application scenarios, the signal to be output is higher than the voltage resistance of the components, which may cause damage to the components. In CMOS integrated circuit design, devices have a voltage resistance range. Exceeding the voltage resistance range will cause damage to the integrated circuit devices; voltage resistance damage of CMOS devices is usually caused by gate-source breakdown and gate-drain breakdown. The voltage resistance range of integrated circuit devices is strongly related to the manufacturing process. If a higher operating voltage needs to be supported, a new manufacturing process needs to be adopted, which increases the chip manufacturing cost. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes a level conversion circuit and a control method, which can use low-voltage devices to implement a high-voltage level conversion circuit, adapt to the application scenarios of high-voltage circuits, reduce the risk of circuit damage, and reduce chip manufacturing costs.

[0005] On the one hand, an embodiment of the present invention provides a level conversion circuit, including a timing control circuit, a pulse fast pull circuit, a differential pair control circuit, a first pull-up circuit, a first clamp pull-down circuit, a first switch pull-down circuit, a second pull-up circuit, a second clamp pull-down circuit, a constant current pull-down circuit, a second switch pull-down circuit and a seventh PMOS tube, wherein the pulse fast pull circuit is connected to the differential pair control circuit, the differential pair control circuit and the first switch pull-down circuit are both connected to the gate of the seventh PMOS tube, the first clamp pull-down circuit is connected to the first pull-up circuit, the second pull-up circuit is connected to the drain of the seventh PMOS tube, the second clamp pull-down circuit, the constant current pull-down circuit and the second switch pull-down circuit are all connected to an output signal VOUT pin, and the timing control circuit is used to perform logic gate delay processing on an input signal VIN to generate a control signal; The pulse fast pull circuit includes a first NMOS tube, a second NMOS tube and a first PMOS tube, the first NMOS tube is used as a control switch, and the first PMOS tube and the second NMOS tube are used to prevent voltage damage; the differential pair control circuit includes a first differential branch and a second differential branch, the first differential branch includes a third NMOS tube, a fourth NMOS tube and a second PMOS tube, the drain of the third NMOS tube is connected to the source of the fourth NMOS tube, the drain of the fourth NMOS tube is connected to the drain of the second PMOS tube, the second differential branch includes a fifth NMOS tube, a sixth NMOS tube and a third PMOS tube, the gates of the fourth NMOS tube and the sixth NMOS tube are controlled by the input power supply VCC3 to protect the gate-drain voltage of the third NMOS tube and the fifth NMOS tube; The first pull-up circuit includes a fourth PMOS tube and a fifth PMOS tube, the fourth PMOS tube and the fifth PMOS tube form a current mirror, and the width-to-length ratio of the fifth PMOS tube is adjusted so that the front-stage voltage VPRE is 1.7V; the first clamping pull-down circuit includes a seventh NMOS tube, an eighth NMOS tube and a sixth PMOS tube, the drain of the seventh NMOS tube is connected to the source of the eighth NMOS tube, and the drain of the eighth NMOS tube is connected to the drain of the sixth PMOS tube, so as to clamp the front-stage voltage VPRE at 1.7V; The first switch pull-down circuit includes a ninth NMOS tube, a tenth NMOS tube and a tenth PMOS tube, the ninth NMOS tube and the tenth PMOS tube are used for switch control, and the tenth NMOS tube is used to prevent withstand voltage damage; the second pull-up circuit includes a ninth PMOS tube, and the width-to-length ratio of the ninth PMOS tube is adjusted so that the output signal VOUT is 1.7V; the second clamp pull-down circuit includes an eleventh NMOS tube, a twelfth NMOS tube and an eighth PMOS tube, the drain of the eleventh NMOS tube is connected to the source of the twelfth NMOS tube, the drain of the twelfth NMOS tube is connected to the drain of the eighth PMOS tube, and the second clamp pull-down circuit is used to clamp the output signal VOUT at 1.7V; The constant current pull-down circuit includes a thirteenth NMOS tube and a fourteenth NMOS tube, the thirteenth NMOS tube is used as a switch control, and the fourteenth NMOS tube is used to prevent voltage damage; the second switch pull-down circuit includes a fifteenth NMOS tube, a sixteenth NMOS tube and an eleventh PMOS tube, the fifteenth NMOS tube and the eleventh PMOS tube are used as switch controls, and the sixteenth NMOS tube is used to prevent voltage damage.

[0006] According to some embodiments of the present invention, the gate of the first NMOS tube is controlled by a control signal VINF0, the control signal VINF0 is generated by the timing control circuit, the gate of the second NMOS tube is controlled by an input power supply VCC3, and the gate of the first PMOS tube is controlled by an input reference voltage VBPX.

[0007] According to some embodiments of the present invention, the gate of the third NMOS tube is controlled by the control signal VINN0, and the gate of the fifth NMOS tube is controlled by the control signal VINP0. The control signal VINN0 and the control signal VINP0 are both generated by the timing control circuit, and the control signal VINN0 and the control signal VINP0 are opposite to each other. When the input signal VIN is 0, the control signal VINN0 is 3.3V, the control signal VINP0 is 0V, the first differential branch is turned on, the second differential branch is turned off, and the front-stage voltage VPRE is pulled to 5V. When the input signal VIN is 3.3, the control signal VINN0 is 0V, the control signal VINP0 is 3.3V, the first differential branch is turned off, the second differential branch is turned on, and the front-stage voltage VPRE is 1.7V.

[0008] According to some embodiments of the present invention, the ninth NMOS tube and the tenth PMOS tube are connected in parallel, and the drain of the ninth NMOS tube and the source of the tenth PMOS tube are both connected to the source of the tenth NMOS tube.

[0009] According to some embodiments of the present invention, the fifteenth NMOS tube and the eleventh PMOS tube are connected in parallel, and the drain of the fifteenth NMOS tube and the source of the eleventh PMOS tube are both connected to the source of the sixteenth NMOS tube.

[0010] According to some embodiments of the present invention, the first clamp pull-down circuit also includes a first RC high-pass circuit, which includes a first resistor and a first capacitor, the first resistor is connected to the gate of the sixth PMOS tube, the first plate of the first capacitor is connected to the gate of the sixth PMOS tube, and the second plate of the first capacitor is connected to the drain of the sixth PMOS tube. When the previous stage voltage VPRE changes from high to low, the gate of the sixth PMOS tube generates a low pulse to enhance the conduction capability of the sixth PMOS tube and accelerate the change of the previous stage voltage VPRE signal from high to low.

[0011] According to some embodiments of the present invention, the second clamp pull-down circuit also includes a second RC high-pass circuit, the second RC high-pass circuit includes a second resistor and a second capacitor, the second resistor is connected to the gate of the eighth PMOS tube, the first plate of the second capacitor is connected to the gate of the eighth PMOS tube, and the second plate of the second capacitor is connected to the drain of the eighth PMOS tube. When the output signal VOUT changes from high to low, the gate of the eighth PMOS tube generates a low pulse to enhance the conduction capability of the eighth PMOS tube and accelerate the change of the output signal VOUT from high to low.

[0012] According to some embodiments of the present invention, the second pull-up circuit also includes an RC low-pass circuit, which includes a third resistor and a third capacitor, the third resistor is connected to the gate of the ninth PMOS tube, the first plate of the third capacitor is connected to the gate of the ninth PMOS tube, and the second plate of the third capacitor is connected to the drain of the ninth PMOS tube. When the output signal VOUT changes from high to low, the gate of the ninth PMOS tube is delayed to open to speed up the change of the output signal VOUT from high to low.

[0013] On the other hand, an embodiment of the present invention provides a level converter, comprising the above-mentioned level conversion circuit.

[0014] In another aspect, an embodiment of the present invention provides a level conversion control method, comprising: The timing control circuit performs logic gate delay processing on the input signal VIN to generate a control signal, and controls each sub-module circuit according to the control signal; The fourth PMOS tube and the fifth PMOS tube of the first pull-up circuit form a current mirror, the first clamp pull-down circuit can clamp the front-stage voltage VPRE at 1.7V, and the second clamp pull-down circuit can clamp the output signal VOUT at 1.7V; The gates of the fourth NMOS tube and the sixth NMOS tube of the differential pair control circuit are controlled by the input power supply VCC3 to protect the gate-drain voltage of the third NMOS tube and the fifth NMOS tube; When the input signal VIN is 0V, the first pull-up circuit is turned on, the first clamp pull-down circuit and the first switch pull-down circuit are turned off, the front-stage voltage VPRE generates a 5V voltage, the seventh PMOS tube is turned off, and the output signal VOUT is pulled down to 1.7V by the second clamp pull-down circuit and the second switch pull-down circuit; When the input VIN is 3.3V, the first clamp pull-down circuit and the first switch pull-down circuit are turned on, the front-stage voltage VPRE is pulled to 1.7V, the seventh PMOS tube is turned on, the second clamp pull-down circuit and the second switch pull-down circuit are turned off, and the output signal VOUT is 5V.

[0015] The embodiments of the present invention have at least the following beneficial effects: The level conversion circuit provided by the present invention includes a timing control circuit, a pulse fast pull circuit, a differential pair control circuit, a first pull-up circuit, a first clamp pull-down circuit, a first switch pull-down circuit, a second pull-up circuit, a second clamp pull-down circuit, a constant current pull-down circuit, a second switch pull-down circuit and a seventh PMOS tube. The pulse conduction is realized by the timing control circuit, and the transmission conversion of the level is realized by the pulse fast pull circuit and the differential pair control circuit. The level conversion module with a higher working voltage can be realized by using low-voltage components; and the seventh PMOS tube is used as an output tube, and the conversion time is reduced by the rapid discharge of the output tube. The input level can be adjusted to an output level higher than the withstand voltage of the process device, adapting to the application scenario of the high withstand voltage circuit, and accelerating the level conversion time, having a shorter conversion time under high load, thereby reducing the risk of circuit damage, improving the conversion speed, and reducing the chip manufacturing cost.

[0016] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 is a functional block diagram of a level conversion circuit according to an embodiment of the present invention; Figure 2 A schematic diagram of the working timing of the level conversion circuit according to an embodiment of the present invention; Figure 3 Schematic diagram of the circuit structure of the level conversion circuit according to an embodiment of the present invention; Figure 4 Schematic diagram of the circuit structure of a timing control circuit of a level conversion circuit according to an embodiment of the present invention; Figure 5 A schematic diagram of the circuit structure of a pulse fast pull circuit of a level conversion circuit according to an embodiment of the present invention; Figure 6 Schematic diagram of the circuit structure of a differential pair control circuit of a level conversion circuit according to an embodiment of the present invention; Figure 7 Schematic diagram of the circuit structure of a first pull-up circuit of a level conversion circuit according to an embodiment of the present invention; Figure 8 Schematic diagram of the circuit structure of a first clamp pull-down circuit of a level conversion circuit according to an embodiment of the present invention; Fig. 9 Schematic diagram of the circuit structure of a first switch pull-down circuit of a level conversion circuit according to an embodiment of the present invention; Fig.10 A schematic diagram of the circuit structure of a second pull-up circuit of a level conversion circuit according to an embodiment of the present invention; Fig.11 A schematic diagram of the circuit structure of a second clamp pull-down circuit of a level conversion circuit according to an embodiment of the present invention; Fig.12 A schematic diagram of the circuit structure of a constant current pull-down circuit of a level conversion circuit according to an embodiment of the present invention; Fig.13 A schematic diagram of the circuit structure of a second switch pull-down circuit of a level conversion circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0019] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0020] In the description of the present invention, "several" means one or more, "multiple" means more than two, greater than, less than, and exceeding are understood as not including the number itself, and "above", "below", and "within" are understood as including the number itself. If there is a description of "first", "second", etc., it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0021] In the description of the present invention, unless otherwise clearly defined, words such as “set”, “install”, “connect” and “connected” should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above words in the present invention based on the specific content of the technical solution.

[0022] The technical solution of the present invention is described in detail below through the accompanying drawings and specific embodiments.

[0023] Please refer to Figures 1 to 3The present embodiment discloses a level conversion circuit, including a timing control circuit 100, a pulse fast pull circuit 110, a differential pair control circuit 120, a first pull-up circuit 130, a first clamp pull-down circuit 140, a first switch pull-down circuit 150, a second pull-up circuit 160, a second clamp pull-down circuit 170, a constant current pull-down circuit 180, a second switch pull-down circuit 190 and a seventh PMOS transistor PM6. The pulse fast pull circuit 110 is connected to the differential pair control circuit 120. The differential pair control circuit 120 and the first switch pull-down circuit 150 are both connected to the gate of the seventh PMOS transistor PM6. The first clamp pull-down circuit 140 is connected to the first pull-up circuit 130. The second pull-up circuit 160 is connected to the drain of the seventh PMOS transistor PM6. The second clamp pull-down circuit 170, the constant current pull-down circuit 180 and the second switch pull-down circuit 190 are all connected to the output signal VOUT pin. The timing control circuit 100 is used to perform logic gate delay processing on the input signal VIN to generate a control signal. The seventh PMOS tube PM6 serves as an output tube. When the input signal VIN is 0V, the first pull-up circuit 130 is turned on, the first clamp pull-down circuit 140 and the switch pull-down circuit are turned off, the front-stage voltage VPRE generates a voltage of 5V, the seventh PMOS tube PM6 is turned off, and the output signal VOUT is pulled down to 1.7V by the second clamp pull-down circuit 170 and the second switch pull-down circuit 190. When the input VIN is 3.3V, the first clamp pull-down circuit 140 and the first switch pull-down circuit 150 are turned on, the front-stage voltage VPRE is pulled to a voltage of 1.7V, the seventh PMOS tube PM6 is turned on, the second clamp pull-down circuit 170 and the second switch pull-down circuit 190 are turned off, and the output signal VOUT is 5V. The pulse conduction is realized by the timing control circuit 100, and the level transmission conversion is realized by the pulse fast pull circuit 110 and the differential pair control circuit 120. The level conversion module with higher working voltage can be realized by using low-voltage components, for example, a level converter with 5V working voltage can be realized by using components with working voltage of 3.3V; and the conversion time is reduced by fast discharge of the output tube. The input level can be adjusted to an output level higher than the withstand voltage of the process device, adapting to the application scenario of the high withstand voltage circuit, and accelerating the level conversion time, having a shorter conversion time under high load, thereby reducing the risk of circuit damage, improving the conversion speed, and reducing the chip manufacturing cost.

[0024] Please refer to Figure 1 and Figure 3 The level conversion circuit of this embodiment includes interface pins including input power supply VCC3, input power supply VCC5, module ground GND, input signal VIN, output signal VOUT and input reference voltage VBPX. Please refer to the input and output timing diagram of the level conversion circuit Figure 2 .

[0025] Please refer to Figure 3The pulse fast pull circuit 110 includes a first NMOS tube NM0, a second NMOS tube NM1 and a first PMOS tube PM0. The first NMOS tube NM0 is used as a control switch, and the first PMOS tube PM0 and the second NMOS tube NM1 are used to prevent voltage withstand damage. The differential pair control circuit 120 includes a first differential branch and a second differential branch. The first differential branch includes a third NMOS tube NM2, a fourth NMOS tube NM3 and a second PMOS tube PM1. The drain of the third NMOS tube NM2 is connected to the source of the fourth NMOS tube NM3, and the drain of the fourth NMOS tube NM3 is connected to the drain of the second PMOS tube PM1. The second differential branch includes a fifth NMOS tube NM4, a sixth NMOS tube NM5 and a third PMOS tube PM2. The gates of the fourth NMOS tube NM3 and the sixth NMOS tube NM5 are controlled by the input power supply VCC3 to protect the gate-drain voltage of the third NMOS tube NM2 and the fifth NMOS tube NM4 to avoid gate-drain breakdown.

[0026] Please refer to Figure 3 The first pull-up circuit 130 includes a fourth PMOS transistor PM3 and a fifth PMOS transistor PM4, which form a current mirror, and the width-to-length ratio of the fifth PMOS transistor PM4 is adjusted to make the front-stage voltage VPRE 1.7V. The first clamp pull-down circuit 140 includes a seventh NMOS transistor NM6, an eighth NMOS transistor NM7 and a sixth PMOS transistor PM5, the drain of the seventh NMOS transistor NM6 is connected to the source of the eighth NMOS transistor NM7, and the drain of the eighth NMOS transistor NM7 is connected to the drain of the sixth PMOS transistor PM5, so as to clamp the front-stage voltage VPRE at 1.7V.

[0027] Please refer to Figure 3 The first switch pull-down circuit 150 includes a ninth NMOS tube NM8, a tenth NMOS tube NM9 and a tenth PMOS tube PM9. The ninth NMOS tube NM8 and the tenth PMOS tube PM9 are used for switch control, and the tenth NMOS tube NM9 is used to prevent withstand voltage damage. The second pull-up circuit 160 includes a ninth PMOS tube PM8, and the width-to-length ratio of PM8 is adjusted to make the output signal VOUT 1.7V. The second clamp pull-down circuit 170 includes an eleventh NMOS tube NM10, a twelfth NMOS tube NM11 and an eighth PMOS tube PM7. The drain of the eleventh NMOS tube NM10 is connected to the source of the twelfth NMOS tube NM11, and the drain of the twelfth NMOS tube NM11 is connected to the drain of the eighth PMOS tube PM7. The second clamp pull-down circuit 170 is used to clamp the output signal VOUT at 1.7V.

[0028] Please refer to Figure 3The constant current pull-down circuit 180 includes a thirteenth NMOS tube NM12 and a fourteenth NMOS tube NM13, the thirteenth NMOS tube NM12 is used for switch control, and the fourteenth NMOS tube NM13 is used to prevent withstand voltage damage. The second switch pull-down circuit 190 includes a fifteenth NMOS tube NM14, a sixteenth NMOS tube NM15 and an eleventh PMOS tube PM10, wherein the fifteenth NMOS tube NM14 and the eleventh PMOS tube PM10 are used for switch control, and the sixteenth NMOS tube is used to prevent withstand voltage damage.

[0029] Please refer to Figure 4 The timing control circuit 100 includes a plurality of NOT gates, NAND gates and resistors, and performs logic gate delay processing on the input signal VIN to generate control signals VINF0, VINN0, VINN1, VINP1 and VINP2, thereby providing control signals for each submodule circuit. Exemplarily, the gate of the first NMOS tube NM0 is controlled by the control signal VINF0, the gate of the second NMOS tube NM2 is controlled by the input power supply VCC3, and the gate of the first PMOS tube PM0 is controlled by the input reference voltage VBPX, wherein the input reference voltage VBPX is 1.7V. The gate of the third NMOS tube NM2 is controlled by the control signal VINN0, and the gate of the fifth NMOS tube NM4 is controlled by the control signal VINP0. The control signal VINN0 and the control signal VINP0 are opposite to each other. When the input signal VIN is 0, the control signal VINN0 is 3.3V, the control signal VINP0 is 0V, the first differential branch is turned on, the second differential branch is turned off, and the front-stage voltage VPRE is pulled to 5V. When the input signal VIN is 3.3, the control signal VINN0 is 0V, the control signal VINP0 is 3.3V, the first differential branch is turned off, the second differential branch is turned on, and the front-stage voltage VPRE is 1.7.

[0030] Please refer to Figure 5 , the first NMOS tube NM0 of the pulse fast pull circuit 110 is used as a control switch, and the first PMOS tube PM0 and the second NMOS tube NM1 are used as a protection circuit to prevent voltage damage. The circuit works briefly when the input signal VIN changes from a high level to a low level. When the input signal VIN changes from a high level to a low level, a short pulse VINF0 is generated by the timing control circuit 100, for example, about 10nS, at which time the first NMOS tube NM0 is turned on and the entire path works. When the control signal VCTL is pulled down to 1.7V, the first PMOS tube PM0 is turned off. The circuit provides a method of quickly pulling down the control signal VCTL when the input signal VIN changes from a high level to a low level, thereby quickly pulling up the front-stage voltage VPRE and quickly pulling down the output signal VOUT.

[0031] Please refer to Figure 6, the control signals VINN0 and VINP0 of the differential control circuit are generated by the timing control circuit 100, and the two signals are opposite to each other. When the input signal VIN is 0, VINN0 is 3.3V, VINP0 is 0V, at this time, the I0 path is turned on, the I1 path is turned off, and the front-stage voltage VPRE is pulled to 5V. When the input signal VIN is 3.3, VINN0 is 0V, VINP0 is 3.3V, at this time, the I0 path is turned off, the I1 path is turned on, and the front-stage voltage VPRE is determined by the I1 current and the first pull-up circuit 130, which is 1.7V. The gates of the fourth NMOS tube NM3 and the sixth NMOS tube NM5 are controlled by the input power supply VCC3 to protect the gate-drain voltage of the third NMOS tube NM2 and the fifth NMOS tube NM4 to avoid gate-drain breakdown.

[0032] Please refer to Figure 7 , the first pull-up circuit 130 is composed of a current mirror composed of a fourth PMOS transistor PM3 and a fifth PMOS transistor PM4. When the input signal VIN is 0V, the differential pair control circuit 120 and the first clamp pull-down circuit 140 are turned on, and the current provided by the fifth PMOS transistor PM4 is equal to the current provided by the first differential circuit. The voltage of the front-stage voltage VPRE is determined by the gate-source voltage of the fifth PMOS transistor PM4, and the voltage of the front-stage voltage VPRE is 1.7V by adjusting the width-to-length ratio of the fifth PMOS transistor PM4. At the same time, a current is mirrored to the control signal VCTL through the fourth PMOS transistor PM3, which is used for the differential control circuit to form positive feedback to accelerate the conversion of the front-stage voltage VPRE. When the input signal is VIN3.3V, the differential pair control circuit 120 and the first clamp pull-down circuit 140 are disconnected, and the front-stage voltage VPRE is weakly pulled up by the fifth PMOS transistor PM4.

[0033] Please refer to Figure 8, the first clamp pull-down circuit 140 includes a seventh NMOS tube NM6, an eighth NMOS tube NM7 and a sixth PMOS tube PM5. When the input signal VIN is 0V, the seventh NMOS tube NM6 is turned off, the entire path is closed, and the front-stage voltage VPRE is controlled to 5V by the pull-up circuit 1 and the differential control circuit. When the input signal VIN is 3.3V, the path begins to conduct. When the front-stage voltage VPRE drops to 1.7V, the gate-source voltage of the sixth PMOS tube PM5 is 0, the sixth PMOS tube PM5 is turned off, and the path will also be closed, so the front-stage voltage VPRE is clamped at 1.7V. When the current stage voltage VPRE decreases from 5V to 1.7V, the gate-source voltage of the sixth PMOS tube PM5 gradually decreases, and the conduction capability of the sixth PMOS tube PM5 gradually weakens. A falling pulse is also generated at the gate of the sixth PMOS tube PM5 through the first RC high-pass circuit composed of the first resistor R0 and the first capacitor C0, so that the gate-source voltage decreases slowly, and the conduction capability of the sixth PMOS tube PM5 is enhanced, thereby accelerating the falling process of the previous stage voltage VPRE and reducing the transition time.

[0034] Please refer to Fig. 9 , the ninth NMOS tube NM8 and the tenth PMOS tube PM9 of the first switch pull-down circuit 150 are used for switch control, and the tenth NMOS tube NM9 is used as a protection circuit to prevent voltage damage. When the input signal VIN is 0V, the control signal VINP0 is 0V, and the control signal VINN0 is 3.3V. At this time, the ninth NMOS tube NM8 and the tenth PMOS tube PM9 are both in the cut-off state, and the front-stage voltage VPRE is controlled to 5V by the first pull-up circuit 130 and the differential control circuit. When the input signal VIN is 3.3V, the control signal VINP0 is 3.3V, and the control signal VINN0 is 0V. At this time, the ninth NMOS tube NM8 and the tenth PMOS tube PM9 are both in the on state, and the front-stage voltage VPRE is pulled to 1.7V.

[0035] Please refer to Fig.10, the second pull-up circuit 160 includes a ninth PMOS tube PM8 connected with a gate and a drain and an RC low-pass circuit. When the input signal VIN is 3.3V, the front-stage voltage VPRE is 1.7V, and the output signal VOUT outputs a 5V level. At this time, the ninth PMOS tube PM8 does not work. When the input signal VIN is 0V, the front-stage voltage VPRE is 5V, and the output signal VOUT is pulled down by the second clamp pull-down circuit 170, the constant current pull-down circuit 180, and the second switch pull-down circuit 190. The current provided by the ninth PMOS tube PM8 is equal to the current provided by the constant current pull-down circuit 180, and the voltage of the output signal VOUT is determined by the gate-source voltage of the ninth PMOS tube PM8. The voltage of the output signal VOUT is 1.7V by adjusting the width-to-length ratio of the ninth PMOS tube PM8. The RC low-pass circuit composed of the third resistor R2 and the third capacitor C2, when the output signal VOUT changes from high to low, the gate of the ninth PMOS transistor PM8 is opened with a delay, so that the output signal VOUT changes from high to low more quickly and the conversion time is shorter.

[0036] Please refer to Fig.11 , the second clamp pull-down circuit 170 includes an eleventh NMOS tube NM10, a twelfth NMOS tube NM11 and an eighth PMOS tube PM7. When the input signal VIN is 3.3V, the eleventh NMOS tube NM10 is turned off, the entire path is closed, and the output signal VOUT is controlled to 5V by the second pull-up circuit 160 and the seventh PMOS tube PM6. When the input signal VIN is 0V, the path begins to conduct. When the output signal VOUT voltage drops to 1.7V, the gate-source voltage of the eighth PMOS tube PM7 is 0, the eighth PMOS tube PM7 is turned off, and the path will also be closed, so the output signal VOUT is clamped at 1.7V. When VOUT decreases from 5V to 1.7V, the gate-source voltage of the eighth PMOS tube PM7 gradually decreases, and the conduction capability of the eighth PMOS tube PM7 gradually weakens. The second RC high-pass circuit composed of the second resistor R1 and the second capacitor C1 will also generate a falling pulse at the gate of the eighth PMOS tube PM7, so that the gate-source voltage decreases slowly, and the conduction capability of the eighth PMOS tube PM7 is enhanced, thereby accelerating the decline of VOUT and reducing the transition time. A key indicator of the level conversion circuit is the conversion time, which indicates the time required to convert from the input signal to the output signal; the smaller the conversion time, the faster the circuit response and the faster the processing.

[0037] Please refer to Fig.12, the thirteenth NMOS tube NM12 of the constant current pull-down circuit 180 is used for switch control, and the fourteenth NMOS tube NM13 is used as a protection circuit to prevent voltage damage. When the input signal VIN is 0V, the control signal VINN1 is 3.3V, at this time the thirteenth NMOS tube NM12 is in the on state, and the output signal VOUT is determined by the second pull-up circuit 160 and the I2 current, that is, 1.7V. When the input signal VIN is 0V, the control signal VINN1 is 3.3V, at this time the thirteenth NMOS tube NM12 is turned off, and the output signal VOUT is pulled to 5V by the seventh PMOS tube PM6 and the second pull-up circuit 160.

[0038] Please refer to Fig.13 , the fifteenth NMOS tube NM14 and the eleventh PMOS tube PM10 of the second switch pull-down circuit 190 are used for switch control, and the sixteenth NMOS tube NM15 is used as a protection circuit to prevent voltage damage. When the input signal VIN is 3.3V, the control signal VINP1 is 0V, and the control signal VINP1 is 3.3V. At this time, the fifteenth NMOS tube NM14 and the eleventh PMOS tube PM10 are both in the cut-off state, and VOUT is controlled to 5V by the first pull-up circuit 130 and the seventh PMOS tube PM6. When the input signal VIN is 3.3V, the control signal VINP1 is 3.3V, and the control signal VINN1 is 0V. At this time, the fifteenth NMOS tube NM14 and the eleventh PMOS tube PM10 are both in the on state, and VOUT is pulled to 1.7V.

[0039] This embodiment further provides a level converter, comprising the above-mentioned level conversion circuit.

[0040] This embodiment also provides a level conversion control method, which mainly includes the following steps: The timing control circuit 100 performs logic gate delay processing on the input signal VIN to generate a control signal, and controls each sub-module circuit according to the control signal; The fourth PMOS transistor PM3 and the fifth PMOS transistor PM4 of the first pull-up circuit 130 form a current mirror, the first clamp pull-down circuit 140 can clamp the front-stage voltage VPRE at 1.7V, and the second clamp pull-down circuit 170 can clamp the output signal VOUT at 1.7V; The gates of the fourth NMOS transistor NM3 and the sixth NMOS transistor NM5 of the differential pair control circuit 120 are controlled by the input power supply VCC3 to protect the gate-drain voltage of the third NMOS transistor NM2 and the fifth NMOS transistor NM4 to avoid gate-drain breakdown; When the input signal VIN is 0V, the first pull-up circuit 130 is turned on, the first clamp pull-down circuit 140 and the switch pull-down circuit are turned off, the front-stage voltage VPRE generates a 5V voltage, the seventh PMOS transistor PM6 is turned off, and the output signal VOUT is pulled down to 1.7V by the second clamp pull-down circuit 170 and the second switch pull-down circuit 190; When the input VIN is 3.3V, the first clamp pull-down circuit 140 and the first switch pull-down circuit 150 are turned on, the front-stage voltage VPRE is pulled to 1.7V, the seventh PMOS transistor PM6 is turned on, the second clamp pull-down circuit 170 and the second switch pull-down circuit 190 are turned off, and the output signal VOUT is 5V.

[0041] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present invention.

Claims

1. A level conversion circuit, characterized in that: It includes a timing control circuit, a pulse fast pull circuit, a differential pair control circuit, a first pull-up circuit, a first clamp pull-down circuit, a first switch pull-down circuit, a second pull-up circuit, a second clamp pull-down circuit, a constant current pull-down circuit, a second switch pull-down circuit and a seventh PMOS tube, wherein the pulse fast pull circuit is connected to the differential pair control circuit, the differential pair control circuit and the first switch pull-down circuit are both connected to the gate of the seventh PMOS tube, the first clamp pull-down circuit is connected to the first pull-up circuit, the second pull-up circuit is connected to the drain of the seventh PMOS tube, the second clamp pull-down circuit, the constant current pull-down circuit and the second switch pull-down circuit are all connected to the output signal VOUT pin, and the timing control circuit is used to perform logic gate delay processing on the input signal VIN to generate a control signal; The pulse fast pull circuit includes a first NMOS tube, a second NMOS tube and a first PMOS tube, the first NMOS tube is used as a control switch, and the first PMOS tube and the second NMOS tube are used to prevent voltage damage; the differential pair control circuit includes a first differential branch and a second differential branch, the first differential branch includes a third NMOS tube, a fourth NMOS tube and a second PMOS tube, the drain of the third NMOS tube is connected to the source of the fourth NMOS tube, the drain of the fourth NMOS tube is connected to the drain of the second PMOS tube, the second differential branch includes a fifth NMOS tube, a sixth NMOS tube and a third PMOS tube, the gates of the fourth NMOS tube and the sixth NMOS tube are controlled by the input power supply VCC3 to protect the gate-drain voltage of the third NMOS tube and the fifth NMOS tube; The first pull-up circuit includes a fourth PMOS tube and a fifth PMOS tube, the fourth PMOS tube and the fifth PMOS tube form a current mirror, and the width-to-length ratio of the fifth PMOS tube is adjusted so that the front-stage voltage VPRE is 1.7V; the first clamping pull-down circuit includes a seventh NMOS tube, an eighth NMOS tube and a sixth PMOS tube, the drain of the seventh NMOS tube is connected to the source of the eighth NMOS tube, and the drain of the eighth NMOS tube is connected to the drain of the sixth PMOS tube, so as to clamp the front-stage voltage VPRE at 1.7V; The first switch pull-down circuit includes a ninth NMOS tube, a tenth NMOS tube and a tenth PMOS tube, the ninth NMOS tube and the tenth PMOS tube are used for switch control, and the tenth NMOS tube is used to prevent withstand voltage damage; the second pull-up circuit includes a ninth PMOS tube, and the width-to-length ratio of the ninth PMOS tube is adjusted so that the output signal VOUT is 1.7V; the second clamp pull-down circuit includes an eleventh NMOS tube, a twelfth NMOS tube and an eighth PMOS tube, the drain of the eleventh NMOS tube is connected to the source of the twelfth NMOS tube, the drain of the twelfth NMOS tube is connected to the drain of the eighth PMOS tube, and the second clamp pull-down circuit is used to clamp the output signal VOUT at 1.7V; The constant current pull-down circuit includes a thirteenth NMOS tube and a fourteenth NMOS tube, the thirteenth NMOS tube is used as a switch control, and the fourteenth NMOS tube is used to prevent voltage damage; the second switch pull-down circuit includes a fifteenth NMOS tube, a sixteenth NMOS tube and an eleventh PMOS tube, the fifteenth NMOS tube and the eleventh PMOS tube are used as switch controls, and the sixteenth NMOS tube is used to prevent voltage damage.

2. The level conversion circuit according to claim 1, characterized in that: The gate of the first NMOS tube is controlled by a control signal VINF0 generated by the timing control circuit, the gate of the second NMOS tube is controlled by an input power supply VCC3, and the gate of the first PMOS tube is controlled by an input reference voltage VBPX.

3. The level conversion circuit according to claim 2, characterized in that: The gate of the third NMOS tube is controlled by the control signal VINN0, and the gate of the fifth NMOS tube is controlled by the control signal VINP0. The control signal VINN0 and the control signal VINP0 are both generated by the timing control circuit, and the control signal VINN0 and the control signal VINP0 are opposite to each other. When the input signal VIN is 0, the control signal VINN0 is 3.3V, the control signal VINP0 is 0V, the first differential branch is turned on, the second differential branch is turned off, and the front-stage voltage VPRE is pulled to 5V. When the input signal VIN is 3.3, the control signal VINN0 is 0V, the control signal VINP0 is 3.3V, the first differential branch is turned off, the second differential branch is turned on, and the front-stage voltage VPRE is 1.7V.

4. The level conversion circuit according to claim 1, characterized in that: The ninth NMOS tube and the tenth PMOS tube are connected in parallel, and the drain of the ninth NMOS tube and the source of the tenth PMOS tube are both connected to the source of the tenth NMOS tube.

5. The level conversion circuit according to claim 4, characterized in that: The fifteenth NMOS tube and the eleventh PMOS tube are connected in parallel, and the drain of the fifteenth NMOS tube and the source of the eleventh PMOS tube are both connected to the source of the sixteenth NMOS tube.

6. The level conversion circuit according to claim 1, characterized in that: The first clamp pull-down circuit also includes a first RC high-pass circuit, which includes a first resistor and a first capacitor, the first resistor is connected to the gate of the sixth PMOS tube, the first plate of the first capacitor is connected to the gate of the sixth PMOS tube, and the second plate of the first capacitor is connected to the drain of the sixth PMOS tube. When the previous stage voltage VPRE changes from high to low, the gate of the sixth PMOS tube generates a low pulse to enhance the conduction capability of the sixth PMOS tube and accelerate the change of the previous stage voltage VPRE signal from high to low.

7. The level conversion circuit according to claim 6, characterized in that: The second clamp pull-down circuit also includes a second RC high-pass circuit, which includes a second resistor and a second capacitor. The second resistor is connected to the gate of the eighth PMOS tube, the first plate of the second capacitor is connected to the gate of the eighth PMOS tube, and the second plate of the second capacitor is connected to the drain of the eighth PMOS tube. When the output signal VOUT changes from high to low, the gate of the eighth PMOS tube generates a low pulse to enhance the conduction capability of the eighth PMOS tube and accelerate the change of the output signal VOUT from high to low.

8. The level conversion circuit according to claim 7, characterized in that: The second pull-up circuit also includes an RC low-pass circuit, which includes a third resistor and a third capacitor. The third resistor is connected to the gate of the ninth PMOS tube, the first plate of the third capacitor is connected to the gate of the ninth PMOS tube, and the second plate of the third capacitor is connected to the drain of the ninth PMOS tube. When the output signal VOUT changes from high to low, the gate of the ninth PMOS tube is opened with a delay to speed up the change of the output signal VOUT from high to low.

9. A level converter, characterized in that: A level conversion circuit comprising any one of claims 1 to 8.

10. A level conversion control method, characterized in that: A level conversion circuit as claimed in any one of claims 1 to 8, comprising: The timing control circuit performs logic gate delay processing on the input signal VIN to generate a control signal, and controls each sub-module circuit according to the control signal; The fourth PMOS tube and the fifth PMOS tube of the first pull-up circuit form a current mirror, the first clamp pull-down circuit can clamp the front-stage voltage VPRE at 1.7V, and the second clamp pull-down circuit can clamp the output signal VOUT at 1.7V; The gates of the fourth NMOS tube and the sixth NMOS tube of the differential pair control circuit are controlled by the input power supply VCC3 to protect the gate-drain voltage of the third NMOS tube and the fifth NMOS tube; When the input signal VIN is 0V, the first pull-up circuit is turned on, the first clamp pull-down circuit and the first switch pull-down circuit are turned off, the front-stage voltage VPRE generates a 5V voltage, the seventh PMOS tube is turned off, and the output signal VOUT is pulled down to 1.7V by the second clamp pull-down circuit and the second switch pull-down circuit; When the input VIN is 3.3V, the first clamp pull-down circuit and the first switch pull-down circuit are turned on, the front-stage voltage VPRE is pulled to 1.7V, the seventh PMOS tube is turned on, the second clamp pull-down circuit and the second switch pull-down circuit are turned off, and the output signal VOUT is 5V.

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