Method for forming electrode, semiconductor device and semiconductor wafer

Abstract

Disclosed is a method for forming an electrode, a semiconductor device, and a semiconductor wafer.

Description

Technical Field

[0001] The present disclosure generally relates to a method for forming a conductive electrode over a semiconductor body and a kerf region of a semiconductor wafer. Background Art

[0002] Depending on the specific type of semiconductor device implemented in the semiconductor body, various types of electrodes can be formed above the semiconductor body. The electrode is connected to the active device region of the semiconductor device and can provide external connections to the active device region. The electrodes formed above the semiconductor body of the vertical transistor device include, for example, a source electrode connected to the source region of the transistor device, a gate runner and a gate pad connected to the gate electrode of the transistor device, and, for example, a drain runner.

[0003] Forming a semiconductor device may include multiple process sequences. Such a process sequence may include an implantation process in which dopant atoms are implanted into a semiconductor body. The process sequence for forming a semiconductor device is usually performed at the wafer level. That is, multiple semiconductor bodies included in a wafer are processed simultaneously using the same process sequence. The wafer is separated at the end of the manufacturing process to obtain multiple separate semiconductor bodies (bare die, chips). The wafer includes multiple semiconductor bodies and a kerf area, which is a region located between the semiconductor bodies, and when the wafer is separated, the kerf area is at least partially removed.

[0004] In order to be able to monitor the quality of the manufacturing process, a test structure is formed in the kerf region using the same manufacturing process used to form the semiconductor device. For example, the quality of the manufacturing process can be evaluated by measuring the electrical properties of the test structure. In order to be able to measure the electrical properties of the test structure, one or more electrodes connected to the test structure can be formed above the kerf region.

[0005] The same process sequence can be used to form electrodes above the semiconductor body and electrodes above the kerf area. Conventionally, the electrodes of semiconductor devices (such as the source, gate flow channel or gate pad of a transistor device) contain aluminum (Al) or copper (Cu). With regard to separating wafers, it is not ideal to have these materials in the kerf area because these materials tend to adhere to the saw blade used to separate the wafers. This may have a negative impact on the sawing results. In conventional processes, the electrodes formed above the kerf area are therefore removed after measuring the electrical characteristics of the test structure and before separating the wafers. However, this is not convenient.

[0006] Therefore, there is a need for an improved method for forming electrodes over the semiconductor body and kerf regions of a wafer. Summary of the invention

[0007] One example relates to a method. The method includes: forming a device electrode over a semiconductor body of a semiconductor wafer, wherein the semiconductor wafer includes a semiconductor body and a kerf region between the semiconductor bodies; and forming a kerf electrode over the kerf region. Forming the device electrode and the kerf electrode includes: forming a first conductive layer on top of an insulating layer formed over the semiconductor body and the kerf region, patterning the first conductive layer to form a first device electrode layer and a first kerf electrode layer, forming a second conductive layer on top of the insulating layer, the first device electrode layer, and the first kerf electrode layer, and patterning the second conductive layer to form a second device electrode layer at least partially on top of the first device electrode layer and removing the second conductive layer from over the kerf region.

[0008] Another example relates to a semiconductor device. The semiconductor device includes a first device electrode and a second device electrode. The first device electrode includes a first device electrode layer and a second device electrode layer formed at least partially on top of the first device electrode layer, and the second device electrode includes a first device electrode layer and a second device electrode layer formed at least partially on top of the first device electrode layer. A distance between the first device electrode layers of the first and second device electrodes is shorter than a distance between the second device electrode layers of the first and second device electrodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The following examples are explained with reference to the accompanying drawings. The accompanying drawings are used to illustrate certain principles, and therefore only the aspects necessary for understanding these principles are described. These drawings are not drawn to scale. In the accompanying drawings, the same reference numerals represent the same features.

[0010] Figure 1 schematically shows a top view of a semiconductor wafer including a plurality of semiconductor bodies and kerf regions between the semiconductor bodies;

[0011] Figures 2A-2F and 3A-3F illustrate one example of a method for forming an electrode over a semiconductor body and an electrode over a kerf region of a wafer;

[0012] Figures 4A-4D One example of a method for forming two electrodes spaced apart from each other over a semiconductor body is shown;

[0013] Figure 5 It is shown in detail according to Figures 4A-4D A portion of an electrode formed in the method;

[0014] Figure 6A-6B each showing a top view of a transistor device according to an example;

[0015] Figure 7shows transistor cells according to one example, the transistor cells each including a gate electrode;

[0016] Figure 8 An example of a gate electrode is shown in more detail;

[0017] Fig. 9 Shows Figure 6A-6B An example of an edge region of a transistor device of the type shown in;

[0018] Figures 10A-11C Conductive vias according to various examples are shown, which may be used in Fig. 9 In a transistor device of the type shown in;

[0019] Fig.12 Shown in Fig. 9 In different cross-sectional planes, Fig. 9 An example of a marginal zone is shown in;

[0020] Fig.13 shows a vertical cross-sectional view of a portion of a transistor device including a drain flow channel;

[0021] Fig.14 Shown in more detail Fig.13 An example of a transistor device of the type shown in; and

[0022] Fig.15 An example of a cutout region and an adjoining region of a semiconductor body is shown. DETAILED DESCRIPTION

[0023] In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings form part of the specification and, for illustrative purposes, show examples of how the invention may be used and implemented. It should be understood that the features of the various embodiments described herein may be combined with each other unless otherwise specifically noted.

[0024] Figure 1 Schematically shown is a top view of a semiconductor wafer 1. The semiconductor wafer 1 comprises a plurality of semiconductor bodies 100 and kerf regions 200 arranged between the semiconductor bodies 100 and separating the semiconductor bodies 100 from each other. The wafer is, for example, a continuous single-crystalline semiconductor wafer which is separated at the end of the manufacturing process to obtain a plurality of individual semiconductor bodies (bare dies) 100. The single-crystalline semiconductor material is a conventional single-crystalline semiconductor material such as, for example, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), etc.

[0025] During the manufacturing process, a device region of the semiconductor device is formed in the semiconductor body 100. The manufacturing process may include an implantation process, wherein in each implantation process, dopant atoms are implanted into a predetermined region of the semiconductor body 100. The manufacturing process may also include forming an insulating layer and an electrode layer over the wafer 1 before separating the wafers.

[0026] The number of semiconductor bodies 100 in the wafer 1 depends on the size of the individual semiconductor bodies 100 and the size of the wafer. The total number is, for example, between several tens and several hundred. The wafer 1 is separated, for example, by sawing along the kerf area 200. In this way, at least part of the kerf area 200 is removed.

[0027] During the process of manufacturing the device area of ​​the semiconductor device in the semiconductor body 100, a test structure can be formed in the kerf area 200. The test structure, also referred to as a PCM (process control monitoring) structure, is formed by at least some of the manufacturing processes that form the device area of ​​the semiconductor device. Based on the electrical characteristics of the test structure, the quality of the manufacturing process can be evaluated after the manufacturing process is completed. In the manufacturing process, a test structure can be formed for each of the semiconductor bodies 100. In this example, the number of test structures is equal to the number of semiconductor bodies 100. According to another example, one test structure is formed for several semiconductor bodies. Providing test structures on semiconductor wafers in order to be able to evaluate the manufacturing process is well known, so no further explanation is needed in this regard.

[0028] In order to be able to measure electrical properties of the test structure, kerf electrodes are formed over the kerf region 200 of the wafer 1. Furthermore, device electrodes are formed over the semiconductor body 100 of the wafer 1. The device electrodes are connected to a device region of a semiconductor device implemented in the semiconductor body 100, for example.

[0029] Figures 2A-2F 3A-3F show one example of a method for forming the device electrode 41 over the semiconductor body 100 and the kerf electrode 45 over the kerf region 200 of the semiconductor wafer 1 . Figures 2A-2F Each shows a vertical cross-sectional view of a portion of the semiconductor body 100 during a process of forming the electrodes 41 , 45 , and Figures 3A-3F Each shows a vertical cross-sectional view of a portion of the cutout region 200 during a process of forming the electrodes 41 , 45 . Figures 2A-2F The cross-sectional plane shown in may correspond to Figure 1 The cross-sectional plane AA shown in FIG. Figures 3A-3F The cross-sectional plane shown in may correspond to Figure 1 Section plane BB shown in .

[0030] Figures 2A-2F3A-3F show the formation of one device electrode and one notch electrode. However, this is for illustration purposes only. The same process can be used to form several device electrodes over the semiconductor body 100 and several notch electrodes over the notch region 200.

[0031] exist Figures 2A-2F 3A-3F, only those features of the wafer that are relevant to forming device electrode 41 and notch electrode 45 are shown. That is, a device region that may have been formed in semiconductor body 100 before forming device electrode 41 and one or more test structures that may have been formed in notch region 200 before forming notch electrode 45 are not shown.

[0032] refer to Figure 2A and 3A The method includes forming a first conductive layer 410 on top of the insulating layer 5 formed over the semiconductor body 100 and the kerf region 200. Forming the insulating layer 5 over the semiconductor body and the kerf region 200 may include forming the insulating layer 5 over the entire wafer 1 before forming the device electrode 41 and the kerf electrode 45.

[0033] The first conductive layer 410 is formed on top of the surface 501 of the insulating layer 5. The thickness d410 of the first conductive layer 410 is, for example, between 0.8 microns and 1.5 microns. The thickness d410 of the first conductive layer 410 is the dimension of the first conductive layer in a direction perpendicular to the first surface 501 of the insulating layer.

[0034] According to one example, the first conductive layer 410 includes a metal such as tungsten (W) or titanium (Ti). According to one example, the first conductive layer 410 is a homogeneous layer of the same material such as tungsten or titanium. According to another example, the first conductive layer 410 includes two or more partial layers. According to one example, one of the partial layers is a tungsten layer, and the thickness of each of the one or more other partial layers is less than 10% of the thickness of the tungsten layer.

[0035] According to one example, the first conductive layer 410 includes a first partial layer including titanium (Ti), a second partial layer including titanium nitride (TiN), and a third partial layer including tungsten (W). The first partial layer may be formed on top of the insulating layer 5, the second partial layer may be formed on top of the first partial layer, and the third partial layer may be formed on top of the second partial layer. According to one example, the thickness of each of the first and second partial layers is less than 10% of the thickness of the third partial layer.

[0036] refer to Figure 2B and 3B, the method further includes patterning the first conductive layer 410 to form a first device electrode layer 411 located above the semiconductor body 100 and a first kerf electrode layer 415 located above the kerf region 200. Patterning the first conductive layer 410 may include forming an etch mask 310 above the first conductive layer 310, and etching the first conductive layer 410 with the etch mask 310 in place. The etch mask 310 protects certain areas of the conductive layer 410 from being etched and thus substantially defines the size and position of the first device electrode layer 411 and the first kerf electrode layer 415. According to an example, the etching process used to pattern the first conductive layer 410 is an anisotropic etching process, such as a plasma etching process. Figure 2B and 3B The semiconductor body 100 and the kerf region 200 are shown after the etching process and with the etching mask 310 still in place.

[0037] refer to Figure 2C and 3C The method further includes removing the etching mask 310 and forming a second conductive layer 420 over the insulating layer 5. That is, forming the second conductive layer 420 includes forming the second conductive layer on top of the portion of the insulating layer 5 not covered by the first electrode layers 411, 415 and on top of the first electrode layers 411, 415.

[0038] The second conductive layer 420 includes, for example, a metal such as aluminum (Al) or copper (Cu), or a metal alloy such as AlCu or AlSiCu. AlSiCu is an alloy including aluminum, copper and silicon. According to one example, the second conductive layer 420 is a homogeneous layer including only one material. According to another example, the second conductive layer includes two or more partial layers including different conductive materials.

[0039] According to one example, the second conductive layer 420 is thicker than the first conductive layer 410. That is, the thickness d420 of the second conductive layer 420 is greater than the thickness d410 of the first conductive layer 410. According to one example, the thickness d420 of the second conductive layer 420 is between 3 micrometers and 10 micrometers, in particular, between 3 micrometers and 7 micrometers.

[0040] According to one example, the thickness d410 of the first conductive layer 410 is less than 30% of the thickness d420 of the second conductive layer 420 .

[0041] The method of forming device electrode 41 and kerf electrode 45 further includes patterning second conductive layer 420 to form second device electrode layer 412 at least partially on top of first device electrode layer 411, and removing second conductive layer 420 from over kerf region 200. Patterning second conductive layer 420 may include forming etch mask 320 over second conductive layer 420, and etching second conductive layer 420 with etch mask 320 in place.

[0042] Figure 2D and 3D The second conductive layer 420 is shown after forming the etching mask 320. The etching mask 320 protects certain areas of the second conductive layer 420 from etching and thus substantially defines the size and position of the second device electrode layer 421. According to one example, the etching process used to pattern the second conductive layer 420 is an isotropic etching process, such as a wet etching process. In this type of process, the portion of the second conductive layer 420 located below the edge region of the etching mask 320 is also etched, which needs to be considered in the design of the etching mask 320.

[0043] According to an example, the etching process for patterning the second conductive layer 420 selectively etches the second conductive layer 420 with respect to the first electrode layers 411 , 415 , such that these first electrode layers 411 , 415 remain in place. Figure 2E and 3E The semiconductor body 100 and the kerf region 200 are shown after an etching process for patterning the second conductive layer 420 .

[0044] from Figure 3D and 3E It can be seen that the etching mask 320 used to pattern the second conductive layer 420 causes the second conductive layer 420 to be removed from above the cutout region 200. Therefore, in the cutout region 200, the cutout electrode 45 only includes the first cutout electrode layer 415. However, the device electrode 41 above the semiconductor body 100 includes the first device electrode layer 411 and the second device electrode layer 421 obtained by patterning the second conductive layer 420. This is Figure 2F and 3F is shown in Figure 2F and 3F The semiconductor body 100 and the kerf region 200 are shown after removing the etching mask 320 used to pattern the second conductive layer 420 .

[0045] In the method explained previously, the thicker second conductive layer 420 is removed from above the kerf area 200 so that a portion of the second conductive layer 420 does not adhere to the saw blade when separating the wafer 1. The kerf electrode 45 is formed by a portion of the first conductive layer 410. The first conductive layer 410 is thinner than the second conductive layer 420 and may include a more brittle material, such as tungsten or titanium, than the second conductive layer 420, which may include aluminum or copper. Therefore, the portion of the first conductive layer 410 that forms one or more kerf electrodes 45 does not negatively affect the separation process.

[0046] The test structure (not shown in the drawings) included in the kerf region is measured using one or more kerf electrodes formed by the same process in which the one or more device electrodes 41 are formed over the semiconductor body 100. Therefore, there is no additional process sequence to remove portions of the kerf electrodes after measuring the test structure and before separating the wafer.

[0047] Another positive aspect of the method explained previously is Figures 4A-4D Each of these figures shows a vertical cross-sectional view of a portion of a semiconductor body 100 over which two device electrodes 41 , 42 spaced apart from each other are formed.

[0048] Figure 4A A vertical cross-sectional view of the semiconductor body 100 and the insulating layer 5 is shown after forming a first conductive layer 410 over the insulating layer 5 . Figure 4B 4 shows a vertical cross-sectional view of the semiconductor body 100, the insulating layer 5 and the first conductive layer 420 after patterning the first conductive layer 410 to form the first device electrode layers 411, 412. Figure 4B Patterning the first conductive layer 410 includes etching the first conductive layer 410 using the etching mask 310 that covers those portions of the first conductive layer 410 where the first device electrode layers 411 , 412 are formed.

[0049] The etching mask 310 includes an opening 311. Referring to the above, the etching process is, for example, an anisotropic etching process. In this example, the size of the opening 311 substantially defines the distance between the first device electrode layers 411, 412.

[0050] Figure 4C After removing the etching mask 310 and forming the second conductive layer 420 Figure 4B The arrangement shown in .

[0051] Figure 4D4. It is shown that after patterning the second conductive layer 422 to form the second device electrode layers 421, 422 so that each of the second device electrode layers 421, 422 is at least partially formed on top of the corresponding first device electrode layers 411, 412, Figure 4C Each first device electrode layer 411, 412 and the corresponding second device electrode layer 421, 422 form one of the device electrodes 41, 42. That is, in Figure 4D In the example shown in , first device electrode layer 411 and second device electrode layer 421 form first device electrode 41 , and first device electrode layer 412 and second device electrode layer 422 form second device electrode 42 .

[0052] As explained above, patterning the second conductive layer 420 may include an isotropic etching process. In such a process, a portion of the second conductive layer 420 located below the edge region of the etching mask 320 and adjacent to the opening 321 of the etching mask 320 is also etched. Therefore, the distance d2 between adjacent second device electrode layers 421, 422 may be greater than the corresponding size w321 of the opening 321 in the etching mask 320.

[0053] According to an example, it is possible to Figure 4D The minimum distance between two adjacent second device electrode layers 421, 422 implemented in an etching process of the type shown in FIG. 4 depends on the thickness d420 of the second conductive layer and is between 2 and 3 times the thickness d420. Figure 4D In the example shown in , the distance d2 between the two second device electrode layers 421 , 422 is at least between 1.5 and 3 times the thickness d420 .

[0054] Assuming that the minimum thickness of the second conductive layer 420 is about 3 micrometers, the minimum distance that can be achieved between the second device electrode layers 421, 422 is 6 micrometers. The distance d1 between the first device electrode layers 411, 412 is, for example, much smaller.

[0055] According to an example, the distance d1 between the first device electrode layers 411 , 412 is between 0.5 micrometers and 5 micrometers, in particular between 1 micrometer and 3 micrometers.

[0056] exist Figure 4D In the example shown in , the first device electrode layers 411, 412 may act as a barrier layer for preventing or at least reducing the diffusion of impurity atoms into the insulating layer 5 and the semiconductor body 100. According to one example, the impurity atoms are atoms from a molding compound that may be formed on top of the semiconductor device after the wafer 1 is separated into individual devices. Such impurity atoms may have a negative impact on the functionality of the semiconductor device.

[0057] Therefore, it is desirable to reduce the size of the gap between the first device electrode layers 411, 412 as barrier layers as much as possible. This can be achieved by the method explained previously, in which the first conductive layer 410 and the second conductive layer 420 are patterned by separate processes. Patterning the first conductive layer using, for example, an anisotropic etching process makes it possible to produce a smaller gap between the first device electrode layers 411, 412 than between the second device electrode layers 421, 422, which are formed, for example, by patterning the second conductive layer 420 using an isotropic etching process.

[0058] Figure 5 After removing the second etching mask 320 Figure 4D The arrangement shown in FIG. 1 and the completed first device electrode 41 and second device electrode 42 are shown. Referring to the above, the adjacent second device electrode layer (such as Figure 5 The minimum distance between the second device electrode layers 421, 422) shown in FIG. 4 is greater than that between the adjacent first device electrode layers (such as Figure 5 According to one example, in those regions where the first device electrode 41 and the second device electrode 42 are adjacent to each other, the second device electrode layers 421, 422 are formed such that the edges of the second device electrode layers 421, 421 are spaced apart from the corresponding edges of the first device electrode layers 411, 412. That is, in Figure 5 In the example shown in , the first device electrode layer 411 of the first device electrode 41 protrudes in the direction of the second device electrode 42 below the second device electrode layer 421 of the first device electrode 41. Figure 5 In FIG. 4 , p1 represents the dimension of the first device electrode layer 411 protruding below the second device electrode layer 421. Figure 5 In the example shown in , the first device electrode layer 412 of the second device electrode 42 protrudes below the second device electrode layer 422 of the second device electrode 42. Figure 5 In FIG. 4 , p2 represents the dimension of the first device electrode layer 412 protruding below the second device electrode layer 422 .

[0059] The distance between the second device electrode layers 421, 422 is substantially given by the first protrusion p1 plus the distance between the first device electrode layers 411, 412 plus the second protrusion, d2=p1+d1+p2.

[0060] According to an example, the first device electrode 41 and the second device electrode 42 are asymmetric so that the first protrusion p1 and the second protrusion p2 are different. According to an example, the first protrusion p1 is at least 1.2 times, 1.5 times, 2 times, 2.5 times, 3 times, 4 times or 5 times larger than the second protrusion p2.

[0061] Depending on the specific type of semiconductor device, the first device electrode 41 and the second device electrode 42 may have different functions. According to one example, the first device electrode 41 is a source electrode and the second device electrode 42 is a gate runner of a transistor device. Fig. 6A and 6B As shown in FIG. 4 , the transistor devices each include a first device electrode 41 as a source and a second device electrode 42 as a gate runner. Fig. 6A and 6B Each of the figures shows a top view of the entire transistor device after the wafer 1 is separated into individual devices. After the wafer 1 is separated to form individual transistor devices, the transistor devices may be at least partially encapsulated by a molding compound, wherein portions of the molding compound may abut the device electrodes and portions of the insulating layer 5 not covered by the device electrodes. However, such molding compounds are not Fig. 6A and 6B is shown in .

[0062] refer to Fig. 6A and 6B , the gate runner 42 may surround the source electrode 41 in a lateral direction of the semiconductor body 100. The lateral direction is a direction substantially parallel to the first surface 101 of the semiconductor body 100. Figure 5 , the first surface 101 of the semiconductor body 100 is a surface on top of which the insulating layer 5 is formed.

[0063] As further explained below, the transistor cell 10 of the transistor device may be formed in an inner region of the semiconductor body 100 located below the source electrode 41. The source electrode 41, in particular the first device electrode layer 411, acts as a barrier layer above the transistor cell 10. By implementing the source electrode 41 and the gate runner 42 in an asymmetric manner as explained above, the distance between the inner region in which the transistor cell is integrated and the gap between the first device electrode layers 411, 412 may be maximized to reduce the risk of impurity atoms reaching the transistor cell.

[0064] refer to Fig. 6A and 6B The transistor device may further include a gate pad 44 connected to the gate runner 44. The gate pad 44 forms a gate node G or is connected to the gate node G of the transistor device. The gate pad 44 may be adjacent to the gate runner 42, such as Fig. 6A and 6B Alternatively, the gate pad 44 is spaced apart from the gate flow channel 42 , and a resistor (gate resistor) is connected between the gate pad 44 and the gate flow channel 42 .

[0065] Gate pad 44 is a device electrode that may be formed by the same process as source electrode 41 and gate runner 42. In an example where gate pad 44 adjoins gate runner 42, gate pad 44 and gate runner 42 are formed as one continuous device electrode.

[0066] exist Fig. 6A In the example shown in , the gate pad 44 is arranged substantially in the middle between two opposite side walls 103 , 106 of the semiconductor body 100 . Figure 6B In the example of FIG. 4 , the gate pad 44 is arranged at a position close to a corner formed by two adjacent side walls 105 , 106 of the semiconductor body 100 . The side walls 103 - 106 of the semiconductor body 100 are caused by separating the wafer 1 into individual semiconductor bodies 100 .

[0067] The semiconductor body 100 may include an inner region and an edge region. The inner region is basically a region of the semiconductor body 100 arranged below the source electrode 41. The edge region surrounds the inner region and is arranged between the inner region and the sidewalls 103-106. In the inner region of the semiconductor body 100, a plurality of transistor cells are integrated. Each of the transistor cells includes a gate electrode 21. The transistor cells are Fig. 6A and 6B Examples of transistor cells are further explained below.

[0068] For illustration purposes only, the positions of the two gate electrodes 21 relative to the source electrode 41, the gate runner 42 and the gate pad 44 are shown in FIG. Fig. 6A and 6B is shown in bold. Fig. 6A and 6B In the example shown in , the gate electrodes 21 are strip-shaped electrodes spaced apart from each other in a first lateral direction x. The longitudinal direction of the gate electrodes 21 corresponds, for example, to a second lateral direction y perpendicular to the first lateral direction x.

[0069] The gate electrode 21 of each transistor cell is electrically connected to the gate runner 42 at at least one longitudinal end of the corresponding gate electrode 21. The connection between the gate electrode 21 and the gate runner 42 is not shown in Figure 6. The connection between the gate electrode 21 and the gate runner 42 is further explained below.

[0070] An example of a transistor cell 10 that can be integrated in a semiconductor body 100 below a source electrode 41 is Figure 7 is shown in . Figure 7 A vertical cross-sectional view of a portion of a semiconductor body 100 is shown, in which portion a transistor cell 10 is integrated. Figure 7 A vertical cross-sectional view of a transistor cell shown in FIG. Fig. 6A and6B Vertical cross-sectional view in the cross-sectional plane CC shown in .

[0071] refer to Figure 7 Each transistor cell 10 includes a source region 11 of a first doping type, a body region 12 of a second doping type complementary to the first doping type, and a gate electrode 21. The gate electrode 21 is adjacent to the body region 12, the gate electrode 21 is dielectrically insulated from the body region 12 by a gate dielectric 22, and the gate electrode 21 is arranged in a gate trench 120 extending from a first surface 101 of the semiconductor body 100 into the semiconductor body 100.

[0072] refer to Figure 7 , the source region 11 and the body region 12 of two adjacent transistor cells 10 can be arranged in the mesa region between adjacent gate trenches 120. In this example, the body region 12 of the two adjacent transistor cells 10 can be formed by a continuous doping region of the second doping type. In addition, two (other) adjacent transistor cells can share a gate electrode 21. That is, the gate electrode 21 of the two adjacent transistor cells can be formed by a continuous electrode arranged in a gate trench 120.

[0073] The gate electrode 21 includes a conductive material. Examples of the conductive material include doped polysilicon, or metals such as tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), etc. The gate dielectric 22 includes, for example, an oxide. According to one example, the oxide is silicon oxide (SiO2).

[0074] The source electrode 41 either forms the source node S of the transistor device or is connected to the source node S of the transistor device. Figure 7 4 is schematically shown in the figure, and thus the first device electrode layer 411 and the second device electrode layer 412 are not shown.

[0075] The source electrode 41 is electrically connected to the source region 11 and the body region 12 of the transistor cell 10. The connection between the source electrode 41 and the source region 11 and the body region 12 is only Figure 7 Such connection may be achieved using a conductive via extending from the source electrode 41 through the insulating layer 5 down to the source region 11 and the body region 12. Examples of such vias are further explained below.

[0076] The insulating layer 5 is formed on top of the first surface 101 and on top of the gate electrode 21 , and separates the source electrode 41 from the semiconductor body 100 and the gate electrode 20 .

[0077] refer to Figure 7, the transistor device further includes a drift region 14 of the first doping type. The drift region 14 is adjacent to the body region 12 of the transistor cell 10, so that a PN junction is formed between the body region 12 and the drift region 14. In addition, in the vertical direction, the drift region 14 is arranged between the body region 12 and the drain region 13 of the first doping type. The drain region 13 may be adjacent to a second surface 102 opposite to the first surface 101.

[0078] Optionally, a buffer region 16 of the first doping type and having a doping concentration which is higher than the doping concentration of the drift region 14 and lower than the doping concentration of the drain region 13 is arranged between the drift region 14 and the drain region 13 .

[0079] refer to Figure 7 And as explained above, the gate trenches with the gate electrode 21 can be spaced apart from each other in the first lateral direction x. According to one example, the gate electrode 21 is implemented as a strip electrode (strip electrode). In this example, the longitudinal direction of the gate electrode 21 corresponds to a second lateral direction perpendicular to the first lateral direction x.

[0080] An example of the stripe gate electrode 21 is Figure 8 is shown in . Figure 8 Shows Figure 7 A portion of the semiconductor body 100 in a first horizontal cross-sectional plane DD shown in FIG. 1 , which first horizontal cross-sectional plane passes through the gate trench 120 with the gate electrode 21 and the gate dielectric 22. The horizontal cross-sectional plane DD is substantially parallel to the first surface 101. Figure 8 In the example shown in , the gate electrode 21 extends longitudinally in the second lateral direction y.

[0081] According to one example, the transistor device is implemented as a super junction transistor device. In this example, the transistor device includes a plurality of compensation regions 15 (shown in dashed lines) that are spaced apart from each other in a lateral direction of the semiconductor body 100. Each compensation region 15 is adjacent to a corresponding portion of the drift region 14.

[0082] For illustrative purposes only, Figure 7 In the example shown in , the compensation zones 15 are spaced apart from each other in a first lateral direction x. According to another example (not shown), the compensation zones 15 are spaced apart from each other in a second lateral direction y.

[0083] The transistor device can be operated in an on state or an off state. In the on state, a conductive path exists between the source region 11 and the drift region 14 along the gate dielectric 22 in the body region 12. To this end, the drift region 14 adjoins the body region 12 and the gate dielectric 22 of at least one of the transistor cells 10.

[0084] Furthermore, each of the optional compensation regions 15 is adjacent to at least one of the portions of the drift region 14 and is connected to the source electrode 41 . Figure 7 In the example shown in , each of the compensation regions 15 adjoins the body region 12 of at least one transistor cell and is connected to the source electrode 41 via the corresponding body region 12 .

[0085] The transistor device can be operated in a conventional manner by applying a driving voltage (gate-source voltage) between the gate electrode 21 and the source electrode 41. When the driving voltage causes a conductive channel to be generated in the body region 12 between the source region 11 and the drift region 14 along the gate dielectric 22, the transistor device is in an on state (conductive state). When the conductive channel is interrupted, the transistor device is in an off state (blocking state).

[0086] The transistor device can be implemented as an N-type transistor device or a P-type transistor device. When the driving voltage is higher than a predefined positive threshold voltage, the N-type transistor device, for example, is in an on state, and when the driving voltage is lower than the threshold voltage, the N-type transistor device is in an off state.

[0087] In an N-type transistor device, the doped region of the first doping type is an N-type region and the doped region of the second doping type is a P-type region. In a P-type transistor device, the doped region of the first doping type is a P-type region and the doped region of the second doping type is an N-type region.

[0088] The source region 11 , the body region 12 , the drift region 14 and the compensation region 15 , the buffer region 16 , and the drain region 13 may also be referred to as (active) device regions of the transistor device.

[0089] Fig. 9 Shows that there is Figure 7 A transistor device of a transistor cell of the type shown in FIG. 1 is viewed in a vertical cross-sectional plane EE (see FIG. 1 ). Fig. 6A and 6B ), the vertical cross-sectional plane EE runs through a portion of the inner region 130 and a portion of the edge region 140 of the semiconductor body 100. The inner region 130 is a region in which the transistor unit is integrated and the source electrode 41 is arranged on top thereof. The edge region 140 surrounds the inner region 130 in the lateral direction and is a region on top of which the gate runner 42 and the gate pad 44 are arranged.

[0090] The plurality of transistor cells include an edge transistor cell, which is one of the transistor cells closest to the edge region 140. The edge transistor cell may include a source region 11 (at Figure 8 Alternatively, the source region 11 is omitted in the edge transistor cell.

[0091] Fig. 9 The transistor device shown in FIG. 1 is a super junction transistor device, which includes a compensation region 15 in addition to the drift region 14. Fig. 9 In one example shown in FIG, the drift region and the compensation region are arranged not only in the inner region 130 but also in the edge region 140. The drift region arranged in the edge region 140 may be referred to as an edge drift region 14', and the compensation region arranged in the edge region 140 may be referred to as an edge compensation region 15'.

[0092] Referring to the above, the source region 11 and the body region 12 of the transistor cell are connected to the source electrode 41. Fig. 9 In one example shown in , the source region 11 and the body region 12 are connected to the source 41 by a conductive via 49, which extends from the source 41 through the insulating layer 5 to the source region 11 and the body region 12 in the semiconductor body 100. Optionally, each transistor cell 10 includes a body contact region 17 of a second doping type providing an ohmic contact between the body region 12 and the corresponding conductive via 49. The body contact region 17 has a higher doping concentration than the body region 12.

[0093] In the edge region, the transistor device may include an edge termination structure. According to an example, the edge termination structure includes an edge trench 6 extending from the first surface 101 into the edge region 140 of the semiconductor body 100 and filled with an electrically insulating layer 51. The edge trench 6 with the insulating layer 51 may surround the inner region 130 in a lateral direction.

[0094] Furthermore, the edge termination structure may comprise a field electrode 31 which is arranged above the edge trench 6 and is electrically connected to the gate runner 42 through a conductive via 46. The field electrode 31 comprises, for example, doped polysilicon.

[0095] The gate flow channel 42 is only Fig. 9 That is, the first device electrode layer 412 and the second device electrode layer 422 forming the gate flow channel 42 are not Fig. 9 is shown in .

[0096] According to one example, the conductive via 49 connecting the source region 11 and the body region 12 of the transistor cell 10 to the source electrode 41 is formed by the same process as forming the source electrode 41. Figures 10A-10C Explained, Figures 10A-10C Each shows a detailed view of one of the conductive vias 49 extending from the source electrode 41 through the insulating layer 5 into the semiconductor body 100 .

[0097] Forming the via 49 includes forming a trench extending from the surface 501 of the insulating layer 5 through the insulating layer 5 into the semiconductor body 100 before forming the first conductive layer 410 . Fig. 10A and 10B The conductive via 49 is shown after forming the first conductive layer 410 and the second conductive layer 420. It can be seen that the first conductive layer 410, more specifically the first device electrode layer 411, at least partially forms the via 49. That is, the first device electrode layer 411 at least partially fills the via trench. Fig. 10A In the example shown in , the first device electrode layer 411 completely fills the via trench. In this example, the via 49 is formed by a portion of the first device electrode layer 411 located in the via trench.

[0098] exist Fig. 10B In the example shown in , the first device electrode layer 411 lines the bottom and sidewalls of the via trench, but does not completely fill the via trench. The residual trench remaining after forming the first device electrode layer 411 is filled by the second conductive layer 420, more specifically, by the second device electrode layer 421. In this example, the via 49 is formed by a portion of the first conductive layer 410 and a portion of the second conductive layer 420.

[0099] according to Fig. 10C In another example shown in , the first device electrode layer 411 lines the bottom and sidewalls of the via trench, and after forming the second device electrode layer 421, the void 491 remains in the via trench.

[0100] As via 49 is formed by the same process as source electrode 41, via 46 connecting gate runner 42 to field electrode 31 can be formed by the same process as gate runner 42. An example of conductive via 46 is shown in FIG. Figures 11A-11C is shown in Fig.11A In the example shown in , the first device electrode layer 412 of the gate runner 42 completely fills the via trench extending in the insulating layer 5 to the field electrode 31. Fig. 11B In the example shown in , the first device electrode layer 412 of the gate channel 42 lines the bottom and sidewalls of the via trench, wherein the residual trench remaining after forming the first conductive layer 410 is filled with the second conductive layer 420, more specifically, with the second device electrode layer 422 in the gate channel 42.

[0101] according to Fig. 11C In another example shown in , the first device electrode layer 412 lines the bottom and sidewalls of the via trench, and after forming the second device electrode layer 422, the void 461 remains in the via trench.

[0102] Referring to the above, each of the gate electrodes 21 is connected to the gate runner 42 at at least one longitudinal end. One example of connecting the gate electrode 21 to the gate runner 42 is Fig.12 is shown in .

[0103] Fig.12 The cross-sectional plane FF (see Fig. 6A and 6B ) is a vertical cross-sectional view of the transistor device in FIG. 1 , wherein the cross-sectional plane FF is substantially parallel to the longitudinal direction of the gate electrode 21 and passes through one of the gate electrodes 21 . Fig.12 A portion of an inner region 130 and an edge region 140 of a semiconductor body 100 is shown.

[0104] exist Fig.12 In the example shown in , the gate electrode 21 is connected to the gate runner 42 via the field electrode 31. To this end, contact fingers 32 extend in the insulating layer 5 from the field electrode 31 to the gate electrode 21 and are connected to the gate electrode 21 at its longitudinal ends.

[0105] The field electrode 31 and the contact finger 32 may be formed by the same process, so that the field electrode 31 and the contact finger 32 may be formed by a continuous electrode layer. The electrode layer is, for example, a conductive layer, such as a doped polysilicon layer.

[0106] According to Fig. 6A and 6B In one example shown in dashed lines in FIG. 1 , the transistor device further includes a drain runner 43. The drain runner 43 is arranged between the gate runner 42 and the sidewalls 103-106, and surrounds the gate runner 42 and the source electrode 41 in the lateral direction.

[0107] Fig.13 A vertical cross-sectional view of a portion of an insulating layer 5 is shown, on top of which a source electrode 41 , a gate runner 42 and a drain runner 43 are arranged. Fig.13 The cross-sectional plane shown in corresponds, for example, to Fig. 6A and 6B The cross-sectional plane GG is shown in FIG. Fig.13 In FIG. 1 , the semiconductor body 100 is only schematically shown; the active device region is not shown.

[0108] The drain flow channel 43 is formed by the same process of forming the device electrodes, such as the source electrode 41 and the gate flow channel 42, and the cut electrode 45. The drain flow channel 43 is formed in the same manner as the cut electrode 45. That is, the drain flow channel 43 includes the first device electrode layer 413 obtained by patterning the first conductive layer 410. The drain flow channel 43 includes only the first device electrode layer 413. That is, the drain flow channel 43 does not include the second device electrode layer obtained by patterning the second conductive layer 420.

[0109] Referring to the above, after the wafer 1 is separated, the molding material 500 (in Fig.13 The second device electrode segments 421, 422 based on the relatively thick second conductive layer 420 may include relatively sharp edges. Thermal stresses of the molding compound 500 may lead to damage to the molding compound along these sharp edges. At least in the area of ​​the drain channel 43, this risk can be reduced by manufacturing the drain channel 43 only based on the (relatively thin) first conductive layer 410. Unlike the source electrode 41 and the gate channel 42, the drain channel 43 does not require a low resistance.

[0110] Fig.14 A vertical cross-sectional view of an example of a transistor device is shown, the transistor device comprising Fig.13 The drain channel 43 of the type shown in FIG. The source electrode 41 and the gate channel 42 are only Fig.14 is schematically shown in FIG. Fig.14 The examples shown in are based on Fig. 9 The example shown in .

[0111] refer to Fig.14 , the transistor device comprises a field stop zone 51 of a first doping type extending from the drain region 13 or the buffer region 16 along the sidewalls 103-106 to the first surface 101. The drain runner 43 is electrically connected to the field stop zone 51. According to an example, the drain runner 43 is connected to the field stop zone 51 through a conductive via 48. The conductive via 48 can be produced in the same way as the vias 49, 46 explained previously.

[0112] Furthermore, drain runner 46 is connected to second field electrode 33 embedded in the insulating layer. Drain runner 43 is connected to second field electrode 33 through conductive via 47 extending from drain runner 46 through part of insulating layer 5 to second field electrode 33.

[0113] With regard to the vias 46 connecting the gate runner 42 to the first field electrode 31 and the vias 47 connecting the drain runner 43 to the second field electrode 33, it should be noted that these vias are in contact with the respective field electrodes. This may include the vias 46, 47 contacting the respective field electrodes 31, 33 at the surface. Fig.12 and 14 As another example, which is shown in dashed lines in FIG. 4 , the vias 46 , 47 extend into the corresponding field electrodes 31 , 33 , or even through the corresponding field electrodes 31 , 33 .

[0114] Fig.15Schematically shows a vertical cross-sectional view of a portion of a cutout region 200 located between two semiconductor bodies 100. According to one example, a transistor device is implemented in the semiconductor body 100. An optional drain runner 43 of the transistor device is Fig.15 It is shown in dashed lines.

[0115] Just as an example, Fig.15 Two notch electrodes 45 of the wafer 1 are shown. Each of these notch electrodes 45 is connected to a test structure 8 arranged in the notch region 200 of the wafer. The connection between the notch electrode 45 and the test structure 8 and the test structure 8 are only Fig.15 is schematically shown in FIG.

Claims

1. A method, comprising: forming a device electrode (41) above a semiconductor body (100) of a semiconductor wafer (1), wherein the semiconductor wafer (1) comprises semiconductor bodies (100) and a kerf region (200) located between the semiconductor bodies (100); and forming a notch electrode (45) above the notch region (200), Wherein, forming the device electrode (41) and the cut electrode (45) comprises: forming a first conductive layer (410) on top of the insulating layer formed above the semiconductor body (100) and the cutout region (200); Patterning the first conductive layer (410) to form a first device electrode layer (411) and a first notch electrode layer (415); forming a second conductive layer (420) on top of the insulating layer (5), the first device electrode layer (411) and the first notched electrode layer (415); and The second conductive layer (420) is patterned to form a second device electrode layer (421) at least partially on top of the first device electrode layer (411), and the second conductive layer (420) is removed from above the cutout region (200).

2. The method according to claim 1, wherein: The first conductive layer (410) includes at least one of tungsten and titanium.

3. The method according to claim 1 or 2, wherein: The second conductive layer (420) includes at least one of aluminum and copper.

4. A method according to any one of the preceding claims, wherein: The thickness (d410) of the first conductive layer (410) is less than 30% of the thickness of the second conductive layer.

5. A method according to any one of the preceding claims, wherein: The thickness (d410) of the first conductive layer (410) is between 0.8 micrometers and 1.5 micrometers.

6. A method according to any one of the preceding claims, wherein: The thickness (d420) of the second conductive layer (420) is between 3 micrometers and 10 micrometers, in particular between 3 micrometers and 7 micrometers.

7. A method according to any one of the preceding claims, wherein: The device electrode (41) is a first device electrode, Wherein, the method further comprises: forming a second device electrode (42) spaced apart from the first device electrode (41), and Wherein, forming the second device electrode (42) comprises: forming a first device electrode layer (412) of the second device electrode (42) by patterning the first conductive layer (410); and A second device electrode layer (422) of the second device electrode (42) is formed at least partially on top of the first device electrode layer (412) of the second device electrode (42) by patterning the second conductive layer (420).

8. The method according to claim 7, wherein: The method further comprises: A first device electrode layer (411) of the first device electrode (41) and a first device electrode layer (412) of the second device electrode (42) are formed so as to be spaced closer to each other than a second device electrode layer (421) of the first device electrode (41) and a second device electrode layer (422) of the second device electrode (42).

9. The method according to claim 8, wherein: The method further comprises: The first device electrode layer (411) of the first device electrode (41) and the first device electrode layer (412) of the second device electrode (42) are formed to have a mutual distance (d1) between 0.5 micrometers and 2 micrometers.

10. The method according to claim 8 or 9, wherein: The method further comprises: The second device electrode layer (421) of the first device electrode (41) and the second device electrode layer (422) of the second device electrode (42) are formed to have a mutual distance (d2) greater than 5 micrometers.

11. The method according to any one of claims 7 to 10, wherein: The first device electrode layer (411) of the first device electrode (41) protrudes from the second device electrode layer (421) of the first device electrode (41) toward the second device electrode (42), and The first device electrode layer (421) of the second device electrode (42) protrudes from the second device electrode layer (422) of the second device electrode (42) toward the first device electrode (41).

12. A method according to any one of the preceding claims, wherein: The method further comprises: A third device electrode (43) is formed, the third device electrode (43) comprising only the first device electrode layer (413) obtained by patterning the first conductive layer (410).

13. A semiconductor device, comprising: a first device electrode (41) and a second device electrode (42), wherein the first device electrode (41) comprises a first device electrode layer (411) and a second device electrode layer (421) at least partially formed on top of the first device electrode layer (411), wherein the second device electrode (42) comprises a first device electrode layer (412) and a second device electrode layer (422) at least partially formed on top of the first device electrode layer (412), The distance (d1) between the first device electrode layer (411) of the first device electrode (41) and the first device electrode layer (412) of the second device electrode (42) is shorter than the distance (d2) between the second device electrode layer (421) of the first device electrode (41) and the second device electrode layer (422) of the second device electrode (42).

14. The semiconductor device according to claim 1, wherein The first device electrode layer (411) of the first device electrode (41) protrudes a first protrusion (p1) in the direction of the second device electrode (42) below the second device electrode layer (421) of the first device electrode (41), The first device electrode layer (412) of the second device electrode (42) protrudes a second protrusion (p2) in the direction of the first device electrode (41) below the second device electrode layer (422) of the second device electrode (42), Wherein, the first protrusion (p1) is larger than the second protrusion (p2).

15. The semiconductor device according to claim 14, wherein: A size (d1) of the first protrusion is at least 1.2 times a size of the second protrusion.

16. The semiconductor device according to any one of claims 13 to 15, wherein: The semiconductor device is a transistor device, The first device electrode (41) is a source electrode, and The second device electrode (42) is a gate runner.

17. The semiconductor device according to claim 16, wherein: The transistor device comprises a plurality of transistor cells (10), Each of the transistor cells (10) comprises a source region (11) and a body region (12) connected to the source (41), and Each of the transistor cells (10) includes a gate electrode (21) connected to the gate flow channel (42).

18. A semiconductor wafer, comprising: A plurality of semiconductor bodies (100) and a cutout region (200) arranged between the semiconductor bodies (100), at least one device electrode (41) arranged above at least one of the semiconductor bodies (100), and at least one notch electrode (45), the at least one notch electrode (45) being arranged above at least one of the notch areas (200), wherein the at least one device electrode (41) comprises a first device electrode layer (411) obtained by patterning a first conductive layer (410) and a second device electrode layer (421) obtained by patterning a second conductive layer (420) different from the first conductive layer (410); and The at least one notch electrode (45) includes a first notch electrode layer (415) obtained by patterning the first conductive layer (410), and does not include a second notch electrode layer.

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