Driving substrate and display panel

Abstract

The invention relates to a driving substrate and a display panel. The driving substrate comprises a substrate, a first thin film transistor, a barrier layer and a second thin film transistor, the first thin film transistor is arranged on the substrate and comprises a first active layer and a first grid electrode, and the first grid electrode is located on the side, away from the substrate, of the first active layer; the blocking layer is arranged on the substrate and covers the first thin film transistor, the blocking layer is arranged to be of a stacked multi-film-layer structure, and the blocking layer at least comprises an organic layer located in the middle layer; the second thin film transistor is arranged on the side, away from the substrate, of the blocking layer, the second thin film transistor is electrically connected with the first thin film transistor, the second thin film transistor comprises a second active layer and a second grid electrode, and the second grid electrode is located on the side, away from the blocking layer, of the second active layer. The second active layer and the first active layer are overlapped.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and in particular to a driving substrate and a display panel. Background Art

[0002] AMOLED display technology has been applied to various display screens in recent years due to its superior characteristics (high contrast, high color gamut, high response, high refresh, flexibility, thinness, etc.). Taking VR\AR display screens as an example, since VR / AR display screens are small in size but require high pixel resolution, the requirements for the driving circuit are very high. VR / AR display screens usually use LTPO (full name: Low Temperature Polycrystalline Oxide, Chinese abbreviation: Low Temperature Polycrystalline Oxide) array substrates as driving substrates; in the prior art, the pixel resolution is usually improved by reducing the number of TFTs (thin film transistors), but in order to meet the needs of the pixel circuit functional module, the number of TFTs must not be less than 3; and in order to further compress the space occupied by TFTs and improve the space utilization and resolution of the display panel, the LTPS TFT and IGZO TFT in the LTPO array substrate are usually stacked, but the parasitic capacitance between the stacked TFTs will increase, thereby increasing the negative impact of RC Loading. Summary of the invention

[0003] The embodiments of the present application provide a driving substrate and a display panel, which reduce the negative impact of RC Loading while improving the space utilization and resolution of the display panel.

[0004] In order to achieve the above object, according to a first aspect of the present application, a driving substrate is provided, comprising:

[0005] substrate;

[0006] a first thin film transistor, disposed on the substrate, comprising a first active layer and a first gate, wherein the first gate is located on a side of the first active layer away from the substrate;

[0007] a barrier layer, disposed on the substrate and covering the first thin film transistor, wherein the barrier layer is configured as a stacked multi-layer structure, and the barrier layer at least includes an organic layer located in the middle layer;

[0008] The second thin film transistor is arranged on the side of the barrier layer away from the substrate, and includes a second active layer and a second gate. The second gate is located on the side of the second active layer away from the barrier layer. In the thickness direction of the driving substrate, the second active layer overlaps with the first active layer.

[0009] In one embodiment, the barrier layer also includes a first inorganic layer and a second inorganic layer. In the thickness direction of the driving substrate, the first inorganic layer, the organic layer and the second inorganic layer are stacked in sequence, the first inorganic layer covers the first thin film transistor, and the second thin film transistor is arranged on the side of the second inorganic layer away from the substrate.

[0010] In one embodiment, in the thickness direction of the driving substrate, the thickness of the organic layer is set to be 1 μm to 2 μm.

[0011] In one embodiment, the second active layer includes a second channel portion, and a second source contact portion and a second drain contact portion respectively disposed on both sides of the second channel portion;

[0012] The second thin film transistor further includes a second source electrode, which is disposed on a side of the second gate electrode away from the barrier layer, and the second source electrode is electrically connected to the second source contact portion.

[0013] In one embodiment, in the thickness direction of the driving substrate, the second drain contact portion at least partially overlaps with the first gate;

[0014] The barrier layer is provided with a first via hole, the first via hole is aligned with the second drain contact portion, and the second drain contact portion is electrically connected to the first gate through the first via hole.

[0015] In one embodiment, the driving substrate further comprises a second interlayer insulating layer, the second interlayer insulating layer is arranged on a side of the barrier layer away from the substrate and covers the second thin film transistor, the second interlayer insulating layer is provided with a second via hole, and the second via hole is arranged in alignment with the second source electrode;

[0016] A third via hole is disposed on the barrier layer, and the third via hole is disposed in alignment with the second via hole;

[0017] The second source is electrically connected to the first source of the first thin film transistor through the second via hole and the third via hole in sequence.

[0018] In one embodiment, the driving substrate further includes:

[0019] a dielectric protection layer, disposed on a side of the barrier layer away from the substrate and covering the second thin film transistor, the dielectric protection layer being provided with a fourth via hole, the fourth via hole being aligned with the second drain contact portion; and,

[0020] A pixel electrode is disposed on a side of the dielectric protection layer away from the second thin film transistor, and the pixel electrode is electrically connected to the second drain contact portion through the fourth via hole.

[0021] In one embodiment, the first active layer includes a first channel portion, and a first source contact portion and a first drain contact portion respectively disposed on both sides of the first channel portion;

[0022] The first thin film transistor further includes a first source and a first drain, wherein the first source and the first drain are located on a side of the first gate away from the substrate and are electrically connected to the first source contact portion and the first drain contact portion respectively.

[0023] In one embodiment, the second active layer includes a second channel portion, and a second source contact portion and a second drain contact portion respectively disposed on both sides of the second channel portion;

[0024] In the thickness direction of the driving substrate, the first gate and the second gate are staggered, and the orthographic projection of the second channel portion on the substrate is within the orthographic projection range of the first gate on the substrate.

[0025] According to a second aspect of the present application, a display panel is provided, comprising the above-mentioned driving substrate.

[0026] In the driving substrate of the embodiment of the present application, a first thin film transistor and a second thin film transistor are stacked in sequence on the substrate; the first thin film transistor includes a first active layer and a first gate, and the first gate is located on the side of the first active layer away from the substrate; the second thin film transistor includes a second active layer and a second gate, and the second gate is located on the side of the second active layer away from the barrier layer; by overlapping the second active layer with the first active layer in the thickness direction of the driving substrate, the space occupied by the first thin film transistor and the second thin film transistor is merged, the space occupied by a single pixel is reduced, and the space utilization and resolution of the driving substrate are improved; at the same time, a barrier layer is arranged between the first thin film transistor and the second thin film transistor. Since the barrier layer is arranged as a stacked multi-film layer structure and at least includes an organic layer located in the middle layer, it is possible to increase the distance between the first thin film transistor and the second thin film transistor, thereby reducing the capacitance between the signals of the first thin film transistor and the second thin film transistor, thereby reducing the negative impact of RC Loading.

[0027] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0029] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0030] Figure 1 Film stacking patterning of a drive substrate provided by the prior art;

[0031] Figure 2 The film stacking pattern of the driving substrate provided in the embodiment of the present application;

[0032] Figure 3 Pixel driving circuit of the driving substrate provided in the embodiment of the present application Figure 1 ;

[0033] Figure 4 A wiring diagram of a thin film transistor structure provided in an embodiment of the present application;

[0034] Figure 5 for Figure 4 The cross-sectional view of the local AA in the middle;

[0035] Figure 6 for Figure 4 Sectional view of the local BB;

[0036] Figure 7 A local wiring diagram of a first thin film transistor provided in an embodiment of the present application;

[0037] Figure 8 Pixel driving circuit provided in the embodiment of the present application Figure 2 ;

[0038] Fig. 9 A local wiring diagram of a second thin film transistor provided in an embodiment of the present application;

[0039] Fig.10 Pixel driving circuit provided in the embodiment of the present application Figure 3 . DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0041] VR / AR display screens usually use LTPO (Low Temperature Polycrystalline Oxide, Chinese abbreviation: low temperature polycrystalline oxide) array substrates as driving substrates. LTPO array substrates generally use LTPS (Low Temperature Poly-Silicon, Chinese abbreviation: low temperature polycrystalline silicon) and metal oxides, such as IGZO (Indium Gallium Zinc Oxide, Chinese abbreviation: indium gallium zinc oxide) to make TFT (Thin Film Transistor); LTPS is responsible for driving and metal oxide is responsible for switching. LTPO array substrates have the advantages of higher charge mobility and lower off-state leakage current, which can reduce the overall power consumption of the screen when it is working, achieving the purpose of power saving.

[0042] See also Figure 1 In the prior art, a first thin film transistor 2' and a second thin film transistor 4' are manufactured on a substrate 1', and the first thin film transistor 2' and the second thin film transistor 4' are arranged side by side in the horizontal direction, so that a single pixel occupies a larger area, and fewer pixels can be arranged in the same area, which is not conducive to improving the space utilization and resolution of the driving substrate 100'.

[0043] The embodiment of the present application provides a driving substrate 100 and a display panel. The following are detailed descriptions of each. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0044] In a first aspect, the present invention provides a driving substrate 100. Figures 2 to 4 The driving substrate 100 includes a substrate 1, a first thin film transistor 2, a barrier layer 3 and a second thin film transistor 4; the first thin film transistor 2 is arranged on the substrate 1, and includes a first active layer 21 and a first gate 22, and the first gate 22 is located on the side of the first active layer 21 away from the substrate 1; the barrier layer 3 is arranged on the substrate 1 and covers the first thin film transistor 2, the barrier layer 3 is arranged as a stacked multi-layer structure, and the barrier layer 3 at least includes an organic layer 31 located in the middle layer; the second thin film transistor 4 is arranged on the side of the barrier layer 3 away from the substrate 1, the second thin film transistor 4 is electrically connected to the first thin film transistor 2, the second thin film transistor 4 includes a second active layer 41 and a second gate 42, the second gate 42 is located on the side of the second active layer 41 away from the barrier layer 3, and in the thickness direction F1 of the driving substrate 100, the second active layer 41 and the first active layer 21 are overlapped.

[0045] In the embodiment provided in the present application, a first thin film transistor 2 and a second thin film transistor 4 are sequentially stacked on a substrate 1; the first thin film transistor 2 includes a first active layer 21 and a first gate 22, and the first gate 22 is located on a side of the first active layer 21 away from the substrate 1; the second thin film transistor 4 includes a second active layer 41 and a second gate 42, and the second gate 42 is located on a side of the second active layer 41 away from the substrate 1; the second active layer 41 is overlapped with the first active layer 21 in the thickness direction F1 of the driving substrate 100, so that the space occupied by the first thin film transistor 2 and the second thin film transistor 4 is merged, the space occupied by a single pixel is reduced, and the space utilization and resolution of the driving substrate 100 are improved.

[0046] It should be noted that the material of the first active layer 21 of the first thin film transistor 2 is set to low-temperature polysilicon, and the first thin film transistor 2 is set to be an LTPS transistor; the material of the second active layer 41 of the second thin film transistor 4 is set to metal oxide, and the second thin film transistor 4 is set to be an IGZO transistor.

[0047] It can be known that in the prior art, an inorganic insulating layer 3′ is usually arranged between the first thin film transistor 2′ and the second thin film transistor 4′. Although the inorganic insulating layer 3′ can separate the first thin film transistor 2′ and the second thin film transistor 4′, since the thickness of the inorganic layer 3′ is very thin and the parasitic capacitance between the signals is large, the negative impact of the RCLoading of the driving substrate 100′ is large.

[0048] In an embodiment of the present application, a barrier layer 3 is arranged between the first thin film transistor 2 and the second thin film transistor 4. Since the barrier layer 3 is arranged as a stacked multi-layer structure and includes at least an organic layer 31 located in the middle layer, the distance between the first thin film transistor 2 and the second thin film transistor 4 can be increased, thereby reducing the capacitance between the signals of the first thin film transistor 2 and the second thin film transistor 4, thereby reducing the negative impact of RC Loading.

[0049] See also Figure 3 and Figure 4In one embodiment, the driving substrate 100 includes a first thin film transistor a, a second thin film transistor b, a third thin film transistor c and a fourth thin film transistor d; wherein the first thin film transistor a and the fourth thin film transistor d are configured as the first thin film transistor 2 as driving transistors; the second thin film transistor b and the third thin film transistor c are configured as the second thin film transistor 4 as switching transistors. Since the second thin film transistor 4 and the first thin film transistor 2 are stacked, the space occupied by the four thin film transistors is halved, thereby increasing the pixel resolution of the driving substrate 100 to twice the original. The first thin film transistor a is electrically connected to the second thin film transistor b and the third thin film transistor c.

[0050] See also Figure 3 , Figure 3 Pixel driving circuit of the driving substrate provided in the embodiment of the present application Figure 1 The gate of the first thin film transistor a is electrically connected to the first node P, the source of the first thin film transistor a is electrically connected to the second node Q, and the drain of the first thin film transistor a is electrically connected to the source of the fourth thin film transistor d; the gate of the second thin film transistor b is connected to the WR signal, the main function of the WR signal is to selectively turn on or off the switch transistor in the pixel circuit, the source of the second thin film transistor b is connected to the data line to input the data signal, and the drain of the second thin film transistor b is electrically connected to the first node P; the gate of the third thin film transistor c is connected to the WR signal, the drain of the third thin film transistor c is connected to the Vini reset signal, and the source of the third thin film transistor c is electrically connected to the second node Q; the gate of the fourth thin film transistor d is connected to the En signal for activating each row of pixels row by row, the source of the fourth thin film transistor d is electrically connected to the drain of the first thin film transistor a, and the drain of the fourth thin film transistor d is connected to the power supply voltage (Vdd) signal; the second node Q is electrically connected to the anode of the OLED, one end of the capacitor Cst is electrically connected to the first node P, and the other end of the capacitor Cst is electrically connected to the second node Q.

[0051] See also Figure 2 In one embodiment, the barrier layer 3 further includes a first inorganic layer 32 and a second inorganic layer 33. In the thickness direction F1 of the driving substrate 100, the first inorganic layer 32, the organic layer 31 and the second inorganic layer 33 are stacked in sequence, the first inorganic layer 32 covers the first thin film transistor 2, and the second thin film transistor 4 is arranged on the side of the second inorganic layer 33 away from the substrate 1.

[0052] In this embodiment, the barrier layer 3 includes a first inorganic layer 32, an organic layer 31, and a second inorganic layer 33 which are stacked in sequence; the stacked multi-layer structure can further increase the thickness of the barrier layer 3, thereby further increasing the distance between the first thin film transistor 2 and the second thin film transistor 4, thereby reducing the capacitance between the signals of the first thin film transistor 2 and the second thin film transistor 4, and reducing the negative impact of RC Loading. At the same time, the first inorganic layer 32 and the second inorganic layer 33 are arranged on both sides of the organic layer 31, which can prevent the ions in the first thin film transistor 2 and the organic layer 31 from diffusing into the film layer of the second thin film transistor 4, thereby avoiding affecting the device electrical properties of the second thin film transistor 4.

[0053] The material of the first inorganic layer 32 includes SiN X Or SiO X The material of the second inorganic layer 33 includes SiN X Or SiO X The material of the first inorganic layer 32 and the material of the second inorganic layer 33 may be the same or different; the film thickness of the first inorganic layer 32 is set to The film thickness of the second inorganic layer 33 is set to

[0054] The present application does not impose any specific restrictions on the thickness of the organic layer 31. In one embodiment, in the thickness direction F1 of the drive substrate 100, the thickness H of the organic layer 31 is set to 1 μm to 2 μm. It is known that the thickness of the inorganic layer usually disposed between the first thin film transistor 2 and the second thin film transistor 4 is By disposing an organic layer 31 with a thickness of 1 μm to 2 μm between the first thin film transistor 2 and the second thin film transistor 4 , the distance between the first thin film transistor 2 and the second thin film transistor 4 can be increased.

[0055] See also Figure 2 In one embodiment, the second active layer 41 includes a second channel portion 411, and a second source contact portion 412 and a second drain contact portion 413 respectively arranged on both sides of the second channel portion 411; the second thin film transistor 4 also includes a second source 43, and the second source 43 is arranged on the side of the second gate 42 away from the barrier layer 3, and the second source 43 is electrically connected to the second source contact portion 412.

[0056] Specifically, the material of the second active layer 41 is set to be a semiconductor material, and the material of the second active layer 41 can be one of IGZO, IZTO and IGZTO. The film thickness of the second active layer 41 is set to The material of the second gate is set to be one of molybdenum, aluminum, copper, titanium and their alloys, and the film thickness of the second gate is set to The second source electrode 43 may be configured as a single metal film layer or a metal stacked structure. For example, the material of the second source electrode 43 is configured as Ti / Al / Ti, and the thickness of each film layer of the second source electrode 43 is respectively configured as It can be adjusted according to the actual product.

[0057] See also Figure 5 , Figure 7 and Figure 8 In the thickness direction F1 of the driving substrate 100, the second drain contact portion 413 at least partially overlaps with the first gate 22; the barrier layer 3 is provided with a first via hole 34, the first via hole 34 and the second drain contact portion 413 are arranged in alignment, and the second drain contact portion 413 is electrically connected to the first gate 22 through the first via hole 34.

[0058] Also, see Figure 6 , Fig. 9 and Fig.10 The driving substrate 100 also includes a second interlayer insulating layer 5, which is arranged on the side of the barrier layer 3 away from the substrate 1 and covers the second thin film transistor 4, and the second interlayer insulating layer 5 is provided with a second via hole 51, and the second via hole 51 is arranged in alignment with the second source 43; a third via hole 35 is arranged on the barrier layer 3, and the third via hole 35 is arranged in alignment with the second via hole 51; wherein the second source 43 is electrically connected to the first source 23 of the first thin film transistor 2 through the second via hole 51 and the third via hole 35 in sequence.

[0059] That is to say, the second drain contact 413 is electrically connected to the first gate 22 through the first via 34; the second source 43 is electrically connected to the first source 23 through the second via 51 and the third via 35 in sequence; thereby, the second thin film transistor 4 is electrically connected to the first thin film transistor 2.

[0060] Continuing from the above embodiment, the gate of the first thin film transistor a is electrically connected to the first node P, the source is electrically connected to the drain of the fourth thin film transistor d, and the drain is electrically connected to the second node Q; the drain of the second thin film transistor b is electrically connected to the first node P; the drain of the third thin film transistor c is electrically connected to the second node Q; the gate of the fourth thin film transistor d is connected to the En signal for activating each row of pixels row by row, and the source is connected to the power supply voltage (Vdd) signal; the second node Q is electrically connected to the anode of the OLED; the first via 34 forms the first node P.

[0061] It can be known that the first via 34, the second via 51 and the third via 35 are provided to electrically connect the second thin film transistor 4 with the first thin film transistor 2; however, the occupied area of ​​the thin film transistor will be increased. Therefore, compared with the tiling scheme of the prior art, the occupied area of ​​the stacked second thin film transistor 4 and the first thin film transistor 2 is reduced to 2 / 3 of that of the prior art; thereby, the pixel resolution can be increased to 1.5 times that of the prior art.

[0062] Specifically, the second interlayer insulating layer 5 includes a second gate insulating layer 52 and a second insulating layer 53; the second active layer 41 is arranged on the side of the barrier layer 3 away from the substrate 1; the second gate insulating layer 52 is arranged on the side of the barrier layer 3 away from the substrate 1 and covers the second active layer 41; the second gate 42 is arranged on the second gate insulating layer 52; the second insulating layer 53 is arranged on the second gate insulating layer 52 and covers the second gate 42; the second source 43 is arranged on the second insulating layer 53.

[0063] In one embodiment, the driving substrate 100 further includes a first interlayer insulating layer 8 , which is disposed on the substrate 1 , and covers the first thin film transistor 2 .

[0064] Specifically, the first interlayer insulating layer 8 includes a first gate insulating layer 81 and a first insulating layer 82; the second active layer 41 is arranged on the substrate 1; the first gate insulating layer 81 is arranged on the substrate 1 and covers the first active layer 21; the first gate 22 is arranged on the first gate insulating layer 81; the first insulating layer 82 is arranged on the first gate insulating layer 81 and covers the first gate 22; the first source 23 and the first drain 24 are arranged on the first insulating layer 82; the barrier layer 3 is arranged on the first insulating layer 82 and covers the first source 23 and the first drain 24.

[0065] In one embodiment, the driving substrate 100 further includes a buffer layer 9 , wherein the buffer layer 9 is disposed on one side of the substrate 1 , and the first thin film transistor 2 is disposed on a side of the buffer layer 9 away from the substrate 1 .

[0066] In one embodiment, see Figure 2The driving substrate 100 also includes a dielectric protection layer 6 and a pixel electrode 7; the dielectric protection layer 6 is arranged on the side of the barrier layer 3 away from the substrate 1 and covers the second thin film transistor 4, and the dielectric protection layer 6 is provided with a fourth via hole 61, and the fourth via hole 61 is aligned with the second drain contact portion 413; the pixel electrode 7 is arranged on the side of the dielectric protection layer 6 away from the second thin film transistor 4, and the pixel electrode 7 is electrically overlapped with the second drain contact portion 413 through the fourth via hole 61.

[0067] In one embodiment, the first active layer 21 includes a first channel portion 211, and a first source contact portion 212 and a first drain contact portion 213 respectively arranged on both sides of the first channel portion 211; the first thin film transistor 2 also includes a first source 23 and a first drain 24, the first source 23 and the first drain 24 are located on the side of the first gate 22 away from the substrate 1, and are electrically connected to the first source contact portion 212 and the first drain contact portion 213 respectively.

[0068] Specifically, the material of the first active layer 21 is a Si amorphous silicon material; the material of the first gate is set to be one of molybdenum, aluminum, copper, titanium and alloys thereof, and the film thickness of the first gate is set to The first source 23 and the first drain 24 can be set as a single metal film layer, or can be set as a metal stacking structure. For example, the material of the first source 23 and the first drain 24 is set to Ti / Al / Ti, and the thickness of each film layer of the second source 43 is set to It can be adjusted according to the actual product.

[0069] In one embodiment, the second active layer 41 includes a second channel portion 411, and a second source contact portion 412 and a second drain contact portion 413 respectively arranged on both sides of the second channel portion 411; in the thickness direction F1 of the driving substrate 100, the first gate 22 and the second gate 42 are staggered, and the orthographic projection of the second channel portion 411 on the substrate 1 is within the orthographic projection range of the first gate 22 on the substrate 1.

[0070] In this embodiment, the orthographic projection of the second channel portion 411 on the substrate 1 is set to be within the orthographic projection range of the first gate 22 on the substrate 1. The first gate 22 can serve as a shading portion for the second channel portion 411, and can block the light from the side of the substrate 1 to the second channel portion 411, thereby improving the stability of the second thin film transistor 4.

[0071] In the second aspect, the embodiment of the present application provides a display panel. The display panel includes a drive substrate 100; it should be noted that the drive substrate 100 is set as the above-mentioned drive substrate 100, that is, the drive substrate 100 includes all the technical features of the above-mentioned drive substrate 100, and the display panel includes all the embodiments of the above-mentioned drive substrate 100, and also has all the technical effects of the above-mentioned embodiments, which will not be described one by one here.

[0072] The driving substrate 100 can be configured as a flexible display substrate or a rigid display substrate. The display panel can be configured as a display panel of a display device; the display device can be configured as a wearable device, such as a smart bracelet, a smart watch, VR (Virtual Reality), etc., and can also be configured as an e-book, an e-newspaper, a television, a portable computer, and a foldable, rollable OLED flexible display and lighting.

[0073] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0074] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0075] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0076] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A driving substrate, characterized in that: include: substrate; a first thin film transistor, disposed on the substrate, comprising a first active layer and a first gate, wherein the first gate is located on a side of the first active layer away from the substrate; a barrier layer, disposed on the substrate and covering the first thin film transistor, wherein the barrier layer is configured as a stacked multi-layer structure, and the barrier layer at least includes an organic layer located in the middle layer; A second thin film transistor is arranged on a side of the barrier layer away from the substrate, the second thin film transistor is electrically connected to the first thin film transistor, the second thin film transistor includes a second active layer and a second gate, the second gate is located on a side of the second active layer away from the barrier layer, and in the thickness direction of the driving substrate, the second active layer and the first active layer are overlapped.

2. The driving substrate according to claim 1, wherein: The barrier layer also includes a first inorganic layer and a second inorganic layer. In the thickness direction of the driving substrate, the first inorganic layer, the organic layer and the second inorganic layer are stacked in sequence, the first inorganic layer covers the first thin film transistor, and the second thin film transistor is arranged on the side of the second inorganic layer away from the substrate.

3. The driving substrate according to claim 1, wherein: In the thickness direction of the driving substrate, the thickness of the organic layer is set to be 1 μm to 2 μm.

4. The driving substrate according to claim 1, wherein: The second active layer includes a second channel portion, and a second source contact portion and a second drain contact portion respectively disposed on both sides of the second channel portion; The second thin film transistor further includes a second source electrode, which is disposed on a side of the second gate electrode away from the barrier layer, and the second source electrode is electrically connected to the second source electrode contact portion.

5. The driving substrate according to claim 4, characterized in that: In the thickness direction of the driving substrate, the second drain contact portion at least partially overlaps with the first gate; The barrier layer is provided with a first via hole, the first via hole is aligned with the second drain contact portion, and the second drain contact portion is electrically connected to the first gate through the first via hole.

6. The driving substrate according to claim 4, wherein: The driving substrate further includes a second interlayer insulating layer, which is disposed on a side of the barrier layer away from the substrate and covers the second thin film transistor, and the second interlayer insulating layer is provided with a second via hole, which is aligned with the second source electrode; A third via hole is disposed on the barrier layer, and the third via hole is disposed in alignment with the second via hole; The second source is electrically connected to the first source of the first thin film transistor through the second via hole and the third via hole in sequence.

7. The driving substrate according to claim 4, wherein: The driving substrate further includes: a dielectric protection layer, disposed on a side of the barrier layer away from the substrate and covering the second thin film transistor, the dielectric protection layer being provided with a fourth via hole, the fourth via hole being aligned with the second drain contact portion; and, A pixel electrode is disposed on a side of the dielectric protection layer away from the second thin film transistor, and the pixel electrode is electrically connected to the second drain contact portion through the fourth via hole.

8. The driving substrate according to claim 1, wherein: The first active layer includes a first channel portion, and a first source contact portion and a first drain contact portion respectively disposed on both sides of the first channel portion; The first thin film transistor further includes a first source and a first drain, wherein the first source and the first drain are located on a side of the first gate away from the substrate and are electrically connected to the first source contact portion and the first drain contact portion respectively.

9. The driving substrate according to claim 1, wherein: The second active layer includes a second channel portion, and a second source contact portion and a second drain contact portion respectively disposed on both sides of the second channel portion; In the thickness direction of the driving substrate, the first gate and the second gate are staggered, and the orthographic projection of the second channel portion on the substrate is within the orthographic projection range of the first gate on the substrate.

10. A display panel, characterized in that: The drive substrate comprises the drive substrate as claimed in any one of claims 1 to 9.

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