Barrier-free memristor transistor and preparation method thereof
By adopting a memristor transistor with a barrier-free structure, using a simple physical mask and spin coating process, the problems of complex structure and cumbersome preparation process of the existing memristor transistor are solved, and a high-performance, easy-to-integrate memristor transistor is achieved, reducing cost and process complexity.
Patent Information
- Application Number
- CN202411890546.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-20
- Publication Date
- 2025-04-04
AI Technical Summary
The existing memristor transistor has complex structure and cumbersome preparation process, which leads to high costs and difficulty in large-scale integration.
Memristor transistors with barrier-free structures, including insulated or conductive substrates, solid dielectric layers and semiconductor thin film pattern layers, are prepared through simple processes such as physical masks and spin coating, simplifying the device structure and process flow.
It realizes high-performance, easy-to-integrate memristor transistors, reducing process complexity and cost, while improving the storage state and energy consumption performance of the device.
Smart Images
Figure CN119768042A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of electronic components, and in particular to a barrier-free memristor transistor and a preparation method thereof. Background Art
[0002] Memristors are the focus of research in the field of brain-like chips. They have a simple structure and have important application prospects in the field of neuromorphic computing. Among them, memristor transistors, as a derivative structure of memristors, are new semiconductor devices that combine the characteristics of memristors and transistors. They not only have the non-volatile storage function of memristors, but can also perform signal amplification and switching operations like transistors.
[0003] At present, most memristor transistor structures still use the traditional MOSFET structure, which has great defects in large-scale device integration. The same is true for the manufacturing process, which also uses traditional manufacturing processes, such as photolithography. As a result, the device manufacturing process is particularly cumbersome, and its cost and process complexity cannot meet expectations.
[0004] Therefore, how to select a simple process and structure to prepare a high-performance, easily integrated memristor transistor is a problem that needs to be solved. Summary of the invention
[0005] The main purpose of the present invention is to provide a barrier-free memristor transistor and a preparation method thereof to solve the above technical problems.
[0006] To achieve the above object, the present invention provides a barrier-free memristor transistor, comprising:
[0007] A substrate layer, wherein the substrate layer is an insulating substrate or a conductive substrate;
[0008] a solid dielectric layer, the solid dielectric layer; and
[0009] Semiconductor thin film pattern layer;
[0010] Among them, when the substrate layer is an insulating substrate, the semiconductor thin film pattern layer is deposited on the substrate layer by means of a physical mask, and the solid dielectric layer partially covers the semiconductor thin film pattern layer and the gaps therein; when the substrate layer is a conductive substrate, the solid dielectric layer is coated on the substrate layer, and the semiconductor thin film pattern layer is deposited on the solid dielectric layer by means of a physical mask.
[0011] Preferably, the insulating substrate is an insulating silicon substrate, and the conductive substrate is a FTO conductive glass substrate.
[0012] Preferably, the solid dielectric layer partially covers the semiconductor thin film pattern layer and the gaps therein by drop coating; or, the solid dielectric layer is coated on the substrate layer by spin coating.
[0013] Preferably, the semiconductor thin film pattern layer is a thin film pattern layer formed by a doped semiconductor material, for example, a highly doped semiconductor material, ITO or AZO, etc.
[0014] Preferably, when the substrate layer is an insulating substrate, part of the pattern in the semiconductor thin film pattern layer of the barrierless memristor transistor serves as a side gate; when the substrate layer is a conductive substrate, the semiconductor thin film pattern layer of the barrierless memristor transistor serves as a source, a channel layer, and a drain, and the conductive substrate serves as a bottom gate.
[0015] Preferably, the thickness of the substrate layer is 625±10 microns; the thickness of the semiconductor thin film pattern layer is 10-15 nanometers, and the pattern size is 10-20 nanometers; the thickness of the solid dielectric layer is 10-20 microns.
[0016] The present invention also provides a method for preparing a barrier-free memristor transistor as described in any one of the above items, comprising the steps of:
[0017] S1, providing a substrate and cleaning the substrate;
[0018] S2, providing a dielectric solution for the dielectric layer;
[0019] S3, provides designed mask and heavily doped semiconductor materials;
[0020] S41, when the substrate is an insulating substrate, depositing a heavily doped semiconductor material on the substrate layer by using a radio frequency magnetron sputtering apparatus and a mask to form the semiconductor thin film pattern layer, and partially coating the dielectric solution on the semiconductor thin film pattern layer and gaps therein to form the solid dielectric layer;
[0021] S42, when the substrate is a conductive substrate, coating the dielectric solution on the substrate layer to form the solid dielectric layer, and depositing the heavily doped semiconductor material on the solid dielectric layer through a radio frequency magnetron sputtering apparatus and a mask to form the semiconductor thin film pattern layer.
[0022] Preferably, in the step S41 or S42, after the dielectric solution is applied, heating is performed at 35-40°C to form a solid dielectric.
[0023] Preferably, the step S41 or S42 further includes a step of annealing the prepared device, wherein the annealing temperature is 180-220°C.
[0024] Preferably, the solid dielectric layer is chitosan, PVA, sodium alginate solution or high-K polymer dielectric.
[0025] The barrier-free memristor in the present invention does not require source and drain electrodes. The source, channel layer and drain are all formed by heavily doped semiconductor thin film pattern materials, which greatly simplifies the preparation process and reduces the process cost. It is also possible to drip ionic liquid and other materials between the semiconductor thin film patterns to form a solid gate dielectric, and cooperate with a conductive substrate or a doped silicon substrate to form a bottom-gate or side-gate memristor to regulate the current. Compared with the memristor in the prior art, the present invention has at least the following beneficial effects:
[0026] (1) Barrier-less memristor transistors do not have traditional source-drain junctions and are similar in structure to two-terminal devices, but their performance and adjustability have been greatly improved, such as storage state and energy consumption, and they are extremely easy to integrate over a large area.
[0027] (2) Based on the improvement of the structure, the complexity and cost of the device preparation process have been greatly improved, and it can be prepared only through simple physical masking, spin coating and other methods.
[0028] (3) It has a variety of device structures, such as bottom gate structure, top gate structure, and side gate structure, and the processing technology of each structure is simple. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] The accompanying drawings are part of the present invention and are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention, but do not constitute an improper limitation of the present invention. Obviously, the drawings described below are only some embodiments. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the accompanying drawings:
[0030] Figure 1 Flow chart of a method for preparing a barrier-free memristor transistor in one embodiment of the present invention.
[0031] Figure 2 2a is a schematic diagram of the preparation process of the barrierless memristor transistor of an embodiment of the present invention, wherein 2b is a schematic diagram of the preparation process of the barrierless memristor transistor controlled by the bottom gate, and 2a is a schematic diagram of the preparation process of the barrierless memristor transistor controlled by the side gate.
[0032] Figure 3 Graph showing the transfer curve of the barrier-free memristor transistor prepared in this embodiment.
[0033] Figure 4 This is the control curve of the barrier-free memristor. DETAILED DESCRIPTION
[0034] The following is a clear and complete description of the technical problems solved by the embodiments of the present invention, the technical solutions adopted, and the technical effects achieved in conjunction with the accompanying drawings and specific embodiments. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other equivalent or obviously modified embodiments obtained by ordinary technicians in this field without creative work fall within the scope of protection of the present invention. The embodiments of the present invention can be concretized in a variety of different ways as defined and covered in the claims.
[0035] It should be noted that in the following description, many specific details are given for ease of understanding, but it is obvious that the present invention can be implemented without these specific details.
[0036] It should be noted that, in the absence of clear limitation or conflict, the various embodiments of the present invention and the technical features therein can be combined with each other to form a technical solution.
[0037] This embodiment provides a barrier-free memristor transistor, including:
[0038] A substrate layer, wherein the substrate layer is an insulating substrate or a conductive substrate;
[0039] a solid dielectric layer, the solid dielectric layer; and
[0040] Semiconductor thin film pattern layer.
[0041] Please combine Figure 2 a. When the substrate layer is an insulating substrate, the semiconductor film pattern layer is deposited on the substrate layer by means of a physical mask, and the solid dielectric layer partially covers the semiconductor film pattern layer and its gaps. Part of the pattern in the semiconductor film pattern layer of the barrier-free memristor transistor serves as a side gate. Specifically, in a barrier-free memristor transistor, the semiconductor films on the left and right sides serve as the gates of the device, and the semiconductor film in the middle serves as the source / channel layer / drain of the device, so that the characteristics of the memristor can be modulated through the gates on both sides.
[0042] It should be noted that the solid dielectric layer partially covers the semiconductor film pattern layer and the gaps therein, so that the semiconductor film is not completely covered, which makes it easy to test the connection at the source, drain and gate.
[0043] Please combine Figure 2 b. When the substrate layer is a conductive substrate, the solid dielectric layer is coated on the substrate layer, and the semiconductor thin film pattern layer is deposited on the solid dielectric layer by means of a physical mask. The semiconductor thin film pattern layer of the barrier-free memristor transistor serves as the source, channel layer, and drain, and the conductive substrate serves as the bottom gate.
[0044] In the traditional MOSFET transistor structure, the traditional silicon dioxide gate dielectric transistor usually has a high threshold voltage, resulting in high power consumption. In the double-layer transistor, equal and opposite charges are distributed on both sides of the electrode and dielectric interface, forming a structure similar to a traditional flat capacitor, that is, a double-layer capacitor. This makes it possible to generate a high carrier density in the channel at a low operating voltage, thereby achieving low-voltage TFT operation. The barrier-free memristor in this embodiment uses the characteristics of the memristor regulated by the double-layer to achieve a large-capacitance, low-power memristor. Figure 2 The device in b is a bottom-gate controlled barrier-free memristor transistor, which is controlled by a conductive substrate as the gate. It does not require source and drain electrodes. The source, channel layer, and drain are all heavily doped semiconductor thin film materials, which greatly simplifies the preparation process and reduces the process cost. Figure 2 As shown in a, by using an insulating substrate, ionic liquid and other materials are dripped between semiconductor film patterns to form a solid gate dielectric, and the solid dielectric layer partially covers the semiconductor film pattern layer and the gaps therein. In a barrier-free memristor transistor, the semiconductor films on the left and right sides serve as the gates of the device, and the semiconductor film in the middle serves as the source / channel layer / drain of the device, so that the characteristics of the memristor can be modulated through the gates on both sides.
[0045] Preferably, the insulating substrate is an insulating silicon substrate, and the conductive substrate is a FTO conductive glass substrate.
[0046] Preferably, the solid dielectric layer partially covers the semiconductor thin film pattern layer and the gaps therein by drop coating; or, the solid dielectric layer is coated on the substrate layer by spin coating.
[0047] Preferably, the semiconductor thin film pattern layer is ITO or AZO.
[0048] Preferably, the thickness of the substrate layer is 625±10 microns; the thickness of the semiconductor thin film pattern layer is 10-15 nanometers, and the pattern size is 10-20 nanometers; the thickness of the solid dielectric layer is 10-20 microns.
[0049] Preferably, the solid dielectric layer is chitosan, PVA, sodium alginate solution or high-K polymer dielectric
[0050] The present invention also provides a method for preparing a barrier-free memristor transistor as described in any one of the above items, comprising the steps of:
[0051] S1, providing a substrate and cleaning the substrate;
[0052] S2, providing a dielectric solution for the dielectric layer;
[0053] S3, providing designed mask and doped semiconductor materials;
[0054] S41, when the substrate is an insulating substrate, depositing a heavily doped semiconductor material on the substrate layer by using a radio frequency magnetron sputtering apparatus and a mask to form the semiconductor thin film pattern layer, and partially coating the dielectric solution on the semiconductor thin film pattern layer and gaps therein to form the solid dielectric layer;
[0055] S42, when the substrate is a conductive substrate, coating the dielectric solution on the substrate layer to form the solid dielectric layer, and depositing the heavily doped semiconductor material on the solid dielectric layer through a radio frequency magnetron sputtering apparatus and a mask to form the semiconductor thin film pattern layer.
[0056] Preferably, in step S1, cleaning the substrate comprises ultrasonic cleaning for more than 10 minutes using acetone, alcohol, and deionized water respectively.
[0057] Preferably, in the step S41 or S42, after the dielectric solution is applied, heating is performed at 35-40°C to form a solid dielectric.
[0058] Preferably, the step S41 or S42 further includes a step of annealing the prepared device, wherein the annealing temperature is 180-220°C, preferably 200°C.
[0059] Preferably, the dielectric solution is chitosan, PVA or sodium alginate solution.
[0060] Preferably, the insulating substrate is an insulating silicon substrate, and the conductive substrate is a FTO conductive glass substrate.
[0061] Preferably, in step S41, the solid dielectric layer partially covers the semiconductor thin film pattern layer and the gaps therein by drop coating.
[0062] Preferably, in step S42, the solid dielectric layer is coated on the substrate layer by spin coating.
[0063] Preferably, the semiconductor thin film pattern layer is a thin film pattern layer formed by doping semiconductor materials, for example, highly doped semiconductor materials, such as ITO or AZO.
[0064] The following is a specific example experiment to illustrate the application Figure 2 The electrical performance of the barrier-free memristor transistor (taking ionic solid-state dielectric as an example) with a side-gate control structure in a.
[0065] The preparation steps of barrier-free memristor transistor include:
[0066] Mix 20 ml of 2 wt% acetic acid and 0.4 g of chitosan to prepare a chitosan ionic liquid solution with a concentration of 2 wt%;
[0067] The prepared insulating silicon substrate with a thickness of 62.5 μm was cleaned by ultrasonic cleaning with acetone, alcohol, and deionized water for 15 min respectively;
[0068] Align the cleaned substrate and the mask with designed pattern and place them into the RF magnetron sputtering device to deposit a heavily doped semiconductor film (ITO) of about 10 nanometers;
[0069] Apply the configured ion liquid droplets to the semiconductor film and the gaps between them, but be careful not to cover the entire semiconductor film, so that it is easy to test the connection at the source, drain and gate;
[0070] It is then heated (37°C) to form a solid dielectric, which is used as the gate dielectric of the device;
[0071] The prepared device was annealed at 200°C to obtain Figure 2 The barrier-free memristor transistor with side-gate control structure in a.
[0072] like Figure 3 , is the transfer curve diagram of the barrier-free memristor transistor prepared in this embodiment, Figure 4 It is a control curve diagram of the barrier-free memristor transistor. It can be seen from the figure that the barrier-free memristor transistor prepared by the method of this embodiment has good gate control performance, and has the characteristics of low power consumption and large capacity.
[0073] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.
Claims
1. A barrier-free memristor transistor, characterized in that: include: A substrate layer, wherein the substrate layer is an insulating substrate or a conductive substrate; a solid dielectric layer, the solid dielectric layer; as well as Semiconductor thin film pattern layer; Among them, when the substrate layer is an insulating substrate, the semiconductor thin film pattern layer is deposited on the substrate layer by means of a physical mask, and the solid dielectric layer partially covers the semiconductor thin film pattern layer and the gaps therein; when the substrate layer is a conductive substrate, the solid dielectric layer is coated on the substrate layer, and the semiconductor thin film pattern layer is deposited on the solid dielectric layer by means of a physical mask.
2. The barrier-free memristor according to claim 1, characterized in that: The insulating substrate is an insulating silicon substrate, and the conductive substrate is a FTO conductive glass substrate.
3. The barrier-free memristor according to claim 1, characterized in that: The solid dielectric layer partially covers the semiconductor thin film pattern layer and the gaps therein by drop coating; or, the solid dielectric layer is coated on the substrate layer by spin coating.
4. The barrier-free memristor according to claim 3, characterized in that: The semiconductor thin film pattern layer is a thin film pattern layer formed by doping semiconductor materials.
5. The barrier-free memristor according to claim 1, characterized in that: When the substrate layer is an insulating substrate, part of the pattern in the semiconductor thin film pattern layer of the barrier-free memristor transistor serves as a side gate; when the substrate layer is a conductive substrate, the semiconductor thin film pattern layer of the barrier-free memristor transistor serves as a source, a channel layer, and a drain, and the conductive substrate serves as a bottom gate.
6. The barrier-free memristor according to claim 1, characterized in that: The thickness of the substrate layer is 625±10 microns; the thickness of the semiconductor thin film pattern layer is 10-15 nanometers, and the pattern size is 10-20 nanometers; the thickness of the solid dielectric layer is 10-20 microns.
7. A method for preparing a barrier-free memristor transistor according to any one of claims 1 to 5, characterized in that: Includes steps: S1, providing a substrate and cleaning the substrate; S2, providing a solid dielectric layer dielectric solution; S3, providing designed mask and doped semiconductor materials; S41, when the substrate is an insulating substrate, depositing a heavily doped semiconductor material on the substrate layer by using a radio frequency magnetron sputtering apparatus and a mask to form the semiconductor thin film pattern layer, and partially coating the dielectric solution on the semiconductor thin film pattern layer and gaps therein to form the solid dielectric layer; S42, when the substrate is a conductive substrate, coating the dielectric solution on the substrate layer to form the solid dielectric layer, and depositing the heavily doped semiconductor material on the solid dielectric layer through a radio frequency magnetron sputtering apparatus and a mask to form the semiconductor thin film pattern layer.
8. The method for preparing a barrier-free memristor according to claim 7, characterized in that: In the step S41 or S42, after the dielectric solution is applied, heating is performed at 35-40°C to form a solid dielectric.
9. The method for preparing a barrier-free memristor according to claim 7, characterized in that: The step S41 or S42 further includes a step of annealing the prepared device, wherein the annealing temperature is 180-220°C.
10. The method for preparing a barrier-free memristor according to claim 7, characterized in that: The solid dielectric layer is chitosan, PVA, sodium alginate solution or high-K polymer dielectric.