A method for controlling silicon thickness of MEMS cavity structure

Abstract

The present invention discloses a method for controlling the silicon thickness of a MEMS cavity structure, comprising the following steps: S1, depositing a dielectric layer on a silicon substrate, and using photolithography and etching to form a patterned mask; S2, based on the mask opening position, by wet etching, according to the thickness of the silicon substrate to be etched, that is, the target silicon thickness, the estimated etching time is calculated; S3, adding excess etching time to form a MEMS cavity; the excess etching time is greater than the estimated etching time and less than the time to completely etch through the silicon substrate; S4, measuring the actual silicon thickness at the cavity, and growing crystalline silicon by epitaxial growth technology to compensate for the over-etched thickness to achieve the target silicon thickness requirement. The present invention eliminates the influence of the deviation of the silicon thickness that can only be controlled by controlling the time in wet etching. The device structure is not damaged, so that the final silicon thickness becomes more accurate and controllable, and the existing equipment on the process line is used to expand the existing process capabilities and ensure that the wafer output rate becomes higher.

Description

Technical Field

[0001] The invention relates to the field of MEMS pressure sensors, and in particular to a method for controlling silicon thickness of a MEMS cavity structure. Background Art

[0002] MEMS pressure sensors are widely used in the automotive industry / medical equipment / Internet of Things and other fields. The current MEMS pressure sensors require the preparation of a certain cavity structure. The existing method of controlling the silicon thickness of the cavity structure is relatively simple, that is, through wet etching, where the etching liquids include KOH and TMAH. Different etching liquids have different corrosion rates at different temperatures. In the actual operation process, it is necessary to accurately control the temperature, collect the corrosion rate, and calculate the operation time through the thickness and rate.

[0003] like Figure 1 , the traditional MEMS cavity is to complete the etching of the entire deep cavity structure during the etching stage. This long-term etching of silicon stops at the silicon layer and it is difficult to accurately control the remaining silicon thickness. Therefore, the etching and stopping of silicon are not controllable, so the final result can only be obtained by controlling the time. The tolerance rate for deviations in the etching process is too small, it is difficult to accurately control the silicon thickness, and the wafer qualification rate is low. Therefore, how to accurately control the silicon thickness at the cavity silicon stress film is a technical problem that needs to be solved urgently. Summary of the invention

[0004] In order to solve the existing problems, the present invention provides a method for controlling the silicon thickness of a MEMS cavity structure, and the specific scheme is as follows:

[0005] A method for controlling the silicon thickness of a MEMS cavity structure comprises the following steps:

[0006] S1, depositing a dielectric layer on a silicon substrate, and forming a patterned mask using photolithography and etching;

[0007] S2, based on the mask opening position, by wet etching, according to the thickness of the silicon substrate to be etched, i.e., the target silicon thickness, the estimated etching time is calculated;

[0008] S3, adding excess etching time to form a MEMS cavity; the excess etching time is greater than the expected etching time and less than the time required to completely etch through the silicon substrate.

[0009] S4, measures the actual silicon thickness at the cavity, and grows crystalline silicon through epitaxial growth technology to compensate for the over-etched thickness to achieve the target silicon thickness requirement.

[0010] Preferably, the dielectric layer in step S1 is a silicon dioxide layer or a silicon nitride layer.

[0011] Preferably, the etching solution used for the wet etching in step S2 is potassium hydroxide and tetramethylammonium hydroxide.

[0012] Preferably, the epitaxial growth technique in step S4 is to dissociate or hydrogen-reduce a silicon-containing source gas at high temperature in a vapor phase chemical deposition reactor, wherein the silicon-containing source gas comprises silane, dichlorosilane or silicon tetrachloride.

[0013] Preferably, the epitaxial growth technology in step S4 is a homoepitaxial growth technology, and the grown epitaxial layer and the substrate layer have the same lattice structure.

[0014] The present invention also discloses a computer-readable storage medium, on which a computer program is stored. After the computer program is run, any of the above-mentioned methods is executed.

[0015] The present invention also discloses a computer system, including a processor and a storage medium, wherein a computer program is stored on the storage medium, and the processor reads and runs the computer program from the storage medium to execute any of the methods described above.

[0016] The beneficial effects of the present invention are:

[0017] The present invention lengthens the etching time during the wet etching of the silicon substrate to achieve over-etching, so that the remaining silicon thickness in the cavity is lower than the target value, and then compensates for the thickness difference through epitaxy technology to reach the target value, eliminating the influence of the deviation of the silicon thickness that can only be controlled by controlling the time during wet etching. The device structure is not damaged, and the final silicon thickness becomes more accurately controllable. In addition, the existing equipment on the process line is used to expand the existing process capabilities and ensure a higher wafer output rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 It is a cross-sectional view of the traditional MEMS cavity structure;

[0020] Figure 2 It is a cross-sectional view of the MEMS cavity structure of the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] Example:

[0023] A method for controlling the silicon thickness of a MEMS cavity structure comprises the following steps:

[0024] S1, depositing a dielectric layer on a silicon substrate, and using photolithography and etching to form a patterned mask; the dielectric layer is a silicon dioxide layer or a silicon nitride layer to prevent corrosion by a wet etching solution.

[0025] S2, based on the mask opening position, by wet etching, according to the thickness of the silicon substrate to be etched, that is, the target silicon thickness, the estimated etching time is calculated; the etching solution used in the wet etching is potassium hydroxide and tetramethylammonium hydroxide.

[0026] Specifically, based on the mask opening position, the MEMS cavity is formed by etching silicon with an alkaline etching solution (KOH or TMAH), which prolongs the expected etching time; assuming that the substrate Si thickness is 300μm, the silicon thickness at the deep cavity position needs to remain at 10μm, and the deep cavity etching adopts KOH etching, the KOH etching rate is 23μm / h, and the time required to etch 290μm is 12.6 hours.

[0027] S3, adding excessive etching time to form a MEMS cavity; the excessive etching time is greater than the expected etching time and less than the time to completely etch through the silicon substrate. Specifically, the thickness specification of this over-etching is greater than 1um and less than 5um, and the over-etching time is 2.6 minutes to 13 minutes. When the expected time is extended by 8.5 minutes, the dual effects of actual deviation and over-etching will make the actual silicon thickness less than the target value.

[0028] S4, measuring the actual silicon thickness at the cavity, and growing crystalline silicon by epitaxial growth technology to compensate for the over-etched thickness, so as to achieve the target silicon thickness requirement. The epitaxial growth technology is to dissociate or hydrogen-reduce a silicon-containing source gas at high temperature in a gas phase chemical deposition reactor, and the silicon-containing source gas includes silane, dichlorosilane or silicon tetrachloride. The epitaxial growth technology is a homogeneous epitaxial technology, and the grown epitaxial layer and the substrate layer have the same lattice structure.

[0029] Specifically, the final silicon thickness at the cavity is measured, and the difference between the actual thickness and the target value is calculated. 3.26μm silicon compensation is required to grow crystalline silicon to the target thickness through epitaxial technology. The epitaxial compensation growth technology is a homogeneous epitaxial technology. The grown epitaxial layer has the same lattice structure as the substrate layer. For example, epitaxial technology is used to grow the crystal orientation <100> The growth rate is 1.65μm / min, and the operation time is 2min. The lattice after epitaxial growth is consistent with the cavity silicon lattice after etching, and the film thickness is more accurately controllable than the single silicon etching method.

[0030] The present invention lengthens the etching time during the wet etching of the silicon substrate to achieve over-etching, so that the remaining silicon thickness in the cavity is lower than the target value, and then compensates for the thickness difference through epitaxy technology to reach the target value, eliminating the influence of the deviation of the silicon thickness that can only be controlled by controlling the time during wet etching. The device structure is not damaged, and the final silicon thickness becomes more accurately controllable. In addition, the existing equipment on the process line is used to expand the existing process capabilities and ensure a higher wafer output rate.

[0031] The present invention also discloses a computer-readable storage medium and a computer system, wherein a computer program is stored on the computer storage medium, and after the computer program is run, any of the above methods is executed. A computer system includes a processor and a storage medium, wherein the computer program is stored on the storage medium, and the processor reads and runs the computer program from the storage medium to execute any of the above methods.

[0032] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithm steps described in conjunction with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or a combination of the two. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps are generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. The technician may implement the described functionality in different ways for each specific application, but such implementation decisions should not be interpreted as resulting in a departure from the scope of the present invention.

[0033] The various illustrative logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or executed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in cooperation with a DSP core, or any other such configuration.

[0034] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read and write information from / to the storage medium. In an alternative, a storage medium may be integrated into a processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In an alternative, the processor and the storage medium may reside in a user terminal as discrete components.

[0035] In one or more exemplary embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented as a computer program product in software, each function may be stored on or transmitted by a computer-readable medium as one or more instructions or codes. Computer-readable media include both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another. Storage media may be any available medium that can be accessed by a computer. As an example and not limitation, such a computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of an instruction or data structure and can be accessed by a computer. Any connection is also properly referred to as a computer-readable medium. For example, if the software is transmitted from a website, a server, or other remote source using a coaxial cable, a fiber optic cable, a twisted pair, a digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves, the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of the medium. Disk and disc as used herein include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, wherein disk often reproduces data magnetically, while disc reproduces data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0036] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but should be granted the widest scope consistent with the principles and novel features disclosed herein.

[0037] Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent substitutions for some of the technical features therein; and these modifications or substitutions do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for controlling the silicon thickness of a MEMS cavity structure, characterized in that: The following steps are involved: S1, depositing a dielectric layer on a silicon substrate, and forming a patterned mask using photolithography and etching; S2, based on the mask opening position, by wet etching, according to the thickness of the silicon substrate to be etched, i.e., the target silicon thickness, the estimated etching time is calculated; S3, adding an excess etching time to form a MEMS cavity; the excess etching time is greater than the expected etching time and less than the time for completely etching through the silicon substrate; S4, measures the actual silicon thickness at the cavity, and grows crystalline silicon through epitaxial growth technology to compensate for the over-etched thickness to achieve the target silicon thickness requirement.

2. The method according to claim 1, characterized in that: In step S1, the dielectric layer is a silicon dioxide layer or a silicon nitride layer.

3. The method according to claim 1, characterized in that: The etching solution used for the wet etching in step S2 is potassium hydroxide and tetramethylammonium hydroxide.

4. The method according to claim 1, characterized in that: The epitaxial growth technology in step S4 is to dissociate or hydrogen-reduce a silicon-containing source gas at a high temperature in a vapor phase chemical deposition reactor, wherein the silicon-containing source gas includes silane, dichlorosilane or silicon tetrachloride.

5. The method according to claim 1 or 4, characterized in that: The epitaxial growth technology in step S4 is a homoepitaxial growth technology, and the grown epitaxial layer and the substrate layer have the same lattice structure.

6. A computer-readable storage medium, characterized in that: A computer program is stored on the medium, and after the computer program is run, the method according to any one of claims 1 to 5 is executed.

7. A computer system, characterized in that: The method comprises a processor and a storage medium, wherein a computer program is stored in the storage medium, and the processor reads and runs the computer program from the storage medium to execute the method as claimed in any one of claims 1 to 5.

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