Photoetching imaging simulation method and device, storage medium and electronic equipment

Abstract

The invention discloses a photoetching imaging simulation method and device, a storage medium and electronic equipment, and the method comprises the steps: obtaining a first simulation region of a wafer; decomposing the simulation area into a plurality of first sub-areas based on the surface topography characteristics of the wafer; extracting first electric field information of the first sub-region from the electric field lookup table; performing electric field superposition processing and redundancy elimination processing on the plurality of pieces of first electric field information to obtain second electric field information of the first simulation area; and calculating an optical imaging result of the target mask pattern based on the optical system parameters and the second electric field information. According to the scheme, the efficiency of photoetching imaging simulation can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of photolithography technology, and specifically to a photolithography imaging simulation method, device, storage medium and electronic device. Background Art

[0002] In modern semiconductor manufacturing, wafer topography has an important impact on the imaging effect of the lithography process. As the process node continues to shrink, the optical effects caused by the complex structure on the wafer surface have increased significantly, such as print bias and hotspots. These effects will cause deviations between the mask design size and the actual pattern size, reduce the tolerance range of the lithography process window, and cause local imaging quality problems, thereby affecting the yield of wafer manufacturing.

[0003] Existing electromagnetic field simulation technologies, such as the finite difference time domain method (FDTD) and rigorous coupled wave analysis (RCWA), require huge amounts of computation when dealing with complex wafer topography, making it difficult to quickly and accurately evaluate these effects, which seriously affects the efficiency of lithography imaging simulation. Summary of the invention

[0004] The embodiments of the present application provide a lithography imaging simulation method, device, storage medium and electronic device, which can improve the efficiency of lithography imaging simulation.

[0005] In a first aspect, an embodiment of the present application provides a lithography imaging simulation method, comprising: Acquire a first simulation region of a wafer; Based on the surface morphology characteristics of the wafer, the simulation region is decomposed into a plurality of first sub-regions; Extracting first electric field information of the first sub-region from an electric field lookup table; Performing electric field superposition processing and redundancy removal processing on a plurality of the first electric field information to obtain second electric field information of the first simulation area; Based on the optical system parameters and the second electric field information, an optical imaging result of the target mask pattern is calculated.

[0006] In the lithography imaging simulation method provided in the embodiment of the present application, before determining the simulation area of ​​the semiconductor wafer, the method further includes: Construct the electric field lookup table.

[0007] In the lithography imaging simulation method provided in the embodiment of the present application, the step of constructing an electric field lookup table includes: Acquire a plurality of second simulation areas; Based on the surface morphology characteristics of the wafer, decomposing the corresponding second simulation area into a plurality of second sub-areas; An electric field lookup table is constructed based on the third electric field information of each of the second sub-regions.

[0008] In the lithography imaging simulation method provided in the embodiment of the present application, the constructing of the electric field lookup table based on the third electric field information of each second sub-region includes: decomposing each of the second sub-regions into a plurality of first boundary line segments; The fourth electric field information of each of the first boundary line segments is calculated using a preset electromagnetic field algorithm, and an electric field lookup table is generated based on the fourth electric field information.

[0009] In the lithography imaging simulation method provided in an embodiment of the present application, extracting the first electric field information of the first sub-region from the electric field lookup table includes: dividing the first sub-region into a plurality of second boundary line segments; Based on the second boundary line segment, corresponding fifth electric field information is extracted from the electric field lookup table.

[0010] In the lithography imaging simulation method provided in the embodiment of the present application, the performing electric field superposition processing and redundancy removal processing on the plurality of first electric field information to obtain the second electric field information of the first simulation area includes: Performing electric field superposition processing and redundancy removal processing on a plurality of fifth electric field information of each first sub-region to obtain first electric field information of each first sub-region; Electric field superposition processing and redundancy removal processing are performed on a plurality of the first electric field information to obtain second electric field information of the first simulation area.

[0011] In the lithography imaging simulation method provided in the embodiment of the present application, the performing electric field superposition processing and redundancy removal processing on the plurality of first electric field information to obtain the second electric field information of the first simulation area includes: Perform electric field superposition processing and redundancy removal processing on a plurality of the fifth electric field information to obtain the second electric field information of the first simulation area.

[0012] In a second aspect, an embodiment of the present application provides a lithography imaging simulation device, comprising: A determination unit, configured to obtain a first simulation region of a wafer; A decomposition unit, configured to decompose the simulation region into a plurality of first sub-regions based on the surface morphology characteristics of the wafer; A search unit, configured to extract the first electric field information of the first sub-region from an electric field lookup table; a superposition unit, configured to perform electric field superposition processing and redundancy removal processing on a plurality of the first electric field information to obtain second electric field information of the first simulation area; A calculation unit is used to calculate the optical imaging result of the target mask pattern based on the optical system parameters and the second electric field information.

[0013] In a third aspect, the present application provides a storage medium storing a plurality of instructions, wherein the instructions are suitable for loading by a processor to execute any of the above-mentioned lithography imaging simulation methods.

[0014] In a fourth aspect, the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the above-mentioned lithography imaging simulation methods when executing the computer program.

[0015] In summary, the lithography imaging simulation method provided by the embodiment of the present application includes obtaining a first simulation area of ​​a wafer; decomposing the simulation area into a plurality of first sub-areas based on the surface morphology characteristics of the wafer; extracting first electric field information of the first sub-areas from an electric field lookup table; performing electric field superposition processing and de-redundancy processing on the plurality of first electric field information to obtain second electric field information of the first simulation area; and calculating the optical imaging result of the target mask pattern based on the optical system parameters and the second electric field information. This solution reduces the real-time calculation complexity and improves the efficiency of lithography imaging simulation by decomposing the simulation area into a plurality of sub-areas and using a lookup table to search for the electric field information of the sub-areas. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 It is a schematic diagram of an application scenario of the lithography imaging simulation method provided in an embodiment of the present application.

[0018] Figure 2 It is a flow chart of the lithography imaging simulation method provided in an embodiment of the present application.

[0019] Figure 3 It is a schematic diagram of electric field superposition processing and redundancy removal processing of electric field information provided in an embodiment of the present application.

[0020] Figure 4 It is another schematic diagram of the electric field superposition processing and de-redundancy processing of the electric field information provided in an embodiment of the present application.

[0021] Figure 5 It is a structural schematic diagram of the lithography imaging simulation device provided in an embodiment of the present application.

[0022] Figure 6 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0024] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0025] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0026] In the subsequent description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present application, and have no specific meanings. Therefore, "module", "component" or "unit" can be used in a mixed manner.

[0027] In the description of the present application, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, terms such as "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0028] Existing electromagnetic field simulation technologies, such as electromagnetic wave finite-difference time-domain method and rigorous coupled wave analysis, have huge computational complexity when dealing with complex chip topography, making it difficult to quickly and accurately evaluate these effects, which seriously affects the efficiency of lithography imaging simulation.

[0029] Based on this, the embodiments of the present application provide a lithography imaging simulation method, device, storage medium and electronic device. Specifically, the lithography imaging simulation device can be integrated in an electronic device, and the electronic device can be a server or a terminal. Among them, the terminal can include a mobile phone, a wearable smart device, a tablet computer, a laptop computer, and a personal computer (PC), etc.; the server can be a single server or a server cluster composed of multiple servers, and can be a physical server or a virtual server.

[0030] For example, Figure 1 As shown, after acquiring the first simulation area of ​​the chip, the electronic device decomposes the simulation area into several first sub-areas based on the surface morphology characteristics of the chip; then extracts the first electric field information of the first sub-area from the electric field lookup table; then performs electric field superposition processing and de-redundancy processing on the several first electric field information to obtain the second electric field information of the first simulation area; finally, based on the optical system parameters and the second electric field information, calculates the optical imaging result of the target mask pattern.

[0031] The technical solutions shown in the present application will be described in detail below through specific embodiments. It should be noted that the description order of the following embodiments is not intended to limit the priority order of the embodiments.

[0032] See also Figure 2 , Figure 2 : is a schematic diagram of the process of the lithography imaging simulation method provided in the embodiment of the present application. The specific process of the lithography imaging simulation method can be as follows: 101. Obtain a first simulation region of a wafer.

[0033] The chip refers to a semiconductor chip. The first simulation area refers to an area on the semiconductor chip where a photolithography process is to be performed. The first simulation area may be obtained by user input, automatic system recognition, or pre-setting. For example, the user may input information such as the chip model, size, and location of the area to be simulated, and the system may automatically determine the first simulation area; or the system may pre-store simulation area information of multiple chips, and the user only needs to select the corresponding chip model, and the system may automatically obtain the corresponding first simulation area.

[0034] 102. Based on the surface morphology characteristics of the wafer, decompose the simulation region into a plurality of first sub-regions.

[0035] It is understandable that when forming a wafer, the ion implantation process, the photolithography process and the double exposure technology will cause the morphology of the wafer surface deposited inside the photoresist to change, such as the surface morphology characteristics of the plane, protrusion, depression, etc. For example, as the feature size of semiconductor devices decreases, in the multi-layer photolithography process, the photoresist will produce a chemical reaction after being exposed, so that the photoresist is solidified in a certain area, resulting in local deformation of the photoresist.

[0036] Therefore, in a specific implementation process, the first simulation region can be decomposed into a plurality of first sub-regions according to the surface morphology characteristics. It should be noted that, in the decomposition process, the sub-regions should be ensured to be as independent as possible, but a small range of overlap is allowed.

[0037] 103. Extract first electric field information of the first sub-region from an electric field lookup table.

[0038] It is understandable that the electric field lookup table is preset before the simulation. That is, before step 101, a step of constructing an electric field lookup table may also be included.

[0039] Specifically, several second simulation regions may be obtained first; then, based on the surface morphology characteristics of the wafer, the corresponding second simulation regions may be decomposed into several second sub-regions; and then, an electric field lookup table may be constructed based on the third electric field information of each second sub-region.

[0040] In some embodiments, each second sub-region may be further decomposed into a number of first boundary line segments; then, a preset electromagnetic field algorithm is used to calculate the fourth electric field information of each first boundary line segment, and an electric field lookup table is generated based on the fourth electric field information.

[0041] It can be understood that in the electric field lookup table, there is a one-to-one correspondence between the electric field information and the boundary line segments.

[0042] Therefore, during the simulation process, after the simulation region is decomposed into a number of first sub-regions, the first sub-regions may be divided into a number of second boundary line segments, and then the corresponding fifth electric field information may be extracted from the electric field lookup table based on the second boundary line segments.

[0043] In some embodiments, when the second boundary line segment cannot completely match the electric field information in the electric field lookup table, an interpolation method may be used to calculate an approximate value, and the approximate value is used as the corresponding fifth electric field information.

[0044] 104. Perform electric field superposition processing and redundancy removal processing on a plurality of first electric field information to obtain second electric field information of the first simulation area.

[0045] In one embodiment, electric field superposition processing and redundancy removal processing can be performed on a number of fifth electric field information of each first sub-region to obtain the first electric field information of each first sub-region; then electric field superposition processing and redundancy removal processing can be performed on a number of first electric field information to obtain the second electric field information of the first simulation region.

[0046] In another embodiment, electric field superposition processing and redundancy removal processing may be directly performed on a plurality of fifth electric field information to obtain the second electric field information of the first simulation area.

[0047] It should be noted that the results obtained by the above two methods are exactly the same. Electric field superposition processing refers to merging two electric field information together. De-redundancy processing refers to removing the repeated parts between electric field information. For details, please refer to Figure 3 and Figure 4 As shown. Among them, Figure 3 It represents the process of obtaining the second electric field information by the electric field superposition processing and the redundancy removal processing of the first electric field information. Figure 4 It shows the process of obtaining the first electric field information by performing electric field superposition processing and de-redundancy processing on the fifth electric field information.

[0048] 105. Calculate the optical imaging result of the target mask pattern based on the optical system parameters and the second electric field information.

[0049] In projection lithography imaging, the light intensity in a certain lithographic medium is obtained by the combined action of different plane wave diffraction orders excited by the exit pupil, while the amplitude and phase of the plane wave are jointly determined by parameters such as mask layout, lighting conditions, and objective lens properties, such as the incident angle of the light source, the numerical aperture NA of the objective lens, etc. Therefore, in the embodiment of the present application, the optical system parameter can be the plane wave diffraction order.

[0050] Taking the imaging of a one-dimensional periodic dense mask pattern as an example, the target mask pattern is a one-dimensional periodic dense pattern arranged along the X direction, and the 0th and 1st order plane wave diffraction orders and electric field information are used for imaging. The formula is as follows:

[0051] in, is the plane wave diffraction order, is the amplitude of the corresponding plane wave diffraction order, The final optical imaging result.

[0052] It is understandable that when the light source conditions, objective lens properties and target mask patterns change, it is only necessary to input the corresponding plane wave diffraction order values ​​and the above electric field information to quickly obtain the final optical imaging result.

[0053] In summary, the lithography imaging simulation method provided by the embodiment of the present application includes obtaining a first simulation area of ​​a wafer; decomposing the simulation area into a plurality of first sub-areas based on the surface morphology characteristics of the wafer; extracting first electric field information of the first sub-area from an electric field lookup table; performing electric field superposition processing and de-redundancy processing on the plurality of first electric field information to obtain second electric field information of the first simulation area; and calculating the optical imaging result of the target mask pattern based on the optical system parameters and the second electric field information. This solution can decompose a complex simulation area into a plurality of sub-areas, and use a lookup table to search for the electric field information of the sub-areas, thereby reducing the complexity of real-time calculation and improving the efficiency of lithography imaging simulation.

[0054] In order to better implement the lithography imaging simulation method provided in the embodiment of the present application, the embodiment of the present application also provides a lithography imaging simulation device, wherein the meanings of the terms are the same as those in the above-mentioned lithography imaging simulation method, and the specific implementation details can refer to the description in the method embodiment.

[0055] See also Figure 5 , Figure 5 201 is a schematic diagram of the structure of the lithography imaging simulation device provided in the embodiment of the present application. The lithography imaging simulation device may include a determination unit 201, a decomposition unit 202, a search unit 203, a top overlay unit 204 and a calculation unit 205. A determination unit 201 is used to obtain a first simulation area of ​​a wafer; A decomposition unit 202, configured to decompose the simulation region into a plurality of first sub-regions based on the surface morphology characteristics of the wafer; A search unit 203, configured to extract first electric field information of a first sub-region from an electric field search table; A superposition unit 204 is used to perform electric field superposition processing and redundancy removal processing on a plurality of first electric field information to obtain second electric field information of the first simulation area; The calculation unit 205 is used to calculate the optical imaging result of the target mask pattern based on the optical system parameters and the second electric field information.

[0056] The specific implementation of each of the above units can refer to the above-mentioned embodiment of the photolithography imaging simulation method, which will not be described in detail here.

[0057] In summary, the lithography imaging simulation device provided by the embodiment of the present application can obtain the first simulation area of ​​the chip by the determination unit 201; the decomposition unit 202 decomposes the simulation area into several first sub-areas based on the surface morphology characteristics of the chip; the search unit 203 extracts the first electric field information of the first sub-area from the electric field lookup table; the superposition unit 204 performs electric field superposition processing and redundancy removal processing on the several first electric field information to obtain the second electric field information of the first simulation area; the calculation unit 205 calculates the optical imaging result of the target mask pattern based on the optical system parameters and the second electric field information. This solution can decompose a complex simulation area into several sub-areas, and use the lookup table to find the electric field information of the sub-areas, thereby reducing the real-time calculation complexity and improving the efficiency of lithography imaging simulation.

[0058] The present application also provides an electronic device, in which the photolithography imaging simulation device of the present application can be integrated, such as Figure 6 As shown, it shows a schematic diagram of the structure of the electronic device involved in the embodiment of the present application, specifically: The electronic device may include one or more processors 301 of processing cores and one or more computer-readable storage media memories 302 and other components. Those skilled in the art will appreciate that Figure 6 The electronic device structure shown in the figure does not constitute a limitation on the electronic device, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently. The processor 301 is the control center of the electronic device, which uses various interfaces and lines to connect various parts of the entire electronic device, and executes various functions of the electronic device and processes data by running or executing the software program and / or the present application stored in the memory 302, and calling the data stored in the memory 302, so as to monitor the electronic device as a whole. Optionally, the processor 301 may include one or more processing cores; preferably, the processor 301 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operation storage medium, user interface and application program, etc., and the modem processor mainly processes wireless communication. It is understandable that the above-mentioned modem processor may not be integrated into the processor 301.

[0059] The memory 302 can be used to store software programs and the present application. The processor 301 executes various functional applications and data processing by running the software programs and the present application stored in the memory 302. The memory 302 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating storage medium, an application required for at least one function, etc.; the data storage area may store data created according to the use of the electronic device, etc. In addition, the memory 302 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other volatile solid-state storage devices. Accordingly, the memory 302 may also include a memory controller to provide the processor 301 with access to the memory 302.

[0060] Although not shown, the electronic device may further include a display unit, an input unit, a power supply, etc., which will not be described in detail herein. Specifically in this embodiment, the processor 301 in the electronic device will load the executable files corresponding to the processes of one or more application programs into the memory 302 according to the following instructions, and the processor 301 will run the application programs stored in the memory 302, thereby realizing various functions, as follows: Acquire a first simulation region of a wafer; Based on the surface morphology characteristics of the wafer, the simulation region is decomposed into a plurality of first sub-regions; Extracting first electric field information of the first sub-region from the electric field lookup table; Performing electric field superposition processing and redundancy removal processing on a plurality of first electric field information to obtain second electric field information of the first simulation area; Based on the optical system parameters and the second electric field information, the optical imaging result of the target mask pattern is calculated.

[0061] A person of ordinary skill in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be completed by instructions, or by controlling related hardware through instructions. The instructions may be stored in a computer-readable storage medium and loaded and executed by a processor.

[0062] To this end, an embodiment of the present application provides a storage medium in which a plurality of instructions are stored, and the instructions can be loaded by a processor to execute the steps in any method provided in the embodiment of the present application. For example, the instructions can execute the following steps: Acquire a first simulation region of a wafer; Based on the surface morphology characteristics of the wafer, the simulation region is decomposed into a plurality of first sub-regions; Extracting first electric field information of the first sub-region from the electric field lookup table; Performing electric field superposition processing and redundancy removal processing on a plurality of first electric field information to obtain second electric field information of the first simulation area; Based on the optical system parameters and the second electric field information, the optical imaging result of the target mask pattern is calculated.

[0063] The specific implementation of the above operations can be found in the previous embodiments, which will not be described in detail here.

[0064] The storage medium may include: a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0065] Since the instructions stored in the storage medium can execute the steps in any method provided in the embodiments of the present application, the beneficial effects that can be achieved by any method provided in the embodiments of the present application can be achieved. Please refer to the previous embodiments for details and will not be repeated here.

[0066] The above respectively introduces in detail the lithography imaging simulation method, device, storage medium and electronic device provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the core idea of ​​the present application; at the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A lithography imaging simulation method, characterized in that: include: Acquire a first simulation region of a wafer; Based on the surface morphology characteristics of the wafer, the simulation region is decomposed into a plurality of first sub-regions; Extracting first electric field information of the first sub-region from an electric field lookup table; Performing electric field superposition processing and redundancy removal processing on a plurality of the first electric field information to obtain second electric field information of the first simulation area; Based on the optical system parameters and the second electric field information, an optical imaging result of the target mask pattern is calculated.

2. The lithography imaging simulation method according to claim 1, characterized in that: Before determining the simulation area of ​​the semiconductor wafer, the method further includes: Construct the electric field lookup table.

3. The lithography imaging simulation method according to claim 2, characterized in that: The constructing of the electric field lookup table comprises: Acquire a plurality of second simulation areas; Based on the surface morphology characteristics of the wafer, decomposing the corresponding second simulation area into a plurality of second sub-areas; An electric field lookup table is constructed based on the third electric field information of each of the second sub-regions.

4. The lithography imaging simulation method according to claim 3, characterized in that: The constructing an electric field lookup table based on the third electric field information of each of the second sub-regions comprises: decomposing each of the second sub-regions into a plurality of first boundary line segments; The fourth electric field information of each of the first boundary line segments is calculated using a preset electromagnetic field algorithm, and an electric field lookup table is generated based on the fourth electric field information.

5. The lithography imaging simulation method according to claim 4, characterized in that: The extracting the first electric field information of the first sub-area from the electric field lookup table includes: dividing the first sub-region into a plurality of second boundary line segments; Based on the second boundary line segment, corresponding fifth electric field information is extracted from the electric field lookup table.

6. The lithography imaging simulation method according to claim 5, characterized in that: The performing electric field superposition processing and redundancy removal processing on a plurality of the first electric field information to obtain the second electric field information of the first simulation area includes: Performing electric field superposition processing and redundancy removal processing on a plurality of fifth electric field information of each first sub-region to obtain first electric field information of each first sub-region; Electric field superposition processing and redundancy removal processing are performed on a plurality of the first electric field information to obtain second electric field information of the first simulation area.

7. The lithography imaging simulation method according to claim 5, characterized in that: The performing electric field superposition processing and redundancy removal processing on a plurality of the first electric field information to obtain the second electric field information of the first simulation area includes: Perform electric field superposition processing and redundancy removal processing on a plurality of the fifth electric field information to obtain the second electric field information of the first simulation area.

8. A photolithography imaging simulation device, characterized in that: include: A determination unit, configured to obtain a first simulation region of a wafer; A decomposition unit, configured to decompose the simulation region into a plurality of first sub-regions based on the surface morphology characteristics of the wafer; A search unit, configured to extract the first electric field information of the first sub-region from an electric field lookup table; a superposition unit, configured to perform electric field superposition processing and redundancy removal processing on a plurality of the first electric field information to obtain second electric field information of the first simulation area; A calculation unit is used to calculate the optical imaging result of the target mask pattern based on the optical system parameters and the second electric field information.

9. A storage medium, characterized in that: The storage medium stores a plurality of instructions, and the instructions are suitable for being loaded by a processor to execute the lithography imaging simulation method according to any one of claims 1 to 7.

10. An electronic device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the lithography imaging simulation method according to any one of claims 1 to 7 when executing the computer program.

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