True random number generator based on resistive random access memory

Abstract

The invention provides a true random number generator based on a resistive random access memory, and belongs to the technical field of information security. The true random number generator comprises a resistive random access memory, an MOS (Metal Oxide Semiconductor) transistor, a comparator and a register, the grid electrode of the MOS transistor is connected with a voltage source signal through the resistive random access memory, the source electrode of the MOS transistor is grounded, the drain electrode of the MOS transistor is connected with the positive input end of the comparator, and the output end of the comparator is connected with the input end of the register. The negative input end of the comparator is connected with a reference level, and the reference level is the average value of voltage signals output by the drain electrode of the MOS transistor. According to the true random number generator, the electric signal random characteristic of the resistive random access memory and the 1 / f noise of the MOS tube are combined to serve as entropy source signals, the random number generation rate is high, the area is small, energy consumption is low, the true random number generator is compatible with the CMOS integrated circuit technology, and integration in an integrated circuit chip is easy.

Description

Technical Field

[0001] The present invention belongs to the technical field of information security, and in particular relates to a true random number generator based on a resistance random access memory and a random number generation method. Background Art

[0002] With the increasing popularity of smart interconnection, a large amount of data is intersecting in real time. Data streams are prone to attacks or loss during data transmission, which poses a security risk. Secure data stream transmission requires a stable and highly confidential random key, and the performance of a true random number generator is the key to generating a reliable key.

[0003] Traditional random number generators use single physical phenomena such as metastable states and thermal noise as entropy sources to generate random numbers. The raw output data streams generated will show high autocorrelation and require complex and energy-consuming post-processing circuits. They are easily affected by changes in external conditions, which causes security issues in random number generators. Traditional random number generators have problems such as large area, high energy consumption, and insufficient randomness. Summary of the invention

[0004] In order to solve the defects of the prior art, the present invention provides a true random number generator based on a resistive random access memory. The present invention combines the random phenomenon of the electrical signal of the resistive random access memory itself and the 1 / f noise of the MOS tube as an entropy source signal, converts the changing current noise signal into a voltage noise signal, connects the signal to a comparator, generates random high and low levels, and obtains an initial random sequence after register processing, thereby achieving random number generation with a high degree of confusion.

[0005] The true random number generator based on the resistance random access memory provided by the present invention comprises: a resistance random access memory, a MOS transistor, a comparator and a register;

[0006] The gate of the MOS transistor is connected to a voltage source signal through the resistance random access memory, the source of the MOS transistor is grounded, the drain of the MOS transistor is connected to the positive input terminal of the comparator, and the output terminal of the comparator is connected to the input terminal of the register;

[0007] The negative input terminal of the comparator is connected to a reference level, and the reference level is an average value of a voltage signal output by the drain of the MOS transistor.

[0008] In the embodiment of the present invention, a connection point between the drain of the MOS transistor and the positive input terminal of the comparator is grounded through a resistor.

[0009] In an embodiment of the present invention, the resistance random access memory includes: a top electrode, an oxide dielectric layer and a bottom electrode, and the oxide dielectric layer is located between the top electrode and the bottom electrode.

[0010] In the embodiment of the present invention, the top electrode of the resistance random access memory is connected to the voltage source signal, and the bottom electrode of the resistance random access memory is connected to the gate of the MOS transistor.

[0011] In the embodiment of the present invention, the resistive random access memory and the MOS transistor are integrated using a CMOS process.

[0012] In an embodiment of the present invention, a method for integrating the resistive random access memory and the MOS transistor using a CMOS process includes:

[0013] forming a source region and a drain region on a substrate;

[0014] forming a gate oxide layer on the surface of the substrate between the source region and the drain region, and forming a gate on the gate oxide layer;

[0015] Making ohmic contact electrodes of the source region and the drain region to form a source electrode and a drain electrode to obtain a MOS transistor;

[0016] forming an insulating layer on surfaces of the gate, source and drain;

[0017] A through hole connected to the gate is formed in the insulating layer, and metal is filled in the through hole to form a conductive through hole;

[0018] A bottom electrode, an oxide dielectric layer and a top electrode are formed on an insulating layer with a conductive through hole to obtain a resistance random access memory connected to the gate of a MOS transistor.

[0019] In an embodiment of the present invention, the material of the insulating layer is silicon dioxide or hafnium dioxide.

[0020] In an embodiment of the present invention, the material of the bottom electrode and the top electrode is titanium nitride, and the material of the oxide dielectric layer is hafnium dioxide.

[0021] In the embodiment of the present invention, the thickness of the source region and the drain region is 10 nanometers to 80 nanometers, and the thickness of the gate oxide layer is 20 nanometers to 100 nanometers.

[0022] In the embodiment of the present invention, the comparator is a voltage sensitive amplifier or a dual tail tube differential comparator.

[0023] In the embodiment of the present invention, the register is a D flip-flop, a JK flip-flop or a TSPC flip-flop.

[0024] The present invention also provides a random number generation method, which is based on the above-mentioned true random number generator and comprises:

[0025] Producing a fluctuating electrical signal through a resistive random access memory;

[0026] The fluctuating electrical signal passes through the gate of the MOS transistor, regulating the current at the drain of the MOS transistor, causing the drain current to change;

[0027] The current change of the drain of the MOS transistor is converted into a voltage signal, and the voltage signal is used as a noise signal and input into the positive input terminal of the comparator;

[0028] The average value of the fluctuating electrical signal output from the drain of the MOS transistor is used as a reference level and input into the negative input terminal of the comparator;

[0029] The level signal output by the comparator is input into the register, and the random sequence is saved and output through the register.

[0030] The present invention utilizes the random characteristics of the electrical signal of the resistive random access memory itself, and combines the 1 / f noise of the MOS tube as the entropy source signal, converts the changing current noise signal into a voltage noise signal, connects the voltage noise signal to the comparator, generates random high and low levels, obtains the initial random sequence through register processing, and realizes the generation of random numbers with a high degree of confusion. The true random number generator of the present invention has a high random number generation rate, a small area, low energy consumption, and is compatible with CMOS integrated circuit technology, is easy to integrate in integrated circuit chips, and can be widely used in cryptography, analog computing, simulation and other fields.

[0031] Other features and advantages of the technical solution of the present invention will be described in detail in the specific implementation section below. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0033] Figure 1 is a schematic structural diagram of a true random number generator based on a resistive random access memory according to an embodiment of the present invention;

[0034] Figure 2 is a flow chart of a method for manufacturing a resistive random access memory and a MOS transistor according to an embodiment of the present invention;

[0035] Figure 3 Schematic diagram of the structure of the source region and the drain region formed in the manufacturing method of the embodiment of the present invention

[0036] Figure 4 is a schematic structural diagram of a gate oxide layer and a gate formed in a manufacturing method according to an embodiment of the present invention;

[0037] Figure 5 is a schematic structural diagram of an insulating layer formed in a manufacturing method according to an embodiment of the present invention;

[0038] Figure 6 is a schematic structural diagram of a through hole formed in a manufacturing method according to an embodiment of the present invention;

[0039] Figure 7 It is a schematic structural diagram of a bottom electrode, an oxide dielectric layer and a top electrode formed in a manufacturing method according to an embodiment of the present invention.

[0040] Description of Reference Numerals

[0041] 10-silicon substrate, 11-drain region, 12-source region, 20-gate oxide layer, 21-gate, 30-insulating layer,

[0042] 40 - through hole, 50 - bottom electrode, 51 - oxide dielectric layer, 52 - top electrode. DETAILED DESCRIPTION

[0043] In order to make the technical solutions and advantages of the embodiments of the present invention more clearly understood, the exemplary embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0044] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0045] In the present invention, unless otherwise clearly specified and limited, the terms such as "connected" and "connection" should be understood in a broad sense, for example, it can be mechanical connection, electrical connection or mutual communication; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0046] As introduced in the background technology, traditional random number generators use single physical phenomena such as metastable states and thermal noise as entropy sources to generate random numbers. The generated raw output data stream will show high autocorrelation and require complex and energy-consuming post-processing circuits. They are easily affected by changes in external conditions, which causes security issues in random number generators. Traditional random number generators have problems such as large area, high energy consumption, and insufficient randomness.

[0047] In view of the above problems, the present invention proposes a true random number generator combined with a resistive random access memory. Since the random access memory has the advantages of high scalability, compatibility with CMOS processes, and exhibits unique random signal behavior, it can be used as a reliable entropy source for a true random number generator. The resistive random access memory is a three-layer structure of metal-insulating layer-metal. Its resistance can be adjusted by adjusting the voltage value at both ends of the metal electrode. The fluctuation of the electrical signal flowing through it is applied to the gate of the MOS tube. Due to the existence of 1 / f noise (flicker noise) in the MOS tube, the number of carriers flowing from the source to the drain changes through the fluctuating gate voltage regulation, resulting in a larger drain current fluctuation. The current fluctuation is converted into a voltage fluctuation through a resistor and used as one of the input signals of the subsequent comparator.

[0048] The present invention combines the random characteristics of the electrical signal of the resistive random access memory itself and the 1 / f noise of the MOS tube as an entropy source signal, converts the changing current noise signal into a voltage noise signal, connects the signal to the comparator, generates random high and low levels, obtains an initial random sequence through register processing, and realizes random number generation with a high degree of chaos. The present invention uses the resistive random access memory to enhance the random fluctuation of the electrical signal, and improves the chaos and disorder of the random sequence. The random sequence generated by the present invention has strong randomness, high random number generation rate, small area, low energy consumption, and is compatible with the CMOS integrated circuit process, and can be widely used in cryptography, analog computing, simulation and other fields.

[0049] Figure 1 1 is a schematic diagram of the structure of a true random number generator based on a resistive random access memory according to an embodiment of the present invention. Figure 1As shown, the true random number generator based on the resistive random access memory of this embodiment includes: a resistive random access memory RRAM, a MOS transistor M1, a comparator and a register. The gate of the MOS transistor M1 is connected to the voltage source signal Vsource through the resistive random access memory RRAM, the source of the MOS transistor M1 is grounded, the drain of the MOS transistor M1 is connected to the positive input terminal V+ of the comparator, and the output terminal of the comparator is connected to the input terminal of the register. The connection point between the drain of the MOS transistor M1 and the positive input terminal V+ of the comparator is grounded through a resistor R2. The negative input terminal V- of the comparator is connected to a reference level, which is the average value of the voltage signal output by the drain of the MOS transistor M1.

[0050] In this embodiment, the resistive random access memory RRAM includes: a top electrode, an oxide dielectric layer and a bottom electrode, wherein the oxide dielectric layer is located between the top electrode and the bottom electrode. The top electrode of the resistive random access memory RRAM is connected to a voltage source signal Vsource, and the bottom electrode of the resistive random access memory RRAM is connected to the gate of the MOS transistor M1.

[0051] The principle of the present invention is: when an external voltage input signal (i.e., a voltage source signal Vsource) is applied to the top electrode of the resistive random access memory RRAM, the oxygen vacancies in the oxide dielectric layer of the resistive random access memory RRAM have a capture and release effect on the movement of carriers, which is manifested as a fluctuation phenomenon of the electrical signal, and there is a relatively obvious random characteristic. After the external voltage is divided by the resistive random access memory RRAM, the remaining fluctuation voltage will be applied to the gate of the MOS transistor M1, as the gate voltage regulates the working state of the transistor. Under the action of the random gate voltage and the 1 / f noise (flicker noise) of the MOS transistor, the number of carriers flowing from the source to the drain changes, resulting in a larger drain current fluctuation, and the current fluctuation is converted into a voltage fluctuation through the resistor R2, and used as one of the input signals of the subsequent comparator. By collecting and testing the voltage fluctuation signal output by the drain of the MOS transistor for multiple times, the average value is used as the reference level of the comparator to realize the comparison and amplification between signals, and finally the high and low level signals are output and transmitted to the register, and the initial random number sequence is saved and output through the register.

[0052] In a specific embodiment, the external power supply voltage (i.e., the voltage source signal Vsource) is controlled between 1-1.8V. Different voltages can change the resistance state of the resistive random access memory, and the voltage value transmitted to the gate of the MOS transistor can be adjusted. The resistance value of the resistor R2 is 100k-10M, which can effectively amplify the current signal. The comparator can use a voltage sensitive amplifier or a dual tail tube differential comparator. The register can use a D flip-flop, a JK flip-flop, or a TSPC flip-flop.

[0053] This embodiment utilizes the random phenomenon of the electrical signal of the resistive random access memory itself, and combines the 1 / f noise of the MOS tube as the entropy source signal to convert the changing current noise signal into a voltage noise signal, and connects the voltage noise signal to the comparator to generate random high and low levels, and obtains the initial random sequence after register processing to achieve random number generation with a high degree of confusion. The true random number generator of this embodiment has a high random number generation rate, a small area, low energy consumption, and is compatible with CMOS integrated circuit technology, easy to integrate in integrated circuit chips, and can be widely used in cryptography, analog computing, simulation and other fields.

[0054] In the embodiment of the present invention, the CMOS process can be used to realize the integration of the resistive random access memory and the MOS transistor. Figure 2 As shown, the manufacturing method of the resistive random access memory and the MOS transistor comprises the following steps:

[0055] S201, forming a source region and a drain region on a substrate;

[0056] S202, forming a gate oxide layer on the surface of the substrate between the source region and the drain region, and forming a gate on the gate oxide layer;

[0057] S203, making ohmic contact electrodes in the source region and the drain region, forming a source electrode and a drain electrode, and obtaining a MOS transistor;

[0058] S204, forming an insulating layer on the surfaces of the gate, the source and the drain;

[0059] S205, forming a through hole connected to the gate in the insulating layer, and filling the through hole with metal to form a conductive through hole;

[0060] S206, forming a bottom electrode, an oxide dielectric layer and a top electrode on the insulating layer having the conductive through hole, to obtain a resistive random access memory connected to the gate of the MOS transistor.

[0061] In the above step S201, if Figure 3 As shown, a silicon substrate 10 is used, and photolithography is performed on the silicon substrate 10 to reveal the source region (corresponding to the source diffusion region) and the drain region (corresponding to the drain diffusion region). The photolithography method is ultraviolet lithography or laser direct writing. The source diffusion region and the drain diffusion region on the silicon substrate 10 are doped to form a heavily doped region. The doping type is n-type, and the doping method is ion implantation or thermal diffusion. The doping concentration is 10 17 per cubic centimeter to 10 21Per cubic centimeter, and the source diffusion region and the drain diffusion region are subjected to impurity activation annealing, the annealing method is thermal annealing or laser annealing, the annealing temperature is 1000 degrees Celsius, and finally the source region 12 and the drain region 11 are formed. The thickness of the source region and the drain region is 10 nanometers to 80 nanometers.

[0062] In the above step S202, if Figure 4 As shown, an oxide is deposited on the surface of the substrate between the source region 12 and the drain region 11 to form a gate oxide layer 20. The thickness of the gate oxide layer 20 is 20 nanometers to 100 nanometers. A gate 21 and a gate contact electrode are formed on the gate oxide layer 20. The method for forming the gate 21 and the gate contact electrode is chemical vapor deposition, magnetron sputtering, thermal evaporation, etc.

[0063] Specifically, the material of the source ohmic contact electrode and the drain ohmic contact electrode can be selected from metals such as nickel and aluminum, and the material of the gate contact electrode can be selected from metals such as nickel and aluminum.

[0064] In the above step S204, if Figure 5 As shown, an insulating material is deposited on the surface of the gate, source and drain to form an insulating layer 30. The insulating material is silicon dioxide (SiO2) or hafnium dioxide (HfO2). The thickness of the insulating layer is 400 nanometers. The method of depositing the insulating material is atomic layer deposition, chemical vapor deposition, etc.

[0065] In the above step S205, if Figure 6 As shown, a through hole 40 is etched in the insulating layer 30, and the bottom of the through hole 40 is connected to the gate 21. Metal is filled in the through hole 40 to form a conductive through hole. The metal material filled in the through hole 40 can be tungsten or aluminum, and the metal filling method is magnetron sputtering.

[0066] In the above step S206, if Figure 7 As shown, 100 nanometers of titanium nitride (TiN) is deposited on the insulating layer 30 with the through hole 40 as the bottom electrode 50, 10 nanometers of hafnium dioxide (HfO2) is deposited on the bottom electrode 50 as the oxide dielectric layer 51, and 100 nanometers of titanium nitride (TiN) is deposited on the oxide dielectric layer 51 as the top electrode 52. The method for depositing titanium nitride can be selected from magnetron sputtering.

[0067] In other embodiments, a method for manufacturing a resistive random access memory and a MOS transistor specifically includes the following steps:

[0068] (1) Performing photolithography on the silicon substrate to reveal the source and drain regions;

[0069] (2) performing doping ion implantation or diffusion on the source and drain regions of the substrate;

[0070] (3) performing activation annealing in the source and drain regions to form impurity diffusion regions;

[0071] (4) depositing metal electrodes on the source and drain regions to form ohmic contacts;

[0072] (5) Photolithography of the gate region on the substrate and deposition of gate oxide;

[0073] (6) depositing a gate metal on the gate oxide to prepare a gate contact electrode;

[0074] (7) depositing an insulating oxide layer to isolate the random access memory from the MOS transistor;

[0075] (8) Etching a through hole in the insulating oxide layer and depositing metal to connect to the gate of the MOS transistor;

[0076] (9) Photolithography and deposition of the metal-dielectric layer-metal required for random access memory on the through hole.

[0077] Furthermore, the photolithography process in the above step (1) includes ultraviolet photolithography and laser direct writing;

[0078] Furthermore, the method used to form the source and drain regions in the above step (2) is ion implantation or thermal diffusion;

[0079] Furthermore, the impurity activation annealing method in the above step (3) is thermal annealing or laser annealing, and the annealing temperature is 1000 degrees Celsius;

[0080] Furthermore, in the above step (4), the method for depositing the source-drain contact metal electrode is magnetron sputtering;

[0081] Furthermore, the method of depositing the gate oxide in the above step (5) is chemical vapor deposition or atomic layer deposition;

[0082] Furthermore, the gate metal is deposited by magnetron sputtering or thermal evaporation in the above step (6);

[0083] Furthermore, the method of depositing the insulating layer oxide in the above step (7) is chemical vapor deposition or atomic layer deposition;

[0084] Furthermore, the method for depositing metal in the above steps (8) and (9) is magnetron sputtering.

[0085] The embodiment of the present invention also provides the above-mentioned true random number generator based on resistive random access memory, and a method for generating random numbers, comprising: generating a fluctuating electrical signal through a resistive random access memory; the fluctuating electrical signal passes through the gate of a MOS transistor to regulate the current of a drain of the MOS transistor, so that the current of the drain changes; converting the current change of the drain of the MOS transistor into a voltage signal through a resistor, and inputting the voltage signal as a noise signal into the positive input terminal of a comparator; collecting the fluctuating electrical signal output by the drain of the MOS transistor for multiple times, and taking the average value of the fluctuating electrical signal as a reference level and inputting it into the negative input terminal of the comparator; realizing comparison and amplification between signals through a comparator, and outputting high and low level signals; inputting the high and low level signals output by the comparator into a register, and storing and outputting a random sequence through the register.

[0086] This method combines the random characteristics of the electrical signal of the resistive random access memory itself and the 1 / f noise of the MOS tube as two physical phenomena as entropy source signals, converts the changing current noise signal into a voltage noise signal, connects the signal to the comparator, generates random high and low levels, and obtains the initial random sequence after register processing, thereby realizing random number generation with a high degree of chaos.

[0087] The optional embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the technical concept of the embodiments of the present invention, a variety of simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all belong to the protection scope of the embodiments of the present invention. It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction, and as long as the combination does not violate the concept of the embodiments of the present invention, it should also be regarded as the content disclosed in the embodiments of the present invention.

Claims

1. A true random number generator based on a resistive random access memory, characterized in that: include: Resistive random access memory, MOS transistors, comparators, and registers; The gate of the MOS transistor is connected to a voltage source signal through the resistance random access memory, the source of the MOS transistor is grounded, the drain of the MOS transistor is connected to the positive input terminal of the comparator, and the output terminal of the comparator is connected to the input terminal of the register; The negative input terminal of the comparator is connected to a reference level, and the reference level is an average value of a voltage signal output by the drain of the MOS transistor.

2. The true random number generator based on resistance random access memory according to claim 1, characterized in that: Also includes: A resistor is provided, and a connection point between the drain of the MOS transistor and the positive input terminal of the comparator is grounded through the resistor.

3. The true random number generator based on resistance random access memory according to claim 1, characterized in that: The resistance random access memory comprises: a top electrode, an oxide dielectric layer and a bottom electrode, wherein the oxide dielectric layer is located between the top electrode and the bottom electrode.

4. The true random number generator based on resistance random access memory according to claim 3, characterized in that: The top electrode of the resistance random access memory is connected to the voltage source signal, and the bottom electrode of the resistance random access memory is connected to the gate of the MOS transistor.

5. The true random number generator based on resistance random access memory according to claim 4, characterized in that: The resistance random access memory and the MOS transistor are integrated by using a CMOS process.

6. The true random number generator based on resistance random access memory according to claim 5, characterized in that: The method of integrating the resistive random access memory and the MOS transistor using a CMOS process comprises: forming a source region and a drain region on a substrate; forming a gate oxide layer on the surface of the substrate between the source region and the drain region, and forming a gate on the gate oxide layer; Making ohmic contact electrodes of the source region and the drain region to form a source electrode and a drain electrode to obtain a MOS transistor; forming an insulating layer on surfaces of the gate, source and drain; A through hole connected to the gate is formed in the insulating layer, and metal is filled in the through hole to form a conductive through hole; A bottom electrode, an oxide dielectric layer and a top electrode are formed on an insulating layer with a conductive through hole to obtain a resistance random access memory connected to the gate of a MOS transistor.

7. The true random number generator based on resistance random access memory according to claim 6, characterized in that: The material of the insulating layer is silicon dioxide or hafnium dioxide.

8. The true random number generator based on resistance random access memory according to claim 6, characterized in that: The material of the bottom electrode and the top electrode is titanium nitride, and the material of the oxide dielectric layer is hafnium dioxide.

9. The true random number generator based on resistance random access memory according to claim 6, characterized in that: The thickness of the source region and the drain region is 10 nanometers to 80 nanometers; The thickness of the gate oxide layer is 20 nanometers to 100 nanometers.

10. The true random number generator based on resistance random access memory according to claim 1, characterized in that: The comparator is a voltage sensitive amplifier or a dual tail tube differential comparator.

11. The true random number generator based on resistance random access memory according to claim 1, characterized in that: The register is a D flip-flop, a JK flip-flop or a TSPC flip-flop.

12. A random number generation method, based on the true random number generator based on resistive random access memory according to claim 1, characterized in that: The method comprises: Producing a fluctuating electrical signal through a resistive random access memory; The fluctuating electrical signal passes through the gate of the MOS transistor, regulating the current at the drain of the MOS transistor, causing the drain current to change; The current change of the drain of the MOS transistor is converted into a voltage signal, and the voltage signal is used as a noise signal and input into the positive input terminal of the comparator; The average value of the fluctuating electrical signal output from the drain of the MOS transistor is used as a reference level and input into the negative input terminal of the comparator; The level signal output by the comparator is input into the register, and the random sequence is saved and output through the register.

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