Decoding method, device and storage medium for code word information

Abstract

The application relates to the technical field of memories, and discloses a code word information decoding method and device and a storage medium, and relates to the technical field of memories, which comprises the following steps: when code word information is read, the number of error bits in the code word information is determined; if the number of error bits is greater than a correctable number, the code word information is re-read, and a flip operation is performed on the code word information according to a re-reading result; and a flip result is hard-decoded based on an iterative algorithm to obtain a corresponding decoding result. The application aims to improve decoding capability.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to methods, devices and storage media for decoding codeword information. Background Technology

[0002] NAND Flash (Not AND Flash) is a very important type of non-volatile memory widely used in various portable electronic devices. Although NAND Flash offers advantages such as high density and low cost, it is susceptible to various errors during data storage.

[0003] To improve the reliability of NAND Flash, ECC (Error Correction Code) technology is typically used to detect and correct errors that occur during storage. A common algorithm is BCH (Bose Chaudhuri Hocquenghem), a linear cyclic code. By calculating the adjoint polynomial and applying a specific algorithm, it is possible to locate and correct erroneous bits, thereby recovering the original information.

[0004] However, for a specific BCH code, the number of error-correctable errors is determined during the design phase. Once the actual number of errors exceeds this threshold, the decoding performance will be severely affected.

[0005] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0006] The main purpose of this application is to provide a method, device and storage medium for decoding codeword information, in order to solve the technical problem of insufficient decoding capability.

[0007] To achieve the above objectives, this application proposes a method for decoding codeword information, the method comprising:

[0008] When codeword information is read, determine the number of erroneous bits in the codeword information;

[0009] If the number of erroneous bits is greater than the number of error-correctable bits, the codeword information is reread and the codeword information is flipped based on the reread result.

[0010] The flipping result is hardware-decoded based on an iterative algorithm to obtain the corresponding decoding result.

[0011] In one embodiment, when codeword information is read, the step of determining the number of erroneous bits in the codeword information includes:

[0012] When codeword information is read, a division operation is performed on the codeword information based on the generator polynomial to obtain the corresponding adjoint polynomial.

[0013] The number of error bits is determined based on the coefficients of the adjoint polynomial.

[0014] In one embodiment, the steps of rereading the codeword information and flipping the codeword information based on the rereading result include:

[0015] The voltage is adjusted according to the preset adjustment amount, and the rereading results are collected at each voltage.

[0016] Perform an XOR operation on all reread results and determine the bits to be flipped in the codeword information based on the calculation result;

[0017] Perform a flip operation on the bit to be flipped.

[0018] In one embodiment, the step of performing a toggling operation on the bit to be toggled includes:

[0019] Decoding records of the hierarchical structure containing the detected codeword information;

[0020] If the decoded record is empty, then flip all bits to be flipped.

[0021] If the decoded record is not empty, the bits to be flipped are filtered according to the average number of erroneous bits in the decoded record, and the filtered bits to be flipped are flipped.

[0022] In one embodiment, the step of filtering the bits to be flipped includes:

[0023] Determine the correlation coefficient between the bit to be flipped and the historical erroneous bits in the decoded record;

[0024] All bits to be flipped are sorted according to the correlation coefficient to generate a sequence, and the sequence is then filtered according to the average.

[0025] In one embodiment, before the steps of sorting all bits to be flipped according to the correlation coefficient to generate a sequence and filtering the sequence according to the average, the method further includes:

[0026] Determine the fault mode of the bit to be flipped based on the fault mode of the historical erroneous bits that match the bit to be flipped.

[0027] The correlation coefficients are weighted according to the severity of the failure modes.

[0028] In one embodiment, after determining the number of erroneous bits in the codeword information when it is read, the method further includes:

[0029] If the number of erroneous bits is less than or equal to the number of correctable bits, the codeword information is decoded based on an iterative algorithm to obtain the corresponding decoding result.

[0030] In one embodiment, the step of performing hard decoding on the flipping result based on an iterative algorithm to obtain the corresponding decoding result includes:

[0031] If the number of erroneous bits in the flip result is less than or equal to the number of correctable bits, then the flip result is hard-decoded based on an iterative algorithm to obtain the corresponding decoding result.

[0032] After the step of performing hard decoding on the flipped result based on the iterative algorithm to obtain the corresponding decoded result, the following steps are also included:

[0033] If the number of erroneous bits in the flip result is greater than the number of correctable bits, then the flip result is decoded based on the low-density parity check algorithm to obtain the corresponding decoding result.

[0034] In addition, to achieve the above objectives, this application also proposes a codeword information decoding device, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the codeword information decoding method described above.

[0035] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the codeword information decoding method as described above.

[0036] One or more technical solutions proposed in this application have at least the following technical effects:

[0037] This application provides a method for decoding codeword information. When codeword information is read, the number of erroneous bits is first determined. If it exceeds the correctable error count, the codeword information is reread and flipped. This strategy aims to capture and correct errors that may be introduced by transient interference during the reading process, thus effectively reducing the number of erroneous bits and significantly improving the reliability of the codeword information. After completing the above operations, an iterative algorithm is used for hardware decoding to obtain the final decoding result. This stage focuses on using the hardware decoding algorithm to perform deep analysis on the preprocessed codeword information to obtain a high-quality decoding result. Overall, this scheme integrates the advantages of software decoding and hardware decoding, forming a collaborative decoding process. Especially in high-error-rate storage environments, software decoding technology is prioritized. Its optimization capabilities initially improve the quality of the codeword information, reducing the processing burden of hardware decoding. This allows hardware decoding to perform well in error correction, ultimately maximizing the processing capacity of the entire decoding process and achieving a good balance between error correction capability and hardware resource overhead. Attached Figure Description

[0038] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0039] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 A flowchart illustrating the method for decoding codeword information in this application, provided in Embodiment 1.

[0041] Figure 2 This is a flowchart illustrating the second embodiment of the decoding method for codeword information in this application.

[0042] Figure 3 A flowchart illustrating the third embodiment of the decoding method for codeword information in this application;

[0043] Figure 4 This is a schematic diagram of the device structure of the hardware operating environment involved in the codeword information decoding method in the embodiments of this application.

[0044] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0045] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0046] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0047] The main solution of this application embodiment is: when codeword information is read, the number of erroneous bits in the codeword information is determined; if the number of erroneous bits is greater than the number of correctable bits, the codeword information is reread, and the codeword information is flipped according to the reread result; the flipped result is hard-decoded based on an iterative algorithm to obtain the corresponding decoding result.

[0048] NAND Flash is a crucial type of non-volatile memory widely used in devices such as solid-state drives (SSDs), USB (Universal Serial Bus) flash drives, SD cards (Secure Digital Cards), and embedded systems. While NAND Flash offers advantages such as high density and low cost, it is susceptible to various errors during data storage, including but not limited to:

[0049] 1. Physical damage: NAND Flash memory cells gradually degrade during repeated erase and write processes, leading to decreased cell reliability and eventually causing errors.

[0050] 2. Read interference: During the read process, the charge state of neighboring cells may be disturbed, leading to read errors.

[0051] 3. Charge leakage: When storing data for a long time, the charge in the storage unit may gradually leak, leading to data errors.

[0052] 4. Programming interference: When writing data, the programming voltage may affect adjacent cells, causing programming errors.

[0053] 5. Manufacturing errors: Logic errors introduced during the production of semiconductors and other semiconductors.

[0054] Furthermore, with continuous advancements in manufacturing processes, Nandflash has adopted multi-layer cell manufacturing to increase storage density and page size, currently reaching 8KB. While this change provides a significant increase in storage capacity, it also increases the bit error rate.

[0055] To improve the reliability of NAND Flash memory, ECC technology is typically used to detect and correct errors generated during storage. Traditional algorithms such as CRC (Cyclic Redundancy Check), CRC verification, and Hamming codes are rarely used nowadays due to their low error correction capabilities. LDPC (Low Density Parity Check) and BCH are currently widely used ECC algorithms.

[0056] Among them, BCH codes have relatively simple encoding and decoding circuits, requiring fewer hardware resources, making them suitable for resource-constrained applications. However, for a specific BCH code, the number of error-correctable bits is determined during the design phase. Once the actual number of errors exceeds this threshold, decoding performance will be severely affected. In other words, BCH codes have limited error correction capabilities, typically only able to correct a small number of bit errors, making them unsuitable for high-error-rate storage environments.

[0057] LDPC codes are low-density parity-check codes, which can be divided into several different types, such as LP (Low Power), HP (High Performance), and HT (High Throughput). LDPC codes have strong error correction capabilities, capable of correcting a large number of bit errors, and are suitable for storage media with high error rates. However, the encoding and decoding process of LDPC codes is relatively complex, requiring high hardware resources and computing power, which poses a significant challenge to the area cost and power consumption of storage controllers.

[0058] In practical applications, striking a balance between error correction capabilities and hardware overhead is a major challenge for NAND flash storage systems. In almost all ECC algorithms, the decoding module's area and power consumption are often greater than the encoding module's. Therefore, this solution primarily optimizes the decoding module, improving decoding capabilities based on the BCH algorithm decoding module, which has a smaller area overhead.

[0059] It should be noted that the implementing entity of this solution can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or a codeword information decoding device capable of performing the above functions. The following embodiments will be described using a codeword information decoding device as an example.

[0060] Based on this, embodiments of this application provide a method for decoding codeword information, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the decoding method for codeword information in this application.

[0061] In this embodiment, the decoding method for codeword information includes steps S10 to S30:

[0062] Step S10: When the codeword information is read, determine the number of erroneous bits in the codeword information.

[0063] It is important to note that in communication or data storage systems, data is typically transmitted or stored in the form of codewords. Codeword information refers to data blocks processed by encoding algorithms, and the system can read codeword information from communication channels or storage media.

[0064] After reading the codeword information, the system uses an error detection mechanism to check the number of erroneous bits in the codeword information. Erroneous bits refer to bits that do not match the original data due to various reasons during data transmission or storage, such as physical damage, read interference, or charge leakage. These erroneous bits will prevent the correct identification or understanding of the original data. The number of erroneous bits refers to the total number of bits in the codeword information that do not match the original data; this number is one of the important indicators for evaluating the quality of data transmission or storage.

[0065] Optionally, if there is sufficient historical data and error records, error patterns can be analyzed using machine learning or statistical methods to analyze the distribution patterns of bits and thus infer the bits in the codeword information that may be erroneous.

[0066] Alternatively, a grouping method can be used to divide the original codeword information into multiple groups, and then redundant information, such as parity bits or other types of check bits, can be added to each group. The redundant bits in each group can reflect the integrity of the data in that group. In this way, during the decoding process, data and redundant bits can be extracted from each group, and each group can be checked. Based on the check results of each group, the number of error bits can be calculated. For example, if the check fails for groups 1, 2, and 5, this indicates that there are errors in three independent data groups, thus implying the presence of at least three error bits.

[0067] Step S20: If the number of erroneous bits is greater than the number of correctable bits, the codeword information is reread and the codeword information is flipped based on the reread result.

[0068] This scheme employs a combination of software and hardware decoding. Hardware decoding refers to using direct algorithms to identify and correct errors, such as in BCH codes. In contrast, software decoding focuses more on the confidence level of each bit, i.e., the probability that each bit is classified as 0 or 1.

[0069] It's important to note that the error correction count (ECC) is a quantitative indicator of hardware decoding capability. It defines the maximum threshold of erroneous bits that a system can automatically identify and correct. For example, a BCH code might be designed with an ECC of 3. This means that the BCH code can correct a maximum of 3 bit errors. If 2 bit errors occur, the BCH code decoder will be able to successfully correct these errors and recover the original data; however, if 4 bit errors occur, exceeding the ECC, the BCH code decoder may be unable to recover the data correctly, resulting in decoding failure or data errors.

[0070] Based on the above principle, when the number of detected error bits exceeds this threshold, the system will be unable to fully recover the data through its built-in error correction mechanism. Therefore, when the number of detected error bits is less than or equal to the correctable number, the system can directly enter the hardware decoding stage within the processing capacity of hardware decoding. When the number of error bits is greater than the correctable number, the number of error bits must be reduced before entering the hardware decoding stage.

[0071] In this scheme, it is considered that the charge state of adjacent cells may be disturbed during the reading process, leading to temporary reading errors. For such cases, since they are temporary, a rereading method can be used to obtain more accurate reading results. For example, the codeword information can be reread directly using the original voltage, or the voltage can be adjusted first and then reread with the new voltage, which can improve the accuracy of the reading.

[0072] Next, all reading results are collected, including the codeword information from the first reading in S10.

[0073] This information is compared to analyze whether the bits have changed. For those bits that have changed significantly, the system will perform a flip operation, that is, change the value of certain bits in the codeword information from 0 to 1, or from 1 to 0, to restore the correctness of the data.

[0074] For example, the codeword information read in step S10 is 1010001, while the reread result in step S20 is 1011011. After comparing bit by bit, the 4th and 6th bits from left to right change, so the 4th and 6th bits of the codeword information need to be flipped, and the flipped result is 1011011.

[0075] The number of times to reread and flip can be preset to a fixed value, such as 3 times.

[0076] After completing these operations, the correctness of the codeword information can be verified again. If the number of erroneous bits is less than or equal to the correctable error count, it means that the error has been reduced to an acceptable range, and the process can proceed directly to the hardware decoding stage. If the number of erroneous bits is greater than the correctable error count, it indicates that the error is still relatively serious after software decoding, and the LDPC low-density parity-check algorithm with stronger error correction capabilities can be used for decoding.

[0077] Step S30: Hard decode the flipping result based on the iterative algorithm to obtain the corresponding decoding result.

[0078] In this scheme, the BM (Berlekamp-Massey) iterative algorithm from the BCH algorithm can be used for hard decoding. The BCH decoding process mainly includes three steps: calculating the adjoint polynomial, calculating the error polynomial, and error location and correction.

[0079] The first step is to calculate the adjoint polynomial:

[0080] Based on the preset codeword length n and error correction capability t, a binary polynomial G(x) is first generated, called the generator polynomial. The result is then transformed into a polynomial R(x), typically expressed as R(x) = r0 + r1x. 1 +r2x2 +…+r n x n At this point, we can use polynomial division to divide R(x) by G(x), and the remainder S(x) is the adjoint polynomial, S(x) = S0 + S1x. 1 +S2x 2 +…+S n x n .

[0081] The second step is to calculate the incorrect polynomial:

[0082] First, define the initial structure of the erroneous polynomial E(x), E(x) = e1x P1 +e2x p2 +…+e n x pn Where P1, P2, ..., P n It is the location where the error occurred, e n This is an error marker for the corresponding position.

[0083] Then, the coefficients of the adjoint polynomial S(x) are associated with the structure of the error polynomial to construct the coefficients of the corresponding linear equation. The coefficient of each term reflects the error and location information. For example, for the obtained adjoint polynomial S(x) = S0 + S1x 1 +S2x 2 +…+S n x n A set of linear equations can be derived from the form of the erroneous polynomial.

[0084] Next, the coefficients of the adjoint polynomial are substituted into the resulting linear equations to form a system of equations. This system of equations is solved using Gaussian elimination or other linear algebra techniques to obtain the exponents and corresponding labels at the error locations. Once the exponents and labels at the error locations are determined, they can be inserted into a predefined form of the error polynomial to obtain the final error polynomial E(x).

[0085] The third step is to locate and correct the error:

[0086] The roots of the known error polynomial E(x) correspond to the actual locations where errors occur. These locations are usually represented in exponential form and need to be converted to specific bit positions.

[0087] Once the misplaced polynomial E(x) is obtained, its roots can be found using the Chien search method. This typically involves testing E(α) in a finite field. i ) = 0 for all possible values ​​of i, where α is the primitive element.

[0088] For each error location found, the corresponding error correction operation is performed, which usually involves inverting the corresponding bit, or performing more complex correction actions according to the specific encoding and modulation strategy, and finally obtaining the decoding result.

[0089] This embodiment provides a method for decoding codeword information. When codeword information is read, the number of erroneous bits is first determined. If it exceeds the correctable error count, the codeword information is reread and flipped. This strategy aims to capture and correct errors that may be introduced by transient interference during the reading process, thus effectively reducing the number of erroneous bits and significantly improving the reliability of the codeword information. After completing the above operations, an iterative algorithm is used for hardware decoding to obtain the final decoding result. This stage focuses on using the hardware decoding algorithm to perform deep analysis on the preprocessed codeword information to obtain a high-quality decoding result. Overall, this solution integrates the advantages of software decoding and hardware decoding, forming a collaborative decoding process. Especially in high-error-rate storage environments, software decoding technology is prioritized. Its optimization capabilities initially improve the quality of the codeword information, reducing the processing burden of hardware decoding. This allows hardware decoding to perform well in error correction, ultimately maximizing the processing capacity of the entire decoding process and achieving a good balance between error correction capability and hardware resource overhead.

[0090] Based on the first embodiment of this application, in the second embodiment of this application, the content that is the same as or similar to that in Embodiment 1 above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 2 Step S10 may include steps A10 to A20:

[0091] Step A10: When the codeword information is read, perform a division operation on the codeword information based on the generator polynomial to obtain the corresponding adjoint polynomial.

[0092] Step A20: Determine the number of error bits based on the coefficients of the adjoint polynomial.

[0093] In this embodiment, the number of error bits can be determined by directly referring to the adjoint polynomial in the first step of the iterative algorithm.

[0094] After reading the encoded codeword information, the first step is to perform polynomial division on the codeword information using the known generator polynomial. The key to this step is that the generator polynomial is designed based on the preset codeword length *n* and error correction capability *t*, containing crucial information about the codeword structure and error correction capability. Through polynomial division, a remainder is obtained; this remainder is called the adjoint polynomial. The adjoint polynomial directly reflects the specific relationship between the codeword information and the generator polynomial, containing important information about the location of error bits in the codeword.

[0095] After obtaining the adjoint polynomial, the next step is to determine the number of error bits based on its coefficients, i.e., the adjoint coefficients. The adjoint coefficients are components of the adjoint polynomial, and each coefficient's value corresponds to an error condition for a specific bit in the codeword. Typically, non-zero adjoint coefficients indicate an error at the corresponding bit position. Therefore, by counting the number of non-zero coefficients in the adjoint coefficients, the number of error bits can be preliminarily inferred.

[0096] Specifically, the steps for calculating the adjoint polynomial in the first step are as follows:

[0097] Based on the preset codeword length n and error correction capability t, a binary polynomial G(x) is first generated, called the generator polynomial. The codeword information is then converted into a polynomial R(x), typically expressed as R(x) = r0 + r1x. 1 +r2x 2 +…+r n x n At this point, we can use polynomial division to divide R(x) by G(x), and the remainder S(x) is the adjoint polynomial, S(x) = S0 + S1x. 1 +S2x 2 +…+S n x n .

[0098] Based on the adjoint polynomial S(x), determine the adjoint coefficients S = (S0, S0, ..., S0). n ).

[0099] The value of each synastry coefficient indicates the error condition of the corresponding bit. Generally, a non-zero synastry coefficient indicates that an error exists at the corresponding bit position.

[0100] By counting the number of non-zero coefficients k in the syndrome coefficient S, we can deduce that k bits have been erroneous.

[0101] For example, if the accompanying polynomial is S = (0, 1, 2, 3), which has three non-zero coefficients, then the number of error bits is three.

[0102] This embodiment provides a method for decoding codeword information. It directly utilizes algebraic structures, obtaining the adjoint polynomial by dividing the codeword information by the generator polynomial. The coefficients of the adjoint polynomial directly reflect the error status in the codeword. This scheme, based on rigorous mathematical derivation and proof, can accurately indicate the presence of errors. Unlike machine learning and redundancy checks, this scheme relies directly on algebraic properties, requiring no additional training steps or redundant information. It directly utilizes the codeword itself and the generator polynomial for error detection, making it more efficient and reliable. Furthermore, since the first step of hard decoding is already performed in step S10, the second and third steps of hard decoding can be directly performed in step S30 based on the existing adjoint polynomial. This design not only optimizes the decoding process but also significantly saves computational resources, achieving the goal of efficient decoding.

[0103] Based on the first embodiment of this application, in the third embodiment of this application, the content that is the same as or similar to that in the first embodiment described above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 3 Step S20 may include steps B10 to B30:

[0104] Step B10: Adjust the voltage according to the preset adjustment amount and collect the code word information reading results under each voltage.

[0105] Step B20: Perform an XOR operation on all read results and determine the bit to be flipped based on the result.

[0106] In this scheme, dynamic voltage is used for multiple readings.

[0107] The voltage is adjusted according to a preset adjustment amount. At each different voltage level, the system collects the corresponding reread results. All reread results are collected, and the codeword information from the initial read in S10 can also be included in the statistics.

[0108] Perform an XOR operation on all read results. XOR is a bitwise operation; a result of 0 indicates that the bit value is the same under different voltages, while a result of 1 indicates that the bit value has changed. This suggests that the cell containing the bit may be affected by neighboring cells. For example, when a neighboring cell performs a write operation, it may cause the bit value of this cell to change from 0 to 1.

[0109] Furthermore, the bit positions with a calculation result of 1 are selected, and the corresponding bits are found in the codeword information. These bits are set as the bits to be flipped, and then all the bits to be flipped are flipped to restore the correctness of the data.

[0110] Understandably, by rereading data under different voltages and using XOR calculations to detect changes in bit values, the system can more accurately identify bits affected by interference from neighboring cells or those that are inherently unstable. This refined error detection mechanism helps reduce the bit error rate and improve the overall accuracy of the data.

[0111] For example, a preset adjustment amount is set, such as 0.1V each time. Then, starting from an initial voltage, such as 2.5V, the voltage is gradually increased according to the preset adjustment amount, and the codeword information in the storage unit is read again after each increase. In this process, multiple read results are obtained:

[0112] 2.5V: 10101010

[0113] 2.6V: 10101110

[0114] 2.7V: 10101010

[0115] Next, perform an XOR operation on all the read results:

[0116] 10101010⊕10101110⊕10101010=00000100

[0117] The XOR calculation results show that one bit value changed under different voltage levels, that is, from 0 to 1 and then back to 0. Therefore, this bit is set as the bit to be flipped.

[0118] Step B30: Perform a flipping operation on the bit to be flipped.

[0119] When performing a flip operation on bits to be flipped, you can choose to flip all or part of them, depending on the actual situation:

[0120] Design a data structure in advance based on the hierarchical structure of the storage system, such as pages, blocks, and regions, to store the decoding records of each level, including detailed information on error bits encountered during the decoding operation.

[0121] When reading codeword information, the decoding record corresponding to the hierarchical structure where the current codeword information is located is detected.

[0122] If the decoded record is empty, it indicates that no errors were detected at this level before, and you can choose to flip all the bits to be flipped.

[0123] If the decoded record is not empty, the average number of error bits needs to be obtained and used as the benchmark for filtering. As for the filtering method, random filtering can be used, or certain filtering conditions can be set to achieve more precise filtering.

[0124] For example, if there are 10 bits to be flipped and the average number of erroneous bits in the decoding record is 6, then 6 bits can be randomly selected from these 10 bits to be flipped for subsequent flipping operations.

[0125] For example, it is known that the decoding record contains detailed information about historical error bits in the hierarchical structure. First, relevant features, such as bit position information, bit value, the state of surrounding bits, and context information, need to be extracted from the bits to be flipped and the historical error bits respectively. Then, correlation analysis methods, such as Pearson correlation coefficient or Spearman rank correlation coefficient, can be used to calculate the correlation coefficient between each bit to be flipped and the historical error bits. Based on the calculated correlation coefficients, a sorted sequence is generated for all bits to be flipped. In this sequence, bits with higher correlation coefficients have higher priority because they have a stronger correlation with the historical error bits. From the sorted bit sequence, a corresponding number of bits are selected for flipping based on a set average. For example, the first 6 bits to be flipped in the sorted sequence can be selected for flipping.

[0126] Furthermore, the impact of different failure modes on bit values ​​can be considered during sorting. For example, physical damage usually leads to permanent data loss, while read interference may only be temporary. Therefore, it is necessary to prioritize bits that are prone to major failures. A weighted approach ensures that higher-risk bits have higher priority than lower-risk bits.

[0127] Specifically, during the design phase, different failure modes are pre-defined, including but not limited to physical damage, readout interference, charge leakage, programming interference, and process errors. Then, based on evaluation criteria such as impact range, misalignment frequency, and repair difficulty, these failure modes are classified by severity, resulting in different levels such as severe, moderate, and mild. Furthermore, corresponding weighting strategies are set for different severity levels.

[0128] In practical applications, for a given bit to be flipped, the historical error bit information with the highest correlation coefficient can be matched. Then, the fault mode of this historical error bit information can be found in the decoding record and used as the fault mode of the bit to be flipped. Next, the severity of the fault mode is determined, and an appropriate weighting strategy is used to weight the correlation coefficient of the bit to be flipped.

[0129] For example, if bit A to be flipped is physically damaged, which is a serious fault, then its correlation coefficient needs to be increased by 10%. If bit B to be flipped is due to read interference, which is a minor fault, then its correlation coefficient needs to be decreased by 20%.

[0130] At this point, all bits to be flipped can be sorted according to the weighted correlation coefficient, thus enabling effective filtering.

[0131] This scheme allows for flexible selection of full or partial flipping during the flipping operation based on error detection. Selecting flipped bits based on the average number of erroneous bits allows for flipping only a subset of bits, rather than blindly flipping all bits. This historical data-based optimization strategy reduces unnecessary flips and improves decoding efficiency. Furthermore, the data correlation-based filtering method identifies bits with strong correlation to historical erroneous bits, enabling precise selection of bits to be flipped, reducing the risk of incorrect flips, and thus improving the accuracy of data recovery.

[0132] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the decoding method of the codeword information of this application. Any simple transformations based on this technical concept are within the protection scope of this application.

[0133] This application provides a codeword information decoding device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the codeword information decoding method in the first embodiment described above.

[0134] The following is for reference. Figure 4 This document illustrates a structural schematic diagram of a decoding device suitable for implementing codeword information in the embodiments of this application. The decoding device for codeword information in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 4 The decoding device for codeword information shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0135] like Figure 4As shown, the codeword information decoding device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the codeword information decoding device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the codeword information decoding device to communicate wirelessly or wiredly with other devices to exchange data. Although codeword information decoding devices with various systems are shown in the figure, it should be understood that it is not required to implement or possess all the systems shown. More or fewer systems can be implemented alternatively.

[0136] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0137] The codeword information decoding device provided in this application, employing the codeword information decoding method in the above embodiments, can solve the technical problem of insufficient decoding capability. Compared with the prior art, the beneficial effects of the codeword information decoding device provided in this application are the same as those of the codeword information decoding method provided in the above embodiments, and other technical features in this codeword information decoding device are the same as those disclosed in the method of the previous embodiment, and will not be repeated here.

[0138] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0139] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0140] This application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer-readable program instructions are used to execute the codeword information decoding method in the above embodiments.

[0141] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0142] The aforementioned computer-readable storage medium may be included in a codeword information decoding device; or it may exist independently and not be assembled into a codeword information decoding device.

[0143] The aforementioned computer-readable storage medium carries one or more programs. When the aforementioned one or more programs are executed by the codeword information decoding device, the codeword information decoding device: when reading codeword information, determines the number of erroneous bits in the codeword information; if the number of erroneous bits is greater than the number of error-correctable bits, the codeword information is reread, and the codeword information is flipped based on the reread result; and the flipped result is hard-decoded based on an iterative algorithm to obtain the corresponding decoding result.

[0144] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0145] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0146] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0147] The readable storage medium provided in this application is a computer-readable storage medium that stores a computer program for executing the above-described codeword information decoding method, thereby solving the technical problem of insufficient decoding capability. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as the beneficial effects of the codeword information decoding method provided in the above embodiments, and will not be repeated here.

[0148] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A method for decoding codeword information, characterized in that, The method includes: When codeword information is read, the number of erroneous bits in the codeword information is determined; If the number of error bits is greater than the number of correctable bits, the voltage is adjusted according to the preset adjustment amount, and the rereading results under each voltage are collected. Perform an XOR operation on all the reread results, and determine the bit to be flipped in the codeword information based on the calculation result; Detect the decoding record of the hierarchical structure where the codeword information is located; If the decoded record is empty, then all the bits to be flipped are flipped. If the decoding record is not empty, then the bits to be flipped are filtered according to the average number of error bits in the decoding record, and the filtered bits to be flipped are flipped. The flipping result is hardware-decoded based on an iterative algorithm to obtain the corresponding decoding result.

2. The method as described in claim 1, characterized in that, The step of determining the number of erroneous bits in the codeword information when it is read includes: When codeword information is read, a division operation is performed on the codeword information based on the generator polynomial to obtain the corresponding adjoint polynomial. The number of error bits is determined based on the coefficients of the adjoint polynomial.

3. The method as described in claim 1, characterized in that, The step of filtering the bits to be flipped includes: Determine the correlation coefficient between the bit to be flipped and the historical erroneous bits in the decoding record; All the bits to be flipped are sorted according to the correlation coefficient to generate a sequence, and the sequence is filtered according to the average.

4. The method as described in claim 3, characterized in that, Before the step of sorting all the bits to be flipped according to the correlation coefficient to generate a sequence, and filtering the sequence according to the average, the method further includes: The fault mode of the bit to be flipped is determined based on the fault mode of the historical erroneous bits that match the bit to be flipped. The correlation coefficients are weighted according to the severity of the failure modes.

5. The method as described in claim 1, characterized in that, After determining the number of erroneous bits in the codeword information when it is read, the method further includes: If the number of error bits is less than or equal to the number of correctable bits, the codeword information is decoded based on an iterative algorithm to obtain the corresponding decoding result.

6. The method as described in claim 1, characterized in that, The steps for hard decoding the flipping result based on the iterative algorithm to obtain the corresponding decoding result include: If the number of error bits in the flip result is less than or equal to the number of correctable bits, then the flip result is hard-decoded based on an iterative algorithm to obtain the corresponding decoding result; After the step of performing hard decoding on the flipping result based on the iterative algorithm to obtain the corresponding decoding result, the method further includes: If the number of erroneous bits in the flip result is greater than the number of correctable bits, then the flip result is decoded based on the low-density parity check algorithm to obtain the corresponding decoding result.

7. A decoding device for codeword information, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the method for decoding codeword information as described in any one of claims 1 to 6.

8. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the codeword information decoding method as described in any one of claims 1 to 6.

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