A method for preparing a gate oxide layer, a MOSFET, and an electronic device

Abstract

The present invention relates to the field of semiconductor technology, and provides a method for preparing a gate oxide layer, a MOSFET, and an electronic device. The method for preparing the gate oxide layer includes: providing a silicon carbide substrate, cleaning the silicon carbide substrate, and performing wet oxygen pretreatment to form a first oxide layer on the surface of the silicon carbide substrate; performing high-temperature thermal oxidation on the silicon carbide substrate with the first oxide layer formed thereon to grow a second oxide layer on the first oxide layer; depositing an oxide film by ALD on the second oxide layer, where the oxide film includes silicon oxide and a plurality of hydroxide groups; performing nitridation annealing on the first oxide layer, the second oxide layer, and the oxide film to form a gate oxide layer on the silicon carbide substrate. By adopting the above method, the interface state density of the gate oxide layer can be reduced to the level of 1e10~1e11 cm<supgt;‑2< / supgt;eV<supgt;‑1< / supgt>, and the prepared gate oxide layer has a more stable interface.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly relates to a method for preparing a gate oxide layer, a MOSFET, and an electronic device. Background Art

[0002] A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a field-effect transistor that controls the switching of a semiconductor conductive channel by applying voltages to the gate of a metal layer and the source separated by an oxide layer to generate an electric field effect.

[0003] Silicon carbide has characteristics such as a large bandgap width, a high critical breakdown electric field, a high thermal conductivity, and a high electron saturation drift velocity. Silicon carbide MOSFETs perform better than silicon-based MOSFETs in the fields of high voltage, high temperature, and high power. Therefore, silicon carbide-based MOSFETs are gradually replacing silicon-based MOSFETs, and both can prepare an oxide dielectric layer by a high-temperature thermal oxidation method.

[0004] However, in the process of forming a gate oxide layer by high-temperature oxidation of silicon carbide, due to the different properties of carbon and silicon elements in silicon carbide, a large number of defects with different structures and properties will appear at the interface between silicon carbide and silicon oxide. These defects are easily captured traps for carriers, and the interface state density is high, resulting in a low channel mobility and a high on-resistance of silicon carbide MOSFETs. In the prior art, only methods such as high-temperature thermal oxidation and passivation with nitrogen oxides have limited effects on improving the interface state density. Summary of the Invention

[0005] Aiming at the deficiencies of the prior art, the purpose of the present invention is to provide a method for preparing a gate oxide layer, a MOSFET, and an electronic device. The present invention solves the technical problems of high interface state density and unstable interface in traditional silicon carbide MOSFETs by wet oxygen pretreatment and a method of combining high-temperature thermal oxidation with ALD deposition of an oxide dielectric layer.

[0006] To achieve the above purpose, the present invention is realized by the following technical solutions:

[0007] A method for preparing a gate oxide layer includes the following steps:

[0008] Provide a silicon carbide substrate, clean the silicon carbide substrate, and perform wet oxygen pretreatment to form a first oxide layer on the surface of the silicon carbide substrate;

[0009] Perform high-temperature thermal oxidation on the silicon carbide substrate on which the first oxide layer is formed to grow a second oxide layer on the first oxide layer;

[0010] An oxide film is deposited on the second oxide layer by ALD, and the oxide film includes silicon oxide and a plurality of hydroxyl groups;

[0011] The first oxide layer, the second oxide layer, and the oxide film are subjected to nitridation annealing to form a gate oxide layer on the silicon carbide substrate.

[0012] Compared with the prior art, the beneficial effects of the present invention are as follows: A composite silicon oxide dielectric layer including the first oxide layer and the second oxide layer is formed by wet oxygen pretreatment and high-temperature thermal oxidation. Then, through the ALD (Atomic Layer Deposited) deposition technology, an oxide film with high quality and containing hydroxyl groups can be effectively deposited to form a stacked structure. The stacked structure can capture positive charges and generate positive fixed charges. Compared with the structure formed only by high-temperature thermal oxidation or passivation treatment in the traditional method, the stacked structure can generate a more negative flat-band voltage. After nitridation annealing, the gate oxide layer is formed, and the gate oxide layer is further stabilized. The interface state density of the gate oxide layer can be reduced to the level of 1e10~1e11 cm -2 eV -1 -2, and the prepared gate oxide layer has a more stable interface.

[0013] Furthermore, the thickness range of the first oxide layer is 10 Å to 100 Å.

[0014] Furthermore, the thickness of the second oxide layer is less than 20 nm.

[0015] Furthermore, the temperature range of the wet oxygen pretreatment is 650 °C to 1150 °C, and the time of the wet oxygen pretreatment is 10 min to 200 min.

[0016] Furthermore, the temperature range of the high-temperature thermal oxidation is 650 °C to 1500 °C, and the time of the high-temperature thermal oxidation is 1 min to 120 min.

[0017] Furthermore, the temperature range of the ALD deposition is 260 °C to 360 °C.

[0018] Still further, the temperature of the nitridation annealing is less than or equal to the temperature of the high-temperature thermal oxidation, and the time of the nitridation annealing is 30 min to 180 min.

[0019] A MOSFET includes a gate oxide layer, and the gate oxide layer is prepared by the method for preparing a gate oxide layer as described in the above technical solution.

[0020] An electronic device includes the MOSFET as described in the above technical solution. Description of the Drawings

[0021] Figure 1It is a flowchart of the method for preparing the gate oxide layer in Embodiment 1 of the present invention;

[0022] The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings. Specific Embodiments

[0023] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0024] It should be noted that when an element is referred to as being "fixed on" another element, it can be directly on the other element or there may also be a middle element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be a middle element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are only for the purpose of illustration.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used in the description of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0026] Please refer to Figure 1 , the method for preparing the gate oxide layer in Embodiment 1 of the present invention includes the following steps:

[0027] Step S10: Provide a silicon carbide substrate, clean the silicon carbide substrate, and perform wet oxygen pretreatment to form a first oxide layer on the surface of the silicon carbide substrate;

[0028] Preferably, a silicon carbide wafer is provided for pre-gate cleaning. SC1 solution is used for pre-gate cleaning. Further, a sacrificial oxidation process can also be performed on the wafer, and then the natural oxide layer on the surface is removed to improve the surface morphology of the silicon carbide.

[0029] Specifically, in the step S10, the thickness range of the first oxide layer is 10 Å to 100 Å, the temperature range of the wet oxygen pretreatment is 650 °C to 1150 °C, and the time of the wet oxygen pretreatment is 10 min to 200 min.

[0030] The first oxide layer is silicon oxide, the thickness of the first oxide layer is 50 Å, and the first oxide layer covers the silicon carbide substrate.

[0031] Step S20: Perform high-temperature thermal oxidation on the silicon carbide substrate forming the first oxide layer to grow a second oxide layer on the first oxide layer;

[0032] Preferably, dry oxygen oxidation is used for the high-temperature thermal oxidation.

[0033] Specifically, in step S20, the thickness of the second oxide layer is less than 20 nm, the temperature range of the high-temperature thermal oxidation is 650°C to 1500°C, and the time of the high-temperature thermal oxidation is 1 min to 120 min.

[0034] Preferably, the thickness of the second oxide layer is 12 nm, and the total thickness of the first oxide layer and the second oxide layer is measured by an ellipsometer to obtain the 5-point average thickness.

[0035] Step S30: Deposit an oxide film by ALD on the second oxide layer, and the oxide film includes silicon oxide and several hydroxide groups;

[0036] Specifically, in step S30, the temperature range of the ALD deposition is 260°C to 360°C.

[0037] Preferably, an ALD process precursor capable of generating silicon oxide and hydroxide groups is used. There are oxygen vacancies in the oxide film layer. The oxygen vacancies are similar to donor-like traps that bind positive charges. The oxide layer prepared by the traditional high-temperature thermal oxidation method alone captures electrons and generates negative fixed charges. The structure prepared by the method in this embodiment can generate a more left flat-band voltage compared with the traditional structure.

[0038] Step S40: Perform nitridation annealing on the first oxide layer, the second oxide layer and the oxide film to form a gate oxide layer on the wafer.

[0039] Preferably, the nitridation annealing is performed in a nitrogen monoxide atmosphere, the temperature of the nitridation annealing is selected as 1200°C, and the duration is 100 min.

[0040] Specifically, in step S40, the temperature of the nitridation annealing is less than or equal to the temperature of the high-temperature thermal oxidation, and the time of the nitridation annealing is 30 min to 180 min.

[0041] Preferably, in Example 1, the wet oxygen pretreatment temperature is 1000°C, the wet oxygen pretreatment time is 120 min, the high-temperature thermal oxidation temperature is 1400°C, the high-temperature thermal oxidation time is 2 min, and the ALD deposition temperature is 300°C.

[0042] Embodiment 2 of the present invention also provides a method for preparing a gate oxide layer. The difference between the method for preparing the gate oxide layer in this embodiment and the method for preparing the gate oxide layer in Embodiment 1 is as follows:

[0043] The temperature of the wet oxygen pretreatment is 650 °C.

[0044] Embodiment 3 of the present invention also provides a method for preparing a gate oxide layer. The difference between the method for preparing the gate oxide layer in this embodiment and the method for preparing the gate oxide layer in Embodiment 1 is as follows:

[0045] The temperature of the wet oxygen pretreatment is 1150 °C.

[0046] Embodiment 4 of the present invention also provides a method for preparing a gate oxide layer. The difference between the method for preparing the gate oxide layer in this embodiment and the method for preparing the gate oxide layer in Embodiment 1 is as follows:

[0047] The time of the wet oxygen pretreatment is 10 min.

[0048] Embodiment 5 of the present invention also provides a method for preparing a gate oxide layer. The difference between the method for preparing the gate oxide layer in this embodiment and the method for preparing the gate oxide layer in Embodiment 1 is as follows:

[0049] The time of the wet oxygen pretreatment is 200 min.

[0050] Embodiment 6 of the present invention also provides a method for preparing a gate oxide layer. The difference between the method for preparing the gate oxide layer in this embodiment and the method for preparing the gate oxide layer in Embodiment 1 is as follows:

[0051] The ALD deposition temperature is 260 °C.

[0052] Embodiment 7 of the present invention also provides a method for preparing a gate oxide layer. The difference between the method for preparing the gate oxide layer in this embodiment and the method for preparing the gate oxide layer in Embodiment 1 is as follows:

[0053] The ALD deposition temperature is 360 °C.

[0054] Comparative Example 1

[0055] A method for preparing a gate oxide layer, the difference between which and the method for preparing the gate oxide layer in Embodiment 1 is as follows:

[0056] The temperature of the wet oxygen pretreatment is 400 °C.

[0057] Comparative Example 2

[0058] A method for preparing a gate oxide layer, the difference between which and the method for preparing the gate oxide layer in Embodiment 1 is as follows:

[0059] The time of the wet oxygen pretreatment is 240 min.

[0060] Comparative Example 3

[0061] A method for preparing a gate oxide layer, which is different from the method for preparing the gate oxide layer in Example 1 in that:

[0062] The ALD deposition temperature is 250 °C.

[0063] Comparative Example 4

[0064] A method for preparing a gate oxide layer, which is different from the method for preparing the gate oxide layer in Example 1 in that:

[0065] Provide a wafer with an exposed silicon carbide substrate, clean the wafer; only perform high-temperature thermal oxidation on the wafer, the high-temperature thermal oxidation temperature is 1400 °C, and the high-temperature thermal oxidation duration is 13 min. It can be understood that the method for preparing the gate oxide layer in this comparative example is the traditional full thermal oxidation method.

[0066] The silicon carbide substrate with a deviation of 4° from the (11-20) crystal plane is selected for the experiment, doped with nitrogen element, and the doping concentration is 8e15 cm -3 , and the natural oxide layer on the wafer surface is removed through cleaning and sacrificial oxidation processes. Gate oxide layers are prepared on multiple wafers according to the methods for preparing the gate oxide layer in the above Examples 1 to 7 and Comparative Examples 1 to 4 respectively. Among them, annealing treatment is carried out in a nitrogen monoxide atmosphere. After the gate oxide layer is prepared, the oxide layer on the back of the wafer is removed using BOE etching solution. An aluminum electrode is formed on the front of the wafer through a sputtering process, and a test pattern is formed using a photolithography process and an aluminum etching solution. Aluminum metal is sputtered on the back of the wafer to form a back electrode for testing. Finally, the interface state density is measured by the high-frequency - quasi-static method, and the corresponding preparation parameters and test results are shown in the following table:

[0067]

[0068] It should be noted that in order to ensure the reliability of the verification results, when the above Examples 1 to 7 and Comparative Examples 1 to 4 of the present invention are correspondingly prepared into gate oxide layers, except for the above different parameters, other processes and parameters should be kept consistent.

[0069] It can be obtained from the above table that the gate oxide layer prepared by the method for preparing the gate oxide layer provided in Example 1 of the present invention has a significantly reduced interface state density compared with Comparative Example 4, that is, compared with the traditional full thermal oxidation gate oxide layer. The trap in the gate oxide layer prepared in Example 1 captures positive charges and generates positive fixed charges, resulting in a more leftward flat-band voltage compared with the traditional full thermal oxidation gate oxide layer. By controlling each parameter within a preset range, the stability of the overall structure can be effectively ensured, and the interface quality of the gate oxide layer can be greatly improved.

[0070] In some embodiments, the present invention further provides a MOSFET, which includes a gate oxide layer prepared by the method for preparing the gate oxide layer in the above-mentioned Embodiment 1.

[0071] In some embodiments, the present invention further provides an electronic device, which includes the MOSFET as described in the above embodiments.

[0072] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0073] The above-described embodiments merely represent several implementation manners of the present invention, and the description thereof is relatively specific and detailed. However, it should not be construed as a limitation to the scope of the patent of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the appended claims.

Claims

1. A method for preparing a gate oxide layer, characterized in that: The steps include: Providing a silicon carbide substrate, cleaning the silicon carbide substrate, and performing a wet oxygen pretreatment to form a first oxide layer on the surface of the silicon carbide substrate; Performing high-temperature thermal oxidation on the silicon carbide substrate on which the first oxide layer is formed, so as to grow a second oxide layer on the first oxide layer, wherein the temperature range of the high-temperature thermal oxidation is 650° C. to 1500° C., and the time of the high-temperature thermal oxidation is 1 min to 120 min; ALD deposits an oxide film on the second oxide layer, wherein the oxide film includes silicon oxide and a plurality of hydroxide groups; The first oxide layer, the second oxide layer and the oxide film are subjected to nitridation annealing to form a gate oxide layer on the silicon carbide substrate.

2. The method for preparing a gate oxide layer according to claim 1, characterized in that: The thickness of the first oxide layer ranges from 10Å to 100Å.

3. The method for preparing a gate oxide layer according to claim 1, characterized in that: The thickness of the second oxide layer is less than 20 nm.

4. The method for preparing a gate oxide layer according to claim 1, characterized in that: The temperature range of the wet oxygen pretreatment is 650° C. to 1150° C., and the time of the wet oxygen pretreatment is 10 min to 200 min.

5. The method for preparing a gate oxide layer according to claim 1, characterized in that: The temperature range of the ALD deposition is 260°C to 360°C.

6. The method for preparing a gate oxide layer according to claim 1, characterized in that: The temperature of the nitridation annealing is less than or equal to the temperature of the high-temperature thermal oxidation, and the time of the nitridation annealing is 30 min to 180 min.

7. A MOSFET comprising a gate oxide layer, characterized in that: The gate oxide layer is prepared by the gate oxide layer preparation method according to any one of claims 1 to 6.

8. An electronic device, characterized in that: Comprising a MOSFET as claimed in claim 7.

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