Method for judging position of silicon wafer in etching reaction cavity
By comparing the actual etching rate uniformity and the standard etching rate uniformity of the silicon wafer to be tested, the problem of positioning deviation of the silicon wafer on the etching equipment is solved, and a higher etching accuracy is achieved, ensuring the quality of chip manufacturing.
Patent Information
- Application Number
- CN202411893251.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-20
- Publication Date
- 2025-04-08
AI Technical Summary
During chip manufacturing, the positioning deviation of the silicon wafer when etching the metal contact window leads to inconsistent etching rates, which may cause excessive etching of the underlying metal or incomplete opening of the contact holes, resulting in chip failure. The prior art determines the position of the silicon wafer by monitoring the helium flow, but due to the inaccuracy of the helium flow, the judgment of the positioning of the silicon wafer is affected.
By locking the change in the actual etching rate uniformity of the edge of the silicon wafer to be tested and comparing it with the standard etching rate uniformity, the accuracy of the position of the silicon wafer on the etching device is judged. This method sets the standard etching rate uniformity through standard silicon wafers, providing a reference standard for the silicon wafer to be tested.
This method can more accurately judge the positioning accuracy of the silicon wafer on the etching device, ensure the accuracy of the silicon wafer during etching, and avoid damage or failure of the chip after etching.
Smart Images
Figure CN119786371A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of semiconductor manufacturing, and in particular to a method for determining the position of a silicon wafer in an etching reaction chamber. Background Art
[0002] In the chip manufacturing process, the etching process of the metal contact window plays a key role. If there is a large deviation in the positioning of the silicon wafer when etching the metal contact window, it will lead to differences in the etching rate of different areas of the silicon wafer. This inconsistency may cause the underlying metal in some areas to be over-etched, while the contact holes in other areas are not fully opened, resulting in chip failure. Therefore, strict requirements are placed on the positioning accuracy of the silicon wafer when etching the metal contact window.
[0003] In the prior art, the placement of the silicon wafer is usually monitored by monitoring the helium (He) flow rate on the back of the silicon wafer. Specifically, the He flow rate change can be monitored in real time by a gas flow meter inside the cavity. If the silicon wafer is placed accurately, the He flow rate in the cavity is within the normal value range; if the silicon wafer is placed offset, the He flow rate in the cavity will increase significantly.
[0004] When the placement of the silicon wafer is monitored by He flow, the He flow will often damage the electrode surface due to etching reaction, or the gas channel for introducing He is blocked by residual substances, resulting in inaccurate monitoring results of the He flow in the cavity, which in turn affects the judgment of the silicon wafer positioning. Summary of the invention
[0005] In order to solve the technical problems in the prior art, the purpose of the present invention is to provide a method for determining the position of a silicon wafer in an etching reaction chamber. The method locks the change in the actual etching rate uniformity of the edge of the silicon wafer to be tested, and compares the actual etching rate uniformity with the standard etching rate uniformity, thereby monitoring the accuracy of the silicon wafer placement position.
[0006] To achieve the above object, the present invention provides a method for determining the position of a silicon wafer in an etching reaction chamber, comprising:
[0007] S01: placing a standard silicon wafer in an etching device, ensuring that the standard silicon wafer is placed in a standard position on the etching device;
[0008] S02: using the standard silicon wafer to perform etching under predetermined parameters;
[0009] S03: After etching, detecting etching rates of a plurality of first sampling points on a first predetermined area at the edge of the standard silicon wafer;
[0010] S04: obtaining a standard etching rate uniformity of the standard silicon wafer according to the etching rates of a predetermined number of the first sampling points;
[0011] S05: placing the silicon wafer to be tested in the etching equipment;
[0012] S06: using the silicon wafer to be tested to perform etching under the predetermined parameters;
[0013] S07: Detecting etching rates of a plurality of second sampling points on a second predetermined area at the edge of the silicon wafer to be tested, wherein the second predetermined area has the same coverage as the first predetermined area, and the second sampling points have the same setting positions as the first sampling points;
[0014] S08: Obtaining the actual etching rate uniformity of the silicon wafer to be tested according to the etching rates of the predetermined number of the second sampling points;
[0015] S09: Compare the actual etching rate uniformity with the standard etching rate uniformity, and determine the offset of the silicon wafer to be tested according to the comparison result.
[0016] Optionally, in step S04, the method for obtaining the standard etching rate uniformity of the standard silicon wafer includes:
[0017] Etching is performed on a plurality of the standard silicon wafers, and an etching rate uniformity of each of the standard silicon wafers is obtained, and a maximum value among the plurality of etching rate uniformities is taken as the standard etching rate uniformity.
[0018] Optionally, in step S04, the method for obtaining the standard etching rate uniformity of the standard silicon wafer includes:
[0019] Etching a plurality of the standard silicon wafers, and obtaining the etching rate uniformity of each of the standard silicon wafers; setting a compensation value for the etching rate uniformity, and taking the sum of the maximum value of the plurality of etching rate uniformities and the compensation value as the standard etching rate uniformity.
[0020] Optionally, the compensation value is set to 0.1% to 0.3%.
[0021] Optionally, the standard etching rate uniformity is less than or equal to 3%.
[0022] Optionally, the surfaces of the silicon wafer to be tested and the standard silicon wafer are both covered with oxide films of the same thickness.
[0023] Optionally, in step S09, the step of determining the offset of the silicon wafer to be tested according to the comparison result includes:
[0024] If the actual etching rate uniformity is greater than the standard etching rate uniformity, it is determined that the placement position of the silicon wafer to be tested on the etching equipment is offset;
[0025] If the actual etching rate uniformity is less than or equal to the standard etching rate uniformity, it is determined that the placement position of the silicon wafer to be tested on the etching equipment is accurate.
[0026] Optionally, the radii of the silicon wafer to be tested and the standard silicon wafer are both 150 mm, and the radii of the first predetermined area and the second predetermined area are both in the range of 145 mm to 150 mm.
[0027] Optionally, in step S03, the method for acquiring a plurality of the first sampling points on the standard silicon wafer includes:
[0028] Selecting first sampling circles with at least two radius values on the first predetermined area of the standard silicon wafer, and selecting a plurality of first sampling points at equal intervals from the first sampling circles;
[0029] In step S07, the method for acquiring a plurality of the second sampling points on the silicon wafer to be tested includes:
[0030] Selecting second sampling circles with at least two radius values on the second predetermined area of the silicon wafer to be tested, and selecting a plurality of second sampling points from the second sampling circles at equal intervals.
[0031] Optionally, the first sampling circle and / or the second sampling circle include an external sampling circle and an internal sampling circle, the radius of the external sampling circle is greater than the radius of the internal sampling circle; the number of the first sampling points and / or the second sampling points selected on the external sampling circle is greater than or equal to 24, and the number of the first sampling points and / or the second sampling points selected on the internal sampling circle is greater than or equal to 16.
[0032] Optionally, in step S04, the step of obtaining the etching rates of a predetermined number of the first sampling points includes:
[0033] After acquiring the etching rates of all the first sampling points, removing the highest etching rates of the target number and removing the lowest etching rates of the target number, thereby obtaining the etching rates of a predetermined number of the first sampling points;
[0034] In step S08, the step of obtaining the etching rates of the predetermined number of the second sampling points includes:
[0035] After acquiring the etching rates of all the second sampling points, the highest etching rate of the target number is removed, and the lowest etching rate of the target number is removed, so as to obtain the etching rates of the predetermined number of the second sampling points.
[0036] Optionally, step S03 further includes: establishing a standard etching rate distribution map according to the etching rates of all the first sampling points;
[0037] Step S07 also includes: establishing an actual etching rate distribution map according to the etching rates of all the second sampling points.
[0038] The present application provides a method for determining the position of a silicon wafer in an etching reaction chamber. The method sets a standard etching rate uniformity through a standard silicon wafer, and can provide a reference standard for subsequent position determination of a silicon wafer to be tested. Specifically, the present application locks the change in the actual etching rate uniformity of the edge of the silicon wafer to be tested through the similarity between the etching rate distribution of the silicon wafer and the position of the concentric circles of the silicon wafer, and by comparing the actual etching rate uniformity with the standard etching rate uniformity, the positioning accuracy of the silicon wafer to be tested on the etching equipment is determined, thereby ensuring the accuracy of silicon wafer etching.
[0039] The method for determining the position of a silicon wafer is particularly suitable for calibrating an etching device before etching a metal contact window on the silicon wafer, so as to ensure the accuracy of etching the metal contact window on the silicon wafer and avoid damage or failure of the chip after etching. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] Figure 1 It is a schematic diagram of the etching effect of the metal contact window on the surface of the silicon wafer in the prior art;
[0041] Figure 2 A flow chart of a method for determining the position of a silicon wafer in an etching reaction chamber in a preferred embodiment of the present invention;
[0042] Figure 3 This is a schematic diagram of an application scenario in which a standard silicon wafer is placed on an etching device in a preferred embodiment of the present invention;
[0043] Figure 4 This is a schematic diagram of an application scenario in which a silicon wafer to be tested is placed on an etching device in a preferred embodiment of the present invention, wherein the placement position of the silicon wafer to be tested on the etching device is offset relative to the standard position;
[0044] Figure 5 A schematic diagram of the distribution of first sampling points on the surface of a standard silicon wafer in a preferred embodiment of the present invention;
[0045] Figure 6 A schematic diagram of the distribution of second sampling points on the surface of the silicon wafer to be tested in a preferred embodiment of the present invention;
[0046] Figure 7 This is a schematic diagram showing the distribution of third sampling points on the surface of a silicon wafer in another preferred embodiment of the present invention;
[0047] Figure 8 A schematic diagram of the standard etching rate distribution of each first sampling point on the surface of a standard silicon wafer in a preferred embodiment of the present invention;
[0048] Fig. 9A schematic diagram of the actual etching rate distribution of each second sampling point in a second predetermined area on the surface of the silicon wafer to be tested in another preferred embodiment of the present invention;
[0049] Fig.10 It is a curve diagram of the etching rate uniformity of the silicon wafer to be tested under different offset degrees in a preferred embodiment of the present invention, wherein the horizontal axis is the offset (mm) of the silicon wafer to be tested relative to the standard position, and the vertical axis is the etching rate uniformity (%) of the silicon wafer to be tested.
[0050] The reference numerals are described as follows:
[0051] Silicon wafer 1; first metal contact window 10; second metal contact window 20;
[0052] Standard silicon wafer 11; silicon wafer to be tested 12; example silicon wafer 13; lower electrode 21; plasma 22; base 23; gas channel 24; first predetermined area 31; second predetermined area 32; first sampling point 41; second sampling point 42; third sampling point 43; first sampling circle 51; second sampling circle 52; outer sampling circle 53; inner sampling circle 54. DETAILED DESCRIPTION
[0053] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0054] The orientation or position relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like are based on the orientation or position relationship shown in the drawings and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred mechanism or element must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting the present invention.
[0055] In the present invention, unless otherwise clearly specified and limited, the terms "installation", "connection", "fixation" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or a connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0056] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.
[0057] Furthermore, those skilled in the art may combine and associate different embodiments or examples and features of different embodiments or examples described in this specification without mutual contradiction.
[0058] Reference Figure 1 As shown, in the prior art, if there is a large deviation in the positioning of the silicon wafer 1 when etching the metal contact window (Contact), the etching rate of a part of the silicon wafer 1 will be accelerated, while the etching rate of another part will be slowed down. Specifically, the positioning deviation of the silicon wafer 1 will cause the bottom metal of the silicon wafer 1 to be over-etched when etching the first metal contact window 10, thereby damaging the contact metal. At the same time, the positioning deviation of the silicon wafer 1 will also cause the metal contact hole on the silicon wafer 1 to fail to open completely when etching the second metal contact window 20, and the silicon wafer 1 will be unable to derive electrical signals, thereby causing the silicon wafer 1 to fail.
[0059] It can be seen that the metal contact window is a channel for the chip device to connect to the metal above, and the etching accuracy will directly affect the manufacturing quality of the chip. When etching the metal contact window, the positioning accuracy of the silicon wafer 1 is required to be high. If the positioning deviation of the silicon wafer 1 is large, the above problems will occur, thereby causing damage or failure of the silicon wafer 1.
[0060] The present application provides a method for determining the position of a silicon wafer 1 in an etching reaction chamber. The method can calibrate the placement of the silicon wafer 1 on the etching equipment to ensure that the silicon wafer 1 is accurately positioned when etching a metal contact window, thereby ensuring the etching accuracy of the silicon wafer 1 after etching the metal contact window.
[0061] like Figure 2 to Figure 6 As shown, the present invention provides a method for determining the position of a silicon wafer in an etching reaction chamber, comprising:
[0062] S01: placing a standard silicon wafer 11 in an etching device, and ensuring that the standard silicon wafer 11 is placed in a standard position on the etching device, specifically placing the standard silicon wafer 11 on the lower electrode 21 of the etching device.
[0063] S02: Etching is performed on an etching device using a standard silicon wafer 11 under predetermined parameters.
[0064] S03: After etching, the etching rates of a plurality of first sampling points 41 on the first predetermined area 31 at the edge of the standard silicon wafer 11 are detected.
[0065] S04: Obtaining a standard etching rate uniformity (BSL ER Uni %) of the standard silicon wafer 11 according to the etching rates of a predetermined number of first sampling points 41 .
[0066] S05: placing the silicon wafer 12 to be tested in an etching device, specifically placing the silicon wafer 12 to be tested on the lower electrode 21 of the etching device.
[0067] S06: Etching is performed on the etching equipment using the silicon wafer 12 to be tested under the same predetermined parameters.
[0068] S07: Detect the etching rates of multiple second sampling points 42 on the second predetermined area 32 at the edge of the silicon wafer 12. The second predetermined area 32 has the same coverage as the first predetermined area 31, and the second sampling points 42 and the first sampling points 41 are arranged at the same position.
[0069] S08: Obtaining the actual etching rate uniformity (ER Uni %) of the silicon wafer 12 to be tested according to the etching rates of the predetermined number of second sampling points 42 .
[0070] S09: Compare the actual etching rate uniformity with the standard etching rate uniformity, and determine the offset of the silicon wafer 12 to be tested according to the comparison result.
[0071] The present application provides a method for determining the position of a silicon wafer in an etching reaction chamber. The method sets a standard etching rate uniformity (i.e., a reference value of etching rate uniformity) through a standard silicon wafer 11, and can provide a reference standard for determining the position of a subsequent silicon wafer 12 to be tested. In addition, the present application locks the change in the actual etching rate uniformity at the edge of the silicon wafer 12 to be tested through the similarity between the etching rate distribution of the silicon wafer and the position of the concentric circles of the silicon wafer, and by comparing the actual etching rate uniformity with the standard etching rate uniformity, the accuracy of the positioning of the silicon wafer 12 to be tested on the etching equipment is determined, thereby ensuring the accuracy of etching the silicon wafer 1.
[0072] Specifically, the actual etching rate uniformity of the silicon wafer 12 to be tested can be compared with the standard etching rate uniformity to determine whether the placement position of the silicon wafer 12 to be tested on the etching equipment is offset, thereby monitoring the accuracy of the placement position of the silicon wafer 1. This method is more sensitive and accurate than monitoring by He flow rate, and is particularly suitable for calibrating the etching equipment before etching the metal contact window on the silicon wafer 1, so as to ensure the accuracy of etching the metal contact window on the silicon wafer 1 and avoid damage or failure of the chip after etching.
[0073] It should be noted that the standard silicon wafer and the silicon wafer to be tested in this application both refer to the monitor wafer used to monitor the machine operating status and process parameter stability during chip production. The chip structure is not set on the monitor wafer, but only one or several layers of thin film (such as silicon dioxide film). Since the structure of the monitor wafer is simple and has high consistency, this application uses the monitor wafer used during silicon wafer processing as the standard silicon wafer and the silicon wafer to be tested, and covers the monitor wafer with a film of the same thickness, so that it can ensure that the standard silicon wafer and the silicon wafer to be tested are placed in the same position on the lower electrode 21 during the detection process. The other detection conditions are the same, thereby ensuring the consistency of the processing conditions of the standard silicon wafer and the silicon wafer to be tested, and further ensuring the accuracy of the detection results.
[0074] Further, when measuring the film thickness at the first sampling point 41 (or the second sampling point 42), a detection instrument (such as a thickness measuring instrument) can be used to measure the film thickness of the standard silicon wafer 11 (or the silicon wafer to be tested 12) before the etching process to obtain the first film thickness H1. Then, the detection instrument is used to measure the film thickness of the standard silicon wafer 11 (or the silicon wafer to be tested 12) after the etching process to obtain the second film thickness H2. The ratio of the difference between the first film thickness H1 and the second film thickness H2 of the first sampling point 41 (or the second sampling point 42) to the etching time t is the etching rate V of the first sampling point 41 (or the second sampling point 42), that is, V=(H1-H2) / t. Based on this method, the etching rate of each first sampling point 41 (or the second sampling point 42) on the standard silicon wafer 11 (or the silicon wafer to be tested 12) can be obtained.
[0075] Reference Figure 7 As shown, in a specific case, there are 5 third sampling points 43 on the example silicon wafer 13 (the points with the maximum etching rate and the points with the minimum etching rate have been filtered out). The film thickness of each third sampling point 43 on the example silicon wafer 13 before etching is obtained as: 3500A, 3510A, 3499A, 3501A, 3493A, and the film thickness of each third sampling point 43 on the example silicon wafer 13 after etching is obtained after 60s of etching is: 1500A, 1455A, 1524A, 1451A, 1563A. The etching rates of each third sampling point 43 on the example silicon wafer 13 are calculated as: 2000A / min, 2055A / min, 1975A / min, 2055A / min and 1930A / min respectively. The average etching rate of the example silicon wafer 13 calculated by the above 5 third sampling points 43 is: 2003A / min. The etching rate uniformity ER Uni% of the example silicon wafer 13 is = (2055-1930) / (2x2003) = 3.12%.
[0076] It should be noted that the standard position of the standard silicon wafer 11 placed on the etching equipment refers to the position where the distance between the edge of the silicon wafer 1 and the edge of the lower electrode 21 is within the standard range. In a specific example, the position where the distance between the edge of the standard silicon wafer 11 and the edge of the lower electrode is 0.2 mm can be set as the standard position for placing the standard silicon wafer 11, but it is not limited thereto. In other examples, the standard range of the distance between the silicon wafer 1 and the lower electrode 21 can also be set to other values or ranges as needed.
[0077] It should also be noted that the coverage of the first predetermined area 31 on the standard silicon wafer 11 is the same as the coverage of the second predetermined area 32 on the silicon wafer to be tested 12, and the position of the first sampling point 41 selected on the first predetermined area 31 is the same as the position of the second sampling point 42 selected on the second predetermined area 32, that is, the position of the first sampling point 41 selected on the standard silicon wafer 11 and the position of the second sampling point 42 selected on the silicon wafer to be tested 12 are the same (refer to Figure 4 and Figure 5 ).
[0078] Such a setting can ensure that the positions of the sampling points selected after etching the standard silicon wafer 11 and the silicon wafer to be tested 12 are the same, avoiding the deviation in the sampling point selection positions of the standard silicon wafer 11 and the silicon wafer to be tested 12 causing the deviation between the standard etching rate uniformity and the actual etching rate uniformity itself, thereby affecting the judgment result.
[0079] In addition, the monitoring of the position of the silicon wafer 1 in the etching equipment can be performed in the daily detection steps of the equipment without adding additional processes.
[0080] Continue to refer to Figure 3 and Figure 4 The etching process of the silicon wafer 1 includes: introducing etching gas into the etching chamber, exciting the etching gas into a chemically reactive plasma 22, and etching the to-be-etched area of the silicon wafer 1 by the plasma 22, thereby obtaining the silicon wafer 1 after the etching process. Of course, in addition to the above-mentioned methods, other related technologies can also be referred to, and the specific etching process is not limited in the embodiments of the present application.
[0081] In more detail, the standard silicon wafer 11 and the silicon wafer to be tested 12 are both placed on the lower electrode 21 of the etching device, and the lower electrode 21 is arranged on the base 23 of the etching device. The base 23 is also provided with a gas channel 24. When the etching device is working, helium is introduced through the gas channel 24 to reduce the temperature of the surface of the silicon wafer 1.
[0082] It should be known that the predetermined parameters include, but are not limited to, chamber pressure, gas flow, RF power, reaction time, etc. The standard silicon wafer 11 and the silicon wafer to be tested 12 are both etched using the benchmark etching conditions (BSL recipe) so that the standard silicon wafer 11 and the silicon wafer to be tested 12 have the same chamber pressure, gas flow, RF power, and reaction time during etching, ensuring that the process parameters of the standard silicon wafer 11 and the silicon wafer to be tested 12 are consistent during the etching process, and at this time, the standard silicon wafer 11 and the silicon wafer to be tested 12 have the same etching conditions.
[0083] For example, when etching the standard silicon wafer 11 and the silicon wafer to be tested 12, the chamber pressure can be set to 20mT, the high RF power can be set to 2000W, the low RF power can be set to 1000W, the flow rate of gas CF4 can be set to 200sccm, the reaction time can be set to 60s, the temperature of the lower electrode 21 can be set to 20°C, the temperature of the side wall of the etching chamber and the temperature of the upper electrode can be set to 120°C, and the pressure in the central area and the edge area of the silicon wafer 1 can be set to 40Torr. The above etching process parameters are used as the benchmark etching conditions when etching the silicon wafer 1.
[0084] Since other variables are the same for the standard silicon wafer 11 and the silicon wafer to be tested 12 during the entire process of etching and obtaining the etching rate uniformity, there may only be one variable caused by the different placement of the silicon wafer 1. Therefore, after comparing the standard etching rate uniformity obtained by the standard silicon wafer 11 with the actual etching rate uniformity obtained by the silicon wafer to be tested 12, if there is a difference between the standard etching rate uniformity and the actual etching rate uniformity, it can be indicated that there is a difference in the placement position of the standard silicon wafer 11 and the silicon wafer to be tested 12 on the lower electrode 21.
[0085] In a preferred embodiment, in step S09, the step of determining the offset of the silicon wafer 12 to be tested according to the comparison result includes:
[0086] If the actual etching rate uniformity is greater than the standard etching rate uniformity, it is judged that the placement position of the silicon wafer 12 to be tested on the etching equipment has shifted, indicating that the silicon wafer 12 to be tested has shifted significantly relative to the standard position. At this time, it is necessary to adjust the positioning position of the silicon wafer 1 on the etching equipment through a mechanical device (such as a manipulator) to ensure the accuracy of etching the silicon wafer 1.
[0087] If the actual etching rate uniformity is less than or equal to the standard etching rate uniformity, it is judged that the placement position of the silicon wafer 12 to be tested on the etching equipment is accurate, indicating that the silicon wafer 12 to be tested has no obvious deviation relative to the standard position, and there is no need to change the positioning position of the silicon wafer 1 on the etching equipment.
[0088] In a preferred embodiment, in step S04, the method for obtaining the standard etching rate uniformity of the standard silicon wafer 11 includes:
[0089] A plurality of standard silicon wafers 11 are etched, and the etching rate uniformity of each standard silicon wafer 11 is obtained, and the maximum value of the plurality of etching rate uniformities is taken as the standard etching rate uniformity.
[0090] In more detail, since the uniformity of the etching rate of the silicon wafer 1 during etching will be affected by many factors, such as gas flow, gas type, temperature and differences in the silicon wafer itself, even if multiple silicon wafers 1 are placed in the same position on the lower electrode 21, there will be differences in the uniformity of the etching rate of each silicon wafer 1 after etching.
[0091] In order to ensure the accuracy of the obtained standard etching rate uniformity, in actual testing, a sufficient number of standard silicon wafers 1 can be selected for testing, and the value range of the etching rate uniformity of the multiple standard silicon wafers 1 can be obtained. Preferably, the maximum value in the value range of the etching rate uniformity of the multiple standard silicon wafers 1 can be used as the standard etching rate uniformity to ensure that when the positioning deviation of the silicon wafer 12 to be tested is detected, the silicon wafer 12 to be tested has indeed undergone a large position deviation relative to the standard position, thereby ensuring the accuracy of the monitoring result.
[0092] In another preferred embodiment, in step S04, the method for obtaining the standard etching rate uniformity of the standard silicon wafer 11 includes:
[0093] Etch multiple standard silicon wafers 11, and obtain the etching rate uniformity of each standard silicon wafer 11. Set the compensation value of the etching rate uniformity, and take the sum of the maximum value of the multiple etching rate uniformities and the compensation value as the standard etching rate uniformity. In this way, the standard etching rate uniformity can be increased by a certain value based on the maximum value of the etching rate uniformity. If the actual etching rate uniformity of the silicon wafer 12 to be tested is greater than the standard etching rate uniformity, it can be more accurately determined that the positioning of the silicon wafer 12 to be tested has deviated, thereby ensuring the accuracy of the test result.
[0094] Generally speaking, the compensation value is set to 0.1% to 0.3%, that is, the maximum value of the etching rate uniformity is increased by 0.1% to 0.3% and then used as the standard etching rate uniformity. In other cases, the compensation value can also be set in other numerical ranges as needed, for example, the compensation value can also be set to be above 0.3%.
[0095] Preferably, the standard etching rate uniformity is less than or equal to 3%, because the etching rate uniformity obtained after etching multiple standard silicon wafers 11 varies within 3%, that is, the etching rate uniformity of multiple standard silicon wafers 11 is less than 3%, so the standard etching rate uniformity can be set to 3%, that is, BSL ER Uni% = 3%. In this way, when the etching rate uniformity of the silicon wafer 12 to be tested is greater than 3%, it can be determined that the positioning of the silicon wafer 12 to be tested has deviated, and then the placement position of the silicon wafer 12 to be tested on the lower electrode 21 needs to be adjusted by a mechanical device.
[0096] In one example, the standard etching rate uniformity is set to 3%. If the actual etching rate uniformity of the silicon wafer 12 to be tested is measured to be less than 3%, for example, 2.8%, then it is determined that the placement position of the silicon wafer 12 to be tested on the etching equipment is accurate. If the actual etching rate uniformity of the silicon wafer 12 to be tested is measured to be greater than or equal to 3%, for example, 3.5%, then it is determined that the placement position of the silicon wafer 12 to be tested is greatly offset, and the placement position of the silicon wafer 1 on the lower electrode 21 needs to be readjusted.
[0097] Reference Fig.10 As shown in the figure, each point in the figure represents the corresponding relationship between the offset of the silicon wafer 12 to be tested relative to the standard position and the uniformity of the etching rate of the silicon wafer 12 to be tested. The points in the figure are connected by a curve to show the changing trend of the uniformity of the etching rate of the silicon wafer 12 to be tested with the offset of the silicon wafer 12 to be tested.
[0098] like Fig.10 As shown, the etching rate uniformity of the silicon wafer 12 to be tested increases with the increase of the offset of the silicon wafer 12 to be tested relative to the standard position. In the figure, when the offset of the silicon wafer 12 to be tested relative to the standard position is less than or equal to 0.2mm, the etching rate uniformity of the silicon wafer 12 to be tested is less than or equal to 3%, that is, ER Uni%≤3%, and the offset degree of the silicon wafer 12 to be tested is within an acceptable range; when the offset of the silicon wafer 12 to be tested relative to the standard position increases by 0.1mm, the etching rate uniformity (ER Uni%) of the silicon wafer 12 to be tested increases by 0.5% accordingly. For example, when the offset of the silicon wafer 12 to be tested relative to the standard position is 0.3mm, the etching rate uniformity (ER Uni%) of the silicon wafer 12 to be tested is approximately 3.5%; when the offset of the silicon wafer 12 to be tested relative to the standard position is 0.4mm, the etching rate uniformity (ER Uni%) of the silicon wafer 12 to be tested is approximately 4%, and so on. Therefore, when the offset of the silicon wafer 12 to be tested relative to the standard position is greater than 0.2 mm, the etching rate uniformity of the silicon wafer 12 to be tested is greater than 3%, that is, ERUni%>3%. At this time, it can be judged that the silicon wafer 12 to be tested has shifted, and the positioning position of the silicon wafer 12 to be tested on the etching equipment needs to be readjusted.
[0099] It should be understood that the process parameters of the etching chamber can be changed as needed when etching the silicon wafer 1, especially for abnormal chambers or lower electrodes that have been used for a long time. After the process conditions of the etching chamber are changed, the standard etching rate uniformity of the standard silicon wafer 11 and the actual etching rate uniformity of the silicon wafer to be tested 12 may change, so the specification of the etching rate uniformity (Uni%) of the silicon wafer 1 can be adjusted by changing the process parameters of the etching chamber.
[0100] Preferably, the surfaces of the silicon wafer 12 to be tested and the standard silicon wafer 11 are both covered with an oxide film (e.g., a silicon dioxide film) of the same thickness. At this time, both the standard silicon wafer 11 and the silicon wafer 12 to be tested use an oxide film (Oxide) control wafer and etch the oxide film under benchmark etching conditions to obtain an etching rate uniformity value. This can avoid the difference between the standard etching rate uniformity and the actual etching rate uniformity caused by the difference in surface conditions of the standard silicon wafer 11 and the silicon wafer 12 to be tested, and can effectively ensure the consistency of the etching process of the standard silicon wafer 11 and the silicon wafer 12 to be tested.
[0101] Reference Figure 8 and Fig. 9 As shown, combined with Figure 5 and Figure 6 In a specific example, the radii of the standard silicon wafer 11 and the silicon wafer to be tested 12 are both 150 mm, the radius value range of the first predetermined area 31 selected on the standard silicon wafer 11 is 145 mm to 150 mm, and the radius value range of the second predetermined area 32 selected on the silicon wafer to be tested 12 is also 145 mm to 150 mm, that is, the detection range of the standard silicon wafer 11 and the silicon wafer to be tested 12 are both set within the annular area with a radius value of 145 mm to 150 mm.
[0102] Reference Figure 4 As shown, in step S03, the method for acquiring a plurality of first sampling points 41 on the standard silicon wafer 11 includes:
[0103] A first sampling circle 51 with at least one radius value is selected on the first predetermined area 31 of the standard silicon wafer 11, and a plurality of first sampling points 41 are respectively selected from the first sampling circle 51, and the standard etching rate uniformity of the standard silicon wafer 11 is calculated through the etching rates of the predetermined number of first sampling points 41.
[0104] Preferably, at least two first sampling circles 51 with radius values are selected on the first predetermined area 31 of the standard silicon wafer 11, and a plurality of first sampling points 41 are selected at equal intervals from the first sampling circles 51. In this way, by selecting a plurality of first sampling points 41 at equal intervals on a plurality of first sampling circles 51, interference caused by poor flatness of thin film deposition on the standard silicon wafer 11 can be reduced to a greater extent, thereby ensuring the accuracy of the detection result.
[0105] Reference Figure 5 As shown, in step S07, the method for obtaining a plurality of second sampling points 42 on the silicon wafer 12 to be tested includes:
[0106] A second sampling circle 52 with at least one radius value is selected on the second predetermined area 32 of the silicon wafer 12 to be tested, and multiple second sampling points 42 are selected from the second sampling circle 52 respectively, and the actual etching rate uniformity of the silicon wafer 12 to be tested is calculated through the etching rates of the predetermined number of second sampling points 42.
[0107] Preferably, at least two second sampling circles 52 with radius values are selected on the second predetermined area 32 of the silicon wafer 12 to be tested, and multiple second sampling points 42 are selected at equal intervals from the second sampling circles 52. In this way, by selecting multiple second sampling points 42 at equal intervals on multiple second sampling circles 52, interference caused by poor flatness of thin film deposition on the silicon wafer 12 to be tested can be reduced to a greater extent, thereby ensuring the accuracy of the test results.
[0108] Reference Figure 7 As shown, step S03 preferably further includes: establishing a standard etching rate distribution diagram according to the etching rates of all first sampling points 41 , so that the operator can more intuitively know the etching rate variation degree of each position on the surface of the standard silicon wafer 11 .
[0109] like Figure 8 As shown, after the standard silicon wafer 11 is etched, when the standard silicon wafer 11 is placed in the standard position, the etching rates of the first sampling points 41 on the first sampling circle 51 with the same radius value on the standard silicon wafer 11 are similar. The etching rates of the first sampling points 41 on the first sampling circles 51 with different radius values on the standard silicon wafer 11 vary linearly with the radius value, and the etching rate of the standard silicon wafer 11 gradually changes (increases or decreases) from the center of the standard silicon wafer 11 to the edge of the standard silicon wafer 11.
[0110] Reference Fig. 9 As shown, step S07 further includes: establishing an actual etching rate distribution diagram according to the etching rates of all second sampling points 42, so that the operator can more intuitively know the etching rate variation degree of each position on the surface of the silicon wafer 12 to be tested.
[0111] like Fig. 9 As shown, when the placement position of the silicon wafer 12 to be tested is offset, the centers of the concentric circles with the same etching rate on the silicon wafer 12 to be tested no longer coincide with the center of the silicon wafer 12 to be tested. At this time, the etching rates of the second sampling points 41 on each second sampling circle 52 concentric with the silicon wafer 12 to be tested are different. Therefore, the etching rate uniformity of the silicon wafer 12 to be tested can be calculated according to the etching rates of the second sampling points 41 on the second sampling circle 52 of the silicon wafer 12 to be tested, and the offset of the silicon wafer 12 to be tested can be determined according to the etching rate uniformity of the silicon wafer 12 to be tested.
[0112] Furthermore, when the placement position of the silicon wafer 12 to be tested on the lower electrode 21 is offset, after etching, the etching speeds of the second sampling points 42 on the edge of the silicon wafer 12 to be tested are quite different. Therefore, when the second sampling point 42 is selected on the edge of the silicon wafer 12 to be tested, the obtained etching rate uniformity can better reflect the degree of offset of the placement of the silicon wafer 12 to be tested.
[0113] Preferably, the total number of the first sampling points 41 and / or the second sampling points 42 is greater than or equal to 40, that is, no less than 40 monitoring points are selected on the standard silicon wafer 11 and / or the silicon wafer to be tested 12 to further eliminate the interference caused by poor flatness of thin film deposition on the standard silicon wafer 11 and / or the silicon wafer to be tested 12.
[0114] Continue to refer to Figure 4 and Figure 5 In a specific embodiment, the first sampling circle 51 and / or the second sampling circle 52 includes an outer sampling circle 53 and an inner sampling circle 54, the radius of the outer sampling circle 53 is greater than the radius of the inner sampling circle 54, and the outer sampling circle 53 and the inner sampling circle 54 are both within an annular region with a radius value of 145 mm to 150 mm. The number of the first sampling points 41 and / or the second sampling points 42 selected on the outer sampling circle 53 is greater than or equal to 24, and the number of the first sampling points 41 and / or the second sampling points 42 selected on the inner sampling circle 54 is greater than or equal to 16.
[0115] Reference Fig. 9 As shown, as a specific example, after the silicon wafer 12 to be tested is etched, an external sampling circle 53 and an internal sampling circle 54 can be selected in the second predetermined area 32 of the silicon wafer 12 to be tested, wherein the outer diameter D1 of the external sampling circle 53 is 148 mm, and the outer diameter D2 of the internal sampling circle 54 is 145 mm.
[0116] Preferably, in step S04, the step of obtaining the etching rates of a predetermined number of first sampling points 41 includes:
[0117] After obtaining the etching rates of all the first sampling points 41, the highest etching rate of the target number is removed, and the lowest etching rate of the target number is removed, thereby obtaining the etching rates of the predetermined number of first sampling points 41. In this way, the interference data caused by the sudden change in the flatness of the thin film deposition of the standard silicon wafer 11 can be basically removed, thereby ensuring the accuracy of the etching rate detected at each first sampling point 41.
[0118] Similarly, in step S08, the step of obtaining the etching rates of a predetermined number of second sampling points 42 includes:
[0119] After obtaining the etching rates of all the second sampling points 42, the highest etching rate of the target number is removed, and the lowest etching rate of the target number is removed, thereby obtaining the etching rates of the predetermined number of second sampling points 42. In this way, the interference data caused by the sudden change in the flatness of the thin film deposition on the silicon wafer 12 to be tested can be basically removed, thereby ensuring the accuracy of the etching rate detected at each second sampling point 42.
[0120] In a specific embodiment, after obtaining the etching rates of 40 first sampling points 41 (or second sampling points 42) on the standard silicon wafer 11 (or the silicon wafer to be tested 12), the two first sampling points 41 (or second sampling points 42) with the largest etching rates and the two first sampling points 41 (or second sampling points 42) with the smallest etching rates are removed to obtain the etching rates of 36 first sampling points 41 (or second sampling points 42). Then, the average etching rate ER_Ave of the 36 first sampling points 41 (or second sampling points 42) is calculated, and the etching rate uniformity of the standard silicon wafer 11 (or the silicon wafer to be tested 12) is calculated by the following formula:
[0121] ER Uni%=(ER_max–ER_min) / (ER_Ave*2)
[0122] In the formula, ER_max represents the maximum etching rate of the first sampling point 41 (or the second sampling point 42), and ER_min represents the minimum etching rate of the first sampling point 41 (or the second sampling point 42).
[0123] In summary, the present invention provides a method for determining the position of a silicon wafer in an etching reaction chamber, and the method sets a standard etching rate uniformity through a standard silicon wafer 11, which can provide a reference standard for determining the position of a subsequent silicon wafer 12 to be tested. In addition, the present application locks the change in the actual etching rate uniformity of the edge of the silicon wafer 12 to be tested through the similarity between the etching rate distribution of the silicon wafer 1 and the position of the concentric circles of the silicon wafer 1, and by comparing the actual etching rate uniformity with the standard etching rate uniformity, the accuracy of positioning the silicon wafer 12 to be tested on the etching equipment is determined, thereby ensuring the accuracy of etching the silicon wafer 1.
[0124] The method for determining the position of a silicon wafer is particularly suitable for calibrating an etching device before etching a metal contact window on the silicon wafer 1, so as to ensure the accuracy of etching the metal contact window on the silicon wafer 1 and avoid damage or failure of the chip after etching.
[0125] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the protection scope of the present invention.
Claims
1. A method for determining the position of a silicon wafer in an etching reaction chamber, characterized in that: include: S01: placing a standard silicon wafer in an etching device, ensuring that the standard silicon wafer is placed in a standard position on the etching device; S02: using the standard silicon wafer to perform etching under predetermined parameters; S03: After etching, detecting etching rates of a plurality of first sampling points on a first predetermined area at the edge of the standard silicon wafer; S04: obtaining a standard etching rate uniformity of the standard silicon wafer according to the etching rates of a predetermined number of the first sampling points; S05: placing the silicon wafer to be tested in the etching equipment; S06: using the silicon wafer to be tested to perform etching under the predetermined parameters; S07: Detecting etching rates of a plurality of second sampling points on a second predetermined area at the edge of the silicon wafer to be tested; the second predetermined area has the same coverage as the first predetermined area, and the second sampling points have the same setting positions as the first sampling points; S08: Obtaining the actual etching rate uniformity of the silicon wafer to be tested according to the etching rates of the predetermined number of the second sampling points; S09: Compare the actual etching rate uniformity with the standard etching rate uniformity, and determine the offset of the silicon wafer to be tested according to the comparison result.
2. The method for determining the position of a silicon wafer in an etching reaction chamber according to claim 1, characterized in that: In step S04, the method for obtaining the standard etching rate uniformity of the standard silicon wafer includes: Etching is performed on a plurality of the standard silicon wafers, and an etching rate uniformity of each of the standard silicon wafers is obtained, and a maximum value among the plurality of etching rate uniformities is taken as the standard etching rate uniformity.
3. The method for determining the position of a silicon wafer in an etching reaction chamber according to claim 1, characterized in that: In step S04, the method for obtaining the standard etching rate uniformity of the standard silicon wafer includes: Etching a plurality of the standard silicon wafers, and obtaining the etching rate uniformity of each of the standard silicon wafers; setting a compensation value for the etching rate uniformity, and taking the sum of the maximum value of the plurality of etching rate uniformities and the compensation value as the standard etching rate uniformity.
4. The method for determining the position of a silicon wafer in an etching reaction chamber according to claim 3, characterized in that: The compensation value is set to 0.1% to 0.3%.
5. The method for determining the position of a silicon wafer in an etching reaction chamber according to claim 2 or 3, characterized in that: The standard etching rate uniformity is less than or equal to 3%.
6. The method for determining the position of a silicon wafer in an etching reaction chamber according to claim 1, characterized in that: The surfaces of the silicon wafer to be tested and the standard silicon wafer are both covered with oxide films of the same thickness.
7. The method for determining the position of a silicon wafer in an etching reaction chamber according to any one of claims 1 to 4, characterized in that: In step S09, the step of determining the offset of the silicon wafer to be tested according to the comparison result includes: If the actual etching rate uniformity is greater than the standard etching rate uniformity, it is determined that the placement position of the silicon wafer to be tested on the etching equipment is offset; If the actual etching rate uniformity is less than or equal to the standard etching rate uniformity, it is determined that the placement position of the silicon wafer to be tested on the etching equipment is accurate.
8. The method for determining the position of a silicon wafer in an etching reaction chamber according to any one of claims 1 to 4, characterized in that: The radii of the silicon wafer to be tested and the standard silicon wafer are both 150 mm, and the radii of the first predetermined area and the second predetermined area are both in the range of 145 mm to 150 mm.
9. The method for determining the position of a silicon wafer in an etching reaction chamber according to any one of claims 1 to 4, characterized in that: In step S03, the method for acquiring a plurality of the first sampling points on the standard silicon wafer includes: Selecting first sampling circles with at least two radius values on the first predetermined area of the standard silicon wafer, and selecting a plurality of first sampling points at equal intervals from the first sampling circles; In step S07, the method for acquiring a plurality of the second sampling points on the silicon wafer to be tested includes: Selecting second sampling circles with at least two radius values on the second predetermined area of the silicon wafer to be tested, and selecting a plurality of second sampling points from the second sampling circles at equal intervals.
10. The method for determining the position of a silicon wafer in an etching reaction chamber according to claim 9, characterized in that: The first sampling circle and / or the second sampling circle include an outer sampling circle and an inner sampling circle, the radius of the outer sampling circle is greater than the radius of the inner sampling circle; the number of the first sampling points and / or the second sampling points selected on the outer sampling circle is greater than or equal to 24, and the number of the first sampling points and / or the second sampling points selected on the inner sampling circle is greater than or equal to 16.
11. The method for determining the position of a silicon wafer in an etching reaction chamber according to any one of claims 1 to 4, characterized in that: In step S04, the step of obtaining the etching rates of a predetermined number of the first sampling points includes: After acquiring the etching rates of all the first sampling points, removing the highest etching rates of the target number and removing the lowest etching rates of the target number, thereby obtaining the etching rates of a predetermined number of the first sampling points; In step S08, the step of obtaining the etching rates of the predetermined number of the second sampling points includes: After acquiring the etching rates of all the second sampling points, the highest etching rate of the target number is removed, and the lowest etching rate of the target number is removed, so as to obtain the etching rates of the predetermined number of the second sampling points.
12. The method for determining the position of a silicon wafer in an etching reaction chamber according to any one of claims 1 to 4, characterized in that: Step S03 also includes: establishing a standard etching rate distribution map according to the etching rates of all the first sampling points; Step S07 also includes: establishing an actual etching rate distribution map according to the etching rates of all the second sampling points.